609 lines
15 KiB
C
609 lines
15 KiB
C
/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief Power Manager driver.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support email: avr32@atmel.com
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*
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*****************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "pm.h"
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void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
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{
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union {
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unsigned long oscctrl0;
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avr32_pm_oscctrl0_t OSCCTRL0;
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} oscctrl0 ;
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// Read
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oscctrl0.oscctrl0 = pm->oscctrl0;
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// Modify
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oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;
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// Write
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pm->oscctrl0 = oscctrl0.oscctrl0;
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}
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void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
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{
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union {
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unsigned long oscctrl0;
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avr32_pm_oscctrl0_t OSCCTRL0;
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} oscctrl0 ;
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// Read
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oscctrl0.oscctrl0 = pm->oscctrl0;
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// Modify
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oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
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AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;
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// Write
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pm->oscctrl0 = oscctrl0.oscctrl0;
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}
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void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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union {
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unsigned long oscctrl0;
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avr32_pm_oscctrl0_t OSCCTRL0;
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} oscctrl0 ;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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oscctrl0.oscctrl0 = pm->oscctrl0;
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// Modify
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mcctrl.MCCTRL.osc0en = 1;
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oscctrl0.OSCCTRL0.startup = startup;
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// Write back
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pm->oscctrl0 = oscctrl0.oscctrl0;
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pm->mcctrl = mcctrl.mcctrl;
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while(!pm->ISR.osc0rdy); //For osc output valid
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}
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void pm_disable_clk0(volatile avr32_pm_t *pm)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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// Modify
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mcctrl.MCCTRL.osc0en = 0;
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// Write back
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pm->mcctrl = mcctrl.mcctrl;
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}
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void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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union {
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unsigned long oscctrl0;
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avr32_pm_oscctrl0_t OSCCTRL0;
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} oscctrl0 ;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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oscctrl0.oscctrl0 = pm->oscctrl0;
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// Modify
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mcctrl.MCCTRL.osc0en = 1;
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oscctrl0.OSCCTRL0.startup=startup;
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// Write back
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pm->mcctrl = mcctrl.mcctrl;
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pm->oscctrl0 = oscctrl0.oscctrl0;
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}
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void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
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{
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while(!pm->ISR.osc0rdy);
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}
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void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
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{
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union {
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unsigned long oscctrl1;
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avr32_pm_oscctrl1_t OSCCTRL1;
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} oscctrl1 ;
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// Read
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oscctrl1.oscctrl1= pm->oscctrl1;
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// Modify
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oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;
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// Write
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pm->oscctrl1 = oscctrl1.oscctrl1;
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}
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void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
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{
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union {
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unsigned long oscctrl1;
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avr32_pm_oscctrl1_t OSCCTRL1;
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} oscctrl1 ;
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// Read
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oscctrl1.oscctrl1= pm->oscctrl1;
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// Modify
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oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
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AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;
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// Write
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pm->oscctrl1 = oscctrl1.oscctrl1;
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}
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void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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union {
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unsigned long oscctrl1;
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avr32_pm_oscctrl1_t OSCCTRL1;
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} oscctrl1 ;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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oscctrl1.oscctrl1 = pm->oscctrl1;
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mcctrl.MCCTRL.osc1en = 1;
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oscctrl1.OSCCTRL1.startup=startup;
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// Write back
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pm->oscctrl1 = oscctrl1.oscctrl1;
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pm->mcctrl = mcctrl.mcctrl;
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while(!pm->ISR.osc1rdy);
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}
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void pm_disable_clk1(volatile avr32_pm_t *pm)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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// Modify
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mcctrl.MCCTRL.osc1en = 0;
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// Write back
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pm->mcctrl = mcctrl.mcctrl;
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}
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void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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union {
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unsigned long oscctrl1;
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avr32_pm_oscctrl1_t OSCCTRL1;
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} oscctrl1 ;
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// Read register
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mcctrl.mcctrl = pm->mcctrl;
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oscctrl1.oscctrl1 = pm->oscctrl1;
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mcctrl.MCCTRL.osc1en = 1;
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oscctrl1.OSCCTRL1.startup=startup;
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// Write back
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pm->oscctrl1 = oscctrl1.oscctrl1;
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pm->mcctrl = mcctrl.mcctrl;
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}
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void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
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{
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while(!pm->ISR.osc1rdy);
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}
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void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
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{
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union {
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} u_ctrl;
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u_ctrl.oscctrl32 = pm->oscctrl32;
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u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;
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pm->oscctrl32 = u_ctrl.oscctrl32;
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}
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void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
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{
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union {
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} u_ctrl;
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u_ctrl.oscctrl32 = pm->oscctrl32;
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u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;
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pm->oscctrl32 = u_ctrl.oscctrl32;
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}
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void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} oscctrl32 ;
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// Read register
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oscctrl32.oscctrl32 = pm->oscctrl32;
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// Modify
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oscctrl32.OSCCTRL32.osc32en = 1;
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oscctrl32.OSCCTRL32.startup=startup;
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// Write back
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pm->oscctrl32 = oscctrl32.oscctrl32;
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while(!pm->ISR.osc32rdy);
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}
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void pm_disable_clk32(volatile avr32_pm_t *pm)
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{
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// To get rid of a GCC bug
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// This makes C code longer, but not ASM
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union {
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} oscctrl32 ;
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// Read register
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oscctrl32.oscctrl32 = pm->oscctrl32;
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// Modify
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oscctrl32.OSCCTRL32.osc32en = 0;
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// Write back
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pm->oscctrl32 = oscctrl32.oscctrl32;
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}
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void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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union {
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} oscctrl32 ;
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// Read register
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oscctrl32.oscctrl32 = pm->oscctrl32;
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// Modify
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oscctrl32.OSCCTRL32.osc32en = 1;
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oscctrl32.OSCCTRL32.startup=startup;
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// Write back
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pm->oscctrl32 = oscctrl32.oscctrl32;
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}
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void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
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{
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// To get rid of a GCC bug
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// This makes C code longer, but not ASM
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while(!pm->ISR.osc32rdy);
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}
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void pm_cksel(volatile avr32_pm_t *pm,
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unsigned int pbadiv,
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unsigned int pbasel,
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unsigned int pbbdiv,
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unsigned int pbbsel,
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unsigned int hsbdiv,
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unsigned int hsbsel)
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{
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// Force the compiler to generate only one 32 bits access
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union {
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avr32_pm_cksel_t selval ;
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unsigned long uword32;
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} cksel;
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cksel.uword32 = 0;
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cksel.selval.cpudiv = hsbdiv;
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cksel.selval.cpusel = hsbsel;
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cksel.selval.hsbdiv = hsbdiv;
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cksel.selval.hsbsel = hsbsel;
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cksel.selval.pbbdiv = pbbdiv;
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cksel.selval.pbbsel = pbbsel;
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cksel.selval.pbadiv = pbadiv;
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cksel.selval.pbasel = pbasel;
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pm->cksel = cksel.uword32;
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// Wait for ckrdy bit and then clear it
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while(!(pm->ISR.ckrdy));
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return;
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}
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void pm_gc_setup(volatile avr32_pm_t *pm,
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unsigned int gc,
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unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
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unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
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unsigned int diven,
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unsigned int div) {
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union {
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unsigned long gcctrl;
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avr32_pm_gcctrl_t GCCTRL;
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} u_gc;
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u_gc.GCCTRL.oscsel = pll_osc;
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u_gc.GCCTRL.pllsel = osc_or_pll;
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u_gc.GCCTRL.diven = diven;
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u_gc.GCCTRL.div = div;
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u_gc.GCCTRL.cen = 0; // Disable GC first
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pm->gcctrl[gc] = u_gc.gcctrl;
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}
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void pm_gc_enable(volatile avr32_pm_t *pm,
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unsigned int gc) {
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union {
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unsigned long gcctrl;
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avr32_pm_gcctrl_t GCCTRL;
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} u_gc;
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u_gc.gcctrl = pm->gcctrl[gc];
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u_gc.GCCTRL.cen = 1;
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pm->gcctrl[gc] = u_gc.gcctrl;
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}
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void pm_gc_disable(volatile avr32_pm_t *pm,
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unsigned int gc) {
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union {
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unsigned long gcctrl;
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avr32_pm_gcctrl_t GCCTRL;
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} u_gc;
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u_gc.gcctrl = pm->gcctrl[gc];
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u_gc.GCCTRL.cen = 0;
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pm->gcctrl[gc] = u_gc.gcctrl;
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}
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void pm_pll_setup(volatile avr32_pm_t *pm,
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unsigned int pll,
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unsigned int mul,
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unsigned int div,
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unsigned int osc,
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unsigned int lockcount) {
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union {
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unsigned long pll ;
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avr32_pm_pll_t PLL ;
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} u_pll;
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u_pll.pll=0;
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u_pll.PLL.pllmul = mul;
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u_pll.PLL.plldiv = div;
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u_pll.PLL.pllosc = osc;
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u_pll.PLL.pllcount = lockcount;
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u_pll.PLL.pllopt = 0;
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u_pll.PLL.plltest = 0;
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(pm->pll)[pll] = u_pll.pll;
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}
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void pm_pll_set_option(volatile avr32_pm_t *pm,
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unsigned int pll,
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unsigned int pll_freq,
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unsigned int pll_div2,
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unsigned int pll_wbwdisable) {
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union {
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unsigned long pll ;
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avr32_pm_pll_t PLL ;
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} u_pll;
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u_pll.pll = (pm->pll)[pll];
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u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);
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(pm->pll)[pll] = u_pll.pll;
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}
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unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
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unsigned int pll) {
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return (pm->PLL)[pll].pllopt;
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}
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void pm_pll_enable(volatile avr32_pm_t *pm,
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unsigned int pll) {
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union {
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unsigned long pll ;
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avr32_pm_pll_t PLL ;
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} u_pll;
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u_pll.pll = (pm->pll)[pll];
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u_pll.PLL.pllen = 1;
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(pm->pll)[pll] = u_pll.pll;
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}
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void pm_pll_disable(volatile avr32_pm_t *pm,
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unsigned int pll) {
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union {
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unsigned long pll ;
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avr32_pm_pll_t PLL ;
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} u_pll;
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u_pll.pll = (pm->pll)[pll];
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u_pll.PLL.pllen = 0;
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(pm->pll)[pll] = u_pll.pll;
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}
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void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
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{
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while(!pm->ISR.lock0);
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// Bypass the lock signal of the PLL
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pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;
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}
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void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
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{
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while(!pm->ISR.lock1);
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// Bypass the lock signal of the PLL
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pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;
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}
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void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
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{
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union {
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avr32_pm_mcctrl_t MCCTRL;
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unsigned long mcctrl;
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} mcctrl;
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// Read
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mcctrl.mcctrl = pm->mcctrl;
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// Modify
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mcctrl.MCCTRL.mcsel = clock;
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// Write Back
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pm->MCCTRL.mcsel = mcctrl.mcctrl;
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}
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void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
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{
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pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode
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pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
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pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
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}
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void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {
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|
|
union {
|
|
unsigned long ier ;
|
|
avr32_pm_ier_t IER ;
|
|
} u_ier;
|
|
u_ier.ier = 0;
|
|
u_ier.IER.boddet = 1;
|
|
|
|
pm->ier = u_ier.ier;
|
|
}
|
|
|
|
|
|
void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {
|
|
|
|
union {
|
|
unsigned long idr ;
|
|
avr32_pm_idr_t IDR ;
|
|
} u_idr;
|
|
u_idr.idr = 0;
|
|
u_idr.IDR.boddet = 1;
|
|
|
|
pm->idr = u_idr.idr;
|
|
}
|
|
|
|
|
|
void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {
|
|
|
|
union {
|
|
unsigned long icr ;
|
|
avr32_pm_idr_t ICR ;
|
|
} u_icr;
|
|
u_icr.icr = 0;
|
|
u_icr.ICR.boddet = 1;
|
|
|
|
pm->icr = u_icr.icr;
|
|
}
|
|
|
|
|
|
unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {
|
|
|
|
return pm->ISR.boddet;
|
|
}
|
|
|
|
|
|
unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {
|
|
|
|
return pm->IMR.boddet;
|
|
}
|
|
|
|
|
|
unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {
|
|
union {
|
|
unsigned long bod ;
|
|
avr32_pm_bod_t BOD ;
|
|
} u_bod;
|
|
|
|
u_bod.bod = pm->bod;
|
|
|
|
return (unsigned long) u_bod.BOD.level;
|
|
|
|
}
|
|
|
|
|
|
void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {
|
|
(pm->gplp)[gplp] = value;
|
|
|
|
}
|
|
|
|
|
|
unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {
|
|
|
|
return (pm->gplp)[gplp];
|
|
}
|