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414 Commits

Author SHA1 Message Date
Richard Barry
c3c9c12ce2 Update the common demo death.c to use the updated macro name to give it a secure context. 2019-02-19 02:57:44 +00:00
Gaurav Aggarwal
ce576f3683 First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees. 2019-02-19 02:30:32 +00:00
Richard Barry
58ba10eee8 Update version number in readiness for V10.2.0 release. 2019-02-17 22:36:16 +00:00
Gaurav Aggarwal
55ad3861c5 Sync the Renesas port to AFR Git Repo 2019-02-17 01:27:16 +00:00
Gaurav Aggarwal
0de2a2758a Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE 
tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE was not correctly defined resulting in
dynamically allocated TCB not being freed when MPU was enabled. This commit fixes
the definition to ensure that dynamically allocated RAM (Stack and TCB) is freed
always.
 2019-02-17 01:24:58 +00:00
Gaurav Aggarwal
2c88fb7fa1 Fix build failure when dynamic allocation is not enabled. 
When dynamic allocation is not enabled, vPortFree is not available. The current code used
vPortFree and this resulted in linker error. This commit removes the use of vPortFree when
dynamic allocation is not enabled.
 2019-02-16 20:21:47 +00:00
Richard Barry
6844bef74f Replace the pdf RISC-V documentation with links to the documentation web pages. 2019-02-16 01:15:33 +00:00
Richard Barry
b2b1b09ea5 Fix bug in core_cm3.c atomic macros. 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
 2019-02-16 01:08:38 +00:00
Richard Barry
fb73829148 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). 
Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
 2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655 Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. 2019-01-21 23:39:48 +00:00
Gaurav Aggarwal
817783d75c Copyright updates from Cadence. 
e1df894752
 2019-01-16 19:01:25 +00:00
Richard Barry
11d9c440b8 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). 
Add a project for the Vega board's RI5CY core.
 2018-12-31 18:19:52 +00:00
Richard Barry
e2af102c80 Re-org of RISC-V file structure and naming step 2. 2018-12-30 23:53:47 +00:00
Richard Barry
818eeccc0c Re-org of RISC-V file structure and naming step 1. 2018-12-30 23:20:26 +00:00
Richard Barry
db750d0c82 Update RSIC-V port layer after testing saving and receiving of chip specific registers. 2018-12-30 23:11:40 +00:00
Richard Barry
60b133b2c6 Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. 2018-12-30 20:00:43 +00:00
Richard Barry
d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. 
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
 2018-12-28 00:44:18 +00:00
Richard Barry
ce36928ea8 Rename directories in the RISC-V port. 2018-12-24 17:37:02 +00:00
Richard Barry
148f588f56 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. 
Add the vTimerSetReloadMode() API function.
 2018-12-17 22:04:18 +00:00
Richard Barry
101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. 2018-12-16 23:59:49 +00:00
Richard Barry
7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: 
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
 2018-12-16 20:21:29 +00:00
Richard Barry
65f7a2dc19 Update RISC-V port to use a separate interrupt stack. 2018-12-04 01:23:41 +00:00
Richard Barry
e85ea96f78 Some efficiency improvements in Risc-V port. 2018-11-28 19:35:40 +00:00
Richard Barry
dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 20:59:07 +00:00
Richard Barry
db64297487 Provide each Risc V task with an initial mstatus register value. 2018-11-20 20:12:35 +00:00
Richard Barry
8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. 2018-11-19 06:01:29 +00:00
Richard Barry
baee711cb6 Continue work on Risc V port. 2018-11-06 02:04:28 +00:00
Richard Barry
74d0d16aab Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case. 2018-11-05 19:35:54 +00:00
Richard Barry
55ff89373a Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately. 2018-10-24 21:37:59 +00:00
Richard Barry
6fab2b9e0d Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). 2018-10-08 15:10:18 +00:00
Richard Barry
c6de0001fa Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. 
Allows the task name parameter passed into xTaskCreate() to be NULL.
 2018-09-30 21:50:05 +00:00
Richard Barry
e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. 2018-09-27 17:25:17 +00:00
Richard Barry
2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. 2018-09-23 03:52:23 +00:00
Richard Barry
32f35e9130 RISC-V: 
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
 2018-09-12 16:33:05 +00:00
Richard Barry
b11eb3a59c RISC-V work in progress: 
+ Initialise task stack.
    + Successfully jump to start of first task.
 2018-09-10 20:50:05 +00:00
Richard Barry
0c0f0d0f8f Minor synching - no functional changes. 2018-09-07 22:24:51 +00:00
Richard Barry
92ae8e7aff Update version numbers ready for release. 2018-09-07 18:13:20 +00:00
Richard Barry
be9c0730c3 Update trace recorder code to the latest. 
Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
 2018-09-06 03:23:03 +00:00
Richard Barry
21a8ff35dd Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly. 2018-09-01 02:42:34 +00:00
Richard Barry
e2750cd388 Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up. 
Remove duplicate comment in heap_1.c.
 2018-08-29 15:43:41 +00:00
Richard Barry
0d6e3df7ec Minor updates to fix issues with the Segger kernel aware plug since V10.1.0. 2018-08-28 18:10:42 +00:00
Richard Barry
893db45834 Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0. 2018-08-27 23:11:28 +00:00
Richard Barry
b0ce1f61c9 Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose. 2018-08-27 21:59:26 +00:00
Richard Barry
3a1631fda3 Update copyright date ready for tagging V10.1.0. 2018-08-22 23:23:03 +00:00
Richard Barry
fb9de58f56 Update version numbers in preparation for a new release. 2018-08-21 19:50:48 +00:00
Richard Barry
722ca8fb2b Update demo project for Tensilita - work in progres.. 
Add support for POSIX style errno - work in progress.
 2018-08-21 19:37:04 +00:00
Richard Barry
78d20e2854 Only include the static definition of freertos_tasks_c_additions_init if FREERTOS_TASKS_C_ADDITIONS_INIT is defined, matching the guide used to include the function's prototype. 2018-08-20 15:08:35 +00:00
Gaurav Aggarwal
56dc0dd9b4 Merge bug fixes from Cadence 2018-08-07 07:21:07 +00:00
Richard Barry
f6cbf20019 Update RISC-V project to used official port stubs in place of third party port. 2018-07-07 21:54:41 +00:00
Richard Barry
3bfc32d444 Add stubs for official RISC-V RV32 port. 2018-07-07 21:47:31 +00:00