Provide each Risc V task with an initial mstatus register value.
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Richard Barry
parent
8cef339aec
commit
db64297487
@ -76,6 +76,8 @@ volatile uint32_t ulx = 0;
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint32_t mstatus;
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const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
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/*
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X1 to X31 integer registers for the 'I' profile, X1 to X15 for the 'E' profile.
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@ -94,10 +96,11 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
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x28-31 t3-6 Temporaries Caller
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*/
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/* To ensure alignment. */
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//_RB_ pxTopOfStack--;
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//_RB_ pxTopOfStack--;
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//_RB_pxTopOfStack--;
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/* Start task with interrupt enabled. */
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__asm volatile ("csrr %0, mstatus" : "=r"(mstatus));
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mstatus |= ulMPIE_Bit | ulMPP_Bits;
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pxTopOfStack--;
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*pxTopOfStack = mstatus;
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/* Numbers correspond to the x register number. */
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pxTopOfStack--;
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@ -36,7 +36,7 @@
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#error Assembler has not defined __riscv_xlen
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#endif
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#define CONTEXT_SIZE ( 28 * WORD_SIZE )
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#define CONTEXT_SIZE ( 30 * WORD_SIZE )
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.global xPortStartFirstTask
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.global vPortTrapHandler
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@ -48,41 +48,40 @@
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.align 8
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xPortStartFirstTask:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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csrs mie, 8 /* Enable soft interrupt. */
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ret
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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/*-----------------------------------------------------------*/
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@ -118,59 +117,63 @@ vPortTrapHandler:
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sw x30, 27 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp from first TCB member. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * WORD_SIZE( sp )
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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/*_RB_ Does stack need aligning here? */
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jal handle_trap
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csrw mepc, a0
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/* Save exception return address. */
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sw a0, 0( sp )
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# Remain in M-mode after mret
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li t0, 0x00001800 /* MSTATUS MPP */
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csrs mstatus, t0
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next task. */
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lw t0, 0( sp )
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csrw mepc, t0
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/* Load mret with the address of the next task. */
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lw t0, 0( sp )
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csrw mepc, t0
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * WORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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mret
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mret
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