Commit Graph

174 Commits

Author SHA1 Message Date
Gaurav Aggarwal
618e165fa7 Fix NULL pointer dereference in vPortGetHeapStats
When the heap is exhausted (no free block), start and end markers are
the only blocks present in the free block list:

     +---------------+     +-----------> NULL
     |               |     |
     |               V     |
+ ----- +            + ----- +
|   |   |            |   |   |
|   |   |            |   |   |
+ ----- +            + ----- +
  xStart               pxEnd

The code block which traverses the list of free blocks to calculate heap
stats used a do..while loop that moved past the end marker when the heap
had no free block resulting in a NULL pointer dereference. This commit
changes the do..while loop to while loop thereby ensuring that we never
move past the end marker.

This was reported here - https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/534

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-08-04 09:57:59 -07:00
Gaurav-Aggarwal-AWS
dc9c034c85
Add vPortRemoveInterruptHandler API (#533)
* Add xPortRemoveInterruptHandler API

This API is added to the MicroBlazeV9 port. It enables the application
writer to remove an interrupt handler.

This was originally contributed in this PR - https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/523

* Change API signature to return void

This makes the API similar to vPortDisableInterrupt.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gavin Lambert <uecasm@users.noreply.github.com>
2022-08-03 13:45:27 -07:00
Gavin Lambert
63f86fc7a2
Implement MicroBlazeV9 stack protection (#523)
* Implement stack protection for MicroBlaze (without MPU wrappers)
2022-08-03 12:01:18 +05:30
0xjakob
349e803314
Posix: Removed unused signal set from port (#528)
Co-authored-by: Jakob Hasse <0xjakob@users.noreply.github.com>
2022-07-25 10:05:30 -07:00
NomiChirps
859dbaf504
RP2040: Use indirect reference for pxCurrentTCB (#525) 2022-07-18 16:05:30 -07:00
Paul Bartell
2dfdfc4ba4
Add Cortex M7 r0p1 Errata 837070 workaround to CM4_MPU ports (#513)
* Clarify Cortex M7 r0p1 errata number in r0p1 specific port.

* Add ARM Cortex M7 r0p0 / r0p1 Errata 837070 workaround to CM4 MPU ports.

Optionally, enable the errata workaround by defining configTARGET_ARM_CM7_r0p0 or configTARGET_ARM_CM7_r0p1 in FreeRTOSConfig.h.

* Add r0p1 errata support to IAR port as well

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Change macro name to configENABLE_ERRATA_837070_WORKAROUND

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-06-30 10:35:26 +05:30
Gaurav-Aggarwal-AWS
8e89acfc98
Update submodule pointer of Community Supported Ports (#486)
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Paul Bartell <pbartell@amazon.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
2022-06-29 08:01:00 -07:00
Xinyu Zhang
57530af294
Update to TF-M version TF-Mv1.6.0 (#517)
Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Change-Id: I0c15564b342873f9bd7a8240822e770950a0563e
2022-06-29 12:22:30 +05:30
Graham Sanderson
d2a81539e0
RP2040: Allow FreeRTOS to be added to the parent CMake project post initialization of the Pico SDK (#497)
Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
2022-06-24 17:22:49 +05:30
Graham Sanderson
90d920466e
RP2040: Remove incorrect assertion (#508)
After the xEventGroupWaitBits in vProtLockInternalSpinUnlockWithWait there was an assertion about
pxYiledSpinLock being NULL, however when xEventGroupWaitBits returns, IRQs have been re-enabled
and so it is no longer safe to assert on the state which is protected by IRQs being disabled.

Co-authored-by: graham sanderson <graham.sanderson@raspeberryi.com>
2022-06-22 10:27:26 -07:00
Ravishankar Bhagavandas
0b46492740
Add callback overrides for stream buffer and message buffers (#437)
* Let each stream/message can use its own sbSEND_COMPLETED

In FreeRTOS.h, set the default value of configUSE_SB_COMPLETED_CALLBACK
to zero, and add additional space for the function pointer when
the buffer created statically.

In stream_buffer.c, modify the macro of sbSEND_COMPLETED which let
the stream buffer to use its own implementation, and then add an
pointer to the stream buffer's structure, and modify the
implementation of the buffer creating and initializing

Co-authored-by: eddie9712 <qw1562435@gmail.com>
2022-06-20 17:48:34 -07:00
AndreiCherniaev
daf544fbc4
add extra check for compiler time (#499)
minor change to add extra check for compiler time to prevent bad config

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2022-06-02 22:33:37 +05:30
alfred gedeon
719ceee352
Add suppport for ARM CM55 (#494)
* Add supposrt for ARM CM55

* Fix file header

* Remove duplicate code

* Refactor portmacro.h

1. portmacro.h is re-factored into 2 parts - portmacrocommon.h which is
   common to all ARMv8-M ports and portmacro.h which is different for
   different compiler and architecture. This enables us to provide
   Cortex-M55 ports without code duplication.
2. Update copy_files.py so that it copies Cortex-M55 ports correctly -
   all files except portmacro.h are used from Cortex-M33 ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-06-01 15:00:10 -07:00
Dusan Cervenka
1ec8e49de4
Aligned nullptr check for heap3. (#493)
Signed-off-by: Cervenka Dusan <cervenka@acrios.com>
2022-05-17 22:26:01 +05:30
alfred gedeon
ec7c40335d
Format code, and rmove implicit tests (#489) 2022-04-21 10:18:58 -07:00
Kody Stribrny
15bc8664b5
Add atomic flag for 16-bit ticks PIC24 (#488)
This change allows the PIC24 family of
16 bit processors to read the tick count
without a critical section when the tick
count is 16 bits.

Inspired from discussion - https://forums.freertos.org/t/xtaskgettickcount-with-critical-section-on-16-bit-mcu/14860/5
2022-04-15 08:13:14 -07:00
pierrenoel-bouteville-act
e73fabce9a
Declare vApplicationMallocFailedHook function in task.h instead in each C heap file (#483)
vApplicationMallocFailedHook was declared in each Heap file. which forces users to declare it and can cause problems if the prototype of the function changes.

Co-authored-by: Pierre-Noel Bouteville <pnb990@gmail.com>
2022-04-13 10:44:14 -07:00
Archit Gupta
b00250372e
Enable use of --text-section-literals in Xtensa port (#485)
Patch submitted by customer on forums here: https://forums.freertos.org/t/cannot-compile-xtensa-port-assembly-with-text-section-literals/14838
2022-04-11 15:07:08 -07:00
Gaurav-Aggarwal-AWS
40c37bd3ab
Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports (#484)
This is needed to support the case when SysTick timer is not clocked
from the same source as CPU. This support already exists in other
Cortex-M ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-04-08 11:13:11 -07:00
Gaurav-Aggarwal-AWS
b5b1ff02dd
Add a guard around mpu_wrappers.c (#480)
* Add a guard around mpu_wrappers.c

This avoid linker errors when this file is accidently compiled in
projects using non-MPU ports.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Fix formatting check

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-04-05 22:59:30 +05:30
Gaurav-Aggarwal-AWS
356fff8028
Update portable/ThirdParty/README.md (#474)
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-03-10 19:41:45 -08:00
niniemann
bdec3b6e54
fix: add additional .ltorg directives to GCC CM3/CM4 mpu ports (#473)
Co-authored-by: Nils Niemann <Niemann.N@eppendorf.de>
2022-03-10 09:19:58 -08:00
xinyu-tfm
f18e432d49
Update the README to align with TF-M v1.5.0 in TF-M integration (#469)
Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Change-Id: Ic04b82259ac17d5e0f8662118385c803e68af3e5
2022-03-05 16:31:08 -08:00
Gaurav-Aggarwal-AWS
58770b0f51
Check for add overflow only once (#467)
Update the size calculations such that we only need to check for add
overflow only once. Also, change the way we detect add overflow so that
we do not need to cause an overflow to detect an overflow.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-03-03 15:16:39 -08:00
Gaurav-Aggarwal-AWS
8eb3585252
Move MSB check after final size calculation (#463)
We use the MSB of the size member of a BlockLink_t to track whether not
a block is allocated. Consequently, the size must not be so large that
the MSB is set. The check to see if the MSB in the size is set needs to
be done after the final size (metadata + alignment) is calculated.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-02-28 11:59:00 -08:00
Gaurav-Aggarwal-AWS
82be77995e
Heap improvements (#462)
* Heap improvements

This commit makes the following improvements:

1. Add a check to heap_2 to track if a memory block is allocated to the
   application or not. The MSB of the size field is used for this
   purpose. The same check already exists in heap_4 and heap_5. This
   check prevents against double free.

2. Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4 and
   heap_5. The application writer can set it to 1 in their
   FreeRTOSConfig.h to ensure that a block of memory allocated using
   pvPortMalloc is cleared (i.e. set to zero) when it is freed using
   vPortFree. If left undefined, configHEAP_CLEAR_MEMORY_ON_FREE
   defaults to 0 for backward compatibility. We recommend setting
   configHEAP_CLEAR_MEMORY_ON_FREE to 1 for better security.

3. Add a new API pvPortCalloc to heap_2, heap_4 and heap_5. This API
   has the following signature:
   void * pvPortCalloc( size_t xNum, size_t xSize );
   It allocates memory for an array of xNum objects each of which is of
   xSize and initializes all bytes in the allocated storage to zero. If
   allocation succeeds, it returns a pointer to the lowest byte in the
   allocated memory block. On failure, it returns a null pointer.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-02-24 10:52:10 -08:00
Felipe Torrezan
4539e1c574
Migrated RL78/IAR port to EWRL78v3+ (#461)
Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
2022-02-24 10:04:46 -07:00
imi415
38efd2689e
CMake: Move mpu_wrapper to ports library. (#459) 2022-02-22 08:30:09 -07:00
Ming Yue
09a2c0b324
Remove exception loop tags. (#457) 2022-02-17 15:28:04 -08:00
Ming Yue
25d180a09b
Use a dedicated symbol for in-function loop to avoid the weak symbol JAL range error when a strong symbol is defined outside. (#455) 2022-02-15 14:56:13 -08:00
Shubham Kulkarni
4a490d64a5
portable/Xtensa_ESP32: Add SPDX license identifiers (#452)
Co-authored-by: Paul Bartell <pbartell@amazon.com>
2022-02-08 16:28:07 -08:00
Gaurav-Aggarwal-AWS
d5a10e4595
Add alignment for the direct mode handler (#449)
It is still possible to further relax the alignment using linker script
if needed.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-02-08 11:51:25 -08:00
Gaurav-Aggarwal-AWS
cf248aec2d
Add support for 16 MPU regions to GCC Cortex-M33 ports (#448)
* Add support for 16 MPU regions to GCC Cortex-M33 TZ port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Add support for 16 MPU regions to Cortex-M33 NTZ GCC port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-02-07 16:51:19 -08:00
swaldhoer
89e4823a49
Update uncrustify configuration to 0.69 (#445)
The configuration was updated using

    uncrustify -c .github/uncrustify.cfg -o .github/uncrustify.cfg --update-config-with-doc

to align with the actually used uncrustify version used, i.e., all
configuration is now explicitly set (and no longer implicit).

The files that are common to all ports ("portable/MemMang*" and
"portable/Common/mpu_wrappers.c" are now also autoformatted.

Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
2022-01-28 10:48:03 -08:00
Gaurav-Aggarwal-AWS
9efca75d1e
Riscv re-factoring (#444)
* Refactor RISCV port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Changes to make re-factoring work on ESP32-C3

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove alignment and place handlers in separate sections

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Correct section names

This is needed so that the assemblers correctly recognizes functions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move mtvec programming to the application

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Refactor mtimer udpate code

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move critical nesting to port layer

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Respect configTASK_RETURN_ADDRESS

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Formatting changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-01-26 17:55:01 -08:00
yhsb2k
cdd406a62f
Add CMake build (#421)
* Add CMake build

Allows to build and link FreeRTOS using CMake build system.
From top-level project it looks like this:

set(FREERTOS_PORT_GCC_ARM_CM4F ON)
set(FREERTOS_CONFIG_FILE_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} CACHE STRING "")
add_subdirectory(third_party/FreeRTOS-Kernel)

Where FREERTOS_PORT_GCC_ARM_CM4F is FreeRTOS port name.
freertos is target name, which can be used in target_link_libraries()

* Add feature to set custom heap source file

Example how to set it from top-level project:
set(FREERTOS_HEAP ${CMAKE_CURRENT_LIST_DIR}/path_to/my_heap.c CACHE STRING "")

* Set cmake_minimum_required to 3.15

* Fail build when FREERTOS_CONFIG_FILE_DIRECTORY not set

* Rename library to freertos_kernel

* Rework FREERTOS_PORT option to act as combobox

* Use freertos_kernel_port cmake target

* Split port sources multiline

Co-authored-by: Aniruddha Kanhere <60444055+AniruddhaKanhere@users.noreply.github.com>
Co-authored-by: Paul Bartell <pbartell@amazon.com>
2022-01-20 12:35:04 -08:00
Ming Yue
043c2c7ef6
Fix GCC/RX100 function naming error. (#440) 2022-01-13 10:30:26 -08:00
Gaurav-Aggarwal-AWS
8e2dd5b861
Add a Known Issues file in the Third Party folder (#434)
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-01-03 14:26:43 -07:00
Amit Tomar
c13719d2d0
fix alignment exception for ullPortInterruptNesting. (#317)
* fix alignment exception for ullPortInterruptNesting.

While loading (LDR X5, ullPortInterruptNestingConst) the ullPortInterruptNesting
variable, the program control seems to be stuck and there is no abort or stack
trace observed (as there is no exception handler is installed to catch unaligned
access exception).

Program control moves forward, if one just declares this varible to be 2 bytes
aligned but then varible is not updated properly.

One of my colleague, pointed out that issue is due to the fact that
ullPortInterruptNesting must be at 8 bytes aligned address but since
"vApplicationIRQHandler" (that has 4 bytes of address) is sitting between
two 8 bytes aligned addresses that forces ullPortInterruptNesting to be at
4 byte aligned address, causing all sort of mess.

It works on QEMU (on ARM64) as it is, since there is no such check for
unaligned access but on real hardware it is prohibited.

Workaround to this problem is, either we skip 4 byets (using .align 4) after
vApplicationIRQHandler declaration or declare it the end of all declarations.
This commit does the latter one.

Signed-off-by: Amit Singh Tomar <atomar25opensource@gmail.com>

* Update portASM.S

Remove 1 tab = 4 spaces

Co-authored-by: Amit Singh Tomar <atomar25opensource@gmail.com>
Co-authored-by: alfred gedeon <28123637+alfred2g@users.noreply.github.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
2021-12-29 13:53:10 -07:00
Fabian
481c722ef3
RISC-V: No #error on RV64 regarding byte alignment (#367)
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2021-12-28 11:52:33 -08:00
leona
81d15dc550
Fix: Interrut Handler Register Function and Exception Process (#41)
Signed-off-by: shiode <shiode@aptpod.co.jp>

Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
Co-authored-by: David Chalco <59750547+dachalco@users.noreply.github.com>
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
2021-12-28 10:54:23 -07:00
Gaurav-Aggarwal-AWS
53b9a80b8e
Update third party ports readme (#428)
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2021-12-21 14:10:06 -08:00
Graham Sanderson
debbd254b6
RP2040 fixes (#424)
* RP2040: malloc needs to be thread safe for FreeRTOS whether both cores are used or not

* RP2040: CMake file had broken left over test code

* RP2040: portIS_FREE_RTOS_CORE() returned an incorrect value prior to scheduler init when the application was compiled without multicore support

* RP2040: Bad initialization code was causing IRQs to get disabled before main() was called when using non static allocation
2021-12-21 11:08:41 -08:00
Gaurav Aggarwal
44fc137428 Add option to disable unprivileged critical sections
This commit introduces a new config
configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS which enables developers to
prevent critical sections from unprivileged tasks. It defaults to 1 for
backward compatibility. Application should set it to 0 to disable
critical sections from unprivileged tasks.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2021-11-15 15:09:12 -08:00
Gaurav Aggarwal
7a3848753b Change xPortRaisePrivilege and vPortResetPrivilege to macros
This prevents non-kernel code from calling these functions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2021-11-15 15:09:12 -08:00
Kevin Thibedeau
cd0b7fc271
Build with -Wmissing-prototypes flags vPortYieldFromISR() in the Posix port. (#409)
There's already a portYIELD_FROM_ISR() macro that calls vPortYield() which wraps the FromISR code.
It doesn't appear that vPortYieldFromISR() is intended to be publicly accessible in this port so
I've marked it as private to silence the warning.

event_create() also got flagged due to missing void in prototype.

Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2021-11-08 13:51:25 -08:00
andrewtjs
a432a688ca
bugfix: Initialise stack correctly on dsPIC port (#405)
* Use compiler predefined constants.

Use of MPLAB_DSPIC_PORT is deprecated.
2021-11-01 12:38:37 -07:00
Gaurav-Aggarwal-AWS
06fb777e43
Update comments for the ARM_CA53_64_BIT_SRE port (#403)
Mention that FreeRTOS_IRQ_Handler should not be used for FIQs and the
reason for assuming Group 1 for Interrupt Acknowledge and End Of
Interrupt registers.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
2021-10-16 13:45:03 -07:00
Stephane Viau
68ddb32b55
Handle interrupt acknowledge register in Cortex-A53 SRE port (#392)
Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.

Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
2021-10-15 09:21:56 -07:00
swaldhoer
a030d0a02b
fix typo (#399) 2021-10-06 15:32:07 -07:00