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57 Commits

Author SHA1 Message Date
Richard Barry
4b2f9dad42 Force the SysTick clock bit to be set in Cortex-M3 and Cortex-M4F bits if configSYSTICK_CLOCK_HZ is not defined, otherwise leave the bit as it is found as the SysTick may use a divided clock. 2013-12-15 10:27:37 +00:00
Richard Barry
0d1e12522b Update Cortex-M3 and Cortex-M4F ports to allow the SysTick to be clocked at a different speed than the system clock (as is done in the recent STM32L demo. ). 
Add additional asserts and isb instructions into the Cortex-M3 and Cortex-M4F ports.
 2013-12-12 14:07:20 +00:00
Richard Barry
00ad1a0200 Multiple tidy up, documentation corrections and typo corrections highlighted by Tamas Kleiber's diligent review. 2013-11-28 10:48:33 +00:00
Richard Barry
0cd79ad81d Change version numbers in preparation for V7.6.0 release. 2013-11-08 11:47:35 +00:00
Richard Barry
b181a3af99 Ensure the definition of prvTaskExitError()does not result in a compiler warning in ports where its use can be overridden (GCC Cortex-M ports). 
Remove duplicate save/restore of r14 in Cortex-M4F ports.
 2013-11-07 16:43:54 +00:00
Richard Barry
dcd261bb8b Update the Keil and IAR CM0 port layers to match the changes made to the GCC version. 2013-10-22 11:26:16 +00:00
Richard Barry
a12ea2d212 Update FreeRTOS version number to V7.5.3 
Update FreeRTOS+CLI version number to V1.0.2
Update FreeRTOS+UDP version number to V1.0.1
 2013-10-14 19:56:47 +00:00
Richard Barry
0c56f5018d Add some defensive programming in the default tickless mode in case the application supplied post tick hook takes a long time to complete. 2013-10-08 12:33:46 +00:00
Richard Barry
aedf7824cb Introduce the prvTaskExitError() function for all ARM_CMn ports. 
Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
 2013-10-08 11:30:40 +00:00
Richard Barry
eaacbb099a Clear up a few compiler warnings. 
Correct header comments in the UARTCommandConsole.c file used in the SmartFusion2 demo.
Exercise the new xQueueSpacesAvailable() function in the MSVC demo.
Add defaults for the new traceMALLOC and traceFREE trace macros.
Catch tasks trying to exit their functions in the Cortex-M0 ports.
Add additional comments to timers.c in response to a support forum question.
Initialise _impure_ptr prior to the first task being started.
Prior to V7.5.0 a yield pended in the tick hook would have occurred during the same tick interrupt.  Return pdTRUE from xTaskIncrementTick() if a yield is pending to revert to that behaviour.
 2013-10-07 12:06:17 +00:00
Richard Barry
73606369c4 Make Cortex-M0 set/clear interrupt flag from ISR functions nestable. 
Don't reset the stack location when starting the scheduler in Cortex-M0 ports as the vector offset register is not implemented and XMC1000 devices have their application vector address somewhere other than 0x00.
 2013-09-01 19:53:24 +00:00
Richard Barry
c40370e96a Fix a few typos and remove the "register" keyword. 2013-08-16 13:31:54 +00:00
Richard Barry
2f754d9b0c Add additional critical section to the default tickless implementations. 
Update version number for maintenance release.
 2013-07-24 09:45:17 +00:00
Richard Barry
3cbe0a724d Update version number. 2013-07-23 10:51:45 +00:00
Richard Barry
679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 2013-07-23 09:44:00 +00:00
Richard Barry
7d6758ee1a Minor updates and change version number for V7.5.0 release. 2013-07-17 18:32:57 +00:00
Richard Barry
7d1292ced2 Linting and MISRA checking 2013-07-15 14:27:15 +00:00
Richard Barry
e5d9640863 Update RX ports to only include additional check on the existing IPL (so it is not lowered) if configASSERT() is defined. 2013-07-13 11:31:35 +00:00
Richard Barry
ad8fa53043 Kernel optimisations. 2013-07-12 11:11:19 +00:00
Richard Barry
5d902f2b9c Complete additions of portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for all RX compiler ports. 2013-07-11 10:05:06 +00:00
Richard Barry
65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler. 
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
 2013-07-09 17:57:59 +00:00
Richard Barry
0f6b0d3a59 Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed. 
Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
 2013-07-09 12:49:49 +00:00
Richard Barry
c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 2013-07-04 11:20:28 +00:00
Richard Barry
0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 2013-06-30 10:38:31 +00:00
Richard Barry
a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 2013-06-25 13:39:50 +00:00
Richard Barry
04dafed839 IAR ARM Cortex-A port layer. 2013-06-20 12:20:40 +00:00
Richard Barry
2fd431e971 Modify the GCC/AVR port to make use of the xTaskIncrementTick return value. 
Add pre-processor directives in the dsPIC and PIC24 port layers that allows both port files to be included in the same project.
 2013-06-11 20:15:15 +00:00
Richard Barry
62c0ae0926 Update port layers to make better use of the xTaskIncrementTick() return value. 2013-06-08 18:36:25 +00:00
Richard Barry
c04b074707 Convert the remaining ports to use xTaskIncrementTick() in place of vTaskIncremenTick(). 2013-06-07 12:16:58 +00:00
Richard Barry
f904d26957 Convert more ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 2013-06-06 16:31:15 +00:00
Richard Barry
15ec6c87f7 Convert mpre ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 2013-06-06 16:06:48 +00:00
Richard Barry
686d190798 Convert some ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 
Move DSB instructions to before WFI instructions in line with ARM recommendations.
 2013-06-06 15:46:40 +00:00
Richard Barry
a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler. 
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
 2013-05-19 09:43:00 +00:00
Richard Barry
fb9662009a Update comments in Atmel Studio CreateProjectDirectoryStructure.bat files to remove references to replace references to Eclipse with references to Atmel Studio. 
Update the tickless idle implementations that use up counters for tick interrupt generate to ensure they remain in low power mode for the desired time instead of one tick less than the desired time.
 2013-05-09 09:56:04 +00:00
Richard Barry
96ceae8edd Update version number ready to release the FAT file system demo. 2013-04-30 21:42:41 +00:00
Richard Barry
f9918345e1 Update version numbers to V7.4.1. 2013-04-18 12:58:17 +00:00
Richard Barry
0013028c7a Update yield code in RX600/IAR compiler port. 2013-04-17 08:46:10 +00:00
Richard Barry
74290b4425 Add RX100 IAR port layer. 2013-04-16 15:58:46 +00:00
Richard Barry
895ee2bb3e Add barrier instructions to IAR CM3 ports. 2013-04-16 14:56:49 +00:00
Richard Barry
3762630f27 RL78/IAR port - Allow the end user to define their own tick interrupt configuration by defining configSETUP_TIMER_INTERRUPT(). 2013-03-25 17:00:13 +00:00
Richard Barry
caf1fbc899 Ensure IAR RL port layer works on devices using two different naming conventions for the interval timer registers. 2013-03-18 16:40:47 +00:00
Richard Barry
8c66fdbb8c Updated IAR RL78 port layer. 2013-03-17 16:54:17 +00:00
Richard Barry
17bba16fa6 Added YRDKRL78G14 build configuration to the IAR RL78 demo. 2013-02-24 19:48:26 +00:00
Richard Barry
a5d0e3f0c1 Prepare for V7.4.0 release. 2013-02-19 18:36:58 +00:00
Richard Barry
902f9e1a58 Update PIC32 demo application to remove reliance on PLIB functions. 
Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
 2013-02-18 16:41:11 +00:00
Richard Barry
ac78adae4b Added INCLUDE_xSemaphoreGetMutexHolder() default. 
Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
 2013-01-31 14:18:03 +00:00
Richard Barry
96f93690ce Add warning suppression to IAR header. 2012-10-31 13:30:44 +00:00
Richard Barry
ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 2012-10-29 15:56:26 +00:00
Richard Barry
f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 2012-10-22 16:40:45 +00:00
Richard Barry
f06a945444 Prepare for V7.3.0 release. 2012-10-16 12:17:47 +00:00