Commit Graph

2621 Commits

Author SHA1 Message Date
Richard Barry
35f5990e7a Update the MSVC and MingW demos to use the latest FreeRTOS+Trace recorder library. 2017-05-29 21:45:31 +00:00
Richard Barry
f289bfb388 Update to the latest trace recorder library. 2017-05-29 21:43:07 +00:00
Richard Barry
9f84f353d0 Remove configurations other than 'debug' from the Win32 demo. 2017-05-07 18:22:31 +00:00
Richard Barry
2e89c13c1c Cosmetic changes only. 2017-04-26 00:23:57 +00:00
Richard Barry
a99cd32208 Updated name of CORTEX_MPU_CEC_MEC_17xx_Keil_GCC to CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC. 2017-04-20 05:33:05 +00:00
Richard Barry
59925359ed Added traceQUEUE_CREATE_FAILED() trace macros into the queue create functions. 2017-04-10 01:58:58 +00:00
Richard Barry
b080f13543 Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version. 2017-04-10 01:58:01 +00:00
Richard Barry
0f85ead175 Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC. 2017-04-10 01:01:11 +00:00
Richard Barry
0a7a0a79d6 Updates to prevent warnings when compiled with LLVM. 2017-04-10 00:26:22 +00:00
Richard Barry
8ca40d80a9 Ensure the PIC32 interrupt stack is 8 byte aligned for all values of configISR_STACK_SIZE. 2017-04-09 20:13:48 +00:00
Richard Barry
96db5a3600 PIC32MZ project using later MPLAB X tools. 2017-04-09 19:35:32 +00:00
Richard Barry
ffb228e448 Change name of the CEC and MEC directory to CORTEX_CEC_MEC_17xx_51xx_Keil_GCC as it is also applicable to the MEC5105 part. 2017-04-04 20:21:40 +00:00
Richard Barry
7fc04bfebe Change name of the CEC and MEC directory to CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC as it is also applicable to the MEC5105 part. 2017-04-04 20:16:37 +00:00
Richard Barry
464c2660ad Updates to the Cortex-M tickless idle code to reduce clock slippage.
Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
2017-03-28 03:13:48 +00:00
Richard Barry
7ee26c1b5e Enable button interrupts in the MSP432 demos in order to test code paths when an MCU exits low power mode for a reason other than a tick interrupt. 2017-03-28 03:12:20 +00:00
Richard Barry
aa810cb926 Ensure vTaskGetInfo() sets the sate of the currently running task to eRunning - previously it was set to eReady. 2017-03-27 20:31:03 +00:00
Richard Barry
3b2bbcb56a Maintenance on MSP432 demo. 2017-03-09 02:13:40 +00:00
Richard Barry
ad5659e93d Housekeeping check-in, no code changes. 2017-03-08 22:19:14 +00:00
Richard Barry
34b194150e Add CEC and MEC 17xx demo that is completely statically allocated. NOT FULLY TESTED YET. 2017-03-08 18:38:02 +00:00
Richard Barry
b9fe24962e Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive. 2017-03-07 04:06:10 +00:00
Richard Barry
c3acc441ac Introduce vTaskInternalSetTimeOutState() which does not have a critical section, and add a critical section to the public version of the same. 2017-02-24 02:16:54 +00:00
Richard Barry
9b213e8c34 Add SimpleLink CC3220SF demo. 2017-02-24 02:12:27 +00:00
Richard Barry
67def3c14b Update Reliance Edge fail safe file system to the latest version. 2017-01-24 00:20:35 +00:00
Richard Barry
8d041c8e21 Update version number in preparation for maintenance release. 2017-01-22 05:28:13 +00:00
Richard Barry
979e41c9da Update UltraScale R5 hardware definition and BSP for 2016.4 SDK tools. 2017-01-21 21:59:25 +00:00
Richard Barry
ff55eb920c Update Zynq MPSoC hardware definition and BSP files to be those shipped with the 2016.4 SDK. 2017-01-19 16:33:13 +00:00
Richard Barry
992a3c8c71 Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
2017-01-19 04:11:21 +00:00
Richard Barry
6ffaa6f018 Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
2017-01-18 18:33:48 +00:00
Richard Barry
d67dcf9c74 Enhanced priority dis-inheritance functionality in the case where a task that caused another task to inherit its priority times out before obtain a mutex.
Added test code to GenQTest to test the new priority dis-inheritance functionality.
Allow the default names given to the Idle and Timer tasks to be overwridden by definitions in FreeRTOSConfig.h.
2017-01-16 03:58:51 +00:00
Richard Barry
883541bc8e Rename the CORTEX_MPU_MEC17xx_KEIL_GCC directory to CORTEX_MPU_CEC_MEC_Keil_GCC as it is also applicable to the CEC17xx parts. 2017-01-09 21:29:42 +00:00
Richard Barry
c882141175 Change how volatile is used in some of the standard demos to remove compiler warnings in the latest GCC versions. 2017-01-04 05:07:12 +00:00
Richard Barry
ca9edf3531 Increase the priority of the Windows threads used by the FreeRTOS Windows port, and, because the threads have high priority and run on the same core, prevent the port running on single core hosts so as to avoid locking up the host. 2017-01-04 04:48:22 +00:00
Richard Barry
f98b675671 Add MPU project for multiple MEC17xx devices. 2016-12-11 22:56:30 +00:00
Richard Barry
225f13bac2 Update TaskNotify.c to test the condition where a direct to task notification is sent to a suspended task.
Introduce configSTACK_DEPTH_TYPE so the application writer change the type used to specify a stack size from uint16_t to whatever they like.  Defaults to uint16_t if not defined.
Introduce configINITIAL_TICK_COUNT to allow users to start the tick count at something other than 0.  Used for testing, but overflows can be better tested by setting configUSE_16_BIT_TICKS to 1.
Split xQueueGenericReceive() into xQueueReceive(), xQueuePeek() and xQueueSemaphoreTake() as the first step in refactoring xQueueGenericReceive().
Add Cortex-M3 port layer for Code Composer Studio - previously there was only a Cortex-M4F port.
Introduce configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING() to allow applications to prevent portSUPPRESS_TICKS_AND_SLEEP() being called.  Previously the portPRE_SLEEP_PROCESSING() macro could only be used to abort entry into sleep time after clocks had been re-programmed for the distant wake time.
2016-11-25 21:07:56 +00:00
Richard Barry
7fcc976248 Update version of Reliance Edge. 2016-11-21 04:30:49 +00:00
Richard Barry
7cce089e40 Add support for statically allocated memory protected tasks - previously only dynamically allocated tasks could be memory protected. 2016-09-20 13:54:28 +00:00
Richard Barry
5c75e5a38a Correct the definition of StaticTask_t and add additional configASSERT() statements to catch future errors. 2016-09-14 08:21:24 +00:00
Richard Barry
40201bc253 Introduce configRECORD_STACK_HIGH_ADDRESS, which when set will result in both limits of the stack being saved in the TCB to allow enhanced debug capabilities.
Introduce configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H, which allows a user provided header file to be included at the bottom of the tasks.c source file, which can add user functions and access file scope data.
Replace global on/off switches used for lint errors with save/restore switches.
2016-09-04 15:46:34 +00:00
Richard Barry
f11912c5de Clean up lint errors. 2016-08-16 13:44:30 +00:00
Richard Barry
75ffac21d7 Changes to core code and port layer:
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
      bit settings.
    + Clear the 'control' register before starting ARM Cortex-M4F ports in case
      the FPU is used before the scheduler is started.  This just saves a few
      bytes on the main stack as it prevents space being left for a later save
      of FPU registers.
    + Added xSemaphoreGetMutexHolderFromISR().
    + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
2016-08-16 11:38:58 +00:00
Richard Barry
bdbf347c22 Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry. 2016-06-28 10:39:25 +00:00
Richard Barry
c296e2cff8 Improvements to the Cortex-M ports:
- Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler).
- Ensure atomic operations are thread safe by executing clrex in the context switch.
2016-06-27 13:13:05 +00:00
Richard Barry
6c975cd46a Final check in before tagging V9.0.0. 2016-05-25 11:47:42 +00:00
Richard Barry
2bd7884ace Prepare for V9.0.0 release:
+ Change version number from V9.0.0rc2 to V9.0.0.
2016-05-20 18:05:46 +00:00
Richard Barry
e23eca901d Preparing for V9.0.0 formal release:
+ Update various projects to use the latest versions of their build tools.
2016-05-20 12:18:59 +00:00
Richard Barry
0063b29cdf Prepare for V9.0.0 release.
+ Set flash wait states on MSP432 demos.
+ Remove use of obsolete IO library in PIC32 demos.
+ Remove obsolete item left on stack of first task to run in the Cortex-M0 ports.
+ Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
2016-05-19 13:28:12 +00:00
Richard Barry
e10647f9c0 Increase the test coverage of the GCC MPU demo that runs in the Keil simulator.
Add an MPU demo that uses the Keil simulator that also uses the Keil compiler.
Correct a few version numbers for files recently added to the repository.
2016-05-18 19:51:14 +00:00
Richard Barry
ee9cd40b6d Add GCC ARM Cortex-M4F MPU port.
Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.
2016-05-18 10:41:28 +00:00
Richard Barry
fedb98c5f6 Recreated MicroBlaze example using Vivado 2016.1 - the Microblaze project is still a work in progress - not yet fully functional. 2016-05-10 14:05:22 +00:00
Richard Barry
501be60574 Update the Microblaze hardware design and BSP to the latest IP and tool versions. 2016-05-09 15:55:51 +00:00