Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version.
This commit is contained in:
Richard Barry
parent
0f85ead175
commit
b080f13543
@ -86,6 +86,16 @@ task.h is included from an application file. */
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the same
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as the core. */
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#define portNVIC_SYSTICK_CLK ( 0 )
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#endif
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/* Constants required to access and manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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@ -110,7 +120,6 @@ task.h is included from an application file. */
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#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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/* Constants required to access and manipulate the SysTick. */
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#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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#define portNVIC_SYSTICK_INT ( 0x00000002UL )
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#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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@ -139,16 +148,6 @@ task.h is included from an application file. */
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* Each task maintains its own interrupt status in the critical nesting
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variable. Note this is not saved as part of the task context as context
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switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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*/
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static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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/*
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* Configure a number of standard MPU regions that are used by all tasks.
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*/
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@ -168,6 +167,13 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVI
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*/
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BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void );
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/*
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* Standard FreeRTOS exception handlers.
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*/
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@ -186,6 +192,13 @@ static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVIL
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*/
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static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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/*-----------------------------------------------------------*/
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/* Each task maintains its own interrupt status in the critical nesting
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variable. Note this is not saved as part of the task context as context
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switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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* FreeRTOS API functions are not called from interrupts that have been assigned
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@ -243,7 +256,7 @@ void vPortSVCHandler( void )
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" mrs r0, psp \n"
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#endif
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" b %0 \n"
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::"i"(prvSVCHandler):"r0"
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::"i"(prvSVCHandler):"r0", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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@ -266,7 +279,7 @@ uint8_t ucSVCNumber;
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but do ensure the code is completely
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within the specified behaviour for the
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architecture. */
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__asm volatile( "dsb" );
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__asm volatile( "dsb" ::: "memory" );
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__asm volatile( "isb" );
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break;
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@ -276,7 +289,7 @@ uint8_t ucSVCNumber;
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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:::"r1"
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::: "r1", "memory"
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);
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break;
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@ -357,6 +370,24 @@ BaseType_t xPortStartScheduler( void )
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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@ -379,7 +410,7 @@ BaseType_t xPortStartScheduler( void )
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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@ -396,7 +427,7 @@ BaseType_t xPortStartScheduler( void )
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" isb \n"
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" svc %0 \n" /* System call to start first task. */
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" nop \n"
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:: "i" (portSVC_START_SCHEDULER) );
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:: "i" (portSVC_START_SCHEDULER) : "memory" );
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/* Should not get here! */
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return 0;
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@ -454,6 +485,8 @@ void xPortPendSVHandler( void )
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" stmdb sp!, {r3, r14} \n"
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" mov r0, %0 \n"
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" msr basepri, r0 \n"
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" dsb \n"
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" isb \n"
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" bl vTaskSwitchContext \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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@ -499,15 +532,15 @@ uint32_t ulDummy;
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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static void prvSetupTimerInterrupt( void )
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__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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{
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/* Reset the SysTick timer. */
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/* Stop and clear the SysTick. */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
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}
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/*-----------------------------------------------------------*/
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@ -609,7 +642,7 @@ BaseType_t xPortRaisePrivilege( void )
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" svcne %0 \n" /* Switch to privileged. */
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" moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
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" bx lr \n"
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:: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
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:: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
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);
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return 0;
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@ -720,7 +753,7 @@ uint32_t ul;
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uint8_t ucCurrentPriority;
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/* Obtain the number of the currently executing interrupt. */
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__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
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/* Is the interrupt number a user defined interrupt? */
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if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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@ -88,6 +88,16 @@ task.h is included from an application file. */
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the same
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as the core. */
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#define portNVIC_SYSTICK_CLK ( 0 )
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#endif
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/* Constants required to access and manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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@ -112,7 +122,6 @@ task.h is included from an application file. */
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#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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/* Constants required to access and manipulate the SysTick. */
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#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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#define portNVIC_SYSTICK_INT ( 0x00000002UL )
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#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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@ -146,16 +155,6 @@ task.h is included from an application file. */
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have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/* Each task maintains its own interrupt status in the critical nesting
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variable. Note this is not saved as part of the task context as context
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switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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*/
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static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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/*
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* Configure a number of standard MPU regions that are used by all tasks.
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*/
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@ -175,6 +174,13 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVI
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*/
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BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void );
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/*
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* Standard FreeRTOS exception handlers.
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*/
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@ -198,6 +204,13 @@ static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline ))
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*/
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static void vPortEnableVFP( void ) __attribute__ (( naked ));
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/*-----------------------------------------------------------*/
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/* Each task maintains its own interrupt status in the critical nesting
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variable. Note this is not saved as part of the task context as context
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switches can only occur when uxCriticalNesting is zero. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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* FreeRTOS API functions are not called from interrupts that have been assigned
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@ -261,7 +274,7 @@ void vPortSVCHandler( void )
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" mrs r0, psp \n"
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#endif
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" b %0 \n"
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::"i"(prvSVCHandler):"r0"
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::"i"(prvSVCHandler):"r0", "memory"
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);
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}
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/*-----------------------------------------------------------*/
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@ -284,7 +297,7 @@ uint8_t ucSVCNumber;
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but do ensure the code is completely
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within the specified behaviour for the
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architecture. */
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__asm volatile( "dsb" );
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__asm volatile( "dsb" ::: "memory" );
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__asm volatile( "isb" );
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break;
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@ -294,7 +307,7 @@ uint8_t ucSVCNumber;
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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:::"r1"
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::: "r1", "memory"
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);
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break;
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@ -414,7 +427,7 @@ BaseType_t xPortStartScheduler( void )
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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@ -425,9 +438,9 @@ BaseType_t xPortStartScheduler( void )
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/* Lazy save always. */
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*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the SVC stack
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the SVC stack
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for lazy saving of FPU registers. */
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__asm volatile(
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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@ -442,7 +455,7 @@ BaseType_t xPortStartScheduler( void )
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" isb \n"
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" svc %0 \n" /* System call to start first task. */
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" nop \n"
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:: "i" (portSVC_START_SCHEDULER) );
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:: "i" (portSVC_START_SCHEDULER) : "memory" );
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/* Should not get here! */
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return 0;
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@ -555,15 +568,15 @@ uint32_t ulDummy;
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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static void prvSetupTimerInterrupt( void )
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__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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{
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/* Clear the SysTick. */
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/* Stop and clear the SysTick. */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
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}
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/*-----------------------------------------------------------*/
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@ -680,7 +693,7 @@ BaseType_t xPortRaisePrivilege( void )
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" svcne %0 \n" /* Switch to privileged. */
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" moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
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" bx lr \n"
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:: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
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:: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
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);
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return 0;
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@ -791,7 +804,7 @@ uint32_t ul;
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uint8_t ucCurrentPriority;
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/* Obtain the number of the currently executing interrupt. */
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__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
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/* Is the interrupt number a user defined interrupt? */
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if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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