2018-09-23 11:52:23 +08:00
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/*
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* FreeRTOS Kernel V10.1.1
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* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define WORD_SIZE 8
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#elif __riscv_xlen == 32
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#define WORD_SIZE 4
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#else
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#error Assembler has not defined __riscv_xlen
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#endif
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2018-11-21 04:12:35 +08:00
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#define CONTEXT_SIZE ( 30 * WORD_SIZE )
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2018-09-23 11:52:23 +08:00
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2018-11-06 10:04:28 +08:00
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.global xPortStartFirstTask
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2018-09-23 11:52:23 +08:00
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.global vPortTrapHandler
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.extern pxCurrentTCB
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2018-11-25 04:59:07 +08:00
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.extern ulPortTrapHandler
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2018-09-23 11:52:23 +08:00
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/*-----------------------------------------------------------*/
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.align 8
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2018-11-06 10:04:28 +08:00
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xPortStartFirstTask:
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2018-11-25 04:59:07 +08:00
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la t0, vPortTrapHandler
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csrw mtvec, t0
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2018-11-21 04:12:35 +08:00
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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2018-09-23 11:52:23 +08:00
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/*-----------------------------------------------------------*/
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.align 8
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vPortTrapHandler:
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addi sp, sp, -CONTEXT_SIZE
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2018-11-19 14:01:29 +08:00
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sw x1, 1 * WORD_SIZE( sp )
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2018-09-28 01:25:17 +08:00
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sw x5, 2 * WORD_SIZE( sp )
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sw x6, 3 * WORD_SIZE( sp )
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sw x7, 4 * WORD_SIZE( sp )
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sw x8, 5 * WORD_SIZE( sp )
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sw x9, 6 * WORD_SIZE( sp )
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sw x10, 7 * WORD_SIZE( sp )
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sw x11, 8 * WORD_SIZE( sp )
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sw x12, 9 * WORD_SIZE( sp )
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sw x13, 10 * WORD_SIZE( sp )
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sw x14, 11 * WORD_SIZE( sp )
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sw x15, 12 * WORD_SIZE( sp )
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sw x16, 13 * WORD_SIZE( sp )
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sw x17, 14 * WORD_SIZE( sp )
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sw x18, 15 * WORD_SIZE( sp )
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sw x19, 16 * WORD_SIZE( sp )
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sw x20, 17 * WORD_SIZE( sp )
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sw x21, 18 * WORD_SIZE( sp )
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sw x22, 19 * WORD_SIZE( sp )
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sw x23, 20 * WORD_SIZE( sp )
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sw x24, 21 * WORD_SIZE( sp )
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sw x25, 22 * WORD_SIZE( sp )
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sw x26, 23 * WORD_SIZE( sp )
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sw x27, 24 * WORD_SIZE( sp )
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sw x28, 25 * WORD_SIZE( sp )
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sw x29, 26 * WORD_SIZE( sp )
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sw x30, 27 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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2018-11-21 04:12:35 +08:00
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * WORD_SIZE( sp )
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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2018-09-23 11:52:23 +08:00
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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2018-11-21 04:12:35 +08:00
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/*_RB_ Does stack need aligning here? */
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2018-11-25 04:59:07 +08:00
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jal ulPortTrapHandler
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2018-09-23 11:52:23 +08:00
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csrw mepc, a0
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2018-11-19 14:01:29 +08:00
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/* Save exception return address. */
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sw a0, 0( sp )
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2018-09-23 11:52:23 +08:00
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2018-11-21 04:12:35 +08:00
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next task. */
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lw t0, 0( sp )
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csrw mepc, t0
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * WORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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mret
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2018-09-28 01:25:17 +08:00
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