mirror of
https://github.com/panpaul/tiny_os
synced 2024-09-20 09:45:19 +08:00
chore: add conversion between PageError
and SysError
This commit is contained in:
parent
3f6f0ac18c
commit
d4b2f78505
@ -1,5 +1,9 @@
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use super::{cap::RawCap, Cap, KernelObject};
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use super::{cap::RawCap, Cap, KernelObject};
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use crate::{arch::layout::mmap_phys_to_virt, objects::cap::CapEntry, vspace::*};
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use crate::{
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arch::layout::{mmap_phys_to_virt, PAGE_SIZE},
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objects::cap::CapEntry,
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vspace::*,
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};
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use uapi::{
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use uapi::{
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cap::ObjectType,
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cap::ObjectType,
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error::{SysError, SysResult},
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error::{SysError, SysResult},
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@ -50,8 +54,7 @@ impl<'a> FrameCap<'a> {
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pub fn mint(ptr: PhysAddr, size: usize, attr: MapAttr, is_device: bool) -> RawCap {
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pub fn mint(ptr: PhysAddr, size: usize, attr: MapAttr, is_device: bool) -> RawCap {
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let size_bits = size.ilog2() as usize;
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let size_bits = size.ilog2() as usize;
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debug_assert!(size_bits <= FrameCap::FRAME_SIZE_BITS);
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debug_assert!(size_bits <= FrameCap::FRAME_SIZE_BITS);
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assert!(size >= PAGE_SIZE);
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// NOTE: we are not checking frame size
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let arg0 = 0
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let arg0 = 0
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| ((attr.bits() & Self::VM_RIGHT_MASK) << Self::VM_RIGHT_OFFSET)
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| ((attr.bits() & Self::VM_RIGHT_MASK) << Self::VM_RIGHT_OFFSET)
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@ -126,14 +129,10 @@ impl<'a> FrameCap<'a> {
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self.as_object_mut().fill(fill.unwrap_or(0));
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self.as_object_mut().fill(fill.unwrap_or(0));
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}
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}
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pub fn map_page<T: TableLevel>(&self, root: &mut Table<T>, vaddr: VirtAddr, attr: MapAttr) -> SysResult {
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pub fn map<T: TableLevel>(&self, root: &mut Table<T>, vaddr: VirtAddr, attr: MapAttr) -> SysResult {
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let masked_attr = attr & self.attr();
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let masked_attr = attr & self.attr();
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root.map(vaddr, self.cte.cap.get().ptr, masked_attr).map_err(|e| match e {
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root.map(vaddr, self.cte.cap.get().ptr, masked_attr)?;
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PageError::AlreadyMapped => SysError::AlreadyMapped,
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PageError::MissingEntry => SysError::MissingEntry,
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PageError::NotAligned => SysError::InvalidArgument,
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})?;
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self.set_mapped_asid(0);
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self.set_mapped_asid(0);
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self.set_mapped_vaddr(vaddr);
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self.set_mapped_vaddr(vaddr);
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@ -147,11 +146,13 @@ impl<'a> FrameCap<'a> {
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return Err(SysError::NotMapped);
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return Err(SysError::NotMapped);
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}
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}
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match root.lookup_mut(self.mapped_vaddr()) {
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match root.lookup_mut(vaddr) {
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Some(entry) if entry.is_leaf() && entry.paddr() == self.cte.cap.get().ptr => {
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Some(entry) if entry.is_leaf() && entry.paddr() == self.cte.cap.get().ptr => {
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entry.set_paddr(PhysAddr::default());
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entry.set_paddr(PhysAddr::default());
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entry.set_attr(MapAttr::empty());
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entry.set_attr(MapAttr::empty());
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// todo: sfence.vma
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self.set_mapped_asid(0);
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self.set_mapped_asid(0);
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self.set_mapped_vaddr(VirtAddr(0));
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self.set_mapped_vaddr(VirtAddr(0));
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Ok(())
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Ok(())
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@ -100,13 +100,8 @@ impl<'a> TableCap<'a> {
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array.fill(0);
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array.fill(0);
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}
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}
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pub fn map_table<T: TableLevel>(&self, root: &mut Table<T>, vaddr: VirtAddr) -> SysResult {
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pub fn map<T: TableLevel>(&self, root: &mut Table<T>, vaddr: VirtAddr) -> SysResult {
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root.map(vaddr, self.cte.cap.get().ptr, MapAttr::PAGE_TABLE)
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root.map(vaddr, self.cte.cap.get().ptr, MapAttr::PAGE_TABLE)?;
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.map_err(|e| match e {
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PageError::AlreadyMapped => SysError::AlreadyMapped,
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PageError::MissingEntry => SysError::MissingEntry,
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PageError::NotAligned => SysError::InvalidArgument,
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})?;
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self.set_mapped_asid(0);
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self.set_mapped_asid(0);
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self.set_mapped_vaddr(vaddr);
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self.set_mapped_vaddr(vaddr);
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@ -120,11 +115,13 @@ impl<'a> TableCap<'a> {
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return Err(SysError::NotMapped);
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return Err(SysError::NotMapped);
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}
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}
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match root.lookup_mut(self.mapped_vaddr()) {
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match root.lookup_mut(vaddr) {
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Some(entry) if !entry.is_leaf() && entry.paddr() == self.cte.cap.get().ptr => {
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Some(entry) if !entry.is_leaf() && entry.paddr() == self.cte.cap.get().ptr => {
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entry.set_paddr(PhysAddr::default());
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entry.set_paddr(PhysAddr::default());
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entry.set_attr(MapAttr::empty());
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entry.set_attr(MapAttr::empty());
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// todo: sfence.vma
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self.set_mapped_asid(0);
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self.set_mapped_asid(0);
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self.set_mapped_vaddr(VirtAddr(0));
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self.set_mapped_vaddr(VirtAddr(0));
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Ok(())
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Ok(())
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20
kernel/src/vspace/error.rs
Normal file
20
kernel/src/vspace/error.rs
Normal file
@ -0,0 +1,20 @@
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use uapi::error::SysError;
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#[derive(Debug)]
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pub enum PageError {
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AlreadyMapped,
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MissingEntry,
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NotAligned,
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}
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pub type PageResult<T = ()> = Result<T, PageError>;
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impl From<PageError> for SysError {
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fn from(e: PageError) -> Self {
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match e {
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PageError::AlreadyMapped => SysError::AlreadyMapped,
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PageError::MissingEntry => SysError::MissingEntry,
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PageError::NotAligned => SysError::InvalidArgument,
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}
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}
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}
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@ -1,9 +1,11 @@
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mod addr;
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mod addr;
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mod entry;
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mod entry;
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mod error;
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mod level;
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mod level;
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mod table;
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mod table;
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pub use addr::*;
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pub use addr::*;
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pub use entry::*;
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pub use entry::*;
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pub use error::*;
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pub use level::*;
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pub use level::*;
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pub use table::*;
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pub use table::*;
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@ -1,16 +1,6 @@
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use super::{MapAttr, TableLevel};
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use super::{MapAttr, PageResult, TableLevel};
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use core::fmt::Debug;
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use utils::addr::{PhysAddr, VirtAddr};
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use utils::addr::{PhysAddr, VirtAddr};
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#[derive(Debug)]
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pub enum PageError {
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AlreadyMapped,
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MissingEntry,
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NotAligned,
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}
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pub type PageResult<T = ()> = Result<T, PageError>;
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pub trait TableOps<'a, T: TableLevel> {
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pub trait TableOps<'a, T: TableLevel> {
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/// # Safety
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/// # Safety
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/// `location` must be a page-aligned virtual address and will not be dropped.
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/// `location` must be a page-aligned virtual address and will not be dropped.
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