chore: move vspace to kernel and rename features

This commit is contained in:
Paul Pan 2024-04-01 15:37:47 +08:00
parent c899797fa0
commit cc5049353a
19 changed files with 38 additions and 73 deletions

8
kernel/Cargo.lock generated
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@ -75,7 +75,6 @@ dependencies = [
"spin 0.9.8",
"static_assertions",
"uart_16550",
"vspace",
]
[[package]]
@ -236,13 +235,6 @@ version = "1.0.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
[[package]]
name = "vspace"
version = "0.1.0"
dependencies = [
"bitflags 2.5.0",
]
[[package]]
name = "x86"
version = "0.52.0"

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@ -6,14 +6,20 @@ edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[features]
default = ["arch_riscv64", "board_virt", "log_color"]
default = ["riscv.board.virt", "log_color"]
arch_riscv64 = ["vspace/riscv_sv39"]
# TODO: riscv32 not supported yet
arch_riscv32 = []
riscv = []
board_default = []
board_virt = []
"riscv.pagetable.sv32" = []
"riscv.pagetable.sv39" = []
"riscv.pagetable.sv48" = []
"riscv.pagetable.sv57" = []
"riscv.riscv64" = ["riscv", "riscv.pagetable.sv39"]
"riscv.riscv32" = ["riscv", "riscv.pagetable.sv32"]
"riscv.board.default" = ["riscv.riscv64"]
"riscv.board.virt" = ["riscv.riscv64"]
log_color = []
@ -26,7 +32,6 @@ lto = "thin"
[dependencies]
api = { path = "../api" }
vspace = { path = "../lib/vspace", default-features = false }
bitflags = "2.4"
cfg-if = "1.0"
@ -35,8 +40,10 @@ lazy_static = { version = "1.4", features = ["spin_no_std"] }
log = "0.4"
num-derive = "0.4"
num-traits = { version = "0.2", default-features = false }
riscv = { version = "0.11", features = ["s-mode"] }
sbi-rt = { version = "0.0" }
spin = "0.9"
static_assertions = "1.1"
uart_16550 = "0.3"
[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
riscv = { version = "0.11", features = ["s-mode"] }
sbi-rt = { version = "0.0" }

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@ -1,7 +1,7 @@
pub use arch::*;
// Arch Level
#[cfg(any(feature = "arch_riscv64", feature = "arch_riscv32"))]
#[cfg(feature = "riscv")]
#[path = "riscv/mod.rs"]
#[allow(clippy::module_inception)]
mod arch;

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@ -1,4 +1,4 @@
use log::{error, warn};
use log::error;
use crate::plat::lowlevel::{Hardware, LowLevel};

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@ -1,10 +1,11 @@
use cfg_if::cfg_if;
cfg_if! {
if #[cfg(feature = "board_virt")] {
if #[cfg(feature = "riscv.board.virt")] {
#[path = "board/virt/mod.rs"]
mod board;
} else {
// fall back to default
#[path = "board/default/mod.rs"]
mod board;
}
@ -19,3 +20,4 @@ mod lowlevel;
mod timer;
mod tls;
pub mod trap;
pub mod vspace;

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@ -9,9 +9,9 @@ use crate::plat::timer::{Timer, TimerOps};
use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
cfg_if! {
if #[cfg(feature = "arch_riscv64")] {
if #[cfg(feature = "riscv.riscv64")] {
core::arch::global_asm!(include_str!("./asm/trap64.S"));
} else if #[cfg(feature = "arch_riscv32")] {
} else if #[cfg(feature = "riscv.riscv32")] {
core::arch::global_asm!(include_str!("./asm/trap32.S"));
}
}

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@ -1,5 +1,5 @@
use crate::addr::{AddressOps, PhysAddr};
use crate::paging::{MapAttr, PageTableEntryOps};
use crate::vspace::addr::{AddressOps, PhysAddr};
use crate::vspace::paging::{MapAttr, PageTableEntryOps};
use bitflags::bitflags;
bitflags! {
@ -73,7 +73,7 @@ impl From<MapAttr> for PTEFlags {
}
}
#[cfg(feature = "riscv_sv39")]
#[cfg(feature = "riscv.pagetable.sv39")]
impl PhysAddr {
const PA_PPN_MASK: u64 = ((1 << Self::PPN_BITS) - 1) << Self::PG_OFFSET;
const PG_OFFSET: u64 = 12;

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@ -1,5 +1,6 @@
mod entry;
mod table;
mod utils;
pub use entry::PageTableEntry;
pub use table::PageTable;

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@ -1,11 +1,12 @@
use crate::addr::{AddressOps, PhysAddr, VirtAddr};
use crate::paging::{
MapAttr, PageError, PageResult, PageSize, PageTableEntry, PageTableEntryOps, PageTableOps,
use super::entry::PageTableEntry;
use crate::vspace::addr::{AddressOps, PhysAddr, VirtAddr};
use crate::vspace::paging::{
MapAttr, PageError, PageResult, PageSize, PageTableEntryOps, PageTableOps,
};
const PAGE_SIZE: usize = 4096;
#[cfg(feature = "riscv_sv39")]
#[cfg(feature = "riscv.pagetable.sv39")]
impl VirtAddr {
const PG_OFFSET: usize = 12;
const VPN_BITS: usize = 9;
@ -62,7 +63,7 @@ impl PageTable {
impl PageTableOps for PageTable {
type Entry = PageTableEntry;
#[cfg(feature = "riscv_sv39")]
#[cfg(feature = "riscv.pagetable.sv39")]
const MAX_PAGE_SIZE: PageSize = PageSize::Giga;
unsafe fn from_va(from: VirtAddr) -> &'static mut Self {

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@ -24,6 +24,7 @@ mod logging;
mod objects;
mod plat;
mod utils;
mod vspace;
// test infrastructure
#[cfg(test)]

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@ -1,4 +1,4 @@
use vspace::addr::PhysAddr;
use crate::vspace::addr::PhysAddr;
extern "C" {
pub type ExternSymbol;

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@ -1,4 +1,2 @@
#![no_std]
pub mod addr;
pub mod paging;

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@ -1,4 +1,4 @@
use crate::addr::PhysAddr;
use crate::vspace::addr::PhysAddr;
use bitflags::bitflags;
use core::fmt::Debug;

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@ -1,7 +1,6 @@
mod arch;
mod entry;
mod table;
pub use arch::*;
pub use crate::arch::vspace::*;
pub use entry::*;
pub use table::*;

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@ -1,5 +1,5 @@
use super::{MapAttr, PageTableEntryOps};
use crate::addr::{PhysAddr, VirtAddr};
use crate::vspace::addr::{PhysAddr, VirtAddr};
use core::fmt::Debug;
#[derive(Debug, Clone, Copy, PartialEq, Eq)]

16
lib/vspace/Cargo.lock generated
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@ -1,16 +0,0 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "bitflags"
version = "2.5.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
[[package]]
name = "vspace"
version = "0.1.0"
dependencies = [
"bitflags",
]

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@ -1,13 +0,0 @@
[package]
name = "vspace"
version = "0.1.0"
edition = "2021"
[features]
default = ["arch_riscv", "riscv_sv39"]
arch_riscv = []
riscv_sv39 = ["arch_riscv"]
[dependencies]
bitflags = "2.4"

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@ -1,7 +0,0 @@
pub use arch::*;
// Arch Level
#[cfg(feature = "arch_riscv")]
#[path = "riscv/mod.rs"]
#[allow(clippy::module_inception)]
mod arch;