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https://github.com/panpaul/tiny_os
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chore: move vspace to kernel and rename features
This commit is contained in:
parent
c899797fa0
commit
cc5049353a
8
kernel/Cargo.lock
generated
8
kernel/Cargo.lock
generated
@ -75,7 +75,6 @@ dependencies = [
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"spin 0.9.8",
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"spin 0.9.8",
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"static_assertions",
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"static_assertions",
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"uart_16550",
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"uart_16550",
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"vspace",
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]
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]
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[[package]]
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[[package]]
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@ -236,13 +235,6 @@ version = "1.0.12"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
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checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
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[[package]]
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name = "vspace"
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version = "0.1.0"
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dependencies = [
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"bitflags 2.5.0",
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]
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[[package]]
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[[package]]
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name = "x86"
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name = "x86"
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version = "0.52.0"
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version = "0.52.0"
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@ -6,14 +6,20 @@ edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[features]
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[features]
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default = ["arch_riscv64", "board_virt", "log_color"]
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default = ["riscv.board.virt", "log_color"]
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arch_riscv64 = ["vspace/riscv_sv39"]
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riscv = []
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# TODO: riscv32 not supported yet
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arch_riscv32 = []
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board_default = []
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"riscv.pagetable.sv32" = []
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board_virt = []
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"riscv.pagetable.sv39" = []
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"riscv.pagetable.sv48" = []
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"riscv.pagetable.sv57" = []
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"riscv.riscv64" = ["riscv", "riscv.pagetable.sv39"]
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"riscv.riscv32" = ["riscv", "riscv.pagetable.sv32"]
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"riscv.board.default" = ["riscv.riscv64"]
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"riscv.board.virt" = ["riscv.riscv64"]
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log_color = []
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log_color = []
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@ -26,7 +32,6 @@ lto = "thin"
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[dependencies]
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[dependencies]
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api = { path = "../api" }
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api = { path = "../api" }
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vspace = { path = "../lib/vspace", default-features = false }
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bitflags = "2.4"
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bitflags = "2.4"
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cfg-if = "1.0"
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cfg-if = "1.0"
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@ -35,8 +40,10 @@ lazy_static = { version = "1.4", features = ["spin_no_std"] }
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log = "0.4"
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log = "0.4"
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num-derive = "0.4"
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num-derive = "0.4"
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num-traits = { version = "0.2", default-features = false }
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num-traits = { version = "0.2", default-features = false }
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riscv = { version = "0.11", features = ["s-mode"] }
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sbi-rt = { version = "0.0" }
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spin = "0.9"
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spin = "0.9"
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static_assertions = "1.1"
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static_assertions = "1.1"
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uart_16550 = "0.3"
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uart_16550 = "0.3"
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[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
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riscv = { version = "0.11", features = ["s-mode"] }
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sbi-rt = { version = "0.0" }
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@ -1,7 +1,7 @@
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pub use arch::*;
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pub use arch::*;
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// Arch Level
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// Arch Level
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#[cfg(any(feature = "arch_riscv64", feature = "arch_riscv32"))]
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#[cfg(feature = "riscv")]
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#[path = "riscv/mod.rs"]
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#[path = "riscv/mod.rs"]
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#[allow(clippy::module_inception)]
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#[allow(clippy::module_inception)]
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mod arch;
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mod arch;
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@ -1,4 +1,4 @@
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use log::{error, warn};
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use log::error;
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use crate::plat::lowlevel::{Hardware, LowLevel};
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use crate::plat::lowlevel::{Hardware, LowLevel};
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@ -1,10 +1,11 @@
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use cfg_if::cfg_if;
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use cfg_if::cfg_if;
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cfg_if! {
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cfg_if! {
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if #[cfg(feature = "board_virt")] {
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if #[cfg(feature = "riscv.board.virt")] {
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#[path = "board/virt/mod.rs"]
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#[path = "board/virt/mod.rs"]
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mod board;
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mod board;
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} else {
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} else {
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// fall back to default
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#[path = "board/default/mod.rs"]
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#[path = "board/default/mod.rs"]
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mod board;
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mod board;
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}
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}
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@ -19,3 +20,4 @@ mod lowlevel;
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mod timer;
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mod timer;
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mod tls;
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mod tls;
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pub mod trap;
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pub mod trap;
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pub mod vspace;
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@ -9,9 +9,9 @@ use crate::plat::timer::{Timer, TimerOps};
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use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
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use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
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cfg_if! {
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cfg_if! {
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if #[cfg(feature = "arch_riscv64")] {
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if #[cfg(feature = "riscv.riscv64")] {
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core::arch::global_asm!(include_str!("./asm/trap64.S"));
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core::arch::global_asm!(include_str!("./asm/trap64.S"));
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} else if #[cfg(feature = "arch_riscv32")] {
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} else if #[cfg(feature = "riscv.riscv32")] {
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core::arch::global_asm!(include_str!("./asm/trap32.S"));
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core::arch::global_asm!(include_str!("./asm/trap32.S"));
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}
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}
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}
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}
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@ -1,5 +1,5 @@
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use crate::addr::{AddressOps, PhysAddr};
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use crate::vspace::addr::{AddressOps, PhysAddr};
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use crate::paging::{MapAttr, PageTableEntryOps};
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use crate::vspace::paging::{MapAttr, PageTableEntryOps};
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use bitflags::bitflags;
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use bitflags::bitflags;
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bitflags! {
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bitflags! {
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@ -73,7 +73,7 @@ impl From<MapAttr> for PTEFlags {
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}
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}
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}
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}
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#[cfg(feature = "riscv_sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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impl PhysAddr {
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impl PhysAddr {
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const PA_PPN_MASK: u64 = ((1 << Self::PPN_BITS) - 1) << Self::PG_OFFSET;
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const PA_PPN_MASK: u64 = ((1 << Self::PPN_BITS) - 1) << Self::PG_OFFSET;
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const PG_OFFSET: u64 = 12;
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const PG_OFFSET: u64 = 12;
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@ -1,5 +1,6 @@
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mod entry;
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mod entry;
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mod table;
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mod table;
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mod utils;
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pub use entry::PageTableEntry;
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pub use entry::PageTableEntry;
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pub use table::PageTable;
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pub use table::PageTable;
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@ -1,11 +1,12 @@
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use crate::addr::{AddressOps, PhysAddr, VirtAddr};
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use super::entry::PageTableEntry;
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use crate::paging::{
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use crate::vspace::addr::{AddressOps, PhysAddr, VirtAddr};
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MapAttr, PageError, PageResult, PageSize, PageTableEntry, PageTableEntryOps, PageTableOps,
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use crate::vspace::paging::{
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MapAttr, PageError, PageResult, PageSize, PageTableEntryOps, PageTableOps,
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};
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};
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const PAGE_SIZE: usize = 4096;
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const PAGE_SIZE: usize = 4096;
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#[cfg(feature = "riscv_sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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impl VirtAddr {
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impl VirtAddr {
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const PG_OFFSET: usize = 12;
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const PG_OFFSET: usize = 12;
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const VPN_BITS: usize = 9;
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const VPN_BITS: usize = 9;
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@ -62,7 +63,7 @@ impl PageTable {
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impl PageTableOps for PageTable {
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impl PageTableOps for PageTable {
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type Entry = PageTableEntry;
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type Entry = PageTableEntry;
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#[cfg(feature = "riscv_sv39")]
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#[cfg(feature = "riscv.pagetable.sv39")]
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const MAX_PAGE_SIZE: PageSize = PageSize::Giga;
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const MAX_PAGE_SIZE: PageSize = PageSize::Giga;
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unsafe fn from_va(from: VirtAddr) -> &'static mut Self {
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unsafe fn from_va(from: VirtAddr) -> &'static mut Self {
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@ -24,6 +24,7 @@ mod logging;
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mod objects;
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mod objects;
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mod plat;
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mod plat;
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mod utils;
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mod utils;
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mod vspace;
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// test infrastructure
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// test infrastructure
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#[cfg(test)]
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#[cfg(test)]
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@ -1,4 +1,4 @@
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use vspace::addr::PhysAddr;
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use crate::vspace::addr::PhysAddr;
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extern "C" {
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extern "C" {
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pub type ExternSymbol;
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pub type ExternSymbol;
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@ -1,4 +1,2 @@
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#![no_std]
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pub mod addr;
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pub mod addr;
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pub mod paging;
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pub mod paging;
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@ -1,4 +1,4 @@
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use crate::addr::PhysAddr;
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use crate::vspace::addr::PhysAddr;
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use bitflags::bitflags;
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use bitflags::bitflags;
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use core::fmt::Debug;
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use core::fmt::Debug;
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@ -1,7 +1,6 @@
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mod arch;
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mod entry;
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mod entry;
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mod table;
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mod table;
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pub use arch::*;
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pub use crate::arch::vspace::*;
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pub use entry::*;
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pub use entry::*;
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pub use table::*;
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pub use table::*;
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@ -1,5 +1,5 @@
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use super::{MapAttr, PageTableEntryOps};
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use super::{MapAttr, PageTableEntryOps};
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use crate::addr::{PhysAddr, VirtAddr};
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use crate::vspace::addr::{PhysAddr, VirtAddr};
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use core::fmt::Debug;
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use core::fmt::Debug;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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16
lib/vspace/Cargo.lock
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16
lib/vspace/Cargo.lock
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@ -1,16 +0,0 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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version = 3
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[[package]]
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name = "bitflags"
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version = "2.5.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
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[[package]]
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name = "vspace"
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version = "0.1.0"
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dependencies = [
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"bitflags",
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]
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@ -1,13 +0,0 @@
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[package]
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name = "vspace"
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version = "0.1.0"
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edition = "2021"
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[features]
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default = ["arch_riscv", "riscv_sv39"]
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arch_riscv = []
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riscv_sv39 = ["arch_riscv"]
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[dependencies]
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bitflags = "2.4"
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pub use arch::*;
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// Arch Level
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#[cfg(feature = "arch_riscv")]
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#[path = "riscv/mod.rs"]
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#[allow(clippy::module_inception)]
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mod arch;
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