feat: record time ticks

kernel/src/arch/riscv/timer.rs

@@ -13,7 +13,7 @@ impl TimerOps for Timer {
 
         // enable timer interrupt and set next tick
         unsafe { riscv::register::sie::set_stimer() }
-        Self::tick();
+        Self::set_next();
         info!("[Timer] begin to tick");
     }
 
@@ -21,7 +21,7 @@ impl TimerOps for Timer {
         riscv::register::time::read64()
     }
 
-    fn tick() {
+    fn set_next() {
         sbi_rt::set_timer(Self::read_cycle() + TIMER_TICKS);
     }
 }

kernel/src/arch/riscv/trap.rs

@@ -41,6 +41,8 @@ fn trap_handler(tf: &mut TrapContext, from_kernel: bool) {
 
     match scause.cause() {
         T::Interrupt(I::SupervisorTimer) => {
+            Timer::do_tick();
+
             if !from_kernel {
                 SCHEDULER.schedule()
             }
@@ -61,7 +63,7 @@ fn trap_handler(tf: &mut TrapContext, from_kernel: bool) {
         _ => panic_fatal!("Unhandled Trap"),
     }
 
-    Timer::tick();
+    Timer::set_next();
     trace!("[Trap] exiting...");
 }
 

kernel/src/plat/timer.rs

@@ -1,7 +1,16 @@
-pub struct Timer;
+use core::sync::atomic::{AtomicU64, Ordering};
+
+#[thread_local]
+pub static CURRENT_TICK: AtomicU64 = AtomicU64::new(0);
+
+pub struct Timer
+where Self: TimerOps;
 
 pub trait TimerOps {
     fn init();
     fn read_cycle() -> u64;
-    fn tick();
+    fn set_next();
+    fn do_tick() {
+        CURRENT_TICK.fetch_add(1, Ordering::Relaxed);
+    }
 }