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fix: support riscv32 build

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This commit is contained in:
Paul Pan 2023-09-23 21:43:39 +08:00
parent 9628d32d54
commit 9c95cb4f5e
3 changed files with 84 additions and 78 deletions
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16
build.rs
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@ -1,18 +1,24 @@
fn main() {
println!("cargo:rerun-if-changed=build.rs");
struct TargetConfiguration {
struct TargetConfig {
target: &'static str,
lds: &'static str,
}
const TARGET_CONFIGURATIONS: &[TargetConfiguration] = &[TargetConfiguration {
const TARGET_LDS: &[TargetConfig] = &[
TargetConfig {
target: "riscv64",
lds: "src/arch/riscv/linker64.ld",
}];
lds: "src/arch/riscv/linker.ld",
},
TargetConfig {
target: "riscv32",
lds: "src/arch/riscv/linker.ld",
},
];
let target = std::env::var("TARGET").unwrap();
for cfg in TARGET_CONFIGURATIONS {
for cfg in TARGET_LDS {
if target.starts_with(cfg.target) {
println!("cargo:rerun-if-changed={}", cfg.lds);
println!("cargo:rustc-link-arg=-T{}", cfg.lds);

144
src/arch/riscv/asm/trap32.S
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@ -12,53 +12,53 @@ __user2kernel:
li a0, {TRAPFRAME} # TRAPFRAME will be mapped to the same virtual address
# save GPRs
sd ra, 0(a0)
sd sp, 4(a0)
sd gp, 8(a0)
sd tp, 12(a0)
sd t0, 16(a0)
sd t1, 20(a0)
sd t2, 24(a0)
sd s0, 28(a0)
sd s1, 32(a0)
#sd a0, 36(a0)
sd a1, 40(a0)
sd a2, 44(a0)
sd a3, 48(a0)
sd a4, 52(a0)
sd a5, 56(a0)
sd a6, 60(a0)
sd a7, 64(a0)
sd s2, 68(a0)
sd s3, 72(a0)
sd s4, 76(a0)
sd s5, 80(a0)
sd s6, 84(a0)
sd s7, 88(a0)
sd s8, 92(a0)
sd s9, 96(a0)
sd s10, 100(a0)
sd s11, 104(a0)
sd t3, 108(a0)
sd t4, 112(a0)
sd t5, 116(a0)
sd t6, 120(a0)
sw ra, 0(a0)
sw sp, 4(a0)
sw gp, 8(a0)
sw tp, 12(a0)
sw t0, 16(a0)
sw t1, 20(a0)
sw t2, 24(a0)
sw s0, 28(a0)
sw s1, 32(a0)
#sw a0, 36(a0)
sw a1, 40(a0)
sw a2, 44(a0)
sw a3, 48(a0)
sw a4, 52(a0)
sw a5, 56(a0)
sw a6, 60(a0)
sw a7, 64(a0)
sw s2, 68(a0)
sw s3, 72(a0)
sw s4, 76(a0)
sw s5, 80(a0)
sw s6, 84(a0)
sw s7, 88(a0)
sw s8, 92(a0)
sw s9, 96(a0)
sw s10, 100(a0)
sw s11, 104(a0)
sw t3, 108(a0)
sw t4, 112(a0)
sw t5, 116(a0)
sw t6, 120(a0)
# save a0
csrr t0, sscratch
sd t0, 36(a0)
sw t0, 36(a0)
# save user epc / sstatus
csrr t0, sepc
csrr t1, sstatus
sd t0, 124(a0)
sd t1, 128(a0)
sw t0, 124(a0)
sw t1, 128(a0)
# restore kernel env
ld sp, 132(a0) # kernel sp
ld tp, 136(a0) # kernel tp
ld t0, 140(a0) # trap handler
ld t1, 144(a0) # page table
lw sp, 132(a0) # kernel sp
lw tp, 136(a0) # kernel tp
lw t0, 140(a0) # trap handler
lw t1, 144(a0) # page table
# load kernel page table
sfence.vma zero, zero
@ -78,44 +78,44 @@ __kernel2user:
li a0, {TRAPFRAME}
# restore user epc / sstatus
ld t0, 124(a0)
ld t1, 128(a0)
lw t0, 124(a0)
lw t1, 128(a0)
csrw sepc, t0
csrw sstatus, t1
# restore GPRs
ld ra, 0(a0)
ld sp, 4(a0)
ld gp, 8(a0)
ld tp, 12(a0)
ld t0, 16(a0)
ld t1, 20(a0)
ld t2, 24(a0)
ld s0, 28(a0)
ld s1, 32(a0)
#ld a0, 36(a0)
ld a1, 40(a0)
ld a2, 44(a0)
ld a3, 48(a0)
ld a4, 52(a0)
ld a5, 56(a0)
ld a6, 60(a0)
ld a7, 64(a0)
ld s2, 68(a0)
ld s3, 72(a0)
ld s4, 76(a0)
ld s5, 80(a0)
ld s6, 84(a0)
ld s7, 88(a0)
ld s8, 92(a0)
ld s9, 96(a0)
ld s10, 100(a0)
ld s11, 104(a0)
ld t3, 108(a0)
ld t4, 112(a0)
ld t5, 116(a0)
ld t6, 120(a0)
ld a0, 36(a0)
lw ra, 0(a0)
lw sp, 4(a0)
lw gp, 8(a0)
lw tp, 12(a0)
lw t0, 16(a0)
lw t1, 20(a0)
lw t2, 24(a0)
lw s0, 28(a0)
lw s1, 32(a0)
#lw a0, 36(a0)
lw a1, 40(a0)
lw a2, 44(a0)
lw a3, 48(a0)
lw a4, 52(a0)
lw a5, 56(a0)
lw a6, 60(a0)
lw a7, 64(a0)
lw s2, 68(a0)
lw s3, 72(a0)
lw s4, 76(a0)
lw s5, 80(a0)
lw s6, 84(a0)
lw s7, 88(a0)
lw s8, 92(a0)
lw s9, 96(a0)
lw s10, 100(a0)
lw s11, 104(a0)
lw t3, 108(a0)
lw t4, 112(a0)
lw t5, 116(a0)
lw t6, 120(a0)
lw a0, 36(a0)
# go back to usermode
sret

0
src/arch/riscv/linker64.ld → src/arch/riscv/linker.ld
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