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https://github.com/panpaul/tiny_os
synced 2024-09-20 09:45:19 +08:00
fix: some parts of physical memory is not mapped
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parent
1d026d8053
commit
774cabc513
@ -96,14 +96,40 @@ pub unsafe fn setup_kernel_paging<const N: usize>(allocator: &mut RamBlock<N>) {
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// map 4 GiB physical memory
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// TODO: walk fdt to get all memory region?
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for addr in (0..(3 * GIB - 1 + GIB)).step_by(TableLevel::Level1.level_size()) {
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let phys_addr = PhysAddr(addr);
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map(
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mmap_phys_to_virt(phys_addr),
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phys_addr,
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MapAttr::READABLE | MapAttr::WRITABLE,
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TableLevel::Level1,
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);
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{
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#[cfg(feature = "legacy")]
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let level = TableLevel::Level1;
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#[cfg(not(feature = "legacy"))]
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let level = TableLevel::Level2;
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let addr_end = PhysAddr(3 * GIB - 1 + GIB);
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let mut phys_addr = PhysAddr(0);
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let mut map_level = level;
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while phys_addr < addr_end {
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let ok = map(
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kernel_phys_to_virt(phys_addr),
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phys_addr,
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MapAttr::READABLE | MapAttr::WRITABLE,
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map_level,
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);
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if ok || map_level.next().is_none() {
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// map success or reach the end, move to next region
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phys_addr += map_level.level_size();
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// check whether we could raise the level
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if let Some(prv) = map_level.previous()
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&& prv.is_aligned(phys_addr)
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{
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map_level = prv;
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}
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continue;
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}
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// already mapped, try smaller level
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map_level = map_level.next().unwrap();
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}
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}
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riscv::register::satp::set(riscv::register::satp::Mode::Sv39, 0, root_pt.to_ppn());
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@ -25,6 +25,18 @@ impl TableLevel {
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Self::Level4 => Some(Self::Level3),
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}
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}
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pub fn previous(&self) -> Option<Self> {
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match self {
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Self::Level0 => Some(Self::Level1),
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Self::Level1 => Some(Self::Level2),
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Self::Level2 => Some(Self::Level3),
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#[cfg(not(feature = "legacy"))]
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Self::Level3 => Some(Self::Level4),
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#[cfg(not(feature = "legacy"))]
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Self::Level4 => None,
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}
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}
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}
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#[derive(Debug)]
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