feat: use tp as hart_id

src/arch/riscv/asm/trap_common.S

@@ -87,7 +87,7 @@ __trap_from_user_next:
 	LD_SP	s10, 10
 	LD_SP	s11, 11
 	LD_SP	ra,  12
-	LD_SP	tp,  13 # not callee-saved
+	LD_SP	tp,  13 # hartid
 	addi	sp,  sp, 14*XLENB
 	# return from switch_to_user
 	ret
@@ -110,7 +110,7 @@ switch_to_user:
 	SD_SP	s10, 10
 	SD_SP	s11, 11
 	SD_SP	ra,  12
-	SD_SP	tp,  13 # not callee-saved
+	SD_SP	tp,  13 # not callee-saved, but used in kernel to save hartid
 
 	# switch to user context
 	mv	t0, sp

src/arch/riscv/cpu.rs

@@ -0,0 +1,9 @@
+pub fn get_hart_id() -> usize {
+    let id;
+    unsafe { core::arch::asm!("mv {}, tp", out(reg) id) }
+    id
+}
+
+pub fn set_hart_id(id: usize) {
+    unsafe { core::arch::asm!("mv tp, {}", in(reg) id) }
+}

src/arch/riscv/entry.rs

@@ -1,5 +1,7 @@
 use core::ptr::addr_of_mut;
 
+use crate::arch::cpu::set_hart_id;
+
 #[naked]
 #[no_mangle]
 #[link_section = ".text.entry"]
@@ -11,9 +13,6 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! {
     #[link_section = ".bss.boot_stack"]
     static mut STACK: [u8; STACK_SIZE] = [0u8; STACK_SIZE];
 
-    // TODO: consider about relocations
-    // TODO: should we emit `la gp, __global_pointer$` here?
-
     core::arch::asm!(
     "csrw sie, 0",
     "csrw sip, 0",
@@ -29,7 +28,8 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! {
 extern "C" fn pre_main(hart_id: usize, device_tree_addr: usize) -> ! {
     // TODO: multiboot
 
-    unsafe { zero_bss() }
+    zero_bss();
+    set_hart_id(hart_id);
 
     // TODO: initialize page table
 
@@ -42,9 +42,11 @@ extern "C" {
 }
 
 #[inline(always)]
-unsafe fn zero_bss() {
-    let cur = addr_of_mut!(__boot_stack_end) as *mut u8;
-    let end = addr_of_mut!(__bss_end) as *mut u8;
+fn zero_bss() {
+    unsafe {
+        let cur = addr_of_mut!(__boot_stack_end);
+        let end = addr_of_mut!(__bss_end);
 
         core::slice::from_raw_parts_mut(cur, end.offset_from(cur) as usize).fill(0);
+    }
 }

src/arch/riscv/mod.rs

@@ -2,6 +2,7 @@
 #[path = "board/virt/mod.rs"]
 mod board;
 
+pub mod cpu;
 pub mod entry;
 pub mod io;
 pub mod layout;

src/arch/riscv/trap.rs

@@ -1,6 +1,7 @@
 use log::trace;
 use riscv::register::scause::{Interrupt as I, Trap as T};
 
+use crate::arch::cpu::get_hart_id;
 use crate::plat::timer::{Timer, TimerOps};
 use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
 
@@ -20,7 +21,11 @@ extern "C" {
 #[no_mangle]
 pub extern "C" fn trap_handler(tf: &mut TrapContext) {
     let scause = riscv::register::scause::read();
-    trace!("[Interrupt] scause: {:?}", scause.cause());
+    trace!(
+        "[Interrupt] cpu@{} scause: {:?}",
+        get_hart_id(),
+        scause.cause()
+    );
     match scause.cause() {
         T::Interrupt(I::SupervisorTimer) => {
             // TODO: refactor this