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https://github.com/panpaul/tiny_os
synced 2024-09-20 09:45:19 +08:00
feat: use tp as hart_id
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@ -87,7 +87,7 @@ __trap_from_user_next:
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LD_SP s10, 10
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LD_SP s11, 11
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LD_SP ra, 12
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LD_SP tp, 13 # not callee-saved
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LD_SP tp, 13 # hartid
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addi sp, sp, 14*XLENB
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# return from switch_to_user
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ret
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@ -110,7 +110,7 @@ switch_to_user:
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SD_SP s10, 10
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SD_SP s11, 11
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SD_SP ra, 12
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SD_SP tp, 13 # not callee-saved
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SD_SP tp, 13 # not callee-saved, but used in kernel to save hartid
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# switch to user context
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mv t0, sp
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9
src/arch/riscv/cpu.rs
Normal file
9
src/arch/riscv/cpu.rs
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@ -0,0 +1,9 @@
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pub fn get_hart_id() -> usize {
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let id;
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unsafe { core::arch::asm!("mv {}, tp", out(reg) id) }
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id
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}
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pub fn set_hart_id(id: usize) {
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unsafe { core::arch::asm!("mv tp, {}", in(reg) id) }
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}
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@ -1,5 +1,7 @@
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use core::ptr::addr_of_mut;
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use crate::arch::cpu::set_hart_id;
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#[naked]
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#[no_mangle]
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#[link_section = ".text.entry"]
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@ -11,25 +13,23 @@ unsafe extern "C" fn _start(hart_id: usize, device_tree_addr: usize) -> ! {
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#[link_section = ".bss.boot_stack"]
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static mut STACK: [u8; STACK_SIZE] = [0u8; STACK_SIZE];
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// TODO: consider about relocations
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// TODO: should we emit `la gp, __global_pointer$` here?
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core::arch::asm!(
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"csrw sie, 0",
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"csrw sip, 0",
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"la sp, {stack} + {stack_size}",
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"j {main}",
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stack_size = const STACK_SIZE,
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stack = sym STACK,
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main = sym pre_main,
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options(noreturn),
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stack_size = const STACK_SIZE,
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stack = sym STACK,
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main = sym pre_main,
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options(noreturn),
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)
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}
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extern "C" fn pre_main(hart_id: usize, device_tree_addr: usize) -> ! {
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// TODO: multiboot
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unsafe { zero_bss() }
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zero_bss();
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set_hart_id(hart_id);
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// TODO: initialize page table
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@ -42,9 +42,11 @@ extern "C" {
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}
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#[inline(always)]
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unsafe fn zero_bss() {
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let cur = addr_of_mut!(__boot_stack_end) as *mut u8;
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let end = addr_of_mut!(__bss_end) as *mut u8;
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fn zero_bss() {
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unsafe {
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let cur = addr_of_mut!(__boot_stack_end);
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let end = addr_of_mut!(__bss_end);
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core::slice::from_raw_parts_mut(cur, end.offset_from(cur) as usize).fill(0);
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core::slice::from_raw_parts_mut(cur, end.offset_from(cur) as usize).fill(0);
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}
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}
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@ -2,6 +2,7 @@
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#[path = "board/virt/mod.rs"]
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mod board;
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pub mod cpu;
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pub mod entry;
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pub mod io;
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pub mod layout;
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@ -1,6 +1,7 @@
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use log::trace;
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use riscv::register::scause::{Interrupt as I, Trap as T};
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use crate::arch::cpu::get_hart_id;
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use crate::plat::timer::{Timer, TimerOps};
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use crate::plat::trap::{Trap, TrapContextOps, TrapOps};
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@ -20,7 +21,11 @@ extern "C" {
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#[no_mangle]
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pub extern "C" fn trap_handler(tf: &mut TrapContext) {
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let scause = riscv::register::scause::read();
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trace!("[Interrupt] scause: {:?}", scause.cause());
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trace!(
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"[Interrupt] cpu@{} scause: {:?}",
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get_hart_id(),
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scause.cause()
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);
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match scause.cause() {
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T::Interrupt(I::SupervisorTimer) => {
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// TODO: refactor this
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