From c3e5c51e57ff8160e1276e26662d8b67e6a3d68a Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Tue, 14 Feb 2023 22:14:16 +0800 Subject: [PATCH] init --- .gitignore | 12 + .petalinux/metadata | 7 + config.project | 11 + project-spec/attributes | 7 + project-spec/configs/busybox/inetd.conf | 22 + project-spec/configs/config | 267 + project-spec/configs/init-ifupdown/interfaces | 31 + project-spec/configs/rootfs_config | 3904 + .../configs/systemd-conf/wired.network | 13 + project-spec/hw-description/SoC.bit | Bin 0 -> 4045674 bytes project-spec/hw-description/metadata | 1 + project-spec/hw-description/ps7_init.c | 12343 ++ project-spec/hw-description/ps7_init.h | 117 + project-spec/hw-description/ps7_init.html | 139986 +++++++++++++++ project-spec/hw-description/ps7_init.tcl | 835 + project-spec/hw-description/ps7_init_gpl.c | 12356 ++ project-spec/hw-description/ps7_init_gpl.h | 131 + project-spec/hw-description/system.xsa | Bin 0 -> 557743 bytes project-spec/meta-user/COPYING.MIT | 17 + project-spec/meta-user/README | 64 + project-spec/meta-user/conf/layer.conf | 16 + project-spec/meta-user/conf/petalinuxbsp.conf | 4 + project-spec/meta-user/conf/user-rootfsconfig | 5 + .../uboot-device-tree/files/system-user.dtsi | 3 + .../uboot-device-tree.bbappend | 16 + .../device-tree/device-tree.bbappend | 28 + .../device-tree/files/pl-custom.dtsi | 4 + .../device-tree/files/system-user.dtsi | 93 + .../recipes-bsp/u-boot/files/bsp.cfg | 2 + .../recipes-bsp/u-boot/files/platform-top.h | 1 + .../recipes-bsp/u-boot/u-boot-xlnx_%.bbappend | 15 + .../recipes-kernel/linux/linux-xlnx/bsp.cfg | 0 .../linux-xlnx/user_2023-02-14-13-57-00.cfg | 16 + .../linux/linux-xlnx_%.bbappend | 6 + 34 files changed, 170333 insertions(+) create mode 100644 .gitignore create mode 100644 .petalinux/metadata create mode 100644 config.project create mode 100644 project-spec/attributes create mode 100644 project-spec/configs/busybox/inetd.conf create mode 100644 project-spec/configs/config create mode 100644 project-spec/configs/init-ifupdown/interfaces create mode 100644 project-spec/configs/rootfs_config create mode 100644 project-spec/configs/systemd-conf/wired.network create mode 100644 project-spec/hw-description/SoC.bit create mode 100644 project-spec/hw-description/metadata create mode 100644 project-spec/hw-description/ps7_init.c create mode 100644 project-spec/hw-description/ps7_init.h create mode 100644 project-spec/hw-description/ps7_init.html create mode 100644 project-spec/hw-description/ps7_init.tcl create mode 100644 project-spec/hw-description/ps7_init_gpl.c create mode 100644 project-spec/hw-description/ps7_init_gpl.h create mode 100644 project-spec/hw-description/system.xsa create mode 100644 project-spec/meta-user/COPYING.MIT create mode 100644 project-spec/meta-user/README create mode 100644 project-spec/meta-user/conf/layer.conf create mode 100644 project-spec/meta-user/conf/petalinuxbsp.conf create mode 100644 project-spec/meta-user/conf/user-rootfsconfig create mode 100644 project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/files/system-user.dtsi create mode 100644 project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend create mode 100644 project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend create mode 100644 project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi create mode 100644 project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi create mode 100644 project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg create mode 100644 project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h create mode 100644 project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend create mode 100644 project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg create mode 100644 project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2023-02-14-13-57-00.cfg create mode 100644 project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..85333e5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,12 @@ +*/*/config.old +*/*/rootfs_config.old +build/ +images/linux/ +pre-built/linux/ +.petalinux/* +!.petalinux/metadata +*.o +*.jou +*.log +/components/plnx_workspace +/components/yocto diff --git a/.petalinux/metadata b/.petalinux/metadata new file mode 100644 index 0000000..bf5a9e6 --- /dev/null +++ b/.petalinux/metadata @@ -0,0 +1,7 @@ +PETALINUX_VER=2022.2 +VALIDATE_HW_CHKSUM=1 +HARDWARE_PATH=/home/vivado/project/SoC.xsa +HDF_EXT=xsa +HARDWARE_CHECKSUM=e45b9019426cf2395b370dbd28044ffb +YOCTO_SDK=85e32bd84b2647e640a2e565ef06077a +RFSCONFIG_CHKSUM=b46c51379f90d101cd485ab49ceb7458 diff --git a/config.project b/config.project new file mode 100644 index 0000000..3d5b675 --- /dev/null +++ b/config.project @@ -0,0 +1,11 @@ +# +# Automatically generated file; DO NOT EDIT. +# PetaLinux SDK Project Configuration +# +CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH="" + +# +# Subsystems of the project +# +CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y +CONFIG_PROJECT_SUBSYSTEMS=y diff --git a/project-spec/attributes b/project-spec/attributes new file mode 100644 index 0000000..41530e7 --- /dev/null +++ b/project-spec/attributes @@ -0,0 +1,7 @@ +#Virtual Providers + + + +#defconfigs + +UBOOT_DEFAULT_DEFCONFIG="xilinx_zynq_virt_defconfig" diff --git a/project-spec/configs/busybox/inetd.conf b/project-spec/configs/busybox/inetd.conf new file mode 100644 index 0000000..b7c0bbc --- /dev/null +++ b/project-spec/configs/busybox/inetd.conf @@ -0,0 +1,22 @@ +#/etc/inetd.conf: see inetd(8) for further informations. +# +# Internet server configuration database +# +# If you want to disable an entry so it isn't touched during +# package updates just comment it out with a single '#' character. +# +# +# +#:INTERNAL: Internal services +#echo stream tcp nowait root internal +#echo dgram udp wait root internal +#chargen stream tcp nowait root internal +#chargen dgram udp wait root internal +#discard stream tcp nowait root internal +#discard dgram udp wait root internal +#daytime stream tcp nowait root internal +#daytime dgram udp wait root internal +#time stream tcp nowait root internal +#time dgram udp wait root internal +telnet stream tcp nowait root telnetd telnetd -i +ftp stream tcp nowait root ftpd ftpd -w diff --git a/project-spec/configs/config b/project-spec/configs/config new file mode 100644 index 0000000..aa673ca --- /dev/null +++ b/project-spec/configs/config @@ -0,0 +1,267 @@ +# +# Automatically generated file; DO NOT EDIT. +# misc/config System Configuration +# +CONFIG_SUBSYSTEM_TYPE_LINUX=y +CONFIG_SYSTEM_ZYNQ=y + +# +# Linux Components Selection +# +CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQ_FSBL=y +CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y +CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set +# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX is not set +# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC=y + +# +# External linux-kernel local source settings +# +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT_LOCAL_SRC_PATH="/home/vivado/project/linux-xlnx/" +CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_LIC_FILES_CHKSUM_LOCAL__SRC="" + +# +# Auto Config Settings +# +CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y +# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set +CONFIG_SUBSYSTEM_HARDWARE_AUTO=y +CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="ps7_cortexa9_0" +CONFIG_SUBSYSTEM_PROCESSOR_ps7_cortexa9_0_SELECT=y +CONFIG_SUBSYSTEM_ARCH_ARM=y + +# +# Memory Settings +# +CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x40000000 +CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0 +CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x400000 +CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PS7_DDR_0" + +# +# Serial Settings +# +CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_FSBL_SERIAL_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y +# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_9600 is not set +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_28800 is not set +CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_115200=y +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_230400 is not set +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_460800 is not set +# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_921600 is not set +CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_0" +CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0" + +# +# Ethernet Settings +# +CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_SELECT=y +# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC_AUTO is not set +CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC="00:0a:35:00:1e:53" +CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_USE_DHCP=y + +# +# Flash Settings +# +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_SELECT=y +# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set +# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set + +# +# partition 0 +# +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_NAME="qspi-boot" +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x500000 + +# +# partition 1 +# +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_NAME="qspi-kernel" +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_SIZE=0xA80000 + +# +# partition 2 +# +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_NAME="qspi-bootenv" +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0x20000 + +# +# partition 3 +# +CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="" +CONFIG_SUBSYSTEM_FLASH_IP_NAME="ps7_qspi_0" + +# +# SD/SDIO Settings +# +CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_0_SELECT=y +# CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_1_SELECT is not set +# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set +CONFIG_SUBSYSTEM_SD_PS7_SD_0_SELECT=y +CONFIG_SUBSYSTEM_SD_PS7_SD_1_SELECT=y + +# +# RTC Settings +# +CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT=y +CONFIG_SUBSYSTEM_I2C_PS7_I2C_0_SELECT=y +CONFIG_SUBSYSTEM_I2C_PS7_I2C_1_SELECT=y +CONFIG_SUBSYSTEM_USB_PS7_USB_0_SELECT=y +CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y + +# +# DTG Settings +# +CONFIG_SUBSYSTEM_MACHINE_NAME="template" +CONFIG_SUBSYSTEM_EXTRA_DT_FILES="" + +# +# Kernel Bootargs +# +CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y +CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y +CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait" +CONFIG_SUBSYSTEM_EXTRA_BOOTARGS="" +CONFIG_SUBSYSTEM_DEVICETREE_COMPILER_FLAGS="-@" +# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set +# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set +# CONFIG_SUBSYSTEM_ENABLE_NO_ALIAS is not set +# CONFIG_SUBSYSTEM_ENABLE_DT_VERBOSE is not set + +# +# FSBL Configuration +# +CONFIG_SUBSYSTEM_FSBL_BSPCOMPILER_FLAGS="" +CONFIG_SUBSYSTEM_FSBL_COMPILER_EXTRA_FLAGS="" + +# +# FPGA Manager +# +# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set + +# +# u-boot Configuration +# +CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="xilinx_zynq_virt_defconfig" + +# +# u-boot script configuration +# +CONFIG_SUBSYSTEM_UBOOT_APPEND_BASEADDR=y +CONFIG_SUBSYSTEM_UBOOT_PRE_BOOTENV="" + +# +# JTAG/DDR image offsets +# +CONFIG_SUBSYSTEM_UBOOT_DEVICETREE_OFFSET=0x100000 +CONFIG_SUBSYSTEM_UBOOT_KERNEL_OFFSET=0x200000 +CONFIG_SUBSYSTEM_UBOOT_RAMDISK_IMAGE_OFFSET=0x4000000 +CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE_OFFSET=0x10000000 + +# +# QSPI/OSPI image offsets +# +CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_OFFSET=0xA00000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_KERNEL_SIZE=0x600000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_OFFSET=0x1000000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_RAMDISK_SIZE=0xF80000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xA80000 +CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x1500000 + +# +# NAND image offsets +# +CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_OFFSET=0x1000000 +CONFIG_SUBSYSTEM_UBOOT_NAND_KERNEL_SIZE=0x3200000 +CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_OFFSET=0x4600000 +CONFIG_SUBSYSTEM_UBOOT_NAND_RAMDISK_SIZE=0x3200000 +CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_OFFSET=0x1080000 +CONFIG_SUBSYSTEM_UBOOT_NAND_FIT_IMAGE_SIZE=0x6400000 +CONFIG_SUBSYSTEM_UBOOT_KERNEL_IMAGE="uImage" +CONFIG_SUBSYSTEM_UBOOT_FIT_IMAGE="image.ub" +# CONFIG_SUBSYSTEM_UBOOT_EXT_DTB is not set + +# +# Linux Configuration +# +CONFIG_SUBSYSTEM_LINUX_CONFIG_TARGET="" + +# +# Image Packaging Configuration +# +# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set +# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set +# CONFIG_SUBSYSTEM_ROOTFS_UBIFS is not set +# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set +CONFIG_SUBSYSTEM_ROOTFS_EXT4=y +# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set +CONFIG_SUBSYSTEM_SDROOT_DEV="/dev/mmcblk0p2" +CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub" +CONFIG_SUBSYSTEM_RFS_FORMATS="cpio cpio.gz cpio.gz.u-boot ext4 tar.gz jffs2" +CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000 +CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT=y +CONFIG_SUBSYSTEM_TFTPBOOT_DIR="/tftpboot" + +# +# Firmware Version Configuration +# +CONFIG_SUBSYSTEM_HOSTNAME="TinySoC" +CONFIG_SUBSYSTEM_PRODUCT="TinySoC" +CONFIG_SUBSYSTEM_FW_VERSION="1.00" + +# +# Yocto Settings +# +CONFIG_YOCTO_MACHINE_NAME="zynq-generic" + +# +# TMPDIR Location +# +CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp" + +# +# Devtool Workspace Location +# +CONFIG_DEVTOOL_WORKSPACE_LOCATION="${PROOT}/components/yocto/workspace" + +# +# Parallel thread execution +# +CONFIG_YOCTO_BB_NUMBER_THREADS="" +CONFIG_YOCTO_PARALLEL_MAKE="" + +# +# Add pre-mirror url +# +CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_MAJOR_VER}/downloads" + +# +# Local sstate feeds settings +# +CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL="" +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y + +# +# Network sstate feeds URL +# +CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_MAJOR_VER}/arm/sstate-cache" +# CONFIG_YOCTO_BB_NO_NETWORK is not set +# CONFIG_YOCTO_BUILDTOOLS_EXTENDED is not set + +# +# User Layers +# +CONFIG_USER_LAYER_0="" diff --git a/project-spec/configs/init-ifupdown/interfaces b/project-spec/configs/init-ifupdown/interfaces new file mode 100644 index 0000000..0acf4cf --- /dev/null +++ b/project-spec/configs/init-ifupdown/interfaces @@ -0,0 +1,31 @@ +# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8) + +# The loopback interface +auto lo +iface lo inet loopback + +# Wireless interfaces +iface wlan0 inet dhcp + wireless_mode managed + wireless_essid any + wpa-driver wext + wpa-conf /etc/wpa_supplicant.conf + +iface atml0 inet dhcp + +# Wired or wireless interfaces +auto eth0 +iface eth0 inet dhcp +iface eth1 inet dhcp + +# Ethernet/RNDIS gadget (g_ether) +# ... or on host side, usbnet and random hwaddr +iface usb0 inet static + address 192.168.7.2 + netmask 255.255.255.0 + network 192.168.7.0 + gateway 192.168.7.1 + +# Bluetooth networking +iface bnep0 inet dhcp + diff --git a/project-spec/configs/rootfs_config b/project-spec/configs/rootfs_config new file mode 100644 index 0000000..019c8ba --- /dev/null +++ b/project-spec/configs/rootfs_config @@ -0,0 +1,3904 @@ +# +# Automatically generated file; DO NOT EDIT. +# Configuration +# +CONFIG_system-zynq=y + +# +# Filesystem Packages +# + +# +# admin +# + +# +# sudo +# +# CONFIG_sudo is not set +# CONFIG_sudo-dbg is not set +# CONFIG_sudo-dev is not set + +# +# base +# + +# +# base-files +# +# CONFIG_base-files is not set +# CONFIG_base-files-dbg is not set +# CONFIG_base-files-dev is not set + +# +# base-passwd +# +# CONFIG_base-passwd is not set +# CONFIG_base-passwd-dev is not set +# CONFIG_base-passwd-dbg is not set +# CONFIG_base-passwd-update is not set + +# +# bc +# +# CONFIG_bc is not set +# CONFIG_bc-dev is not set +# CONFIG_bc-dbg is not set + +# +# busybox +# +# CONFIG_busybox is not set +# CONFIG_busybox-udhcpd is not set +# CONFIG_busybox-httpd is not set +# CONFIG_busybox-dbg is not set +# CONFIG_busybox-inetd is not set +# CONFIG_busybox-dev is not set +# CONFIG_busybox-hwclock is not set +# CONFIG_busybox-udhcpc is not set +# CONFIG_busybox-syslog is not set + +# +# cpio +# +# CONFIG_cpio is not set +# CONFIG_cpio-dbg is not set +# CONFIG_cpio-dev is not set +# CONFIG_cpio-rmt is not set + +# +# dbus +# +# CONFIG_dbus is not set +# CONFIG_dbus-lib is not set +# CONFIG_dbus-dev is not set +# CONFIG_dbus-dbg is not set + +# +# dbus-glib +# +# CONFIG_dbus-glib is not set +# CONFIG_dbus-glib-bash-completion is not set +# CONFIG_dbus-glib-tests is not set +# CONFIG_dbus-glib-dbg is not set +# CONFIG_dbus-glib-dev is not set + +# +# dbus-wait +# +# CONFIG_dbus-wait is not set +# CONFIG_dbus-wait-dbg is not set +# CONFIG_dbus-wait-dev is not set + +# +# diffutils +# +# CONFIG_diffutils is not set +# CONFIG_diffutils-dbg is not set +# CONFIG_diffutils-dev is not set + +# +# dnf +# +# CONFIG_dnf is not set + +# +# e2fsprogs +# +# CONFIG_e2fsprogs is not set +# CONFIG_e2fsprogs-resize2fs is not set +# CONFIG_e2fsprogs-badblocks is not set +# CONFIG_e2fsprogs-e2fsck is not set +# CONFIG_libss is not set +# CONFIG_libcomerr is not set +# CONFIG_libext2fs is not set +# CONFIG_e2fsprogs-dev is not set +# CONFIG_e2fsprogs-tune2fs is not set +# CONFIG_libe2p is not set +CONFIG_e2fsprogs-mke2fs=y +# CONFIG_e2fsprogs-dbg is not set + +# +# ed +# +# CONFIG_ed is not set +# CONFIG_ed-dev is not set +# CONFIG_ed-dbg is not set + +# +# elfutils +# +# CONFIG_elfutils is not set +# CONFIG_libdw is not set +# CONFIG_elfutils-dev is not set +# CONFIG_elfutils-binutils is not set +# CONFIG_libelf is not set +# CONFIG_libasm is not set +# CONFIG_elfutils-dbg is not set + +# +# formfactor +# +# CONFIG_formfactor is not set +# CONFIG_formfactor-dbg is not set +# CONFIG_formfactor-dev is not set + +# +# fpga-manager-script +# +CONFIG_fpga-manager-script=y + +# +# haveged +# +CONFIG_haveged=y + +# +# i2c-tools +# +# CONFIG_i2c-tools is not set +# CONFIG_i2c-tools-dev is not set +# CONFIG_i2c-tools-dbg is not set +# CONFIG_i2c-tools-misc is not set + +# +# init-ifupdown +# +# CONFIG_init-ifupdown is not set +# CONFIG_init-ifupdown-dev is not set +# CONFIG_init-ifupdown-dbg is not set + +# +# initscripts +# +# CONFIG_initscripts is not set +# CONFIG_initscripts-dev is not set +# CONFIG_initscripts-dbg is not set +# CONFIG_initscripts-functions is not set + +# +# iproute2 +# +# CONFIG_iproute2 is not set +# CONFIG_iproute2-tc is not set +# CONFIG_iproute2-nstat is not set +# CONFIG_iproute2-dev is not set +# CONFIG_iproute2-lnstat is not set +# CONFIG_iproute2-rtacct is not set +# CONFIG_iproute2-ss is not set +# CONFIG_iproute2-ifstat is not set +# CONFIG_iproute2-genl is not set +# CONFIG_iproute2-bash-completion is not set +# CONFIG_iproute2-dbg is not set + +# +# kmod +# +# CONFIG_kmod is not set +# CONFIG_kmod-dbg is not set +# CONFIG_libkmod is not set +# CONFIG_kmod-dev is not set +# CONFIG_kmod-bash-completion is not set + +# +# linuxptp +# +# CONFIG_linuxptp is not set +# CONFIG_linuxptp-dev is not set +# CONFIG_linuxptp-dbg is not set + +# +# modutils-initscripts +# +# CONFIG_modutils-initscripts is not set +# CONFIG_modutils-initscripts-dev is not set +# CONFIG_modutils-initscripts-dbg is not set + +# +# mtd-utils +# +CONFIG_mtd-utils=y +# CONFIG_mtd-utils-ubifs is not set +# CONFIG_mtd-utils-dev is not set +# CONFIG_mtd-utils-jffs2 is not set +# CONFIG_mtd-utils-dbg is not set +# CONFIG_mtd-utils-misc is not set + +# +# netbase +# +# CONFIG_netbase is not set +# CONFIG_netbase-dbg is not set +# CONFIG_netbase-dev is not set + +# +# opkg +# +# CONFIG_opkg is not set +# CONFIG_opkg-dev is not set +# CONFIG_libopkg is not set +# CONFIG_opkg-dbg is not set + +# +# opkg-utils +# +# CONFIG_opkg-utils is not set +# CONFIG_update-alternatives-opkg is not set +# CONFIG_opkg-utils-dbg is not set + +# +# procps +# +# CONFIG_procps is not set +# CONFIG_procps-dbg is not set +# CONFIG_procps-dev is not set + +# +# pseudo +# +# CONFIG_pseudo is not set +# CONFIG_pseudo-dbg is not set +# CONFIG_pseudo-dev is not set + +# +# psplash +# +# CONFIG_psplash is not set +# CONFIG_psplash-dbg is not set +# CONFIG_psplash-default is not set +# CONFIG_psplash-dev is not set + +# +# quota +# +# CONFIG_quota is not set +# CONFIG_quota-dev is not set +# CONFIG_quota-dbg is not set + +# +# shared-mime-info +# +# CONFIG_shared-mime-info is not set +# CONFIG_shared-mime-info-dev is not set +# CONFIG_shared-mime-info-dbg is not set +# CONFIG_shared-mime-info-data is not set + +# +# shell +# + +# +# bash +# +# CONFIG_bash is not set +# CONFIG_bash-dev is not set +# CONFIG_bash-dbg is not set + +# +# sysvinit +# +# CONFIG_sysvinit is not set +# CONFIG_sysvinit-pidof is not set +# CONFIG_sysvinit-dbg is not set +# CONFIG_sysvinit-dev is not set +# CONFIG_sysvinit-sulogin is not set + +# +# tar +# +# CONFIG_tar is not set +# CONFIG_tar-dev is not set +# CONFIG_tar-rmt is not set +# CONFIG_tar-dbg is not set + +# +# tzdata +# +# CONFIG_tzdata is not set +# CONFIG_tzdata-asia is not set +# CONFIG_tzdata-arctic is not set +# CONFIG_tzdata-posix is not set +# CONFIG_tzdata-africa is not set +# CONFIG_tzdata-europe is not set +# CONFIG_tzdata-americas is not set +# CONFIG_tzdata-antarctica is not set +# CONFIG_tzdata-atlantic is not set +# CONFIG_tzdata-misc is not set +# CONFIG_tzdata-right is not set +# CONFIG_tzdata-pacific is not set +# CONFIG_tzdata-australia is not set + +# +# update-rc.d +# +# CONFIG_update-rc.d is not set +# CONFIG_update-rc.d-dev is not set +# CONFIG_update-rc.d-dbg is not set + +# +# usbutils +# +# CONFIG_usbutils is not set +# CONFIG_usbutils-dbg is not set +# CONFIG_usbutils-dev is not set + +# +# util-linux +# +# CONFIG_util-linux is not set +# CONFIG_util-linux-dev is not set +# CONFIG_util-linux-fsck.cramfs is not set +# CONFIG_util-linux-swaponoff is not set +# CONFIG_util-linux-sfdisk is not set +# CONFIG_util-linux-uuidd is not set +# CONFIG_util-linux-getopt is not set +# CONFIG_util-linux-findfs is not set +# CONFIG_util-linux-mountpoint is not set +# CONFIG_util-linux-hwclock is not set +# CONFIG_util-linux-mcookie is not set +# CONFIG_util-linux-dbg is not set +# CONFIG_util-linux-mkfs.cramfs is not set +# CONFIG_util-linux-blkid is not set +# CONFIG_util-linux-sulogin is not set +# CONFIG_util-linux-losetup is not set +# CONFIG_util-linux-fstrim is not set +# CONFIG_util-linux-cfdisk is not set +# CONFIG_util-linux-agetty is not set +# CONFIG_util-linux-bash-completion is not set +# CONFIG_util-linux-lscpu is not set +# CONFIG_util-linux-prlimit is not set +# CONFIG_util-linux-umount is not set +# CONFIG_util-linux-partx is not set +# CONFIG_util-linux-mkfs is not set +# CONFIG_util-linux-readprofile is not set +# CONFIG_util-linux-uuidgen is not set +# CONFIG_util-linux-mount is not set +# CONFIG_util-linux-fdisk is not set +# CONFIG_util-linux-fsck is not set + +# +# utils +# + +# +# shadow +# +# CONFIG_shadow is not set +# CONFIG_shadow-base is not set +# CONFIG_shadow-dev is not set +# CONFIG_shadow-dbg is not set + +# +# xz +# +# CONFIG_xz is not set +# CONFIG_xz-dev is not set +# CONFIG_xz-dbg is not set +# CONFIG_liblzma is not set + +# +# baseutils +# + +# +# shadow-securetty +# +# CONFIG_shadow-securetty is not set +# CONFIG_shadow-securetty-dev is not set +# CONFIG_shadow-securetty-dbg is not set + +# +# benchmark +# + +# +# tests +# + +# +# dhrystone +# +# CONFIG_dhrystone is not set +# CONFIG_dhrystone-dev is not set +# CONFIG_dhrystone-dbg is not set + +# +# linpack +# +# CONFIG_linpack is not set +# CONFIG_linpack-dbg is not set +# CONFIG_linpack-dev is not set + +# +# whetstone +# +# CONFIG_whetstone is not set +# CONFIG_whetstone-dev is not set +# CONFIG_whetstone-dbg is not set + +# +# bootgen +# +# CONFIG_bootgen is not set +# CONFIG_bootgen-dev is not set +# CONFIG_bootgen-dbg is not set + +# +# console +# + +# +# network +# + +# +# canutils +# +# CONFIG_canutils is not set +# CONFIG_canutils-dbg is not set +# CONFIG_canutils-dev is not set + +# +# can-utils +# +CONFIG_can-utils=y +# CONFIG_can-utils-dbg is not set +# CONFIG_can-utils-dev is not set + +# +# curl +# +CONFIG_curl=y +# CONFIG_curl-dev is not set +# CONFIG_libcurl is not set +# CONFIG_curl-dbg is not set + +# +# dropbear +# +# CONFIG_dropbear is not set +# CONFIG_dropbear-dev is not set +# CONFIG_dropbear-dbg is not set + +# +# ethtool +# +# CONFIG_ethtool is not set +# CONFIG_ethtool-dbg is not set +# CONFIG_ethtool-dev is not set + +# +# lrzsz +# +# CONFIG_lrzsz is not set +# CONFIG_lrzsz-dbg is not set +# CONFIG_lrzsz-dev is not set + +# +# mailx +# +# CONFIG_mailx is not set +# CONFIG_mailx-dbg is not set +# CONFIG_mailx-dev is not set + +# +# minicom +# +# CONFIG_minicom is not set +# CONFIG_minicom-dbg is not set +# CONFIG_minicom-dev is not set + +# +# nfs-utils +# +CONFIG_nfs-utils=y +# CONFIG_nfs-utils-dev is not set +# CONFIG_nfs-utils-client is not set +# CONFIG_nfs-utils-stats is not set +# CONFIG_nfs-utils-dbg is not set + +# +# openssh +# +# CONFIG_openssh is not set +# CONFIG_openssh-misc is not set +# CONFIG_openssh-dbg is not set +# CONFIG_openssh-sshd is not set +# CONFIG_openssh-keygen is not set +# CONFIG_openssh-ssh is not set +# CONFIG_openssh-dev is not set +# CONFIG_openssh-sftp is not set +# CONFIG_openssh-sftp-server is not set +# CONFIG_openssh-scp is not set + +# +# ppp +# +# CONFIG_ppp is not set +# CONFIG_ppp-minconn is not set +# CONFIG_ppp-l2tp is not set +# CONFIG_ppp-dev is not set +# CONFIG_ppp-password is not set +# CONFIG_ppp-radius is not set +# CONFIG_ppp-tools is not set +# CONFIG_ppp-dbg is not set +# CONFIG_ppp-oe is not set +# CONFIG_ppp-oa is not set +# CONFIG_ppp-winbind is not set + +# +# rpcbind +# +# CONFIG_rpcbind is not set +# CONFIG_rpcbind-dbg is not set +# CONFIG_rpcbind-dev is not set + +# +# rsync +# +# CONFIG_rsync is not set +# CONFIG_rsync-dev is not set +# CONFIG_rsync-dbg is not set + +# +# socat +# +# CONFIG_socat is not set +# CONFIG_socat-dbg is not set +# CONFIG_socat-dev is not set + +# +# subversion +# +# CONFIG_subversion is not set +# CONFIG_subversion-dev is not set +# CONFIG_subversion-dbg is not set + +# +# tcp-wrappers +# +# CONFIG_tcp-wrappers is not set +# CONFIG_tcp-wrappers-dbg is not set +# CONFIG_libwrap-dev is not set +# CONFIG_libwrap is not set + +# +# wget +# +# CONFIG_wget is not set +# CONFIG_wget-dev is not set +# CONFIG_wget-dbg is not set + +# +# tools +# + +# +# parted +# +# CONFIG_parted is not set +# CONFIG_parted-dbg is not set +# CONFIG_parted-dev is not set + +# +# utils +# + +# +# alsa-utils +# +# CONFIG_alsa-utils is not set +# CONFIG_alsa-utils-aconnect is not set +# CONFIG_alsa-utils-alsaloop is not set +# CONFIG_alsa-utils-aseqdump is not set +# CONFIG_alsa-utils-aplay is not set +# CONFIG_alsa-utils-iecset is not set +# CONFIG_alsa-utils-alsaucm is not set +# CONFIG_alsa-utils-dev is not set +# CONFIG_alsa-utils-alsamixer is not set +# CONFIG_alsa-utils-amixer is not set +# CONFIG_alsa-utils-speakertest is not set +# CONFIG_alsa-utils-alsactl is not set +# CONFIG_alsa-utils-dbg is not set +# CONFIG_alsa-utils-midi is not set +# CONFIG_alsa-utils-aseqnet is not set +# CONFIG_alsa-utils-alsatplg is not set + +# +# bash-completion +# +# CONFIG_bash-completion is not set +# CONFIG_bash-completion-dev is not set +# CONFIG_bash-completion-extra is not set +# CONFIG_bash-completion-dbg is not set + +# +# bzip2 +# +# CONFIG_bzip2 is not set +# CONFIG_libbz2 is not set +# CONFIG_bzip2-dbg is not set +# CONFIG_bzip2-dev is not set + +# +# file +# +CONFIG_file=y +# CONFIG_file-dbg is not set +# CONFIG_file-dev is not set + +# +# findutils +# +CONFIG_findutils=y +# CONFIG_findutils-dbg is not set +# CONFIG_findutils-dev is not set + +# +# gawk +# +CONFIG_gawk=y +# CONFIG_gawk-dbg is not set +# CONFIG_gawk-dev is not set + +# +# git +# +# CONFIG_git is not set +# CONFIG_git-bash-completion is not set +# CONFIG_gitweb is not set +# CONFIG_git-perltools is not set +# CONFIG_git-dev is not set +# CONFIG_git-dbg is not set + +# +# grep +# +CONFIG_grep=y +# CONFIG_grep-dbg is not set +# CONFIG_grep-dev is not set + +# +# groff +# +# CONFIG_groff is not set +# CONFIG_groff-dev is not set +# CONFIG_groff-dbg is not set + +# +# gzip +# +# CONFIG_gzip is not set +# CONFIG_gzip-dbg is not set +# CONFIG_gzip-dev is not set + +# +# hdparm +# +# CONFIG_hdparm is not set +# CONFIG_wiper is not set +# CONFIG_hdparm-dbg is not set +# CONFIG_hdparm-dev is not set + +# +# less +# +# CONFIG_less is not set +# CONFIG_less-dev is not set +# CONFIG_less-dbg is not set + +# +# ltp +# +# CONFIG_ltp is not set +# CONFIG_ltp-dev is not set +# CONFIG_ltp-dbg is not set + +# +# man +# +# CONFIG_man is not set + +# +# man-pages +# +# CONFIG_man-pages is not set +# CONFIG_man-pages-dbg is not set +# CONFIG_man-pages-dev is not set + +# +# mc +# +# CONFIG_mc is not set +# CONFIG_mc-dev is not set +# CONFIG_mc-helpers-perl is not set +# CONFIG_mc-helpers is not set +# CONFIG_mc-fish is not set +# CONFIG_mc-dbg is not set + +# +# pciutils +# +CONFIG_pciutils=y +# CONFIG_pciutils-ids is not set +# CONFIG_pciutils-dev is not set +# CONFIG_libpci is not set +# CONFIG_pciutils-dbg is not set + +# +# pkgconfig +# +# CONFIG_pkgconfig is not set +# CONFIG_pkgconfig-dbg is not set +# CONFIG_pkgconfig-dev is not set + +# +# screen +# +# CONFIG_screen is not set +# CONFIG_screen-dbg is not set +# CONFIG_screen-dev is not set + +# +# sed +# +# CONFIG_sed is not set +# CONFIG_sed-dbg is not set +# CONFIG_sed-dev is not set + +# +# setserial +# +# CONFIG_setserial is not set +# CONFIG_setserial-dev is not set +# CONFIG_setserial-dbg is not set + +# +# smartmontools +# +# CONFIG_smartmontools is not set +# CONFIG_smartmontools-dbg is not set +# CONFIG_smartmontools-dev is not set + +# +# strace +# +# CONFIG_strace is not set +# CONFIG_strace-dev is not set +# CONFIG_strace-dbg is not set + +# +# sysstat +# +# CONFIG_sysstat is not set +# CONFIG_sysstat-dev is not set +# CONFIG_sysstat-dbg is not set + +# +# texinfo +# +# CONFIG_texinfo is not set +# CONFIG_texinfo-dev is not set +# CONFIG_info is not set +# CONFIG_texinfo-dbg is not set + +# +# unzip +# +# CONFIG_unzip is not set +# CONFIG_unzip-dbg is not set +# CONFIG_unzip-dev is not set + +# +# vim +# +CONFIG_vim=y +CONFIG_vim-syntax=y +# CONFIG_vim-dev is not set +# CONFIG_vim-help is not set +CONFIG_vim-common=y +CONFIG_vim-vimrc=y +# CONFIG_vim-tutor is not set +CONFIG_vim-tools=y +# CONFIG_vim-dbg is not set + +# +# zip +# +# CONFIG_zip is not set +# CONFIG_zip-dev is not set +# CONFIG_zip-dbg is not set + +# +# devel +# + +# +# autoconf +# +# CONFIG_autoconf is not set +# CONFIG_autoconf-dev is not set +# CONFIG_autoconf-dbg is not set + +# +# automake +# +# CONFIG_automake is not set +# CONFIG_automake-dev is not set +# CONFIG_automake-dbg is not set + +# +# binutils +# +# CONFIG_binutils is not set +# CONFIG_binutils-dev is not set +# CONFIG_binutils-dbg is not set + +# +# bison +# +# CONFIG_bison is not set +# CONFIG_bison-dbg is not set +# CONFIG_bison-dev is not set + +# +# ccache +# +# CONFIG_ccache is not set +# CONFIG_ccache-dbg is not set +# CONFIG_ccache-dev is not set + +# +# diffstat +# +# CONFIG_diffstat is not set +# CONFIG_diffstat-dbg is not set +# CONFIG_diffstat-dev is not set + +# +# distcc +# +# CONFIG_distcc is not set +# CONFIG_distcc-dbg is not set +# CONFIG_distcc-dev is not set + +# +# expect +# +# CONFIG_expect is not set +# CONFIG_expect-dbg is not set +# CONFIG_expect-dev is not set + +# +# flex +# +# CONFIG_flex is not set +# CONFIG_flex-dev is not set +# CONFIG_flex-dbg is not set + +# +# gmp +# +# CONFIG_gmp is not set +# CONFIG_gmp-dbg is not set +# CONFIG_gmp-dev is not set +# CONFIG_libgmpxx is not set + +# +# gnu-config +# +# CONFIG_gnu-config is not set + +# +# intltool +# +# CONFIG_intltool is not set +# CONFIG_intltool-dev is not set +# CONFIG_intltool-dbg is not set + +# +# libarchive +# +# CONFIG_libarchive is not set +# CONFIG_libarchive-dev is not set +# CONFIG_bsdcpio is not set +# CONFIG_bsdtar is not set +# CONFIG_libarchive-dbg is not set + +# +# libcheck +# +# CONFIG_libcheck is not set +# CONFIG_libcheck-dev is not set +# CONFIG_libcheck-dbg is not set + +# +# libpcre +# +# CONFIG_libpcre is not set +# CONFIG_libpcre-dev is not set +# CONFIG_libpcreposix is not set +# CONFIG_libpcre-dbg is not set +# CONFIG_libpcrecpp is not set +# CONFIG_pcretest is not set +# CONFIG_pcregrep is not set + +# +# lsof +# +# CONFIG_lsof is not set +# CONFIG_lsof-dev is not set +# CONFIG_lsof-dbg is not set + +# +# make +# +# CONFIG_make is not set +# CONFIG_make-dbg is not set +# CONFIG_make-dev is not set + +# +# mpfr +# +# CONFIG_mpfr is not set +# CONFIG_mpfr-dev is not set +# CONFIG_mpfr-dbg is not set + +# +# perl +# +# CONFIG_perl is not set +# CONFIG_perl-module-unicore is not set +# CONFIG_perl-dev is not set +# CONFIG_perl-misc is not set +# CONFIG_perl-dbg is not set +# CONFIG_perl-module-cpan is not set +# CONFIG_perl-modules is not set +# CONFIG_perl-pod is not set + +# +# python3-nose +# +# CONFIG_python3-nose is not set +# CONFIG_python3-nose-dbg is not set +# CONFIG_python3-nose-dev is not set + +# +# python3-numpy +# +# CONFIG_python3-numpy is not set +# CONFIG_python3-numpy-dev is not set +# CONFIG_python3-numpy-dbg is not set + +# +# python3-scons +# +# CONFIG_python3-scons is not set +# CONFIG_python3-scons-dev is not set +# CONFIG_python3-scons-dbg is not set + +# +# python3-dbus +# +# CONFIG_python3-dbus is not set +# CONFIG_python3-dbus-dbg is not set +# CONFIG_python3-dbus-dev is not set + +# +# python3-pygobject +# +# CONFIG_python3-pygobject is not set +# CONFIG_python3-pygobject-dbg is not set +# CONFIG_python3-pygobject-dev is not set + +# +# quilt +# +# CONFIG_quilt is not set +# CONFIG_quilt-dbg is not set +# CONFIG_quilt-dev is not set +# CONFIG_guards is not set + +# +# ruby +# + +# +# ruby +# +# CONFIG_ruby is not set +# CONFIG_ruby-dev is not set +# CONFIG_ruby-rdoc is not set +# CONFIG_ruby-dbg is not set + +# +# run-postinsts +# +CONFIG_run-postinsts=y +# CONFIG_run-postinsts-dbg is not set +# CONFIG_run-postinsts-dev is not set + +# +# swig +# +# CONFIG_swig is not set +# CONFIG_swig-dev is not set +# CONFIG_swig-dbg is not set + +# +# tcltk +# + +# +# tcl +# +# CONFIG_tcl is not set +# CONFIG_tcl-dev is not set +# CONFIG_tcl-lib is not set +# CONFIG_tcl-dbg is not set + +# +# vala +# +# CONFIG_vala is not set +# CONFIG_vala-dev is not set +# CONFIG_vala-dbg is not set + +# +# fonts +# + +# +# cantarell-fonts +# +# CONFIG_cantarell-fonts is not set +# CONFIG_cantarell-fonts-dbg is not set +# CONFIG_cantarell-fonts-dev is not set + +# +# kernel +# + +# +# userland +# + +# +# kexec-tools +# +# CONFIG_kexec-tools is not set +# CONFIG_kexec-tools-dbg is not set +# CONFIG_kdump is not set +# CONFIG_kexec-tools-dev is not set +# CONFIG_kexec is not set +# CONFIG_vmcore-dmesg is not set + +# +# libs +# + +# +# acl +# +# CONFIG_acl is not set +# CONFIG_acl-dev is not set +# CONFIG_libacl is not set +# CONFIG_acl-dbg is not set + +# +# apr +# +# CONFIG_apr is not set +# CONFIG_apr-dbg is not set +# CONFIG_apr-dev is not set + +# +# apr-util +# +# CONFIG_apr-util is not set +# CONFIG_apr-util-dev is not set +# CONFIG_apr-util-dbg is not set + +# +# attr +# +# CONFIG_attr is not set +# CONFIG_attr-dbg is not set +# CONFIG_attr-dev is not set +# CONFIG_libattr is not set + +# +# bluez5 +# +# CONFIG_bluez5 is not set +# CONFIG_bluez5-testtools is not set +# CONFIG_bluez5-dbg is not set +# CONFIG_bluez5-obex is not set +# CONFIG_bluez5-dev is not set +# CONFIG_bluez5-noinst-tools is not set + +# +# boost +# +# CONFIG_boost is not set +# CONFIG_boost-random is not set +# CONFIG_boost-regex is not set +# CONFIG_boost-atomic is not set +# CONFIG_boost-thread is not set +# CONFIG_boost-serialization is not set +# CONFIG_boost-filesystem is not set +# CONFIG_boost-test is not set +# CONFIG_boost-system is not set +# CONFIG_boost-graph is not set +# CONFIG_boost-container is not set +# CONFIG_boost-date-time is not set +# CONFIG_boost-math is not set +# CONFIG_boost-wave is not set +# CONFIG_boost-chrono is not set +# CONFIG_boost-timer is not set +# CONFIG_boost-dev is not set +# CONFIG_boost-program-options is not set +# CONFIG_boost-iostreams is not set +# CONFIG_boost-dbg is not set +# CONFIG_boost-log is not set + +# +# cairo +# +# CONFIG_cairo is not set +# CONFIG_cairo-gobject is not set +# CONFIG_cairo-script-interpreter is not set +# CONFIG_cairo-perf-utils is not set +# CONFIG_cairo-dbg is not set +# CONFIG_cairo-dev is not set + +# +# db +# +# CONFIG_db is not set +# CONFIG_db-dbg is not set +# CONFIG_db-cxx is not set +# CONFIG_db-dev is not set +# CONFIG_db-bin is not set + +# +# devel +# + +# +# libyaml +# +# CONFIG_libyaml is not set +# CONFIG_libyaml-dev is not set +# CONFIG_libyaml-dbg is not set + +# +# expat +# +# CONFIG_expat is not set +# CONFIG_expat-bin is not set +# CONFIG_expat-dbg is not set +# CONFIG_expat-dev is not set + +# +# faad2 +# +# CONFIG_faad2 is not set +# CONFIG_faad2-dev is not set +# CONFIG_faad2-dbg is not set + +# +# ffmpeg +# +# CONFIG_ffmpeg is not set +# CONFIG_ffmpeg-dbg is not set +# CONFIG_ffmpeg-dev is not set + +# +# flac +# +# CONFIG_flac is not set +# CONFIG_flac-dbg is not set +# CONFIG_libflacPLUSPLUS is not set +# CONFIG_libflac is not set +# CONFIG_flac-dev is not set + +# +# fontconfig +# +# CONFIG_fontconfig is not set +# CONFIG_fontconfig-utils is not set +# CONFIG_fontconfig-dbg is not set +# CONFIG_fontconfig-dev is not set + +# +# freetype +# +# CONFIG_freetype is not set +# CONFIG_freetype-dbg is not set +# CONFIG_freetype-dev is not set + +# +# gdbm +# +# CONFIG_gdbm is not set +# CONFIG_gdbm-bin is not set +# CONFIG_gdbm-compat is not set +# CONFIG_gdbm-dbg is not set +# CONFIG_gdbm-dev is not set + +# +# gdk-pixbuf +# +# CONFIG_gdk-pixbuf is not set +# CONFIG_gdk-pixbuf-xlib is not set +# CONFIG_gdk-pixbuf-dbg is not set +# CONFIG_gdk-pixbuf-dev is not set + +# +# gettext +# +# CONFIG_gettext is not set +# CONFIG_libgettextlib is not set +# CONFIG_gettext-dev is not set +# CONFIG_gettext-runtime is not set +# CONFIG_libgettextsrc is not set +# CONFIG_gettext-dbg is not set + +# +# glib-networking +# +# CONFIG_glib-networking is not set +# CONFIG_glib-networking-dbg is not set +# CONFIG_glib-networking-dev is not set + +# +# gobject-introspection +# +# CONFIG_gobject-introspection is not set +# CONFIG_gobject-introspection-dev is not set +# CONFIG_gobject-introspection-dbg is not set + +# +# gtk+ +# +# CONFIG_gtkPLUS is not set +# CONFIG_gtkPLUS-dev is not set +# CONFIG_gtkPLUS-dbg is not set +# CONFIG_libgail is not set +# CONFIG_gtk-demo is not set + +# +# gtk+3 +# +# CONFIG_gtkPLUS3 is not set +# CONFIG_gtkPLUS3-demo is not set +# CONFIG_gtkPLUS3-dev is not set +# CONFIG_gtkPLUS3-dbg is not set + +# +# harfbuzz +# +# CONFIG_harfbuzz is not set +# CONFIG_harfbuzz-icu is not set +# CONFIG_harfbuzz-icu-dev is not set +# CONFIG_harfbuzz-bin is not set +# CONFIG_harfbuzz-dev is not set +# CONFIG_harfbuzz-dbg is not set + +# +# libaio +# +# CONFIG_libaio is not set +# CONFIG_libaio-dev is not set +# CONFIG_libaio-dbg is not set + +# +# libcap +# +# CONFIG_libcap is not set +# CONFIG_libcap-dbg is not set +# CONFIG_libcap-dev is not set +# CONFIG_libcap-bin is not set + +# +# libdaemon +# +# CONFIG_libdaemon is not set +# CONFIG_libdaemon-dbg is not set +# CONFIG_libdaemon-dev is not set + +# +# libdmx +# +# CONFIG_libdmx is not set +# CONFIG_libdmx-dbg is not set +# CONFIG_libdmx-dev is not set + +# +# libeigen +# +# CONFIG_libeigen-dev is not set +# CONFIG_libeigen-dbg is not set + +# +# libepoxy +# +# CONFIG_libepoxy is not set +# CONFIG_libepoxy-dev is not set +# CONFIG_libepoxy-dbg is not set + +# +# libevdev +# +# CONFIG_libevdev is not set +# CONFIG_libevdev-dbg is not set +# CONFIG_libevdev-dev is not set + +# +# libevent +# +# CONFIG_libevent is not set +# CONFIG_libevent-dev is not set +# CONFIG_libevent-dbg is not set + +# +# libexif +# +# CONFIG_libexif is not set +# CONFIG_libexif-dbg is not set +# CONFIG_libexif-dev is not set + +# +# libffi +# +# CONFIG_libffi is not set +# CONFIG_libffi-dev is not set +# CONFIG_libffi-dbg is not set + +# +# libfontenc +# +# CONFIG_libfontenc is not set +# CONFIG_libfontenc-dev is not set +# CONFIG_libfontenc-dbg is not set + +# +# libgcrypt +# +# CONFIG_libgcrypt is not set +# CONFIG_libgcrypt-dbg is not set +# CONFIG_libgcrypt-dev is not set +# CONFIG_dumpsexp-dev is not set + +# +# libgpg-error +# +# CONFIG_libgpg-error is not set +# CONFIG_libgpg-error-dbg is not set +# CONFIG_libgpg-error-dev is not set + +# +# libgphoto2 +# +# CONFIG_libgphoto2 is not set +# CONFIG_libgphoto2-dbg is not set +# CONFIG_libgphotoport is not set +# CONFIG_libgphoto2-bin is not set +# CONFIG_libgphoto2-camlibs is not set +# CONFIG_libgphoto2-dev is not set + +# +# libgpiod +# +# CONFIG_libgpiod is not set +# CONFIG_libgpiod-dev is not set +# CONFIG_libgpiod-dbg is not set + +# +# libgudev +# +# CONFIG_libgudev is not set +# CONFIG_libgudev-dev is not set +# CONFIG_libgudev-dbg is not set + +# +# libical +# +# CONFIG_libical is not set +# CONFIG_libical-dev is not set +# CONFIG_libical-dbg is not set + +# +# libice +# +# CONFIG_libice is not set +# CONFIG_libice-dbg is not set +# CONFIG_libice-dev is not set + +# +# libid3tag +# +# CONFIG_libid3tag is not set +# CONFIG_libid3tag-dbg is not set +# CONFIG_libid3tag-dev is not set + +# +# libidn +# +# CONFIG_libidn is not set +# CONFIG_idn is not set +# CONFIG_libidn-dbg is not set +# CONFIG_libidn-dev is not set + +# +# libinput +# +# CONFIG_libinput is not set +# CONFIG_libinput-dbg is not set +# CONFIG_libinput-dev is not set + +# +# libjpeg-turbo +# +# CONFIG_libjpeg-turbo is not set +# CONFIG_libturbojpeg is not set +# CONFIG_jpeg-tools is not set +# CONFIG_libjpeg-turbo-dbg is not set +# CONFIG_libjpeg-turbo-dev is not set + +# +# libmetal +# +# CONFIG_libmetal is not set +# CONFIG_libmetal-dbg is not set +# CONFIG_libmetal-dev is not set + +# +# libmpc +# +# CONFIG_libmpc is not set +# CONFIG_libmpc-dev is not set +# CONFIG_libmpc-dbg is not set + +# +# libnet +# +# CONFIG_libnet is not set +# CONFIG_libnet-dev is not set +# CONFIG_libnet-dbg is not set + +# +# libnewt +# +# CONFIG_libnewt is not set +# CONFIG_libnewt-dev is not set +# CONFIG_libnewt-dbg is not set +# CONFIG_whiptail is not set + +# +# libnotify +# +# CONFIG_libnotify is not set +# CONFIG_libnotify-dbg is not set +# CONFIG_libnotify-dev is not set + +# +# libnss-mdns +# +# CONFIG_libnss-mdns is not set +# CONFIG_libnss-mdns-dbg is not set +# CONFIG_libnss-mdns-dev is not set + +# +# libogg +# +# CONFIG_libogg is not set +# CONFIG_libogg-dev is not set +# CONFIG_libogg-dbg is not set + +# +# libpciaccess +# +# CONFIG_libpciaccess is not set +# CONFIG_libpciaccess-dbg is not set +# CONFIG_libpciaccess-dev is not set + +# +# libpng +# +# CONFIG_libpng is not set +# CONFIG_libpng-dev is not set +# CONFIG_libpng-dbg is not set +# CONFIG_libpng-tools is not set + +# +# libproxy +# +# CONFIG_libproxy is not set +# CONFIG_libproxy-dev is not set +# CONFIG_libproxy-dbg is not set + +# +# libsamplerate0 +# +# CONFIG_libsamplerate0 is not set +# CONFIG_libsamplerate0-dbg is not set +# CONFIG_libsamplerate0-dev is not set + +# +# libsecret +# +# CONFIG_libsecret is not set +# CONFIG_libsecret-dbg is not set +# CONFIG_libsecret-dev is not set + +# +# libsm +# +# CONFIG_libsm is not set +# CONFIG_libsm-dev is not set +# CONFIG_libsm-dbg is not set + +# +# libtasn1 +# +# CONFIG_libtasn1 is not set +# CONFIG_libtasn1-bin is not set +# CONFIG_libtasn1-dev is not set +# CONFIG_libtasn1-dbg is not set + +# +# libtheora +# +# CONFIG_libtheora is not set +# CONFIG_libtheora-dbg is not set +# CONFIG_libtheora-dev is not set + +# +# libtool +# +# CONFIG_libtool is not set +# CONFIG_libtool-dbg is not set +# CONFIG_libltdl is not set +# CONFIG_libtool-dev is not set + +# +# liburcu +# +# CONFIG_liburcu is not set +# CONFIG_liburcu-dev is not set +# CONFIG_liburcu-dbg is not set + +# +# libusb-compat +# +# CONFIG_libusb-compat is not set +# CONFIG_libusb-compat-dev is not set +# CONFIG_libusb-compat-dbg is not set + +# +# libusb1 +# +# CONFIG_libusb1 is not set +# CONFIG_libusb1-dbg is not set +# CONFIG_libusb1-dev is not set + +# +# libvorbis +# +# CONFIG_libvorbis is not set +# CONFIG_libvorbis-dbg is not set +# CONFIG_libvorbis-dev is not set + +# +# libwebp +# +# CONFIG_libwebp is not set +# CONFIG_libwebp-bin is not set +# CONFIG_libwebp-dev is not set +# CONFIG_libwebp-dbg is not set + +# +# libx11 +# +# CONFIG_libx11 is not set +# CONFIG_libx11-dbg is not set +# CONFIG_libx11-xcb is not set +# CONFIG_libx11-dev is not set + +# +# libxau +# +# CONFIG_libxau is not set +# CONFIG_libxau-dbg is not set +# CONFIG_libxau-dev is not set + +# +# libxcomposite +# +# CONFIG_libxcomposite is not set +# CONFIG_libxcomposite-dbg is not set +# CONFIG_libxcomposite-dev is not set + +# +# libxcursor +# +# CONFIG_libxcursor is not set +# CONFIG_libxcursor-dev is not set +# CONFIG_libxcursor-dbg is not set + +# +# libxdamage +# +# CONFIG_libxdamage is not set +# CONFIG_libxdamage-dev is not set +# CONFIG_libxdamage-dbg is not set + +# +# libxdmcp +# +# CONFIG_libxdmcp is not set +# CONFIG_libxdmcp-dev is not set +# CONFIG_libxdmcp-dbg is not set + +# +# libxext +# +# CONFIG_libxext is not set +# CONFIG_libxext-dbg is not set +# CONFIG_libxext-dev is not set + +# +# libxfixes +# +# CONFIG_libxfixes is not set +# CONFIG_libxfixes-dev is not set +# CONFIG_libxfixes-dbg is not set + +# +# libxfont +# +# CONFIG_libxfont is not set +# CONFIG_libxfont-dev is not set +# CONFIG_libxfont-dbg is not set + +# +# libxft +# +# CONFIG_libxft is not set +# CONFIG_libxft-dev is not set +# CONFIG_libxft-dbg is not set + +# +# libxi +# +# CONFIG_libxi is not set +# CONFIG_libxi-dbg is not set +# CONFIG_libxi-dev is not set + +# +# libxinerama +# +# CONFIG_libxinerama is not set +# CONFIG_libxinerama-dbg is not set +# CONFIG_libxinerama-dev is not set + +# +# libxkbcommon +# +# CONFIG_libxkbcommon is not set +# CONFIG_libxkbcommon-dbg is not set +# CONFIG_libxkbcommon-dev is not set + +# +# libxkbfile +# +# CONFIG_libxkbfile is not set +# CONFIG_libxkbfile-dbg is not set +# CONFIG_libxkbfile-dev is not set + +# +# libxml-parser-perl +# +# CONFIG_libxml-parser-perl is not set +# CONFIG_libxml-parser-perl-dbg is not set +# CONFIG_libxml-parser-perl-dev is not set + +# +# libxml2 +# +# CONFIG_libxml2 is not set +# CONFIG_libxml2-dbg is not set +# CONFIG_libxml2-dev is not set +# CONFIG_libxml2-python is not set + +# +# libxmu +# +# CONFIG_libxmu is not set +# CONFIG_libxmu-dev is not set +# CONFIG_libxmu-dbg is not set +# CONFIG_libxmuu is not set + +# +# libxrandr +# +# CONFIG_libxrandr is not set +# CONFIG_libxrandr-dev is not set +# CONFIG_libxrandr-dbg is not set + +# +# libxrender +# +# CONFIG_libxrender is not set +# CONFIG_libxrender-dev is not set +# CONFIG_libxrender-dbg is not set + +# +# libxres +# +# CONFIG_libxres is not set +# CONFIG_libxres-dev is not set +# CONFIG_libxres-dbg is not set + +# +# libxslt +# +# CONFIG_libxslt is not set +# CONFIG_libxslt-dev is not set +# CONFIG_libxslt-bin is not set +# CONFIG_libxslt-dbg is not set + +# +# libxt +# +# CONFIG_libxt is not set +# CONFIG_libxt-dbg is not set +# CONFIG_libxt-dev is not set + +# +# libxtst +# +# CONFIG_libxtst is not set +# CONFIG_libxtst-dev is not set +# CONFIG_libxtst-dbg is not set + +# +# libxv +# +# CONFIG_libxv is not set +# CONFIG_libxv-dbg is not set +# CONFIG_libxv-dev is not set + +# +# libxxf86vm +# +# CONFIG_libxxf86vm is not set +# CONFIG_libxxf86vm-dbg is not set +# CONFIG_libxxf86vm-dev is not set + +# +# lzo +# +# CONFIG_lzo is not set +# CONFIG_lzo-dbg is not set +# CONFIG_lzo-dev is not set + +# +# mtdev +# +# CONFIG_mtdev is not set +# CONFIG_mtdev-dbg is not set +# CONFIG_mtdev-dev is not set + +# +# multimedia +# + +# +# alsa-lib +# +# CONFIG_alsa-lib is not set +# CONFIG_alsa-lib-dbg is not set +# CONFIG_alsa-lib-dev is not set +# CONFIG_alsa-server is not set +# CONFIG_libasound is not set +# CONFIG_alsa-conf-base is not set +# CONFIG_alsa-conf is not set +# CONFIG_alsa-oss is not set + +# +# libsndfile1 +# +# CONFIG_libsndfile1 is not set +# CONFIG_libsndfile1-dbg is not set +# CONFIG_libsndfile1-dev is not set +# CONFIG_libsndfile1-bin is not set + +# +# pulseaudio +# +# CONFIG_pulseaudio is not set +# CONFIG_pulseaudio-misc is not set +# CONFIG_libpulse-mainloop-glib is not set +# CONFIG_pulseaudio-dbg is not set +# CONFIG_libpulsecommon is not set +# CONFIG_pulseaudio-module-console-kit is not set +# CONFIG_pulseaudio-bash-completion is not set +# CONFIG_libpulse-simple is not set +# CONFIG_libpulsecore is not set +# CONFIG_libpulse is not set +# CONFIG_pulseaudio-dev is not set +# CONFIG_pulseaudio-server is not set + +# +# taglib +# +# CONFIG_taglib is not set +# CONFIG_taglib-dev is not set +# CONFIG_taglib-c is not set +# CONFIG_taglib-dbg is not set + +# +# ncurses +# +# CONFIG_ncurses is not set +# CONFIG_ncurses-terminfo-base is not set +# CONFIG_ncurses-dev is not set +# CONFIG_ncurses-tools is not set +# CONFIG_ncurses-terminfo is not set +# CONFIG_ncurses-dbg is not set + +# +# neon +# +# CONFIG_neon is not set +# CONFIG_neon-dev is not set +# CONFIG_neon-dbg is not set + +# +# nettle +# +# CONFIG_nettle is not set +# CONFIG_nettle-dev is not set +# CONFIG_nettle-dbg is not set + +# +# network +# + +# +# libnl +# +# CONFIG_libnl is not set +# CONFIG_libnl-xfrm is not set +# CONFIG_libnl-nf is not set +# CONFIG_libnl-dev is not set +# CONFIG_libnl-cli is not set +# CONFIG_libnl-dbg is not set +# CONFIG_libnl-route is not set +# CONFIG_libnl-idiag is not set +# CONFIG_libnl-genl is not set + +# +# libpcap +# +# CONFIG_libpcap is not set +# CONFIG_libpcap-dev is not set +# CONFIG_libpcap-dbg is not set + +# +# libsocketcan +# +# CONFIG_libsocketcan is not set +# CONFIG_libsocketcan-dbg is not set +# CONFIG_libsocketcan-dev is not set + +# +# libtirpc +# +# CONFIG_libtirpc is not set +# CONFIG_libtirpc-dev is not set +# CONFIG_libtirpc-dbg is not set + +# +# openssl +# +# CONFIG_openssl is not set +# CONFIG_openssl-bin is not set +# CONFIG_openssl-conf is not set +# CONFIG_openssl-dbg is not set +# CONFIG_openssl-engines is not set +# CONFIG_libcrypto is not set +# CONFIG_openssl-dev is not set +# CONFIG_openssl-misc is not set +# CONFIG_libssl is not set + +# +# open-amp +# +# CONFIG_open-amp is not set +# CONFIG_open-amp-dbg is not set +# CONFIG_open-amp-dev is not set + +# +# opencv +# +# CONFIG_opencv is not set +# CONFIG_opencv-dev is not set +# CONFIG_opencv-apps is not set +# CONFIG_opencv-samples is not set +# CONFIG_opencv-dbg is not set + +# +# pango +# +# CONFIG_pango is not set +# CONFIG_pango-dbg is not set +# CONFIG_pango-dev is not set + +# +# popt +# +# CONFIG_popt is not set +# CONFIG_popt-dbg is not set +# CONFIG_popt-dev is not set + +# +# readline +# +# CONFIG_readline is not set +# CONFIG_readline-dev is not set +# CONFIG_readline-dbg is not set + +# +# sbc +# +# CONFIG_sbc is not set +# CONFIG_sbc-dev is not set +# CONFIG_sbc-dbg is not set + +# +# slang +# +# CONFIG_slang is not set +# CONFIG_slang-dev is not set +# CONFIG_slang-dbg is not set + +# +# speex +# +# CONFIG_speex is not set +# CONFIG_speex-dev is not set +# CONFIG_speex-dbg is not set + +# +# speexdsp +# +# CONFIG_speexdsp is not set +# CONFIG_speexdsp-dev is not set +# CONFIG_speexdsp-dbg is not set + +# +# sqlite3 +# +# CONFIG_sqlite3 is not set +# CONFIG_libsqlite3 is not set +# CONFIG_sqlite3-dbg is not set +# CONFIG_libsqlite3-dev is not set + +# +# startup-notification +# +# CONFIG_startup-notification is not set +# CONFIG_startup-notification-dev is not set +# CONFIG_startup-notification-dbg is not set + +# +# tremor +# +# CONFIG_tremor is not set +# CONFIG_tremor-dev is not set +# CONFIG_tremor-dbg is not set + +# +# which +# +# CONFIG_which is not set +# CONFIG_which-dev is not set +# CONFIG_which-dbg is not set + +# +# xrt +# +# CONFIG_xrt is not set +# CONFIG_xrt-dev is not set +# CONFIG_xrt-dbg is not set + +# +# zocl +# +# CONFIG_zocl is not set +# CONFIG_zocl-dev is not set +# CONFIG_zocl-dbg is not set + +# +# opencl-clhpp +# +# CONFIG_opencl-clhpp-dev is not set + +# +# opencl-headers +# +# CONFIG_opencl-headers is not set + +# +# protobuf +# +# CONFIG_protobuf is not set + +# +# zlib +# +# CONFIG_zlib is not set +# CONFIG_zlib-dbg is not set +# CONFIG_zlib-dev is not set + +# +# misc +# + +# +# alsa-state +# +# CONFIG_alsa-state is not set +# CONFIG_alsa-state-dev is not set +# CONFIG_alsa-state-dbg is not set +# CONFIG_alsa-states is not set + +# +# apache2 +# +# CONFIG_apache2 is not set +# CONFIG_apache2-dbg is not set +# CONFIG_apache2-dev is not set + +# +# at-spi2-atk +# +# CONFIG_at-spi2-atk is not set +# CONFIG_at-spi2-atk-dbg is not set +# CONFIG_at-spi2-atk-gnome is not set +# CONFIG_at-spi2-atk-dev is not set +# CONFIG_at-spi2-atk-gtk2 is not set + +# +# at-spi2-core +# +# CONFIG_at-spi2-core is not set +# CONFIG_at-spi2-core-dev is not set +# CONFIG_at-spi2-core-dbg is not set + +# +# babeltrace +# +# CONFIG_babeltrace is not set +# CONFIG_babeltrace-dev is not set +# CONFIG_babeltrace-dbg is not set + +# +# blktool +# +# CONFIG_blktool is not set +# CONFIG_blktool-dev is not set +# CONFIG_blktool-dbg is not set + +# +# blktrace +# +# CONFIG_blktrace is not set +# CONFIG_blktrace-dbg is not set +# CONFIG_blktrace-dev is not set + +# +# ca-certificates +# +# CONFIG_ca-certificates is not set +# CONFIG_ca-certificates-dev is not set +# CONFIG_ca-certificates-dbg is not set + +# +# chrpath +# +# CONFIG_chrpath is not set +# CONFIG_chrpath-dev is not set +# CONFIG_chrpath-dbg is not set + +# +# connman +# +# CONFIG_connman is not set +# CONFIG_connman-tests is not set +# CONFIG_connman-dev is not set +# CONFIG_connman-dbg is not set +# CONFIG_connman-tools is not set +# CONFIG_connman-wait-online is not set +# CONFIG_connman-client is not set + +# +# connman-conf +# +# CONFIG_connman-conf-dbg is not set + +# +# consolekit +# +# CONFIG_consolekit is not set +# CONFIG_consolekit-dbg is not set +# CONFIG_consolekit-dev is not set + +# +# coreutils +# +# CONFIG_coreutils is not set +# CONFIG_coreutils-dev is not set +# CONFIG_coreutils-dbg is not set + +# +# cpufrequtils +# +# CONFIG_cpufrequtils is not set +# CONFIG_cpufrequtils-dev is not set +# CONFIG_cpufrequtils-dbg is not set + +# +# cryptodev-linux +# +# CONFIG_cryptodev-linux is not set +# CONFIG_cryptodev-linux-dev is not set +# CONFIG_cryptodev-linux-dbg is not set + +# +# encodings +# +# CONFIG_encodings is not set +# CONFIG_encodings-dev is not set +# CONFIG_encodings-dbg is not set + +# +# epiphany +# +# CONFIG_epiphany is not set +# CONFIG_epiphany-dbg is not set +# CONFIG_epiphany-dev is not set + +# +# libudev +# +# CONFIG_libudev is not set +CONFIG_udev-extraconf=y +CONFIG_linux-xlnx-udev-rules=y + +# +# fbset +# +# CONFIG_fbset is not set +# CONFIG_fbset-dbg is not set +# CONFIG_fbset-dev is not set + +# +# fbset-modes +# +# CONFIG_fbset-modes is not set +# CONFIG_fbset-modes-dev is not set +# CONFIG_fbset-modes-dbg is not set + +# +# font-util +# +# CONFIG_font-util is not set +# CONFIG_font-util-dev is not set +# CONFIG_font-util-dbg is not set + +# +# gcc-runtime +# +# CONFIG_libstdcPLUSPLUS is not set +# CONFIG_libstdcPLUSPLUS-dev is not set + +# +# gcc-sanitizers +# +# CONFIG_gcc-sanitizers is not set +# CONFIG_libubsan-dev is not set +# CONFIG_libubsan is not set +# CONFIG_gcc-sanitizers-dbg is not set +# CONFIG_libasan is not set +# CONFIG_libasan-dev is not set + +# +# gcr +# +# CONFIG_gcr is not set +# CONFIG_gcr-dev is not set +# CONFIG_gcr-dbg is not set + +# +# gdb +# +# CONFIG_gdb is not set +# CONFIG_gdb-dbg is not set +# CONFIG_gdb-dev is not set +# CONFIG_gdbserver is not set + +# +# glib-2.0 +# +# CONFIG_glib-2.0 is not set +# CONFIG_glib-2.0-codegen is not set +# CONFIG_glib-2.0-utils is not set +# CONFIG_glib-2.0-dbg is not set +# CONFIG_glib-2.0-bash-completion is not set +# CONFIG_glib-2.0-dev is not set + +# +# glibc +# +# CONFIG_glibc is not set +# CONFIG_glibc-dev is not set +# CONFIG_glibc-dbg is not set +# CONFIG_ldd is not set + +# +# gnome-desktop-testing +# +# CONFIG_gnome-desktop-testing is not set +# CONFIG_gnome-desktop-testing-dbg is not set +# CONFIG_gnome-desktop-testing-dev is not set + +# +# gnutls +# +# CONFIG_gnutls is not set +# CONFIG_gnutls-dev is not set +# CONFIG_gnutls-dbg is not set +# CONFIG_gnutls-bin is not set +# CONFIG_gnutls-xx is not set +# CONFIG_gnutls-openssl is not set + +# +# gsettings-desktop-schemas +# +# CONFIG_gsettings-desktop-schemas is not set +# CONFIG_gsettings-desktop-schemas-dev is not set +# CONFIG_gsettings-desktop-schemas-dbg is not set + +# +# gst-player +# +# CONFIG_gst-player is not set + +# +# gstreamer1.0-plugins-bad +# +# CONFIG_gstreamer1.0-plugins-bad is not set +# CONFIG_gstreamer1.0-plugins-bad-meta is not set +# CONFIG_gstreamer1.0-plugins-bad-dev is not set +# CONFIG_gstreamer1.0-plugins-bad-dbg is not set + +# +# gstreamer1.0-plugins-base +# +# CONFIG_gstreamer1.0-plugins-base is not set +# CONFIG_gstreamer1.0-plugins-base-dev is not set +# CONFIG_gstreamer1.0-plugins-base-apps is not set +# CONFIG_gstreamer1.0-plugins-base-meta is not set +# CONFIG_gstreamer1.0-plugins-base-dbg is not set + +# +# gstreamer1.0-plugins-good +# +# CONFIG_gstreamer1.0-plugins-good is not set +# CONFIG_gstreamer1.0-plugins-good-meta is not set +# CONFIG_gstreamer1.0-plugins-good-dev is not set +# CONFIG_gstreamer1.0-plugins-good-dbg is not set + +# +# hicolor-icon-theme +# +# CONFIG_hicolor-icon-theme is not set +# CONFIG_hicolor-icon-theme-dbg is not set +# CONFIG_hicolor-icon-theme-dev is not set + +# +# icu +# +# CONFIG_icu is not set +# CONFIG_libicudata is not set +# CONFIG_libicuio is not set +# CONFIG_libicui18n is not set +# CONFIG_icu-dbg is not set +# CONFIG_libicuuc is not set +# CONFIG_libicutu is not set +# CONFIG_icu-dev is not set + +# +# iotop +# +# CONFIG_iotop is not set +# CONFIG_iotop-dev is not set +# CONFIG_iotop-dbg is not set + +# +# iptables +# +# CONFIG_iptables is not set +# CONFIG_iptables-dbg is not set +# CONFIG_iptables-dev is not set + +# +# iso-codes +# +# CONFIG_iso-codes is not set +# CONFIG_iso-codes-dbg is not set +# CONFIG_iso-codes-dev is not set + +# +# json-c +# +# CONFIG_json-c is not set +# CONFIG_json-c-dbg is not set +# CONFIG_json-c-dev is not set + +# +# l3afpad +# +# CONFIG_l3afpad is not set +# CONFIG_l3afpad-dev is not set +# CONFIG_l3afpad-dbg is not set + +# +# lttng-ust +# +# CONFIG_lttng-ust is not set +# CONFIG_lttng-ust-dbg is not set +# CONFIG_lttng-ust-bin is not set +# CONFIG_lttng-ust-dev is not set + +# +# m4 +# +# CONFIG_m4 is not set +# CONFIG_m4-dbg is not set +# CONFIG_m4-dev is not set + +# +# matchbox-config-gtk +# +# CONFIG_matchbox-config-gtk is not set +# CONFIG_matchbox-config-gtk-dev is not set +# CONFIG_matchbox-config-gtk-dbg is not set + +# +# matchbox-panel-2 +# +# CONFIG_matchbox-panel-2 is not set +# CONFIG_matchbox-panel-2-dbg is not set +# CONFIG_matchbox-panel-2-dev is not set + +# +# mdadm +# +# CONFIG_mdadm is not set +# CONFIG_mdadm-dbg is not set +# CONFIG_mdadm-dev is not set + +# +# mkfontdir +# +# CONFIG_mkfontdir is not set + +# +# mkfontscale +# +# CONFIG_mkfontscale is not set +# CONFIG_mkfontscale-dbg is not set +# CONFIG_mkfontscale-dev is not set + +# +# net-tools +# +# CONFIG_net-tools is not set +# CONFIG_net-tools-dbg is not set +# CONFIG_net-tools-dev is not set + +# +# nicstat +# +# CONFIG_nicstat is not set +# CONFIG_nicstat-dbg is not set +# CONFIG_nicstat-dev is not set + +# +# ofono +# +# CONFIG_ofono is not set +# CONFIG_ofono-tests is not set +# CONFIG_ofono-dev is not set +# CONFIG_ofono-dbg is not set + +# +# openamp-fw-echo-testd +# +# CONFIG_openamp-fw-echo-testd is not set +# CONFIG_openamp-fw-echo-testd-dev is not set +# CONFIG_openamp-fw-echo-testd-dbg is not set + +# +# openamp-fw-mat-muld +# +# CONFIG_openamp-fw-mat-muld is not set +# CONFIG_openamp-fw-mat-muld-dev is not set +# CONFIG_openamp-fw-mat-muld-dbg is not set + +# +# openamp-fw-rpc-demo +# +# CONFIG_openamp-fw-rpc-demo is not set +# CONFIG_openamp-fw-rpc-demo-dev is not set +# CONFIG_openamp-fw-rpc-demo-dbg is not set + +# +# opkg-arch-config +# +# CONFIG_opkg-arch-config is not set +# CONFIG_opkg-arch-config-dbg is not set +# CONFIG_opkg-arch-config-dev is not set + +# +# orc +# +# CONFIG_orc is not set +# CONFIG_orc-dbg is not set +# CONFIG_orc-dev is not set + +# +# p11-kit +# +# CONFIG_p11-kit is not set +# CONFIG_p11-kit-dev is not set +# CONFIG_p11-kit-dbg is not set + +# +# packagegroup-core-boot +# +CONFIG_packagegroup-core-boot=y +# CONFIG_packagegroup-core-boot-dev is not set +# CONFIG_packagegroup-core-boot-dbg is not set + +# +# packagegroup-core-buildessential +# +# CONFIG_packagegroup-core-buildessential is not set +# CONFIG_packagegroup-core-buildessential-dev is not set +# CONFIG_packagegroup-core-buildessential-dbg is not set + +# +# packagegroup-core-sdk +# +# CONFIG_packagegroup-core-sdk is not set +# CONFIG_packagegroup-core-sdk-dbg is not set +# CONFIG_packagegroup-core-sdk-dev is not set + +# +# packagegroup-core-ssh-dropbear +# +CONFIG_packagegroup-core-ssh-dropbear=y +# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set +# CONFIG_packagegroup-core-ssh-dropbear-dev is not set + +# +# packagegroup-core-standalone-sdk-target +# +# CONFIG_packagegroup-core-standalone-sdk-target is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dev is not set +# CONFIG_packagegroup-core-standalone-sdk-target-dbg is not set + +# +# packagegroup-core-tools-debug +# +# CONFIG_packagegroup-core-tools-debug is not set +# CONFIG_packagegroup-core-tools-debug-dev is not set +# CONFIG_packagegroup-core-tools-debug-dbg is not set + +# +# packagegroup-core-tools-profile +# +# CONFIG_packagegroup-core-tools-profile is not set +# CONFIG_packagegroup-core-tools-profile-dbg is not set +# CONFIG_packagegroup-core-tools-profile-dev is not set + +# +# packagegroup-core-tools-testapps +# +# CONFIG_packagegroup-core-tools-testapps is not set +# CONFIG_packagegroup-core-tools-testapps-dbg is not set +# CONFIG_packagegroup-core-tools-testapps-dev is not set + +# +# packagegroup-core-x11 +# +# CONFIG_packagegroup-core-x11 is not set +# CONFIG_packagegroup-core-x11-dbg is not set +# CONFIG_packagegroup-core-x11-utils-dbg is not set +# CONFIG_packagegroup-core-x11-dev is not set +# CONFIG_packagegroup-core-x11-utils is not set +# CONFIG_packagegroup-core-x11-utils-dev is not set + +# +# packagegroup-core-x11-base +# +# CONFIG_packagegroup-core-x11-base is not set +# CONFIG_packagegroup-core-x11-base-dev is not set +# CONFIG_packagegroup-core-x11-base-dbg is not set + +# +# packagegroup-core-x11-xserver +# +# CONFIG_packagegroup-core-x11-xserver is not set +# CONFIG_packagegroup-core-x11-xserver-dev is not set +# CONFIG_packagegroup-core-x11-xserver-dbg is not set + +# +# packagegroup-self-hosted +# +# CONFIG_packagegroup-self-hosted is not set +# CONFIG_packagegroup-self-hosted-extended-dev is not set +# CONFIG_packagegroup-self-hosted-debug-dev is not set +# CONFIG_packagegroup-self-hosted-dev is not set +# CONFIG_packagegroup-self-hosted-extended-dbg is not set +# CONFIG_packagegroup-self-hosted-sdk-dev is not set +# CONFIG_packagegroup-self-hosted-dbg is not set +# CONFIG_packagegroup-self-hosted-graphics-dev is not set +# CONFIG_packagegroup-self-hosted-sdk is not set +# CONFIG_packagegroup-self-hosted-debug is not set +# CONFIG_packagegroup-self-hosted-host-tools is not set +# CONFIG_packagegroup-self-hosted-debug-dbg is not set +# CONFIG_packagegroup-self-hosted-extended is not set +# CONFIG_packagegroup-self-hosted-host-tools-dev is not set +# CONFIG_packagegroup-self-hosted-graphics-dbg is not set +# CONFIG_packagegroup-self-hosted-sdk-dbg is not set +# CONFIG_packagegroup-self-hosted-host-tools-dbg is not set +# CONFIG_packagegroup-self-hosted-graphics is not set + +# +# perf +# +# CONFIG_perf is not set +# CONFIG_perf-tests is not set +# CONFIG_perf-python is not set +# CONFIG_perf-dbg is not set +# CONFIG_perf-dev is not set + +# +# pixman +# +# CONFIG_pixman is not set +# CONFIG_pixman-dbg is not set +# CONFIG_pixman-dev is not set + +# +# powertop +# +# CONFIG_powertop is not set +# CONFIG_powertop-dev is not set +# CONFIG_powertop-dbg is not set + +# +# ptest-runner +# +# CONFIG_ptest-runner is not set +# CONFIG_ptest-runner-dev is not set +# CONFIG_ptest-runner-dbg is not set + +# +# python3 +# +# CONFIG_python3 is not set +# CONFIG_python3-smtpd is not set +# CONFIG_python3-syslog is not set +# CONFIG_python3-pickle is not set +# CONFIG_python3-dbg is not set +# CONFIG_python3-db is not set +# CONFIG_python3-fcntl is not set +# CONFIG_python3-html is not set +# CONFIG_python3-core is not set +# CONFIG_python3-distutils is not set +# CONFIG_python3-terminal is not set +# CONFIG_python3-pprint is not set +# CONFIG_python3-tkinter is not set +# CONFIG_python3-unixadmin is not set +# CONFIG_python3-mime is not set +# CONFIG_python3-logging is not set +# CONFIG_python3-resource is not set +# CONFIG_python3-email is not set +# CONFIG_python3-math is not set +# CONFIG_python3-json is not set +# CONFIG_python3-image is not set +# CONFIG_python3-stringold is not set +# CONFIG_python3-pydoc is not set +# CONFIG_python3-codecs is not set +# CONFIG_python3-debugger is not set +# CONFIG_python3-xmlrpc is not set +# CONFIG_python3-io is not set +# CONFIG_python3-pkgutil is not set +# CONFIG_python3-idle is not set +# CONFIG_python3-difflib is not set +# CONFIG_python3-unittest is not set +# CONFIG_python3-netserver is not set +# CONFIG_python3-netclient is not set +# CONFIG_python3-gdbm is not set +# CONFIG_python3-profile is not set +# CONFIG_python3-sqlite3 is not set +# CONFIG_python3-2to3 is not set +# CONFIG_libpython3 is not set +# CONFIG_python3-xml is not set +# CONFIG_python3-threading is not set +# CONFIG_python3-modules is not set +# CONFIG_python3-dev is not set +# CONFIG_python3-curses is not set +# CONFIG_python3-multiprocessing is not set +# CONFIG_python3-crypt is not set +# CONFIG_python3-compression is not set +# CONFIG_python3-shell is not set +# CONFIG_python3-tests is not set +# CONFIG_python3-numbers is not set +# CONFIG_python3-audio is not set +# CONFIG_python3-pyvenv is not set +# CONFIG_python3-asyncio is not set +# CONFIG_python3-misc is not set +# CONFIG_python3-datetime is not set +# CONFIG_python3-compile is not set +# CONFIG_python3-mmap is not set +# CONFIG_python3-mailbox is not set +# CONFIG_python3-ctypes is not set + +# +# python3-async +# +# CONFIG_python3-async is not set +# CONFIG_python3-async-dev is not set +# CONFIG_python3-async-dbg is not set + +# +# python3-git +# +# CONFIG_python3-git is not set +# CONFIG_python3-git-dbg is not set +# CONFIG_python3-git-dev is not set + +# +# python3-gitdb +# +# CONFIG_python3-gitdb is not set +# CONFIG_python3-gitdb-dev is not set +# CONFIG_python3-gitdb-dbg is not set + +# +# python3-setuptools +# +# CONFIG_python3-setuptools is not set +# CONFIG_python3-setuptools-dev is not set +# CONFIG_python3-setuptools-dbg is not set + +# +# python3-smmap +# +# CONFIG_python3-smmap is not set +# CONFIG_python3-smmap-dbg is not set +# CONFIG_python3-smmap-dev is not set + +# +# qtbase +# +# CONFIG_qtbase is not set +# CONFIG_qtbase-tools is not set +# CONFIG_qtbase-plugins is not set +# CONFIG_qtbase-examples is not set +# CONFIG_qtbase-dbg is not set +# CONFIG_qtbase-dev is not set +# CONFIG_qtbase-mkspecs is not set + +# +# qtcharts +# +# CONFIG_qtcharts is not set +# CONFIG_qtcharts-mkspecs is not set +# CONFIG_qtcharts-dev is not set +# CONFIG_qtcharts-dbg is not set +# CONFIG_qtcharts-qmlplugins is not set +# CONFIG_qtcharts-qmldesigner is not set + +# +# qtconnectivity +# +# CONFIG_qtconnectivity is not set +# CONFIG_qtconnectivity-tools is not set +# CONFIG_qtconnectivity-mkspecs is not set +# CONFIG_qtconnectivity-dev is not set +# CONFIG_qtconnectivity-dbg is not set +# CONFIG_qtconnectivity-qmlplugins is not set + +# +# qtdeclarative +# +# CONFIG_qtdeclarative is not set +# CONFIG_qtdeclarative-dev is not set +# CONFIG_qtdeclarative-dbg is not set +# CONFIG_qtdeclarative-qmlplugins is not set +# CONFIG_qtdeclarative-tools is not set +# CONFIG_qtdeclarative-mkspecs is not set + +# +# qtimageformats +# +# CONFIG_qtimageformats is not set +# CONFIG_qtimageformats-plugins is not set +# CONFIG_qtimageformats-dbg is not set +# CONFIG_qtimageformats-dev is not set + +# +# qtlocation +# +# CONFIG_qtlocation is not set +# CONFIG_qtlocation-plugins is not set +# CONFIG_qtlocation-qmlplugins is not set +# CONFIG_qtlocation-dbg is not set +# CONFIG_qtlocation-dev is not set +# CONFIG_qtlocation-mkspecs is not set + +# +# qtmultimedia +# +# CONFIG_qtmultimedia is not set +# CONFIG_qtmultimedia-plugins is not set +# CONFIG_qtmultimedia-mkspecs is not set +# CONFIG_qtmultimedia-qmlplugins is not set +# CONFIG_qtmultimedia-dev is not set +# CONFIG_qtmultimedia-dbg is not set + +# +# qtquickcontrols +# +# CONFIG_qtquickcontrols is not set +# CONFIG_qtquickcontrols-dbg is not set +# CONFIG_qtquickcontrols-dev is not set +# CONFIG_qtquickcontrols-qmlplugins is not set +# CONFIG_qtquickcontrols-qmldesigner is not set + +# +# qtscript +# +# CONFIG_qtscript is not set +# CONFIG_qtscript-mkspecs is not set +# CONFIG_qtscript-dbg is not set +# CONFIG_qtscript-dev is not set + +# +# qtsensors +# +# CONFIG_qtsensors is not set +# CONFIG_qtsensors-dbg is not set +# CONFIG_qtsensors-mkspecs is not set +# CONFIG_qtsensors-dev is not set +# CONFIG_qtsensors-plugins is not set +# CONFIG_qtsensors-qmlplugins is not set + +# +# qtserialport +# +# CONFIG_qtserialport is not set +# CONFIG_qtserialport-mkspecs is not set +# CONFIG_qtserialport-dev is not set +# CONFIG_qtserialport-dbg is not set + +# +# qtsvg +# +# CONFIG_qtsvg is not set +# CONFIG_qtsvg-plugins is not set +# CONFIG_qtsvg-mkspecs is not set +# CONFIG_qtsvg-dbg is not set +# CONFIG_qtsvg-dev is not set + +# +# qtsystems +# +# CONFIG_qtsystems is not set +# CONFIG_qtsystems-dbg is not set +# CONFIG_qtsystems-tools is not set +# CONFIG_qtsystems-dev is not set +# CONFIG_qtsystems-qmlplugins is not set +# CONFIG_qtsystems-mkspecs is not set + +# +# qttools +# +# CONFIG_qttools is not set +# CONFIG_qttools-mkspecs is not set +# CONFIG_qttools-dbg is not set +# CONFIG_qttools-tools is not set +# CONFIG_qttools-plugins is not set +# CONFIG_qttools-dev is not set + +# +# qttranslations +# +# CONFIG_qttranslations is not set +# CONFIG_qttranslations-qthelp is not set +# CONFIG_qttranslations-assistant is not set +# CONFIG_qttranslations-qtwebsockets is not set +# CONFIG_qttranslations-qtquickcontrols2 is not set +# CONFIG_qttranslations-qtdeclarative is not set +# CONFIG_qttranslations-qtxmlpatterns is not set +# CONFIG_qttranslations-qtmultimedia is not set +# CONFIG_qttranslations-qtconnectivity is not set +# CONFIG_qttranslations-qtbase is not set +# CONFIG_qttranslations-qtserialport is not set +# CONFIG_qttranslations-linguist is not set +# CONFIG_qttranslations-dbg is not set +# CONFIG_qttranslations-qtlocation is not set +# CONFIG_qttranslations-qtscript is not set +# CONFIG_qttranslations-qtwebengine is not set +# CONFIG_qttranslations-designer is not set +# CONFIG_qttranslations-qtquickcontrols is not set +# CONFIG_qttranslations-dev is not set + +# +# qtwebchannel +# +# CONFIG_qtwebchannel is not set +# CONFIG_qtwebchannel-dev is not set +# CONFIG_qtwebchannel-dbg is not set +# CONFIG_qtwebchannel-qmlplugins is not set +# CONFIG_qtwebchannel-mkspecs is not set + +# +# qtwebkit +# +# CONFIG_qtwebkit is not set +# CONFIG_qtwebkit-qmlplugins is not set +# CONFIG_qtwebkit-dev is not set +# CONFIG_qtwebkit-dbg is not set +# CONFIG_qtwebkit-mkspecs is not set + +# +# qtwebsockets +# +# CONFIG_qtwebsockets is not set +# CONFIG_qtwebsockets-dev is not set +# CONFIG_qtwebsockets-qmlplugins is not set +# CONFIG_qtwebsockets-mkspecs is not set +# CONFIG_qtwebsockets-dbg is not set + +# +# qtxmlpatterns +# +# CONFIG_qtxmlpatterns is not set +# CONFIG_qtxmlpatterns-mkspecs is not set +# CONFIG_qtxmlpatterns-dbg is not set +# CONFIG_qtxmlpatterns-dev is not set +# CONFIG_qtxmlpatterns-tools is not set + +# +# rgb +# +# CONFIG_rgb is not set +# CONFIG_rgb-dbg is not set +# CONFIG_rgb-dev is not set + +# +# rpm +# +# CONFIG_rpm is not set +# CONFIG_rpm-build is not set +# CONFIG_rpm-dev is not set +# CONFIG_rpm-dbg is not set + +# +# rpmsg-echo-test +# +# CONFIG_rpmsg-echo-test is not set +# CONFIG_rpmsg-echo-test-dbg is not set +# CONFIG_rpmsg-echo-test-dev is not set + +# +# rpmsg-mat-mul +# +# CONFIG_rpmsg-mat-mul is not set +# CONFIG_rpmsg-mat-mul-dev is not set +# CONFIG_rpmsg-mat-mul-dbg is not set + +# +# rpmsg-proxy-app +# +# CONFIG_rpmsg-proxy-app is not set +# CONFIG_rpmsg-proxy-app-dev is not set +# CONFIG_rpmsg-proxy-app-dbg is not set + +# +# serf +# +# CONFIG_serf is not set +# CONFIG_serf-dev is not set +# CONFIG_serf-dbg is not set + +# +# sysfsutils +# +# CONFIG_sysfsutils is not set +# CONFIG_libsysfs is not set +# CONFIG_sysfsutils-dev is not set +# CONFIG_sysfsutils-dbg is not set + +# +# systemtap +# +# CONFIG_systemtap is not set +# CONFIG_systemtap-dev is not set +# CONFIG_systemtap-dbg is not set + +# +# sysvinit-inittab +# +# CONFIG_sysvinit-inittab is not set +# CONFIG_sysvinit-inittab-dbg is not set +# CONFIG_sysvinit-inittab-dev is not set + +# +# tbb +# +# CONFIG_tbb is not set +# CONFIG_tbb-dev is not set +# CONFIG_tbb-dbg is not set + +# +# tcf-agent +# +CONFIG_tcf-agent=y +# CONFIG_tcf-agent-dbg is not set +# CONFIG_tcf-agent-dev is not set + +# +# tiff +# +# CONFIG_tiff is not set +# CONFIG_tiff-dev is not set +# CONFIG_tiffxx is not set +# CONFIG_tiff-dbg is not set +# CONFIG_tiff-utils is not set + +# +# util-macros +# +# CONFIG_util-macros is not set +# CONFIG_util-macros-dbg is not set +# CONFIG_util-macros-dev is not set + +# +# v4l-utils +# +# CONFIG_v4l-utils is not set +# CONFIG_libv4l is not set +# CONFIG_ir-keytable is not set +# CONFIG_v4l-utils-dev is not set +# CONFIG_media-ctl is not set +# CONFIG_rc-keymaps is not set +# CONFIG_v4l-utils-dbg is not set +# CONFIG_libv4l-dev is not set + +# +# valgrind +# +# CONFIG_valgrind is not set +# CONFIG_valgrind-dbg is not set +# CONFIG_valgrind-dev is not set + +# +# vte +# +# CONFIG_vte is not set +# CONFIG_libvte is not set +# CONFIG_vte-dbg is not set +# CONFIG_vte-dev is not set + +# +# watchdog +# +# CONFIG_watchdog is not set +# CONFIG_watchdog-dbg is not set +# CONFIG_watchdog-keepalive is not set +# CONFIG_watchdog-dev is not set + +# +# watchdog-config +# +# CONFIG_watchdog-config is not set +# CONFIG_watchdog-config-dbg is not set +# CONFIG_watchdog-config-dev is not set + +# +# webkitgtk +# +# CONFIG_webkitgtk is not set +# CONFIG_webkitgtk-dbg is not set +# CONFIG_webkitgtk-dev is not set + +# +# x11perf +# +# CONFIG_x11perf is not set +# CONFIG_x11perf-dbg is not set +# CONFIG_x11perf-dev is not set + +# +# x264 +# +# CONFIG_x264 is not set +# CONFIG_x264-dbg is not set +# CONFIG_x264-dev is not set +# CONFIG_x264-bin is not set + +# +# xauth +# +# CONFIG_xauth is not set +# CONFIG_xauth-dbg is not set +# CONFIG_xauth-dev is not set + +# +# xcb-util-image +# +# CONFIG_xcb-util-image is not set +# CONFIG_xcb-util-image-dev is not set +# CONFIG_xcb-util-image-dbg is not set + +# +# xcb-util-keysyms +# +# CONFIG_xcb-util-keysyms is not set +# CONFIG_xcb-util-keysyms-dev is not set +# CONFIG_xcb-util-keysyms-dbg is not set + +# +# xcb-util-renderutil +# +# CONFIG_xcb-util-renderutil is not set +# CONFIG_xcb-util-renderutil-dbg is not set +# CONFIG_xcb-util-renderutil-dev is not set + +# +# xcb-util-wm +# +# CONFIG_xcb-util-wm is not set +# CONFIG_xcb-util-wm-dbg is not set +# CONFIG_xcb-util-wm-dev is not set + +# +# xdg-utils +# +# CONFIG_xdg-utils is not set +# CONFIG_xdg-utils-dbg is not set +# CONFIG_xdg-utils-dev is not set + +# +# xdpyinfo +# +# CONFIG_xdpyinfo is not set +# CONFIG_xdpyinfo-dev is not set +# CONFIG_xdpyinfo-dbg is not set + +# +# xf86-input-evdev +# +# CONFIG_xf86-input-evdev is not set +# CONFIG_xf86-input-evdev-dbg is not set +# CONFIG_xf86-input-evdev-dev is not set + +# +# xf86-input-keyboard +# +# CONFIG_xf86-input-keyboard is not set +# CONFIG_xf86-input-keyboard-dev is not set +# CONFIG_xf86-input-keyboard-dbg is not set + +# +# xf86-input-mouse +# +# CONFIG_xf86-input-mouse is not set +# CONFIG_xf86-input-mouse-dbg is not set +# CONFIG_xf86-input-mouse-dev is not set + +# +# xf86-video-fbdev +# +# CONFIG_xf86-video-fbdev is not set +# CONFIG_xf86-video-fbdev-dbg is not set +# CONFIG_xf86-video-fbdev-dev is not set + +# +# xhost +# +# CONFIG_xhost is not set +# CONFIG_xhost-dbg is not set +# CONFIG_xhost-dev is not set + +# +# xinetd +# +# CONFIG_xinetd is not set +# CONFIG_xinetd-dbg is not set +# CONFIG_xinetd-dev is not set + +# +# xinit +# +# CONFIG_xinit is not set +# CONFIG_xinit-dev is not set +# CONFIG_xinit-dbg is not set + +# +# xinput +# +# CONFIG_xinput is not set +# CONFIG_xinput-dev is not set +# CONFIG_xinput-dbg is not set + +# +# xinput-calibrator +# +# CONFIG_xinput-calibrator is not set +# CONFIG_xinput-calibrator-dbg is not set +# CONFIG_xinput-calibrator-dev is not set + +# +# xkbcomp +# +# CONFIG_xkbcomp is not set +# CONFIG_xkbcomp-dev is not set +# CONFIG_xkbcomp-dbg is not set + +# +# xmodmap +# +# CONFIG_xmodmap is not set +# CONFIG_xmodmap-dbg is not set +# CONFIG_xmodmap-dev is not set + +# +# xprop +# +# CONFIG_xprop is not set +# CONFIG_xprop-dbg is not set +# CONFIG_xprop-dev is not set + +# +# xrandr +# +# CONFIG_xrandr is not set +# CONFIG_xrandr-dbg is not set +# CONFIG_xrandr-dev is not set + +# +# xserver-common +# +# CONFIG_xserver-common is not set +# CONFIG_xserver-common-dev is not set +# CONFIG_xserver-common-dbg is not set + +# +# xset +# +# CONFIG_xset is not set +# CONFIG_xset-dbg is not set +# CONFIG_xset-dev is not set + +# +# xtrans +# +# CONFIG_xtrans-dev is not set +# CONFIG_xtrans-dbg is not set + +# +# xwininfo +# +# CONFIG_xwininfo is not set +# CONFIG_xwininfo-dev is not set +# CONFIG_xwininfo-dbg is not set + +# +# yavta +# +# CONFIG_yavta is not set +# CONFIG_yavta-dbg is not set +# CONFIG_yavta-dev is not set + +# +# multimedia +# + +# +# alsa-plugins +# +# CONFIG_alsa-plugins is not set +# CONFIG_alsa-plugins-dev is not set +# CONFIG_alsa-plugins-dbg is not set +# CONFIG_alsa-plugins-pulseaudio-conf is not set + +# +# gstreamer1.0 +# +# CONFIG_gstreamer1.0 is not set +# CONFIG_gstreamer1.0-dev is not set +# CONFIG_gstreamer1.0-dbg is not set + +# +# net +# + +# +# bridge-utils +# +CONFIG_bridge-utils=y +# CONFIG_bridge-utils-dbg is not set +# CONFIG_bridge-utils-dev is not set + +# +# net-snmp +# +# CONFIG_net-snmp is not set +# CONFIG_net-snmp-server-snmptrapd is not set +# CONFIG_net-snmp-libs is not set +# CONFIG_net-snmp-dev is not set +# CONFIG_net-snmp-client is not set +# CONFIG_net-snmp-mibs is not set +# CONFIG_net-snmp-dbg is not set +# CONFIG_net-snmp-server-snmpd is not set +# CONFIG_net-snmp-server is not set + +# +# netcat +# +# CONFIG_netcat is not set +# CONFIG_netcat-dbg is not set +# CONFIG_netcat-dev is not set + +# +# tcpdump +# +# CONFIG_tcpdump is not set +# CONFIG_tcpdump-dbg is not set +# CONFIG_tcpdump-dev is not set + +# +# network +# + +# +# avahi +# +# CONFIG_avahi-dbg is not set +# CONFIG_libavahi-glib is not set +# CONFIG_libavahi-client is not set +# CONFIG_libavahi-core is not set +# CONFIG_avahi-dev is not set +# CONFIG_avahi-dnsconfd is not set +# CONFIG_avahi-autoipd is not set +# CONFIG_avahi-utils is not set +# CONFIG_libavahi-common is not set +# CONFIG_avahi-daemon is not set +# CONFIG_libavahi-gobject is not set + +# +# mobile-broadband-provider-info +# +# CONFIG_mobile-broadband-provider-info is not set +# CONFIG_mobile-broadband-provider-info-dbg is not set +# CONFIG_mobile-broadband-provider-info-dev is not set + +# +# wpa-supplicant +# +# CONFIG_wpa-supplicant is not set +# CONFIG_wpa-supplicant-passphrase is not set +# CONFIG_wpa-supplicant-cli is not set +# CONFIG_wpa-supplicant-dev is not set +# CONFIG_wpa-supplicant-dbg is not set + +# +# ntp +# +# CONFIG_ntp is not set +# CONFIG_ntp-dev is not set +# CONFIG_ntp-dbg is not set + +# +# optional +# + +# +# libatomic-ops +# +# CONFIG_libatomic-ops is not set +# CONFIG_libatomic-ops-dbg is not set +# CONFIG_libatomic-ops-dev is not set + +# +# mtools +# +# CONFIG_mtools is not set +# CONFIG_mtools-dev is not set +# CONFIG_mtools-dbg is not set + +# +# utils +# + +# +# dosfstools +# +# CONFIG_dosfstools is not set +# CONFIG_dosfstools-dev is not set +# CONFIG_dosfstools-dbg is not set + +# +# patch +# +# CONFIG_patch is not set +# CONFIG_patch-dev is not set +# CONFIG_patch-dbg is not set + +# +# resize-part +# +# CONFIG_resize-part is not set +# CONFIG_resize-part-dbg is not set +# CONFIG_resize-part-dev is not set + +# +# u-boot-tools +# +CONFIG_u-boot-tools=y +# CONFIG_u-boot-tools-dbg is not set +# CONFIG_u-boot-tools-dev is not set + +# +# x11 +# + +# +# base +# + +# +# libdrm +# +# CONFIG_libdrm is not set +# CONFIG_libdrm-omap is not set +# CONFIG_libdrm-amdgpu is not set +# CONFIG_libdrm-dev is not set +# CONFIG_libdrm-dbg is not set +# CONFIG_libdrm-drivers is not set +# CONFIG_libdrm-nouveau is not set +# CONFIG_libdrm-tests is not set +# CONFIG_libdrm-freedreno is not set +# CONFIG_libdrm-radeon is not set +# CONFIG_libdrm-kms is not set + +# +# xcursor-transparent-theme +# +# CONFIG_xcursor-transparent-theme is not set +# CONFIG_xcursor-transparent-theme-dev is not set +# CONFIG_xcursor-transparent-theme-dbg is not set + +# +# xserver-xf86-config +# +# CONFIG_xserver-xf86-config is not set +# CONFIG_xserver-xf86-config-dbg is not set +# CONFIG_xserver-xf86-config-dev is not set + +# +# xserver-xorg +# +# CONFIG_xserver-xorg is not set +# CONFIG_xserver-xorg-extension-record is not set +# CONFIG_xserver-xorg-dev is not set +# CONFIG_xserver-xorg-extension-glx is not set +# CONFIG_xserver-xorg-extension-dbe is not set +# CONFIG_xserver-xorg-utils is not set +# CONFIG_xserver-xorg-module-libint10 is not set +# CONFIG_xserver-xorg-extension-dri2 is not set +# CONFIG_xserver-xorg-dbg is not set +# CONFIG_xf86-video-modesetting is not set +# CONFIG_xserver-xorg-module-exa is not set +# CONFIG_xserver-xorg-extension-extmod is not set +# CONFIG_xserver-xorg-extension-dri is not set +# CONFIG_xserver-xorg-xvfb is not set +# CONFIG_xserver-xorg-module-libwfb is not set + +# +# builder +# +# CONFIG_builder is not set +# CONFIG_builder-dev is not set +# CONFIG_builder-dbg is not set + +# +# fonts +# + +# +# liberation-fonts +# +# CONFIG_liberation-fonts is not set + +# +# glew +# +# CONFIG_glew is not set +# CONFIG_glew-dbg is not set +# CONFIG_glew-bin is not set +# CONFIG_glew-dev is not set + +# +# gnome +# + +# +# adwaita-icon-theme +# +# CONFIG_adwaita-icon-theme is not set +# CONFIG_adwaita-icon-theme-symbolic is not set +# CONFIG_adwaita-icon-theme-hires is not set +# CONFIG_adwaita-icon-theme-symbolic-hires is not set +# CONFIG_adwaita-icon-theme-cursors is not set + +# +# gconf +# +# CONFIG_gconf is not set +# CONFIG_gconf-dev is not set +# CONFIG_gconf-dbg is not set + +# +# gnome-common +# +# CONFIG_gnome-common is not set +# CONFIG_gnome-common-dbg is not set +# CONFIG_gnome-common-dev is not set + +# +# gnome-desktop3 +# +# CONFIG_gnome-desktop3 is not set +# CONFIG_gnome-desktop3-dbg is not set +# CONFIG_gnome-desktop3-dev is not set +# CONFIG_libgnome-desktop3 is not set + +# +# gnome-themes-standard +# +# CONFIG_gnome-theme-adwaita is not set + +# +# libsoup-2.4 +# +# CONFIG_libsoup-2.4 is not set +# CONFIG_libsoup-2.4-dev is not set +# CONFIG_libsoup-2.4-dbg is not set + +# +# libglu +# +# CONFIG_libglu is not set +# CONFIG_libglu-dbg is not set +# CONFIG_libglu-dev is not set + +# +# libs +# + +# +# atk +# +# CONFIG_atk is not set +# CONFIG_atk-dbg is not set +# CONFIG_atk-dev is not set + +# +# libfm +# +# CONFIG_libfm is not set +# CONFIG_libfm-mime is not set +# CONFIG_libfm-dev is not set +# CONFIG_libfm-dbg is not set + +# +# libfm-extra +# +# CONFIG_libfm-extra is not set +# CONFIG_libfm-extra-dev is not set +# CONFIG_libfm-extra-dbg is not set + +# +# libmatchbox +# +# CONFIG_libmatchbox is not set +# CONFIG_libmatchbox-dev is not set +# CONFIG_libmatchbox-dbg is not set + +# +# libpthread-stubs +# +# CONFIG_libpthread-stubs-dev is not set +# CONFIG_libpthread-stubs-dbg is not set + +# +# libwnck3 +# +# CONFIG_libwnck3 is not set +# CONFIG_libwnck3-dbg is not set +# CONFIG_libwnck3-dev is not set + +# +# libxcb +# +# CONFIG_libxcb is not set +# CONFIG_libxcb-dev is not set +# CONFIG_libxcb-dbg is not set + +# +# menu-cache +# +# CONFIG_menu-cache is not set +# CONFIG_menu-cache-dev is not set +# CONFIG_menu-cache-dbg is not set + +# +# xcb-proto +# +# CONFIG_xcb-proto-dev is not set +# CONFIG_python-xcbgen is not set +# CONFIG_xcb-proto-dbg is not set + +# +# xcb-util +# +# CONFIG_xcb-util is not set +# CONFIG_xcb-util-dev is not set +# CONFIG_xcb-util-dbg is not set + +# +# xkeyboard-config +# +# CONFIG_xkeyboard-config is not set +# CONFIG_xkeyboard-config-dbg is not set +# CONFIG_xkeyboard-config-dev is not set + +# +# matchbox-keyboard +# +# CONFIG_matchbox-keyboard is not set +# CONFIG_matchbox-keyboard-dbg is not set +# CONFIG_matchbox-keyboard-applet is not set +# CONFIG_matchbox-keyboard-dev is not set +# CONFIG_matchbox-keyboard-im is not set + +# +# matchbox-session +# +# CONFIG_matchbox-session is not set +# CONFIG_matchbox-session-dev is not set +# CONFIG_matchbox-session-dbg is not set + +# +# matchbox-session-sato +# +# CONFIG_matchbox-session-sato is not set +# CONFIG_matchbox-session-sato-dev is not set +# CONFIG_matchbox-session-sato-dbg is not set + +# +# mesa +# +# CONFIG_mesa is not set +# CONFIG_libgles2-mesa is not set +# CONFIG_libgbm is not set +# CONFIG_libegl-mesa is not set +# CONFIG_mesa-dbg is not set +# CONFIG_libgles1-mesa is not set +# CONFIG_libgl-mesa-dev is not set +# CONFIG_libegl-mesa-dev is not set +# CONFIG_mesa-megadriver is not set +# CONFIG_libgles2-mesa-dev is not set +# CONFIG_libgles1-mesa-dev is not set +# CONFIG_libglapi-dev is not set +# CONFIG_mesa-dev is not set +# CONFIG_libglapi is not set +# CONFIG_libgbm-dev is not set +# CONFIG_libgl-mesa is not set +# CONFIG_libgles3-mesa-dev is not set + +# +# mesa-demos +# +# CONFIG_mesa-demos is not set +# CONFIG_mesa-demos-dev is not set +# CONFIG_mesa-demos-dbg is not set + +# +# mini-x-session +# +# CONFIG_mini-x-session is not set +# CONFIG_mini-x-session-dbg is not set +# CONFIG_mini-x-session-dev is not set + +# +# pcmanfm +# +# CONFIG_pcmanfm is not set +# CONFIG_pcmanfm-dbg is not set +# CONFIG_pcmanfm-dev is not set + +# +# settings-daemon +# +# CONFIG_settings-daemon is not set +# CONFIG_settings-daemon-dev is not set +# CONFIG_settings-daemon-dbg is not set + +# +# utils +# + +# +# libcroco +# +# CONFIG_libcroco is not set +# CONFIG_libcroco-dbg is not set +# CONFIG_libcroco-dev is not set + +# +# librsvg +# +# CONFIG_librsvg is not set +# CONFIG_librsvg-gtk is not set +# CONFIG_librsvg-dbg is not set +# CONFIG_librsvg-dev is not set +# CONFIG_rsvg is not set + +# +# matchbox-terminal +# +# CONFIG_matchbox-terminal is not set +# CONFIG_matchbox-terminal-dbg is not set +# CONFIG_matchbox-terminal-dev is not set + +# +# xrestop +# +# CONFIG_xrestop is not set +# CONFIG_xrestop-dev is not set +# CONFIG_xrestop-dbg is not set + +# +# wm +# + +# +# libfakekey +# +# CONFIG_libfakekey is not set +# CONFIG_libfakekey-dev is not set +# CONFIG_libfakekey-dbg is not set + +# +# matchbox-desktop +# +# CONFIG_matchbox-desktop is not set +# CONFIG_matchbox-desktop-dev is not set +# CONFIG_matchbox-desktop-dbg is not set + +# +# matchbox-theme-sato +# +# CONFIG_matchbox-theme-sato is not set +# CONFIG_matchbox-theme-sato-dev is not set +# CONFIG_matchbox-theme-sato-dbg is not set + +# +# matchbox-wm +# +# CONFIG_matchbox-wm is not set +# CONFIG_matchbox-wm-dbg is not set +# CONFIG_matchbox-wm-dev is not set + +# +# xserver-nodm-init +# +# CONFIG_xserver-nodm-init is not set +# CONFIG_xserver-nodm-init-dbg is not set +# CONFIG_xserver-nodm-init-dev is not set + +# +# Petalinux Package Groups +# + +# +# packagegroup-petalinux +# +CONFIG_packagegroup-petalinux=y +# CONFIG_packagegroup-petalinux-dev is not set +# CONFIG_packagegroup-petalinux-dbg is not set + +# +# packagegroup-petalinux-audio +# +# CONFIG_packagegroup-petalinux-audio is not set +# CONFIG_packagegroup-petalinux-audio-dbg is not set +# CONFIG_packagegroup-petalinux-audio-dev is not set + +# +# packagegroup-petalinux-display-debug +# +# CONFIG_packagegroup-petalinux-display-debug is not set +# CONFIG_packagegroup-petalinux-display-debug-dbg is not set +# CONFIG_packagegroup-petalinux-display-debug-dev is not set + +# +# packagegroup-petalinux-lmsensors +# +CONFIG_packagegroup-petalinux-lmsensors=y +# CONFIG_packagegroup-petalinux-lmsensors-dbg is not set +# CONFIG_packagegroup-petalinux-lmsensors-dev is not set + +# +# packagegroup-petalinux-matchbox +# +# CONFIG_packagegroup-petalinux-matchbox is not set +# CONFIG_packagegroup-petalinux-matchbox-dbg is not set +# CONFIG_packagegroup-petalinux-matchbox-dev is not set + +# +# packagegroup-petalinux-networking-debug +# +# CONFIG_packagegroup-petalinux-networking-debug is not set +# CONFIG_packagegroup-petalinux-networking-debug-dbg is not set +# CONFIG_packagegroup-petalinux-networking-debug-dev is not set + +# +# packagegroup-petalinux-networking-stack +# +CONFIG_packagegroup-petalinux-networking-stack=y +# CONFIG_packagegroup-petalinux-networking-stack-dbg is not set +# CONFIG_packagegroup-petalinux-networking-stack-dev is not set + +# +# packagegroup-petalinux-openamp +# +CONFIG_packagegroup-petalinux-openamp=y +# CONFIG_packagegroup-petalinux-openamp-dbg is not set +# CONFIG_packagegroup-petalinux-openamp-dev is not set + +# +# packagegroup-petalinux-opencv +# +# CONFIG_packagegroup-petalinux-opencv is not set +# CONFIG_packagegroup-petalinux-opencv-dbg is not set +# CONFIG_packagegroup-petalinux-opencv-dev is not set + +# +# packagegroup-petalinux-python-modules +# +# CONFIG_packagegroup-petalinux-python-modules is not set +# CONFIG_packagegroup-petalinux-python-modules-dbg is not set +# CONFIG_packagegroup-petalinux-python-modules-dev is not set + +# +# packagegroup-petalinux-qt +# +# CONFIG_packagegroup-petalinux-qt is not set +# CONFIG_packagegroup-petalinux-qt-dbg is not set +# CONFIG_packagegroup-petalinux-qt-dev is not set +# CONFIG_imageclass-populate-sdk-qt5 is not set + +# +# packagegroup-petalinux-qt-extended +# +# CONFIG_packagegroup-petalinux-qt-extended is not set +# CONFIG_packagegroup-petalinux-qt-extended-dbg is not set +# CONFIG_packagegroup-petalinux-qt-extended-dev is not set + +# +# packagegroup-petalinux-self-hosted +# +# CONFIG_packagegroup-petalinux-self-hosted is not set +# CONFIG_packagegroup-petalinux-self-hosted-dbg is not set +# CONFIG_packagegroup-petalinux-self-hosted-dev is not set + +# +# packagegroup-petalinux-utils +# +CONFIG_packagegroup-petalinux-utils=y +# CONFIG_packagegroup-petalinux-utils-dbg is not set +# CONFIG_packagegroup-petalinux-utils-dev is not set + +# +# packagegroup-petalinux-v4lutils +# +# CONFIG_packagegroup-petalinux-v4lutils is not set +# CONFIG_packagegroup-petalinux-v4lutils-dbg is not set +# CONFIG_packagegroup-petalinux-v4lutils-dev is not set + +# +# packagegroup-petalinux-vitis-acceleration +# +# CONFIG_packagegroup-petalinux-vitis-acceleration is not set +# CONFIG_packagegroup-petalinux-vitis-acceleration-dbg is not set +# CONFIG_packagegroup-petalinux-vitis-acceleration-dev is not set + +# +# packagegroup-petalinux-x11 +# +# CONFIG_packagegroup-petalinux-x11 is not set +# CONFIG_packagegroup-petalinux-x11-dbg is not set +# CONFIG_packagegroup-petalinux-x11-dev is not set + +# +# Image Features +# +CONFIG_imagefeature-ssh-server-dropbear=y +# CONFIG_imagefeature-ssh-server-openssh is not set +CONFIG_imagefeature-hwcodecs=y +# CONFIG_imagefeature-package-management is not set +# CONFIG_imagefeature-debug-tweaks is not set +# CONFIG_auto-login is not set +# CONFIG_Init-manager-systemd is not set +CONFIG_Init-manager-sysvinit=y + +# +# user packages +# +# CONFIG_gpio-demo is not set +# CONFIG_peekpoke is not set + +# +# PetaLinux RootFS Settings +# +CONFIG_ADD_EXTRA_USERS="root:root;petalinux::passwd-expire;" +CONFIG_CREATE_NEW_GROUPS="aie;" +CONFIG_ADD_USERS_TO_GROUPS="petalinux:audio,video,aie;" +CONFIG_ADD_USERS_TO_SUDOERS="petalinux" diff --git a/project-spec/configs/systemd-conf/wired.network b/project-spec/configs/systemd-conf/wired.network new file mode 100644 index 0000000..7406287 --- /dev/null +++ b/project-spec/configs/systemd-conf/wired.network @@ -0,0 +1,13 @@ +[Match] +Type=ether +Name=!veth* +KernelCommandLine=!nfsroot +KernelCommandLine=!ip + +[Network] +DHCP=yes + +[DHCP] +UseMTU=yes +RouteMetric=10 +ClientIdentifier=mac diff --git a/project-spec/hw-description/SoC.bit b/project-spec/hw-description/SoC.bit new file mode 100644 index 0000000000000000000000000000000000000000..9d9e8178a92b5a4d02f24fb7f4114b238dcce2ef GIT binary patch literal 4045674 zcmeFa3wUHlbuLHC3QVkRjpO~U%RUIqiUBJ89QhHgz&Btv+w>-@4n?7 z?>u_!=Id^}@f|n6dhy-wxcU3$UpxEOLovPj+IQUi?w|bGcfI!V*~>3~@#W%2#po-3 zZuauoAN!e~xMFrz{Ft}^33D%*z5FFFofFrKk;`BDs@b_$z3dg@9pbg0eR_Qp5<)yO zJ}u^5w$s0|_~R1HSzmha;0x;uZG4kv!#gN!;{KA&<4MmK`~P~@I}^vXm%I7KUz)Y~ zM{HS23%pse20sr!&YKgajFZ{QpB2)|wlX~{Q;CJKpSe{qF#?PLBftnS0*nA7zz8q` zi~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7 zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS z0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGK zBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N% zFanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS z03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R z2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q` zi~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7 zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS z0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGK zBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N% zFanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS z03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R z2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q` zi~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7 zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS z0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGK zBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N% zFanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS z03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R z2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q` zi~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7 zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS z0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGK zBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N% zFanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS z03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R z2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q` zi~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7 zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS z0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGK zBftnS0*nA7zz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7zz8q`i~u9R2rvSS03*N% zFanGKBhar1_@S-YCVpX)bP=a_n$P8TzANW^$9KNtJKyoEzSucl4WDOSoSc@rTFH-X zT=3&SBWBg~dd#bO;&dUF;!u0vlkL-;oKEw({LXjfobUL~cYNnNe$@|m|86xLA5+V` zT{`BC@-38}ls2$Ik4s;wORvd^*~W8*wLDo(s)eeoJ_-1O{)F(Q^@X_jKUkjOo>whZ zhozJH>JjWvKnK~p4)XL*79|4w38C;K|5^W^3)whW8Iejsk2}*gv-M`_DO7D!k%1z6 zfYk0YWFu=Q%SziN&9U~hRS8|yPzzOAsRiP3Pgvi@TC0=wNs;$=#AtTjq>WocP3r5l z%^3AruB|u`_SmLf)cEQ4ZBDxNU97GG4Uzi3YivRZ)roa|{uVDIz7^J|f8N zI@$5ninZs@g-_I!)VG$++gz-$iO^o!|U%kdQMLJE2L}cwiE*(KA0;9xmjh#9b zRm%qfot*5o0_PcuzJ8tp`mDH&>tij`XO(MS9c|dkxLUw}_VW;?^9SLcQ1|po)A*_f zArYbxb8BC z)=ekV4l7adUH>By;b1)inxf7!z6;dnNg=lLffR&xB9abKcapJJc`yRmLCEv0FPxut zjV@kFTSIgC@nJSk?00U;l`rUi2cXmX`3XXgW2ovU)67G^I6c8n2B|pohQuTNNuO90 zZ$$;aV3LB^Z_KwLy;v+#9(d#z@oZ(nhRLaia) zl5q-~x|#>?9uAWpOV{*JNh$`e;ZwSkPic;Xm^kdh&L>ct<#p+s`J0u8NvKYyMmUB9 z=5$20V=%|J!KtNh#CAjG7K{d!EpjzhjZT1;SrZ93I77})B-Qa-r3c`J4v@ zqJ8 z7y(9r5nu!ufqqAzcmPi_yePW(nsD3`QABY;@z;km-{5>Ecx8O(rGLp-VQT75&4`K+ zTAx~53Pa58Iwj2nuQ;BX+7txupm{4pNzxpZbqDJJi~p%s-wlswYe^hp1h$QUs+Lru z7OpY}B5>hbYSrX+Qp18n-9SJ>NQlcTUuc9dMO8+ac!D5ki!)Q*$r=0F$bjScE}oKq z(PB!1+lfu**w9(gLPosxim!X|>P$!h7I>-)*TP*8fx2u?-d}8;k zux-oiO~L3Dz0sS7)@tA4Ya^aq!;9mFIRH-Zvjb4cj;iQdgAzFr=trxqgW{1;VWlG} z%`?g7?3B3Uccmn_hhnMc!Y~4|onu~NOrhwuNt%+@-L{a93tsfWj`BU#ha zE{M`%8iFMSF`(dI)3{>d@H-)QK@j`OT}*q`#@C6IZRg2l|ILDMdlx~Q9%2w`iSMzM z{jw;Bq1FRrldA@&uI+1j-QK(NKwqK*69*@XFoh)*C?OU+7i}-3FH$F8*ca94 zMkPjPA}^4_pCtUH$RCc(XQId$cD{Evlw=_z_s3ai$w&uU$Oek9XBRdk^e-d&^Zu>d z)@vp)c9d|L1q(dxN|$u8g!lj%C3?H7`=I-{4xaXL#p^869uZi?7l5HxacFvg z4zDyceb;#Dkhu4Vl-kqyxPZnOg3GN5;lVOmFJC)AMu~oZfKH&cRsFR~-u}AJ9+~;? z%Rjy9Ex+hbmoGSeUvXqgj4ZFNYW={U43JHB{ASw&9iYVBQ}3Pr=-Xc@PyWT~$*(Q{ z$>SFU$BW@qI8s_&J@K{WKmFR^9LnVP4^Ca%*L1un#>ADyaj|ay7II=vh{Z7zYhSeA zQVac7q3zb^k>cXq*(;CMZ1UtfY=VEX(O}W=*yQNq-1?PAAF-`OtRH<6ZA8r3R>L;w z2?FCs*T?3rEY@t2Bb#vF)e~dHO0TO-d@@oN0EC z-^=Q@(Y^a8+awND(oJ7pzID&TFQ2+@r82wcmf*xqmE~9BNpXqdGl7^NoP*gtG;<`b zoLj_zehvDofv2Gv;xJfn+VfRnjPby@rK7HXQ|t|=G>qephBj zwzi!V>|+DuVy4$XQBDt3b=y@|+dfK)3U$}?^M!<~g_wq;Z6^-K=A<^yl46eWlPL<% zR5UuP0$PU`Z}3Ya2dxQ0Lot2Xw(FwM_sO`l^S3Rmqk@ww9cAloCUeHB?#e`a2#rYT zui-oVB7`x*Q0|oop(oSSawPcl+mzI%InvCq>((@-XDnMopQcZ(#8fsuIxT6tHOKFB zKf1BcE7)=M&?G{cljy0?SNQ@fOeK{Kd|w%hXo?L4<=#6G)!afQJ*{nS^jK&%o{bEY z`;CFBZM(__NGxm0VI24?6cNFSv5pB3gflq|^E?dFc(QHUgfcOOAw59{4kRLdAN;Al zuVKd(tg`}2*>1~I9Si7}jKA0~73o4fG-M3o_|b6a(N8om1~+QP_Ii^H*gz6vAH9EY zjj*BSc;=|RWldweuHMem8anVdWbR+a*L&M`Z@>9BK(uB$i(p;O_8Np)W!v z*hRmMGUIJZNc@%s`z|4Re&1E8YZV%AG6}kC!qXHqG=0}bke*5o}u{q(AISW#oD7o-Un`Gc* zfelpJl5Cs0^~4=RbI;gt><#C9{X5}?ye`^NV{)0d@9Ry9UUX=a44ljeY#RX?m$bf) z8wRFv$9(eW`@`KQx~%Ia1^0DRT90L+zao6-SM9n2?*MVI2}h4B*SY%O>CW>GMoxRy z;@Pl{l<+Z`8|G2MGcJX;O!O`9OlhQd-?FWq%H26&6=>Xsgm8>tG>gi-h>ZZII4GoP zK?wFa?KaP|`@E8!SFdVkw2s=@9r{|445i8Kd)l$9@2l8h1*MQ0Sz#4jp&~S`3*?`n z4h#m;lw^6tZ%e9eYTAkU%hJ}6m3(*g6B+Ck4IrRE8PAL(mSf|6?fz3=*KVto!wORr zL9aCd3m-#oOBK5lF;!$)z|H7;PPtx}k{ zTG(pYZRIb$U|Yrdvrv7@E6s*5!y1@UMOyY}m7CQn_XEwigUIu>MzzsH;U8niGP%@! z+57q>vezNpz$oJMH%*TBcm1|dJ1I@(`t5`ZLQN*^{iL8+)QQEv23j zZ2B;4VvTP}c;dL+Bm6>uK1`>jwaap&>$@zlXX0RpGGHe&po_v!`TqUpx>%tHi^L6Y zkJhF~C0PAVx&PVkHQYx1Gz}@?G#prH>Vw5g_NY9pGE25utP@tq?f&ol=+*E1 z_wRjY@!)6Q^M(j}3H3Wg@i(9Qy`G!buc(i&(io2q5z#tEFMRLIcTzj~r_Vj}3qSbm zr+@IBZ-4W5ZoXje|Jqzq&vQJ|^BQ!i0{O46*X>8+<^OVe_Qr(;Eq?Gd;^=MvJcjL2 z=H^cK;+v#fJi=&b_A$+WeY(LWLck_?+(kB7Ux!WB2g4@0>$YgbzRjLrueS+R6gD{* zh=r))8d?J+IlYAgS?x8!KI!2YM;aR1kFt2Nvo z+XUlCOiz4Ah<|kAnoLZwPP8U(Eiva zwRZB&zqjpVFl>TPBQr4qjKBs27GjR^!wdg6iaOqg%qcOPKIf;TCPT6Aw#WKO*Hyyh zaPgYom~!EV8#%SS-3Yal-Y#u>y6OEQk@IaVYu9PFzKgZ0g-bWH0!^l8E!rcX6qnkn zbOT>D#5;^y-CNYvq3prT)-a^2;13!&86H;mHM^S+=Vy2@2~|$J^<6BHp)Tms?c@$5 zMZurjNgkBqQtOJejzq1K+NIPcmbA;&7im3e%=t(A;^@0kiJ<%AQ|HxkZQlAx*U4}> zT)ed({7dV!ZlrWxlWu4;GGH3~VrXe&lUk0{pxMw1>(q`R z1;M)?OhIT5MW$xv438=I#tfCEt%^EIwN)jx-c@h4XiE8`m!>4Rr(!qsU8=r1H9OSv z`y=+8dwN)p6rjOkEl4$jWoJiLtAuVWu)(yA8PbUtelH!lER_)e0%2G?* z04lwIpsLH2Wds-jMt~7u1Q-EEfDvE>7y(9r5nu!u0Y-okUX2akTwA*<3YfAN#6J6a;waK0) z7^lej&GLK~^Df@T_aJqj;w86OFPpzfDL2wP-^#5{=-r~4Eoa|(L#;@C6>9v(kZfdZ zH{Pkj4&`sC7Z`1u;)VhpDoQ!qBrX9PXKtpfa?6v&JFE}BV22rZ(HWb)*@h=g4>Zo- zp^_}J1wWOAmJD?$=#mM2WC!<4ux(JAG<;hXo24WYd;B##?{$f~40O=LmgIB*ikt)~ z!%+#&#$cB_(TxhW#KG3y!$N`7cD9`xL$-YTXKv+t569G7dtZlc)nHT#aR7Z#b$$7C z`yt+%02ag-3!9TNZ0k19kp|cMjWne8MCQgdL1v6-(|0Auke*bzxzgOB=KMkA&g!_< z)BvRU*#=<4U^J2jL)RKpt?!aHr!t;(Ehh_i@*`Pj$wbFAZN(UBRmFG|7HKzn8xu%u z%HiV!-YDBIwCixc)Z~2Y;YA(>k^^Wgku2dj4VJSd6Y1FoOCQfxUy9nK zjD_RQ(UNw7*8V81i=YAxW@%j_{ghqbPG3ic8loUq)mAl4l~WghEllTC$Lxzp?$doy zjc!x|?IZ|=vPhfLzU@=PTEl>8R5vQnEg8GNw_B2WFNaS1O&UkCk}{5H7_+a)8=7xE z?+nE1HlWoD;i?*uYipZ4L*9ny?G~B%t?icV!*ZVRy^hBSPe@}1&sz$=G_|1m=Xl27 z*FSYRznTR2N^OW;9TMGFxq7S8MD$2RBhRQ9@fMDVm4zlbdc}%Ot+yzH4+t?5 zi{1Pd!>4wF+xY14r@~OKE%#5~wR=oji5V=0;!zZiXbZ>tI{hxZF3EN>+Ahz zliX$fk9KD@T>sAc^Mp9AJGV)#?-HkLkI6dImS(Qu*~b(pZS}n&r-X_mn`FWN&jU2s>Ax>vwg2Zj!g zW|O1#8br9b^Ba=47q!BiNcfTXne9p1yp+?@BxjqXCb_r7`e7~TkI1?vxK&4PD3D^6 zH|UxiqHh+^!OhV8xc~uAjK`P1t>L762~sZHx)U5bETc-{vrr)s(pzk&VzHrDt@qXPUdOm`;Lm zY9+w>`J0N5eBCBbyRW_MKp%wuyI(_jW z@2%pE$CcP8e5uJi5={CvA=9#?NwBU7no-GwdgSbWpht?kuU3i`JS#e&3xt31Ll{}$ z<07o7Igk_yCE+#8fa^A8l6vBdFZV=k3QF-newMyI;737ll{b1VP{m_-Wy~Tf8x?BD zssDf~13$6*TJoa>`zx@yzuTe?BDmx!Z%^^A6ZvS+Hhthf>a zeT*n;0@H#5{6*$-QD`}Yuk>4~i!aw&CHH_obyW|PrlN8$o#s9)vp`o_=A4gD_7U`F zx|vSZj7dCyx>ZUR{9R|W(2|7?PnWQyQJ)b-aS=6*KdY3Z@k>8L^X^)<5nC@LC%Y{v zG_It3*nD!I&jPP3bm)j4t`O0a#RWZ$sg0xgyqYSC(t=n<>uEu@P}M5SxPr#liCbjO zf?b%-LQ57p<}VVVdLA@gDn#khh2z(ht_b{K-?O~p3R;S8QUz_80l8I+AZWP8K|(Jm z`o3OhO+)7eE8@K(_+q{yUi`s>LhStH-QT+fTp!8|%;f_KPom$y3kG?OgG_-~8H!!_(#> z8JB2f*u;Es!rEkcjcoFZJ+w*b^&2WXpp3^pTKt7WFZ|*itEXT5!E0Z#@KM<0NZ}>l z{{Gz`{NU8pw?BS$<6$+}1j$L8+|@&y1Y4O>(0Ew=7B|#YJP0ZQ2B-dqz>>ilb+h=!#->w)j;N z^xULP$T(tgYwuEx6&H_orBd4xGWlcMD%PKc5`9?z>ROxhvYpTk)=9(!2=?CCHzD1!!QsBvGjdbh%?QO(Od-MQn`{$yk10?BR-YnWg8Bz%vN7|+9LaX zb9}_Q0-J<~ZW0BUgl_GZVUvw?gQ%`|RLRtvR;YY0ZIb`xWPJuXyuSXJ_~&Ezn8eYS z?SJ>&ZTpWtxIThWzk}}=;Ohl_MY*B5kB3dx|M{PV*njk8>#u-K7EiC|#M~g-MC|FS zQ{+4<6Gda=$EckwzU*bk=8nycjg5>fJ|Q~z#!tV^aT}iRtvnfxtslcx*8atpJ@pFM z1m94}EgtKrooww|`8>{>&Wc7u^F7GUj+b*W0*t_LAaKdS6pjP81^rB_Rprb*WFoOK zo=8eFSlXGU^!}9H?~g9_JeC4(J$(0YUPsgTJhm}@Ucx&s+!ei^qrMJoA5w6(ds}|w_Rni zvNTCD8QCPfmAspX>O%6=yv*n%Y`ghMlN!q=yxy=1$9tnUbFG_P3vQB} zX>~i_nz6;j^%@p_7U8MKw zW_27y-Z*`YHbM0xej=eUs2Ul)ju(dKT3FU$DFyz}N^~8!Wh6xQexcky^h-^+9*h7Z zzz8q`i~u9R2rvSS03*N%FanGKBftnS0*nA7P(#312z%mdzBE2Qb7y?FAIeF@3>6hT zJT!K`PjM`;GcNf4UbA0{iT1>iZ~1ml^roQn4lKL^*lOjl{es$xGD`HRnfhnLrzG+H zyBvSn#4(%Vu+6t}Mpa+BP|nOLeD439xz2PIN+VviR$?=>PN$ThNpdq@lWZNb+DMC@ z{jW74&GI$lxf1QtT%K(G#%Xq2e}9;iQ2h|gCI^u$LsR`+-1;uoN=Pj|4n?Jx+6jZT zlvZWC#kX}f`ns+Z6Fwx>^SCBg2xZ)Qrx~w4M~`DFcuB1Wz3oP8_1Jz0Lv%N3o8nwC z>$_O1idEB(yU=rf+Rle^@m3|f$G7vYjK1zFrB4Y{zX8|$HmkC3mLXZCWVl&g$E(j* zA9H!O;+NjDmE3)v7vH`yWMMI%=-8| zrKXwcDYO>+48Au3gyNNFHOH`drxtYLa@fF^kFu0C^Uk~mnbau{fdDihki zP;g^v=wtnAJZ>;?yzKIm1YM0}AMkF>UT0bwy~x~vqfr1Yuut zXHB#zUpA+>ZzI?dB}P5jcZC~Ufiz|N#3}qzpH$?$s}URw3t~D?dk6SuumOsY)CWn( z4e^(tTAT2T6qfzgcZr`&)OOH=;c@gvWg+frJP_AKS-!adu34rbbA4W8)P@{sM|a$i zwuTJluhH17Kc2se28s)$6tn|MBZYzER0D?LV#Zi5;<9GyPrNHrbtx*7A}kS<;ld2I z*HC~~OGJsK@vF8A-$YG{<57B&YL9l4+|0t`Pi3YmeMOp7l!F6eR+pp@d$9;jnU0G1 zRa!!bcHR;~;b$ER)JWBWy$F?V>xI@dbovDU5gOIkW>-x6z?u>%r(I)crL%c@-Bm%W zqABqwA52Mb=3=I;0Ya!2VY!TP)Gc5s2GYjO8J8Sw9uM2CHazQ9(=rW=|4ydr z(p09k*sY`T9hH692<6S?BMV1v2{5|EDibF@Se9#edSjg`XeLeA8#AWE$;)))W-oQ2 z=r4#FZ+XYh%U18dzamQGZ^o7yx~?|v#qi2X9Xp_G=(}J=yDeH>YL=1UZ?e>u zrmpv_mXGXy;O;;9^dEfd8$W;bFMQ{je|hHV;58q4Z)}rVA9Vt@2vC!il``Dia$G60 z36|97%Yj}MJ9^o7?fT0!amrHm!s_a|-S>}w>EA#1x!?Zbci#NF-+cP%XQrlp`KV{x ziRq`PKE>n4CLU~Jcv=Yj!%VPA+)h?Sp@2xQXtIOvRQIZG+tiCsJ?G~BabD~a>!*ci zvOhx+S7=1Dv(~S7=gb}g^}LK@ugX|o`s!elw;cPpCQl9^~g|V%BmiDdVOwg zeqJmJfxc@4zNb&Ow+Z?#_c5K6E80r@@az+GV5L-%ftY~*85}L1dPVkI{NN{#eqKbh zw<)f>N_F2Zqw>U-9_^PR0t)wr@}KXG-tKFSlztn4^lx3L+zRRQHwkTR0)A3kg8x?H z<3``uC{p4u#jjhbkWJ<(+#A{z_pQCr-c7Afj4v*lvET!9x5%TP_{7PRPo5LvbF>%x zhW;zoThFh>YN2jcuwz-d4|SZi&oe$Te){zK`V-$=zh&+gjMD4tC->tz|L>ncwOe6a z&#%R5p`IM`(zo%GE?#_nm`D#kZTZ0` z>iNQ!!}>;3-mPU&6#Lm!3Oo`Q(Ey z9N!;ZmQ)P8)k$)DK_2?up`tVHXc`06hmbBq-})tUjo!D_>q^C>lM=YVCO(;up37J> zx>+pF-=y&QC-3?~O-ANtQsxS4$J#O^;}qw&%$Q=rnG|LBiD)|Iw?yvUz4hHk)}6m4 zQQOHJ?5mY>RjF}O4s}-{MrtBy+}P3ZV?IJbePY}<#aUx-%Lc43-i?^|FWr#R4>B-V zDAa>IgDVV9;|Jcb2gJv$qI`r=!t*e(rMAd{#tq7*@VJZoexO2+?^(Nw0gX@EjLu?j zqhM_ru#Y6$Df~dnS8lr$y0aka#VReF_xRQC{JwdIWO_O(SVyka)G@P(OuZ)?Jy~d>vz>mXnN$O$IbIc{ zH70gzjg23)2-o7lUke{>BG&21}2B?TTz6b#D5GtPX19F#Pmi@iQ<0xzL%Z!CA9BpYBi<|CH4d5 z?(BzJbfpeKST=G>A97-%q>Y=oT(slGOs4w>k;U<@A;3228kAiVG&k2y)FM_nHcRJr(hQYu@z^Ha zLb6+OupaSVUxlB?od_3%CX_oi+Gp*gNhJrA zRaB_B7rf8QtQyT^EZZ zK@(;(UXyGovrvm@{AW{ElDYWSXSPCJ+>fe7;kHEgmNA*2i#y*XHt{>iLT__GN!JS6 z@j~l2b32jSteoYwDcvTiwY*MK8id=4b)6ROdA>b3RdOd=Riok9T4ftxzTB+tiC2v# z=;F@btUS_jy|4*cVM&n}zpho0WUf|u+VR_zZ5H|U6r5nIHlvFSbI9eks`YZfXNE;s+GNx!~-u(tr z94GMn>4+vlQ0pLc$s#JC1X|P>Hy&bE?j@#2c{C*k5?5{@Y??ye$LTTwa+uBofx1=# zIhdSEgm2(zcr*BEDYU|y6tV&M5qT7_K25xbZA>X&%u^Cb88>6+XEN58p1P8TY`=za zy{0gjpWQPXuFMkKod48@Y(vn*!`%sdta?~c8WxnqgO!?GPg6>o zO4a$Up+rwq#zAY4JN7b~k4FDR-x z)~M7tPWU0(m%GEXDcQIaznzVq474mmN8;3WVB1G4qhjIB`a|=0;1VDk ze)&K=RP+ipBhj-KQ5eM)*A0b{V7FNEXsj7ew5$w{!KjFaW{fwt83AFeH5@Vt`GRgY zX2kUUNSV1@|M^4UXoP*drO>dBy(t0H*K7C)jvxAwKl5^bX$EtM#YEh)kengy`rZtc zrK-wb);P~=Ho<)d7`VPFY1rh&_rLw-&ph+qd%yKGW_oEnb=>j6-+6d-`OZ7v2jiK1 zt0x~u!p_Q9C!Trn=XM@@;QCx~WlCIauLMX?X0-b^GE1{p=;Pc$<-tyY|#9v_b`8XFsb#I29V=1j-bjmi9&caP}eV*bIoxp7c3 zE!%K(LALtR({{-vEp4)HZL&z9pK~>sKXw(~u_l&Aj4dKUHd$O8AAh2$eO=jf{o%36 z*T3F;y#kQNO2$VXdFZp)8}M|^Cj0mQz->vJtdEUhjyHD9JO*c-ZPJbN?(xT)OQDU= ztWD4-J@V93F4ySj>)-9dJvX-_IKBRcH_&SP z-q^(UrF{-(SE{%F+*9XHpWaV4Ico&2yVg)I9yZxwZL;_V9zK!2){Xo|CW5i{Z zho@g={bDIz$A}r!2Tb`#&AtO(!SHF_qfc^#xWl-qI;GvIiqB9u)*(V0tw$uKw2sjP zXuV#JyJ{@-O<^6cjZc zTM8<+CK5OCG1058R-{@bWX#WBlCi=J)k)~0UmexVQ)NpRYBZR6``bi@%b$|JGmZC* zjmMT!-J6Tmn4Hx}^xg^+QxhZ;Vbif`ype3xzGWge@}*5v|CF|dtmFr10V*PGff7m_ z5G%^;JX&&heQ^t+O&VjGS7y3|i7DhhAWR-F4}K4+RQJ5PhZX6D>cf~YhqVjJ$nrEi z{IEv={R$t$17N(E55x*3D||yuk#(ZIhY=t`QTj>~wKB|b#T-e)4{9bfxyY#+waV#g zpmb+f#r05_>9I;0cQcm!M)_@_+RGNOZd@kGLgv)S|EbhOXD_%w zDz$cZBQ)C%5s9TJq15Ceg1Pi7;N~&x`;xNbhq+yF$byo3KTFzpQs}CgvT8GvFO91( z@Lm9XX$gtK;2s~$1g3J)fZ{0{^Fg+ifJe;(d1JCC{f`Cl)j(u?Z4yl;RW*w%k*YuO zcd3fcR`@8|fmox{Sz{tLe67(2rt!mt@C+r+h;T_;V@SM6l*lUM=7jtensAT*qG@Re zfa))y$>fHt8Ev@RZt0e8OYEUMpZXb3tCd6@%o-C3hG5M17YJgOX`ts$M+TSS~3YKl(~Ka1su8^r?gK^B_I!Udokv4J~bDURv$4Aercz+dkC$cux zx=S4QamQi^t-vH656}#-KF%;#;A*mfnNm+IEN_tHgFNdQ7i?Q1!Amh1T$rNpj74kc z!zwxQKu1Ky-zP4=%tUaNWqf!cnhNsy8(<#A`#nkmX@O?cGm3WhOm){4qa}FeTPxK6 zVE(nF74dry8a*R8?}-c4!v)g_>@`^29PqRe8=axWxGSvCWTpZEv0MuzM*4Jl`YN)~ z;7M@+qc}PlMGF1E^D6g^XpJZ_d~uk%DKFS7q(r<*C~$xxBl?f+r^P-*v?eIwppgWo3E|=xgHGIM5g!j(;&qJ(cyvpT{{#hK`+l-O zA~B7i|7U4P?S)J~3X1N#Ptfnl(E#JTDA_T8MT=+!HqoLK%#^Sm8(B1dK60Q(!&;&# z@l$(*x3^#u3Y2Imn#IEHENv3K(WxGEpDtt30z!fs|KfQJ$L=?iNf+7u*nLlh}G~XPSCo><(GfuZ-2G$ z#}9l8HbIFU%gz+#(!;CoFPJ+^NX~-t?&2>CWvS{YM)wuNLScmVS=8ve{>xpTI{o%* zulj{$m_#h!sl^G{;PKTLJ!j|ZO4z5d;A~PXMYOKbn|jl~zOr!fixM`m)h#|Wt4D$Y zjVBPB1$j?qp(P6)<4>rou%5lT4)IECG;_^03k#S(Z)eG4o1lv?&gb(_(V9lH568b! zy{^Q{M)GOSHd6D|{KN$LlO`RhSy8kjD@|$Z!Mdv-5Tdr`?aH&Xm(%QQ72`UanA%vI zoXwe=_OUUnWhCo48^#r0{mAGj%p0$MNc$*^e7XP`3fjN_-M7`-WOVf0xtdMZ7su8w zzWBih^H0^*&(VQjx&D}0{6IEYU*FhHzWUAm``ISjJ4MEyxDo4klYQ6d=rz|IJ?hT; zdYiaCgkY07*LPvzV-uSkdP~-Qm$^{i9teF`isnK1n0!h;ky*F+oa;sDGcqvyF;0+w zz1fdZOdubve}rEu%fP4o8fl-#FCm?tHw7r~?eCZ}(_GvWfGl7^#nt3qeebm`zX&LkAS;A1#Z~ohpPhx*% zx`wT@$=n>qm?rciw~&0R-6&Jpmu8FywG{a`QyrRO8?1`@x6(m&GF&4}|jEKkU7K1;u>A|P1 zk93p2>dQFYug{142Sbv3$9C)2dAX}jbe^}rbDok474+08NzbLs{)`o@ORVj~IJ1Q3 zlgo#Z4$7U4{VykcDpxr*W1eeO8uDFb)-`HmNu5eJr>-J91r~|dYkgH8t;XuJVM218Vtp60%=#GdY8)3D z|9#7K@mO4no~^Ud*L9`7tgCo^%qHROdY_Xjeyh)Gxb^Bayb)4X0tRSH$_1MG^qRzy zO1x`yyykwb45gdJVJ4&H*QaijP)m2AJ^v3$vA>P^)8N=T8~v^lT~iYa^zo=l<5>vV zVcI+)kz#MGWV(ei$}6jBOB_2txeqFs7Kfvmg@Yj`2`?Enm3>MgP!c}eK&;^x6Pk*$_(w{rn7@Q}rjViFa;5K2 zyghv#nQ6EWn&gBp?gid^-wKCjvPAK~ZwGe`UWB<4W?C`5&m)VN^YXYghtfi$o#3f4 z=6XAlHsHH>x_<7zrz<~0=`mtK04!;AQ1~N4Cq)~UDs*e6xarf>_oS~Q8x6GnMB=|<)R9rJ+$RKwKn<2PJX*3nilj}G*QBi>Gx@+! z;tymTCEl!Lc-agwFzJricvxZvZnMe+nPM}VuB5CZ9amB?H>=kqne%qrx+YX(1Gb0(DR*qZTd_lIOSOo5a{5jvrnq3IDv= zvr$nAuwl~Bi#IpTY-OYATjQz?wueVlbl%%O$G~Z^x1Vankepp3LQOqo-p|CyrfOhvmEAH#-$Lqk9PuzWGTwt@k0`nMuYB7$nFu7+Fy zE9ks7&>b+RtmBD!P+PqDBD+jMLNlWHnW*$ip89=>vi z`x8GGTO}}UBGHPB%`>q{@Eu#NVQ@8`qG+7Q1hJ+eL~AX|xI4!alt7#z?lK&k!7Nxr z9?E8zD7aGegNhI*uvXQl_Fxh`UB*Wz1nxLBrg)pIDLeVsrmP?{@lTakkDw7u(%Lz( ztjlH%o%V09{OU*VS}qjs_zUotmvzCU!xqcPMmE84%H@Jp5Jg%wtrYJm9(GL~zAqb(r1gtfDzz?u>`S#+TOFoG8iiN*G zZI+k)I|ca87UUx@@(XY0zS2EKzwiMOn05m5f{z!~d0k$icJfehRR$wjj3<*1K;5vC zohLjd+*-uCdBcqdJ!W#owZ`U!>K8!P1pLnZ6eAGXL$0rw2tth{(o%OF1`mKnU zBBkGo^0eO3q}P0LQ4pH@7F#SeH-8{C(HRR?H%7E?2=z~{k23!JvAHo*75WxI!}kc1 zRXn$Tn=Q8?57x|s!V9xn@0fpmvR;E6zUt>6|9Xu1Hf<8GncrZOSD5#Hm%ciy^^Osm z>2S~w-1djxtfFcUX^ZWoTH4t(2FCK=bsK$8B9pasqr+hlAzuIP$>+vkI!ukb{Vu}M(@Ew6B$^{1ru@iN5n8`dobla^2G8bg%BzKtdy#Q{lmJtX#b zH0v1Mn*iuYopw*9t|B7^rz9!zIh6 zmapoPX|`#Ca*1%Opfg2mLKXY%-chy^wH>}!u9b3Csc}*crK~W9(hLQ07zb1fZGLnq zSFl9|riSL7R_y>K1>HsgHMR@U1pM}dcPfUg@5$JwcP&|vuWMQ|QklNOQc}FyANknc$uLCh*+?(k@&DEft*Pi#m@lVF?!;1fcdl>+rRV8oA=WttG$$_z zaFa{{LEHX0ih~M#baWBqSW-f{EN$9dHA}Yw!}IPpl0p+I#}A9^#0xxmTxr`L;06F! zV@@8DwU%+;MKOT{lPgf6q=?C=4Zp67i~BDmq)*;2r>`S34K#*Gi=Om@P)nF#?;0iv zp$6kC!3|Oiii{M@NO6}CGcsDn0(TirLoGIvQ|PdKSWD~q>3Ljrecu|* z9ft8R+-TdEnGpjG%bE!9;Y9^4him~u8M>WZX@b^5Hkg*X>-*A@oVi@Bp%TB~IF02( zUZ@JjJAbTFVix(X&||* ztzzRAB5_UiqSO`unuY%n&B#-*vVIp5idpM(iwoiu2!v{VL`9i_R&;FwY z83uTU$N);gF`EDr%dXHCo)&UG#Qu%h(c~Xzrz;yxfx>h;0J>LPJzoe*`(mt}a!ia@ zHtbu^6A}R|b5u4?E_h@lEH9--gBAA@fy^j+QD&;LRAk0+QdsMB2;b(U>)By>%`&Xf z%0km$L#Fy7-HlEBb$8|URGK#0Wz`N+7%Y?4uvtt#BwD|kKW3YLikL3lpA-{GA#uL6 zyvgabBxf#n*=p2R08ZMIY;;BhXI22P8|8tq)|81HU`!tT2-`K!Q~8T~L~t0Mn2$nOOjAIC!^Zjbg5J34I&I&n3w;z7VpM3Il+O`v{ zUj*pO8s|Ud6U!bJEW-DSC9IVz;L2CqIBaqsp4%7lp1*>0|Et08e&yGmb5Gm~!AYIG z|D3vttQ0H@ZEX@%$R?LQ^Vv_0{n4jBysT~Cg=7uG??xqi{CbHt5?S-%*>KE&DejBefH0eZx5$odDcJ`zLyp;mgk&kz1b_ht4* zV!ZB<_FKFdw|lryf*<;Ca_bh!havnM>^jAHT%)=5jK~km#BrD3r6Z2@kik9K9aXT9 zovv&(<)3^3t$B0ngGhNY+_EzBi}bGK^yylLvuD@W-|&W7Jnhh~_oc0&SMr~F@>8FK z8IpELhFew(Ho5!y8OP)Gjv~9~UGm7#JQuzL7gTtRrLezZg&tj{+LPAvyY0c4UdxD<}jspufm^j9S@cku<5s^_q zD)zH#Et5ZF^$xykPGoyF!x;EXIzbv@m!N>obu=6_7(?Vq{O0i^QpP=FJql}bz*oxn zCWnme5_3}Z@LlTRp*IR2H|%yj)eP)m+KHySc(OtfiT2+fvEw7A4M$0MXTo`8BGTIM z|C}tF>5#JP-$?y15Efzs%mB-Rgfhode`YIj215ij9*v225;^CQ4ga)&n@AyCM`$Oy z#-PC_BPtEg`V&G-hT?vBn%aeazZBxnHCAsauyD4AS`*)r#I8V?K99(Om?Neswiaqr zT$2H@)wx`gR33seqv)?QQbsP`P_2kT zoh+yY_yj$Cao|JbgRONu%*Xb~YK+gv^)j^>Y)5$-Uv|bZ6vCM(+Jm)>G!kG{;uLL+ zQYG|N6$}r7uuDnTU=YGwiy~nTI06;tH5bE>qC6RMvhj9(BO5*GYr$!)NsHYLV;QZ( zQV8^E)bK?35CZ<))E1IGkqMJMG=8o;8OIVftxKBJu~YOX&!i|kQ_;o-Fw4Grtzd%* zBP?Lm`9wv`%Xn))4EB`MD_Qsh%1DetylC6Tz)0GUGNewshvxny?(H!|D{)ZK{fHx* z5`pjImL6QQCa#+5D}sG*9H;i7JQxTbIXxh6Xl!D@BSZtSM5nd_86I3k-|SLeh1f{D z5kHf~q{j}jSu*!ERin^)d7=^PW#Rf4W}zi(9cICMQ>ADD6*63nbQxjl-l}9jtzoQU zc)rG9q^rrP2TDg$SCOp(KZdsosW$p;ZzLpQFi9k%#64hm!mnNtWLw$h+9uo1DQ{k; zKe@04{xsd9N7&m8l{D7D6G@2#Vu~-)QlNdfFGLI+L+I2(To{|HH4P5gl6)Um)`q0b z9LFp#UDrF8uKbLp15w&{4t*C~s~f%vq0_<#2$Wb}Exy58B+hXG`X=13m`sAMyNbB> zMPsry#mM6ah!7(q8qfIJJH5j)djMkp#ZRp2<9F&iDXO8(t7wTpUW~7<{!y;-=&nz! z7XNx;CK|^OVbX&Stez<7y9>*4yb$a>fh{x9PE0zUsuWM4_1u|W%^M|0ztqSX)c6{; z2dp9e3$2geuHT1Mj283C${GU2k(+eoTjOhwe&N%r#ivTf#r}LIN!>nl2H8WXNq-%N__LN!NvS415wPnaQE6~&?$+Zic2{?Lm zvmBhhMFck51ar6R);w$?@F?>4l7?`tLsOg3+TBiRtj9L#w4VK+kM?1dLHPOW8unql zUPPCp_5s!_=42o)IzUe%F^3yJbA3zvX|wO5J3s9@M)2e7UmMR3fvK-%rz>4e*oP7O zGW!1be0T%x!|2u}-n3GA1Doh0mVFS0-Yb&YSN@ROeJR?u(s! zOAa}+?9Qglx#H?K(0*)_qepR#)zl{Rd5-=27xN3V>+A9JFL0(G>^qxWJkWMXR=#Qz zS`)hQ#C~jk4(&snn|t0-tQyT#pHUurkjC`IYD0MJF}t?ZiAFm?L#ZY^c8Y#MrYJmH z(Xma6MO@ew(_`4AP3$^GSNZI1lFM){zB@|x839J1Ul5R{BJ_&4 z6H=XI$|z5s_Dml_qU%?oHXfMaZ)77YQsR5WYI0+|nvibbqQfc3@6oX|JCf?kKIrxiQzYU!r!q^;OS12)Fn7Vci+=$~~@R#j4OjzyDx5!j?L z%Vgec!{cf6UD+N&Q*EBWvn`^M@$s;$MsZ5aaIv~9wah&TO}@MbN>fp3)|g6cA{XwV zSt*i?f;qxfUGbzjiHVYikm7bV!8~tT`e52r)ihKxAeJ#2{LEg?L@$}&<6Q;B}lTmK7!KtU>EOD6(yy)jLP?C)bg|l5s8Df_? z35cE2c$8Oo)uo6RkMYQdh_n;zX(^+fx!qU}8B8wYQ#b>f`rk89lA#J!9Z%x(TS2); z6;RfrprLqIQwmqxmq}3Mnj$8ey;Jzr>~*H2vDWKLqkx(LHXog7(B{W2gV=Ess`?FC z)9U`BuuU<4QeMt~7u1Q-EEfDvE>7y(9r5nu#{9RXeZiP{6W zT4>l0dwa(>o6+|jCLa$gu7^0jrD9Ojx%(ncaU9UI>QM!znpWeuBS*e6(*+ zl27{vSw3Y>mvZk+SALe#rBkM0oklVo)yVC~cy!TA`>|T*QzyK&Rqe~$KW^)6^rfH_tFfud@nyY5 zH=Y3*9}2}rI{cKNj>}}~sqoXJ4;^r(1( zgN!&@-`Hw<`B;8qYNL!=x(kiH&^BNfZ!FRMIMq3>cejap-0K^zT2^ub`I&9N!UTm68r z?bobLV%KChxlFG|T$*a+DRRwDL0LkS%W~m2L6aWEpG7&2bDqANs-ell)=NsPPzb*R z_*MI935y9IE-XkvYDn4?@=Xk!KwFaq$Vhu~35i@8P=08xyY|?RpyRd?lY=Eb{b;(b zur@7tK^f4sK^15R(SZcO)QsjuAki-DAmiiXok%B>1zH3MYXq|(@4+mzWTk@uw1hq< zNh+WZqiV1;e4=^lk*mm|c3^xsD6B+KhC_cYD?-`O#7}0UCmSu{KH#~gNtyJ?U7;>1 zN5KX3T7eGGi^ZEQ+Rh3oWiUZf9QN@!PZPE-1$9N57J^npvG_;f^l0+Gr6)UE$<#99 zbDd6ZVUe~j;g20ov_cA{!7@KCg5w5b6Gi8Q4EP;)W4e}h10iMF2@O!0(bRRBsY+du zwaERko>ll-OR?&@D_A25w19UQ$o75V|cz7 z3z9~CaRxu36uBADj$h0`NhT_Qp~6picVH}uB2W1k*CiJIQjeyn_ktr_qoE*rvuQLC z--I>RpL`x6jf_OTS9UD}qm;-KPii>yOPBly(v_c`bO2@_rD>yc8JDzs0t)&TTNEpJ%Kx5^~aZMcC3BkkDUeiZapOyq+dEXA|&hS_a zxB763a1am6aFzeb5ce%oj|#uCX3E1!mnK%zm7kq-snNxh{r6ELS=Qy{d;G#j{UCqG z-DT5GypxsHlE1thL>IspVu!z?aTnr?li}*au!$esUJiV{oGY!ao|vfI?e7g&&rF3^ z=l=b-#9u~xPn?ZbSMMt<-;K-Wv}xC=v^8WUe`$rf9k3kq z#oa}{5_n$W?r`;lu}OgZXb~ritJF?*iQED09|V5_{M__>_#xan=B$*+>@#w}Op1^K={}W<^L^g( z#X<5h{o;`0x2{3AQg+qx1sp_j4=0MRZvp4$}TWsM9>{9|WKF2Ws38$b9L} z?I(mg60?s`6z3z~mMdR`E3`w7pZ;+Mc#be6WOqGr{g)V9zvdb`vbi}smLEH|e?P^a zTqsVH?`YhUh|^wybH|8xEJu6PTyxFhqI@y9Z!jatoEW?GCE_gh((Z@$L0;@Pc9s7u*ogp)AjED+l);fqjBb%Yv$%=_k#t6wRP8y z^k2Issn>!UY*M@XsBb5^#&%*xd^-Qfj?y8_KSs-YshyZsVQqqEmN&kKY+`Je@{#Tu zn)i(Hdc&`g@8PL%Q2{!$P7!aXykOGC0~x2wIQ?YI|8yJ|)%Y7Bz%%a_Ne-SKhZM(S znY3xg&1q}MO1@cdC~{{{%`B11$|*@6ty4Ti{#We!ME@?Ek9=a&Iz{qP&iF#a@vBZr zV)%Ex04~uBgdz`yNu9R!p3zgO*K5lP`mjn{J_cJL_quHs?B`;5cV((a4}S6F*HLb^ zKJNJB+X8WBSH${wqhfM8KUpl5aPDI@v92mLPRgOKD%2fT_IT5LU9Cz}4V^Qmc6FY2 zP;vrw+v^*k;}&2mkEFVI^Fwl3tWU3jiJafOOgFh7t_gEhsc}*cby=Z|t4lAd_ULNe zrRjUfKJCHPR5<(fE5isYw zLMEk50`ZBBm<><_rA$_Gh)9b28Akd}>F?6lk&Om-M*DP882EdkRU2#23`cG1fCM7L zCA$!*7<^@76pw^Y{5am|$wo%^=V(FuP{}JtPzUCIK!Q(Li7l9 zzQbMtJrC9t1S$N;NO~WBCUXHXBI@Z(npUxej4>%GU7ET+UHKVGUx{@|z-~~saX+w# z`qipD*xH4>^M*Y6ir^ zyf1Cm`UGH9$9svqh?v_DlBDsoB@oDxg8ws1ZE5OKfw^8$VhM11K-&UNL-qmEi*X}w z&i(K>r6}TolyPf5<+3e{QnX1`)m$c;wv+$&v^8WVUs_FmSyN~lKWmjDkk#T0;u=4= zKFs5-nXuyt%+Cf%io+2;&DVx+TZ#$9j!Z_<2~T__9l1S_>Pugn&PI5ER>{K{<40v6 zR|-CALv4h5B8>aNm$m7;d=(f2ln=zUl>uzv8*@?-5MIRN(jns>%%^wNLqV5R0<2w( zqGj|_!C|}<(KK1LHd-J|QH|DM07t-(jQx@nN+XZdCLdjKDI~$ZRZ51d%^zCM6E70e;3p4><17$rHd1T_^}v?%Oefr#xxX48Nu9fXb$r0LoqWAcAA zV}+@y)3_1QV$Cd5z)EVYTnH4D(O6(fnd`C%L|_Voe%uqkm!$ao@=Fq0?+rvQXpRB1)fy4>DcjtYDVcGNhLSp9|Vdnt+S)( zOWEm4SJQH({J36Q!N)jY2@$N+v}qGGUzR|~rXx#J@==(Q=oga)k3M~nWSCpygXNo7ly58XVeYzQ&KGrRa^X zr6@d8(Jw9f(vzhCeUvYj3k6_4A6Gz=@9%@RK##jLj0NNP)@GDObO|}M)=_J1+74Vn zzcP54QttLl)upKHAO5!dkGDVY%YStG;S=Te-*M;rJ|>D}lY`3!V=xo>sm+DqTR zS~?NxprAcJyblcncxz47x&-aS4<`ad5!bjDwn?+At5@J&6h<`JC~L|z-mL3QS!X)p z-}BSO8yDqU-ZFEaE_%OoXW^wH{36~wme6-;X!QJl{6`_K9hG6ESA}1|O80Od2JTV} zfcF~MBnT%;UezWmKJ4R_%Egt55Q9`^wCfKtQ9RoPOfxcKQ3++alA>~~k`l#o zNyj4T=s)uPbx+UCn>X+Oo7q43Ht?pqfBoxUcYl7AYVXR5n1Ll!;8A zUsLCjPNE)^^@}=be=c2zxR#{f_plyOzW3o`3fIc`VK}T;^m%zocSn9_T1)ko5HD%0 zZ_M?Y`rdf@(EL6AC)M?P-vpmv{o*|j|77wr?@iYy{)k_fh;MyX&e?B5{^aUUCb%Z^ z>lK4f-lMGe1b>9|a>VlNLiwYle321-MLj-o9Oa*HdHz2xp`cbHTj*P^186xtpkz275yxz zuX)TBDtvOTX`h__ro2A~JJtEWWQG)ca_ji{TepOJb?`pP*NommQ0hdFQ|8W#PmaH= z+DaYLg;&;Lbx&-H$a%xy(LE@u5Dt;AL~4TS2$P_;DePUp;r`gd$#&HmN)sKjLL>MZ3F-Wgt| zidS! zLEB4vw{!nFXq4k>J7ul@`2qC@6!o_^T8Y(O&z7b|DeIJ~WKv*VX?fF6yR0{T{^U1L zZ)1O0z`PHKh-@}wJ%c0^dYQ`=MV%~@)=u-eJTo?ZV(<~@%-@{8h5ced?%?XEy8yF; z=Vup#@I|3Ranu)pwWpr*X}L8-N3)+AQ?I0kYMk6@3n5xKG|!Rnk9p|k7)FV>;-ThO z3dJrN=9jU^Hg~KlcjM08vgE+#ag&huNcSGyovR+5)3McM%}Y=IQuA%r)uO=xs;>u( zLa_@*X-tTaOND(RgO@h;DXLH0*{#oZvzFlvjdMgtt4L}53nBGV`r05Tb%iatZ88l~ zS6O8I$;B8X(|SlX9p>NIbc=Ph=NI{E)oy`rMOaN`SoE6)Pd%LDU44|awU?xF6ZD&# zFL!=4^zh)v7cd0*NH89_&tMyEWJfFG?h3}XC#2{2LQx@EGT2jjc7h{?XW-1v>Yi9? zxn&G#)7^WuTqPrfDIrOXPa!YG#qun>>Pi~jB!9cn=GYhskN^pg011!)36KB@kN^pg z011!)36KB@kibX;+VYcdl$>urW+aZ&IDM}P-h1N9!+TIp%6m}oN0O)7M&jguZlfCF zv|L50{O@}`dB#LjA^NVSTB^I9XIJHS;rLgcUDasH;{7KQhxeMe_niQ~yaxqa7hi#z z#rsYSveD;rIkN7(DF#t=(Z4UH{F||;)D`Xw_XX6|K*M&6yR$sgt}5g@wyL;Cmh1Nv z)gn0cEwz~4OQYdWx|J*cMd%ru-abk}@lRJxJ0tDUU3lQd%)=gyB_D^$lievfdJPU0 zefM|646ZiI(&Xwat?dh2w!0T5&0d!n#6w=sD zA#yvp!PB3TEQco0#r8( zqK@@VZ>VJ)gK$NY=H=SP-wSNK0!q`AXh}#TpJ{Nr@ZAkIR(n$h&qTj~jobr~&H%F$ zt%*S9kcf1+n_IhV=0I&xC?Sdb3`tT0kYp*ZQTH~!RCfza*_h~d1_;1 zq!9;oJ!{TpDWx_eJSi>B8yBbOov$=JWmE_@B$|y+{a&-})!3T#wsGWX;mCEvx?>Zz zB0y0KGX_&7mMy&EBBXBMfscrg-}T2V$sj-@%bQHwm({#odS}fIG-uulNc<>*jY*8c ze*_$md@zVGks>??GL?uQT(CZpbB#uF!)Fs8WwXd*A%lU-bP2Hw#>ONSIBAd+;Uk{?D!rZSl)lx(4T(S6elIWvqGkFqC#s&_N z6HTXe@gnl_sB{-3()gN)SRMzZ%+V{07MVPl*ZQtdN@jfN9XHria> zjag|xHh71;BtwWpVj(0D$9QmELCdd)Ig*yTC&zi6c&&= z|3Hu|s7;XK85xKc-7CMOTK48)q@$jU=HM~suSU?phfDmA8-URR^>Mok;EW&k$A>N&j13@MQy z7`H{~E+Ov*z!7fCWw7y5$#oyKAV@^oT$ul(=GtnsrQn19jfyv{m2$U{L>jD* zeYAyQq*9qLsd@XEn(a4d-c~kM*y%F`mq?T?p75n|P)H<`hvhhu*9iZzNoC)yn19!i%&iPwpMUQY8&$=Nh1GVlZ8!5 zpfk~r#~=LWSjls0UBI!+%i+Lnk$3}GFE7WgL|!}8R5tx_w%*! zv|9h%Xa9`bLO0Bt3Yosi`Csg|*H>|N1xIIRYL6|YKJgyNpXHo-M4pmfdM5X~|IR2q zURgOW&sc9V98#YY_`Bz81L=f5dE$w}bD^8@%%Ss1dhE*P#Pr9mf`93gu?W0#d-yKmyxGvqs&mUc_ zBUAp(r(Aw;@?-ks@*_{cCskf){5q@5__p=Q#<}%A3sg8y$~(!#`LNTEcz? zD(LUnY^tfc+j&+?3tKx_*JuIPJat9#k@51dj#2VbAnO~A&C6xoqlVn+LoVf#cd_J~ z`ySUidT9Rk3xFZGYhBC&BLc)(h}{`Pn@muds5s3yiy~sC56^U>|8uxf zZ5jhdI%%t>r=k$jMX4!f^0ep`yR;yG@QTt;t~PSY+bUY@w(kw)Rko=8c+)J_*!fh?Oa3M@tXf@ryIDdtQ!aJZRyot^{-XfANXKvo+WKSgJ5~ z(<_fzc9Gygjdb|aO4s49Txmew+X@!FVs}ntxg<;Bd?M*A@2l3hjnJ0-n{^Q0vZvwx zZMXIIwZ+jLMIA`}vuh(QCCEwC9aam+7Nl`MYhG^iWZkLG->tiahV2`yRRGEe?lD%{ zP7-Ah;gc8x-$=#>nMu$y*guSy7)e0OC>wTExnZSh%J~X?wiW*FqgfQ&G;`M%iqZp~ z)<&J_d;%-x)+4RnZ#+!-MG^sb+Jo*!WYhzZBkyNT%cT6SKxYS^wMf=4itDU0F$4%{ z9iCVqVa09n7m^kpQ-l>MPN4lnvX5KP*WLk0x)5QjtrAaQj=_*5 zTR`fNA5U%-1w^i#bZdRM+c(z|YcSyxFU zyVjr6MG}h?P6~cPaZfNk66I$iOG?WvPW`21z@YO{zN86OAcO%`WQx%;HEkC z0lB0)rGzka47O@>!(w3y-e7}tY(;{AFNs$EVok#L+lTWNH-Hsy{nma8fXQt zo!M4rci&}O>SOsa3Qv`QXB_8v3G)ZfUx}e-G{gwVU3UqM?UuzRKD(3Hvno+b;T~1d zQtw7lLm|6IqoMZdYX(yTK*17wwo5B(MHKn1!edl6WWU!tGJA}{60L1)5S#)YQD8s0 zgh_-2Tw)+{Yvv4!lhhoN&4kmhY^I(1TQTs4+Eg+A17mlvlC}8dQ>&+vct^!;brKTe z#3+$ij#lfdF6B4Yh>z3YoEI`R$ID-?xq$}F8?*(8{%fPjaQYssor~5Lj!GX@T78FA z-_U{>M>rd>!%gBf^-dg9=0?XIv)pB{D+wEXsjLiE zq~f23!t%E^)KLA+STy0jYV079y97UMSt)`~K8c5?eL-EfPvZx%$hMW1Nr7^dDz%QQ z;5Tdh(w{){D#Z8+z=dU8Tqi!+%=XkJ3!6JT0Jv$xF=-PnvAE0b z>(_R^_Uo(aH-7ZPANW^m-}IJCA8ofjZr~H~8O9%dy?yPs-nRPY?`u819jmKbbL~&P zh+_{r`hzOu~!Sly&4fM&SOQ-M?vQkexasD`ba_iEiC!QE! zu7;w+|I1cQrVAPfT9eUY2!?HxSF!Fn*Ws zS*JJ$`TdY1j_<#qmUmi-T7xXTrV_cjdtEJmMB|rwtapSB`QGC5l5Qp}KhjJ)^|vDH z69w;kjeQ4N182WZ@eE?El=%_FtBHCP@ja_QnS2iG7vF&i5hL%|OS#m;`p376JX;5u z=Ib9pXd#k*9FCB#1v-yVH6Tcjw^!PiPqdG#^Or82Us-7*sGC7|W8)2PNM4BEjC^^a zP&pr})D_EoJsctRNx!qorAu#lOZ$lvCqCUiek=Io^5ydx@5`6f`B#7KqhA4xOqPNv z=j-Nm+xX=8@wdF?@)Mu_^rzdGlstk(=1I{fb6>rA>s$W6fBMJt$qaY7A;&It>!n+l z-LXr2g1^j{j$LzKeZw1${F|5k0DUq$pR^5ZMGIfa-oyA91d%%7<%lmxxvXn!N&LKj z@1ne)G00u~JW8dWO6$4xk8-PbsxPHAhlLN<+(2XIpViXTT>73xi}x@(!J3yVi3K<0 zkBT1FFJ5s!Q~LFfVZGzr%?D8`!Pk@Zj90ABUy-PR(0NS*jWpJTmX_Q%KE&b^jemC=nM`$H3zFtTYBUz(^}YX^^NP0?%%E9goB2Uvs@BV{cX>r8!_>YX+MiNl>#|#3SiKD=s_N3&N$>mF z+1VP|QouEGg^?7E*TS8p<^kNyojjoB>ag9F3eT_Hq>1EvujCS2V}&Yxd`U)g~2TlYT<#SkXitS6U=sNTUIL?@f2>#wHoT~ zjIz;E3rM?=I6q|PCHH+Llr<8c{E0@IX`qoeseuk|yVB4Jf3e2`3Ar<64O?hqD{&!cq@CvqvRade=AJvpA6|JN;4*GOHfDoc zjei{u5;x$!EjR@8q!5hzHkk`#YP6J1eFN7bE#C4UMD>P+ll9tf(7JF2NsGwhl#QL; zx`mCg!i^^gJL++*^d~fy_~6|q1`=%n8f$)})XD}SmZzOaWu=U@vD!*=P9oC!!=3W? zpF5e2ir)89B4STGQdKuQuHx+UvI`&ZsLmNi-CaryFXh_GaeQt5woUHb14-jlzAu z>chC~U6Wg-l4Q$Gp_W=TJ4bP_`Z$C*)nx0gmHO${g|>V6hwG-F8r}<-Dfmsmrbjwg zT=ypVMBObkZ6EVvQ`)?MT|4aDX>9ZN0?7=B6PZfTN3dz^GP3D7BS@sjt_4>jRca3> z9NB!6KDnxt zc2f6+My+)&E*rN*K2-E-HEuh5agMKXJSy%Om^T;J5SetEh$MqAauMioRPx@)iAUl? zl!}rI4=f{#fK6&pa`lDNZ>Z1qURjRNupEBUqmN4!H`ZnB4kBy4VyGY`?u#bk)Jt1! zi=$Y}ZdnWA7Cv={!}Fa{Jb-`h;MDsYv;CT`nUGQJ) zWgoY4IVB!L8uGS#`wYC|@^ZvOh&t}r)#=!4)(IYJYfQS<0<>|J*2GkqJ2dBbi?E4* zAN}&?W@L|CeMz;qKle(^lU8dxfrDfX9elF6sSsnHy!zU;r%zvdGL>V7xpEaPx7+wz zOJ{le8uYAs>bYzG^102s?|I-G1oj9{Sm6 z`Tm9Wsb%=2iFvZ{r_E7osHOBC)t=Tw-WBFHy0U#T$B+B_^xN&lNBXGDTI_#so3+)w zv^TO(zB-amE+HuO(n~A2C%>U#(I>+|yZLqN*2)uK`qD7f8I|A0J{j%UbskGiWd-o% z%RF|CyU(rTK0BSL)BZh;?H4ZK0=9+qiV};h$J6&SuFFL-9+e9HlPh>XqpW{Ky(OtH zdO<(6wF4ps2iSGQzc z_A9uebbYkDr%k7o2+prCrx!C*7k9@seP7ZpRn;`Spg^$Io3qRQ`~`q&~TY zx0Z`f`n^LLMb$nzd179k>e20!bzFNj6;3ZV)ly^abj=fWv)?>Xm*lxCz4N4_#3#=^ zck7aWF2x?qlkLV>HPuk+6S-D8e_Y+{H%~ARs(sR_@(Jh3B<@Ss8|Lq0{7#%IW&Pq~ z#>W?6HHx3{>l(B7GGcwB$P=B$&&QHi>KV7i#@&+_C9z)zx$yI`aV1Z=Z7rMcktMK) zBKY-*oB8_~S0A?+SXkHiD_FOoUTJAlJ63^Y-)DlNVwh|sxMxxfU zTH?8jn;KD}TynDwcmBEA+S@~Gi&@*PEQN$EX2wgGuY1e+KGyP%1O;4ER|GFDZk7OTUTW8po_y3dUgY&bo#A)+Cg^hM%9R?Z9?ihSDyH#zNWfe-B+z& zLDwj{m1-GNYE=8CTI#I5D9P*=E?15_?0mU6ONAwlP5fYzHaki*{|lpN9R!{97!}D$ z#ientqg5~XyB$P?zvx~-nepF}J4pw7jeKwsB~=o+-?11Hljbt9J6{E9xiHPoAewi- zyUoDR-kZ?a@A24kyB>EedUMn+D62aP*;Gt6j_dL5q{x^*rbs@1Eo@IAe<11s_8lkE#G27T3vu<0m`PfM++l`Ad$ zOq_IH>1T{OW0f^-7If6^rb`%=o`9Sqka3|CRvJmpq#sGw5~3ff#q6FK&5ki>T@FXM zT^Q3wnXtbaNPId{Scn?bjsFfQ`e`sBk;bUh<)TvYth4tu@ve;kW!9Z9+l#GZ=lMlS zYbeA=wZ)meB}FT0S6kff731VCcWUjT+~&MdPooq9g93z-BSJRBUTOB*xwp^W=3ZHJ zeB@~ngOnIv*&d-ZC6ig*2ecNFH0KRTh3bp_rvc%NNk zA^!HpnyR}YjRx@9!F`OoICiy-JFRH-P^@6f~LidqeE#dCxYBAewH0jRPlRFEu)|vMEbQC|lf~D8-QPslV z&;eMt^h=0$65Fvles{ZrL!J7pkrfd#NAUZv_I`0j3L7nH(MY|NJFB2H!{pNZ42|uz zsYuIeUiY{aK)kNh&qR2~qFfmx4XQET&+u-{k0%p(p%%~@5o`bVdZewFWV=uiKFWN^ z5-_zGB?nC&xvwDMic8@XZ`}|gA0cf8Itpaj5O(`4*enH|sF2yC zWc*k6sNp)AwJ@6PM0**Q4$b?1aZM#R zasjpRKySDx+wa$0K}%f}m%v>n=;1Vi5X)wNgoXcUfAnMeUTlDV>Hs6w0NKToMlf!> zW)LTzH*#s^|HbpJz$rML*d$uWF^&3ue(GEMcGCYrC`&1h)cz@$|kRym8HG5^Zd1I zpIWe+3%KaD=u5P@i+N(VuBHnWH)U;|-MqShdGf_CsM9wj57oJLvMtxbm`5%zM?a}w z2sTZl+=mdS*;z*?UYfPVy|Q<<-LeaKi2#sV^dX8~gbOwoo)TvuAAE8ZKG}s&j73oR z-%ggrCvcr?tvlvPsv_7_7UBw(S%_lXpLs}w+@tF6Q}qK3=@6&GzULlU^TW^x0q>D~ z9YgR%h|^BcCyjW+H!`wM`n~O`!M@%uP0=TN?rE$yoRjs5=m@TdmGbKvoBzI;W=Iz)Ld<2v&1P1ifVR^l^wKO_1Xztg?fQ7Kp7`P09zu`mXAU50D2^uDW} z@`CCtlJSqv!peTIap}0b&9?WP9y*tv+u!n*bLafKmAlt51~taBBXC|}RaP;SuCKy% zvG_#Ra6vWqU$Gw3Gb3>R)~G&t>O*wq)~Obf#M z6Wa!6i|=K841x&j7hQ~Xi;rDIKKUo9Ui$t;ls_u+Oz-(}=TiGmwWOfdACHgxM!D^S zn#X!Z+{9?p_bR&gG0ITzUPg^5!a7HZ<$a4kEb)JOR@SC=yRlNXyHIlF z?}RR&KC&CdMsykocYLIVM#^KWp^4E<;*Y`ZCY5e&gRFe2f~gQbT_LMebn?Hd)B2v+ zPI`Cv5&IF9^vd~Cab4NYU#rV<<96Mjepi&0$>D=>H=wGmkoEJoFpJ$aRC>k07?&#T8?uivWR5*qgk*#B`hNs?h00XGlw0-YzjQYDX- zYIUhjm$`F&y88R7HWn?){=S7FJ8du-C|a}Nu~vYtj>}Ex>hENq~%6Q)UznU zT}Ti}TDB@(euqrM;m9Gn7M3%&ydpMnxUuzEaWe6bDNwjw8_$4>toTI55XNc_q6^0Q zStC^nA!NNH(}HYzWQjtJuB7S8jgdL=hhr%3YgHWswHA)?78d$qGQ?J6o?yX=T@?Wq zF0RDtdW`jspu8piL)eAZHI(8X`~xL?JnqCG>4M~~Pd2eVb!hJIiq5Lmrn-)m*Mbj+ zuWgl{Qldvwl2YI%k9LV|d47b7&Pm3~jB#PJ1$X(7ghY32yR$RTo&L6&o7^jd*VTMS zt;)sIqU_ii*&R$Es}i*pJ8z)~)5J}M>q;5C(t`og`VtjVCMkezNw>XVsOXa7t?zCzz!ZKn+D3 zVSa4r(lI|n2&oc|+jyk5yTA3E!-K3108{dCXmRmoJv%sIP%jqH_({*&JJF;sG`ModWx2YS#@Bpz1WTt?%bi{91LY3GD7@-}=!bMFsv(;Dxf+b_jmcztR~k0> zA3l;tRt`=p`b6u(P4^0*55QMv@Tega`MrKaDXnfGe>Bln3{-`45Z3PxY5CMYt7`us z$`TxoFdcfju5$@~bHT4$;tL$kaIErS2a&bn4N1tRI&4+juU4K$y0kh??fq0YV_fQ# z#rZ-W8HIlu7swwm*8K?6N>aT9&oFQ+?b2Cey<^04T_I8JW$49S!dfz?bR6W{rZxkCBulPBIedz*V?FucA(_UP*MxBch;`w#!p?|z@1K5B`l0 z{?s$=o!$ACI{oyu_PMK@AG-QA=&i4Q;rnncEY-6h4wetz=lH1@i}7%*%gX9WocgAE z>^5)p;qU&VzjI8z{>O0a+D7YkGxf>WuU&imdslC~?azMwPk!&;{&&Cpn`^)EXFqxW z5C4S+o{6tLz0gt%A8K!HUyV*&{c@}QweMT)Jesb5%+4plC$Ea}E=_mrs@o^YA2(00 zo)%y88o5i`ze};Qg`4UY-rD+{+TGYVj>i!0weFs`pvc6ZHG^E%F+RK)KPoZQv-dPg-D1FR0b#vl%|7WIE4F)()AyZ!=`~pCjx|A#JmSYO zC;PoR@yG{$q5Wxf>*nIuzpm7mzO=qBYl0SUZfxMH0PpZ~p49VxHVO_Y#g(SZ8|ve3&PfFP}gEidTfX zMeg1wD^Dyg7Ns?&4~a2P$q3EerYiF5{iNag z@QUVm`u%FS>Y>x9L>rBCP#R|sE?jn0BJ3?cY5c`XZ%L(reJ<41{p&*5l_}_t{(xNETbHuo;U4_1klrPnSMDlpG_&;EjW$8X*;81HIm0;P^3uXE+kc)b7jg9K(FKYH9L!7Y@vsfu)lcT0cKz zlE^$Uxt$zHo^toA<|maS|MY>e9* zajURxt>7576x(madPkABTUtwuj|A(s-5b-L?Vpo5kfQsg^8qM8FFhwL5mDa@0Y<%LnYFJGRuHVTcdSy{UkboWl_d zvmt~{m#}FTv6UD4DvdaP!2h14b!!JTvKb~Gl?B8D!kFii0ham{bw1yx-~ft0;4$~> zx!mY04ioI~OM3CEPT`3KB8o&jVpteaZ!)zL-#uBq{Z}jTyd81hJL{s-E!nc#1i@;2 zBmq~rubK|ClZbR!C``s-s^gc>{j2fo?9Uq5^W_j!-rdXeWC4Wyj8gEO8&6rU?;s~X zjrKKJDpkJ`(hRO*I$CFCv?>R6k~hDCWJ!!#!;UpO?+7hcZZ&sgFRNLwY> z!jamQaxI>+lIpZu*CpPR&AtdnuI`I&%%Bth@EX>_ZQ1;*gLOtDoMR*vscq|g(*Bgp z6a7kjKXDqT+O4M(obxxm;?VQS6&PEHv8gR257uV7VZ+PqW6M|oTJVXL9>^+dmniro zRyTHE8GN<;vTIKR@%$!y1Vyilii1KjsBr4C=$}t*VxJhebZOXo7X7`~?e>Wi?Kajm zP8`CW_7fXm#S#JU6Zfu^QVFxo6Y%@@<;$P`G*+25aesXCL)>RAj(Y6!KH;&e3HLpY z^^7`E*aSA zLg7_vV^qEER4*MrKhc;k9bXyyp%V1TXsF?niLRySlhOE2qJ>vxUYe}l<;&yLuRjjnWGY}~U)_C-$) zTPIq|=C>$~HMo2Khq2VX@;>-pHMG}5e{&yTA$-U2ah?mQ0aeRIlXT;*Z!cT%58&;Q z4iJppZWvpL2iQL7MU(8li@ocM>FAg(hMmmES*{gQBbkep&VN)G zsYXy*{>LHJU>wF4;s%?Zrm3d7d-~!uy*yxbjqh(H6T3LMk)AQ{v?br(xZ8VQHEs>) z7mo`QRNvz&Mj7cryHkYJhPl9p{0o^E}fgG+5xVlJ^g|Q7 z+oOpL^_m$hY5Wpe7B)(kWGx-iQJNRuhh_@VtBpUn z?i%m~1X$k)hrlhlPn_D!=gXRy9S^1J2v)E@mL>|3dq`g)KkMWk`DE6^7;5ji+x41u zD4D%epilOWeZQ9JlYV6OPEMZ;V;|NpuH*L=jWvzw`bAW$ejnp7d-aufUR|H<{bd<{ zGjVI=5X(gdK7Jh|(i2@B)i=6Rzf+&>+uO1%8oQ-#-kb%6n>XuycEzmvIg7E@X=AoN zsk5iE+jr{i<@DCE4i!81Ud@y7=GCnFIX$&{EzH&@^`KJA(f7^T@Cf$OwnxxBs47#9 z@XmjBP={S(zpIE=$!hAt+-^;V4})1#If!a$rRtc%)biawJZ8Pg)zcPXAWuzhjWtPt z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1on);-D?$1@8ymD72Rn} z6z(8VJ1X`^Pm}&%QBkFKW>b_nP;MYiYFC=$W_o$_7h9 zhX-rj9;NlLSonk6gWf?JW&8CNz1_KIjw%WqKAG-=GkicFOFv{$8 z7iw?+b{J#r5O4Da`t3ueE-t4(SC?hlos_^HtTFAk-%UCM)*}HDAOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5;zb9cGF&l_&{`;ojmje_UGcj z#gu#U=|k^;$^i~qZ5G}G6k;)ur{~n5y1ubody*IOocxNnGQ1tHH~BX2XP%ne+F`DF z$DYoUgSq%?Rt*i%RP~8lK=^j zz|0AlnOhuYu&2dSKZ7bg(qU#;P67=QFb%flo9bzi^Q3Vfut5?a0TLhq5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLLAK^`#xy`nF=p_i6d9{q;yV&+JI1W14c4jBP6!FVR9)6o^} zjB96H{fZ_jB7unrm1tm0?w>L0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2J zBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBygw*l$I^_9b58+zC|-A7_}EOXlh0#x>hNc z*Z8IRAf8Q=T`fA3$3I_uALMLW>9I1~LG+lX;5H%<){~Xukgbb^%#+$f-Giuo0Bqo} z5-2TO>^scXdf%dH3pz@T+KXwMV*LX^z#M=+_U+=_A=011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg z011!)36KB@kN^pgz(FCfQAdfO6MyjtVXO^vo`ngmGTwkE)1*KO^74xR)^fCNZ@1W14c zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCO$c0@JN?sjz0P%5u1(PQP>=V?J@c4y#o*^HJrg zDm}_bV0Hv%b*x!@X_`LGsu$DrfptlM1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c zNPq-LfCNZ@1W14cNPq-LfCNb3fD#yTi*0prL0U-8g22%aPhe%neVCvJ^;QWt&$>9y zb0Jl4>*~JG*VjPxoz$_)hL$Dj>%%N8SKq}}EuBSsoiEJ7$|186Zk}~<)Rk*ur1$JJ z(Mqw6NQFV>iDLOaPG=pjw~q^^Ui$~a`m~3kY3r9D9esUCFiLjDeHf)l>W}~lkN^pg z011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!) z36KB@kN^pg0150Zf$AlL)zV=-&1>bUP^W!&NL9tX`c+y7O*UxBUSVaQ$`<*B3L&m} zz<0c^<_5%kLt|-RBsDbAyO`(bx7N_i0XEsSJT7F)an0kq_Z!hb-S0pNW2$*9qnaPw zox!D}wlR%f)S0IC?Nzt;C?n&qmJTB`sMbk6sP>?mgX*!21W14cNMPR)F!lCm;cC71 zX`KWbAzLCq$3D?(da#||(q2igO-e{$A_8IATscmS1@SnxC#iG)dwW|LY^S%hSJG>9 zKTE3nUoCB79Jj@LOh;V;*iWyYye0=#p5q(tLrp`YSrQ-t5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TO7K!0?-Ehiil`_i8SNq5*MltpUne zk+1dgdosaopD5pBTg>-M4~JH)Ib2&b&b)Cnz3H{`zU8UutyWtYeuLU@jcUtHNbmT= z;jPrqaCjf~LZf(hYQJB%H&z1TZ6gVh(LB2Dvi0HyrfoJw$y&>uhiBO4U+%~kN^pg011!)36KB@kN^pg z011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg01507 zfzlGe0lnze?3MIZA4O-1}%astn5?SBEL`}#5DuD<8?JRAm$qyO9LZe z6EzVSv}CWavQK4;{6d8g*VM0I_P*DKRE=>%W2tcjG(7_Xr6qy`EcR;lN_wl0qBCi& zJNSOaUUZa@011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@ zkN^pg011!)36KB@kN^pg011!)36Q`+B+ze>VL!PWW;LYpcyQajrM;5e)`3dxlYz{e14V6cXZsx}`pKQOfrW$H z8?|)IChquyQ4Ld%1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L;NTJHT};?3=^fP|o&IJ0OL|-AFPXay z-_O{OMtKcjF<(sgt6wc2zvlfnsx8f4n)fYF&Ayc;ERMOvXM`>Vi+-LhJT^j=+eD?j zbgq~$rpLoEPED_S=MRj~!u1h!hN|R!%Tq%u-6jg%=b^jaaoC3)jtluXdnI{UNR6Ts zbn|$!T6uk+n%^x;m?r@eAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLjA!$;trpPFP$2mP+ONygk;fvs+U}$P|oDxCs4SDw~(CGxSh!v z+r2H%@w0LW?T`QokN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg z011!)36KB@kN^pg011!)36KB@kN^pgz&<1}%JRZNI{nM~mkh=*UcGyNbg;F=jn_scey7s1V|s$2OCBGHmf= zLu08K70pjUV3g&BgLL|r^)DIR-SO%z{KK8=-hNToG@rEE5Cou#Hr1UpAw(`%<++g`J`v{%w= zb3aS2S9Wfcbv&c!R2m;BJoya+iw|Vs)TB3zwd0lCLulq2l_Z>Z`^x&3N z&4b~inXHyllh&*5(Fxu!Tn&a&67U4vguCnS5eEs7011!)2~0)6ec3#EnAXlsg@ctz zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@ z1ojgFcaz(6%c^ERoD;t@bCU<(U|3id;_`@eSui+1rn&*H(W^z9e#Ej8!(& zEHSL+?Nxrq(dNc`Xj~9pR5BvEG1XP_ss4t?wbkEJTH+QFM)_L8{ko_y^ee}?(zi(z3|Ij(ttcbS?S5c6S74Ky`M6N7H|Z_W69Wux?`tdsohvV{4JKv+9hjx&XN z5{=B0Fs6EjK&uCuz@Venpn*+VZ;;LYWwGgB#u5@B0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+H#?K%l%F zG2}zscZiF9O9mF0fu+5LCH*`9b+1Z~q*SM;{IChaTE7t2JU(5rAHP@}v$|RxWfX89|Wr!Od&Y^riW45!TFw4skeZDjH zvg@+lS^3I#8+zGSyYntrZo5>cq6S4IFggJJo&l((i8S05LkRPq-GeK8QP+$ z!$CmTG>p3Jmb&}$A1VnXt1Dy&Rb&oc$6s!1=<@;OPy+>;9G`$5ze+PTmVdpOcGwCD zkN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg z00~S=V0O#Rik6D$5qmZ_q8`;qfCO$o0_F9A`-s3@pKPo%jZr8sDIGdOU9B-zTcRI8>LcO5cKpbCcppoX9aObQrKSJEqeDI0xl2&F4^&2}EN=MFoyx5&q zEp4Y`)1jrpSc7Or@re6-IH6@d8d}ff9UQ8gt4^3Y{r(9nvKk50NkG?We0U?+@8Wr@^AIX}AT!J6R) zvJeMtn`%Dc+%O=BlL%RZ7E@r-)z@gu;#8KW^2`Tv6<_W zmsehQHPiM?JyB__-#CIi#FdrzO!)Hesl91kdkZ5sF!l@<%lL_CqIx6us;rnSmnAdH zho8G(uyRaIk2Uls#4^xul|IU#i}gm)pI9e(tf%U@ z0u2!ele1rQ!^+F`#?>#^A3J~K$9t;Gx(~Cq*VExa0$nN`mM^LIWXtt?6lNeeddCcm z3^1WfWyA6%^@+3YN0ai;28DcO`GD5O)gNGLXwlM>)hgrs5L9KMJce@K)hRHlvN5^L z{k&sJ^$YpR@{)QnJFb4Q?)d3r|FNo$>qAw+I5LwfSB|Mro@>q^m4D|bA2ofxe|dG| z`pYVB|Nqs)c_DSeWZnIQJtP${3AmcT~L<6({4A`w;34i}QAk z@*%`m(!7r%9kM1(g!oD+pJovmd|pgHN?GUa7wxvvNbf?vi+?)%XOU_)n1RjR^X*l| zgX{Fx7*F3gX5Cg|6)UA<2db^wNVV0Limd`q>!`L=OG^#`aoDzzMlCCT2>+zeWFMmv zzG^>-ktXrhzJI?HMvnPnAaB1s^(oJ$hqB_~_|&uO@{ zHx&%}*ocWNgrORE)?`vi<+)6}XNlOHe6g{{bF>vrCI)-0P7L;XS1PGAzb#z87fNIGdKa*@?VP^G!uz@2G6=`aK`3ln)kOA6(q8bYM?V zNqBqaV!@HplG0WnrItIdy z*pTC12+sK-QxW@eT~RVvB=sylNlV(w+ROS0VV`jPe=q3w(HShxS{tN>9VwjyDU(#$ z@7p&0uHtt2UlP) zbQp2m5;-uX@n7_q=)R9-HnO=?<4hSy`rq zJ*p6*4KQ|PTloD7+;PO&QLEai_^nI&JjzoUn6E-#JoB!WT6{t6%I{!O8sVc6jt()4j^~nXp*d{7=)~wfktnLw)14{_xV=m zD0ICDMmlOEIu{ugN9F{Cc0(JryagvX%f9gfa4$gp?D_(Z%0rUr8a-8`SCQX_j9eP9pUM$_pxzz_%E63y?t+X7D za=!A%m!r-xaxX*%nw-?ZId6#ADBD;d51seAj`8r?>>g;1}53}6!EM3C}!dAG>~NCYpa1?WkE z`@uwf;k2-cB$ZwZ<7^=(jB9dWJa$Yn?YkxI&li%q`|h?spCE3#^NL6juHoZOFOumO zjJi;6pQ!bc#PD&%a|vv#l>aW?^<#ikWzQ7UR>N>#Fu=WOGF~) z2gKnRTs}W|`LX2wsm>>()>rEIzfSukQF`tgvk#^7$+2bM_ntT%)3M~38yj}=^cVzU zf>!298c9mQCn7+~%@d>~Rts_Bd=n#%oJ-t6%vBc?3?x7TBtQZrKmsH{0wh2JBtQZr zKmz-pKzu=d|LXjj#P|)^-<*n6+h7wdd?l7xsS`e*JRcj$s%K&&k$T3<)n`)uR|UPc zX`w!Taxl>9)&Edi+KWyHds(}&fgB;VyNTqs6Aaz7pHBPm<=8mo&x9(eEp@chl3Nk7 z5F1J2zFmU|A=GbgIIX9=6hAP@EhAF?od$jGbW(er_B-Ar@{S)1+z-KNj?!)sLb) zzRT+?6=GkmbgFkTm1pf{daKGRyY)&na(LN4d{*kHxzr}^2T6l(D_(qX$Dlk0ARjh$ zcZ~WwQvcaqVS@i@c+g6srJh}tTe7T8$6%k`ecb8!dXR^5v127K{ZWY5TQ0AW15?Pw zjFdZjn;Ln9V0T3+E&t^QGAlofNwzX*l=Lf8%HUrycujPX{_>eI~-4<`Sw(a9q#Tx>9oc zY)*^uyY-uF!IEkrnC zMM;EiN4VKrVs{inHdB;@RmN?*3Cqf`?jS}BU9(-Kg1i<6crhHdZDThSH19;2JIg1RZW_Xvz4CRb}VScW_-uySukr zN^UmRqG5f#g`}koY%D0d1mS{8EZk?48`y3uzhDLBNNITNf#5Jmq<6Bu>w%yIJxL?`_-x>g@#HwwBe$TstXwye-s~w3mI29z$vNsQ91Tla- z?(H&28Ca4JCP6H#<~p)KPSmv&c6+oV*Is!*dQ+KHVxa6V0i?Q-y7mD#R*`4*AT{P) zVk4Fff{`|TkU0HV6j*JgG!0f_lse<7tek^5n9Vdo;!F}!CL}Ok8`7STiZ&sUwDiLu zt<(efbX(OT#y!wDkY0(S2SaTrm+a==ygX264wG^AB?EG zF{Xmv$nTAr{N#5jlVz$Ct_j~yD983MvQ{)QAbAv4P)kLim`KeX?9`p0`jeWeTwz zz&l!6)$)NWT@OsU596o^u{)i^2Ev-u+DY4%GVJAIM?!o?wmZ^AE2)+&9dR>COV&zH zTtEl#uVvd_f|)0!2pE#P7CQMk0M)Jkh=2w=79_BU-FXY<6%ri3q~nm((_nF;;|_Ds%c8VjQ&=A{dBb zy$jB<)l#~vtQ)KrZ84)IMgcx{7aoXJYYW;aP!Hqh8nl7j4wU4%Ij*PLO*3eqlNyoi z3@DIoORR3m#_iG;V?d8nl9+zN4QrLMAbF*pw4NyJNigD0tjBj5>{tkLZnG*eqTf;5 zZVwaf#A4&DO58ViQ&Q}j$g>J-g36)f4c{r_w66I2E-eQ!FO@T<3AN@EE3L$ZYml?h zRG$=aJg+4USDJaL4JC^l*6^u$Zy*Lmqt??Q1*4)X$1eFI=*EsM{EZ6(BqE%zw0v8S ztZ0cRb= z&X+DmN;}8Hkkx1h!KNQcOD-Qk?8-#y_7O?AAR1Ac_R*1l;A5NB$WsMHi#BBfblg0V zPOjmDkzgwy1nd5*cuV{FB4dHfeQ=tN=3ENrkvQJnIg9-kB<#{f4V45R*xW*-l#z{g zTXfed_2IRX@rTtS$e{M;jJMq)o^F-z1HB-38V*qo!CNinO`Ro8B6*GXhECpEOB z+))T|OI?fQDA-Ex3l4I45X7xC7~=yCiRTR>$%`F}Uig%Y!X|KlzTOJL5#oEk0ZQIB zdQ%EIl(b_Rtq%)I1{o)6YugJLb|f zOtvG(m@LSc5}cM6T}u`@IYpsQ%8$sO^idlPc}pm@_=gY~2odH@qVSam0oJrjNZL(J zWj9r8!*;#{zn^cRJiE^udSWj^Q$`MTt~m=y2!4izTrp0*T^S<+w~>UjY7xn35TsY~ zkp|?0OO0(wXh|b18y8`pI4cRMViwXh)fkw$x|MnIq_xI83S6!zu=h{|4r@>@8x& zcS5Y-gWwjh_#|Z3rTjKi38fXW*9`ipg10i~M&d+W<-nxWI=YF-;@{{YdYe@V)J<;{ zh%xL8zEh9}TzJ?Gy4As~?SQO-o?B69gsTrNbt2MW72`TULuB3mNXyY(qfzKXl)?+g zSc5{x7zHhSJG_8{g|uOAh~`=N6?nzaqexhMQofRu6P&A?^%4TnvM%o46lE~zLQ$5A z5P4~Jnbfoi%H&fKaQHS}Y%5Cph!+2Sp91IKL<%jCYh3JLowM`0(XtP&c2+T;6P%fi zL9ANqz+tkftJD|ZP$6t!NxHt74(?H0s)}4`{PTc!05(!rwsd6GW+&UjQQAsQd`Ge@ zU+W^sWum>xIy(!S7R3@`*;p~?LV~S)3c;Wc@;?p6NZM5sNl1uL!dj{-y+;VeSt1BR zEK0drLAopQL>Y;c!YOssaEFGb8KQk%0D?ydZu}RKbE|J;o?vgjf~}UX(`h(^{^$hX z@s{MgXo6VjqfWlEl3Xx2rs|G8BMRV%1C^LE#%o6x+&LnN*th>=IgVV+;F2x>5tI42IpfvoVOuV{+wDBKY zYt3QWplnX9sQ8MOD>$_>uQaUg;>dpmWsds|1&LDII)Q1WJ|WgHJ8#@jHzc11BeB~^ zV!wp8bg3hcW3Wp8j~PZMo594OPTW-wt7%-m^hlQ0va+k#|Iwb5Cr|HOyZapQ z%VEnA>@uJf|%euI=ptg}Pot9GAq*R?D^*JG$?YY|7!I0*$X$u|4ulDz@gWI3HIO%1Kj!(z4s*GX>*P za0tqE^bit@?GsWTsh$vn=Z!?o*-(N+B7WI+rehl?2KAyC!ekrQoFd2Mwbzw;0Y@VX zzogA;y>%AOwbkPjn;M$X5Ej{9V5LTPa3ax9gO%7S>tac}kSbW0@mrV7?4|l2$3;3q z!Jbo#)(tK>@f)ZsuueAG=FCM@F@1EG9p%)jA7qZb^=h^JkkHc_6!ng3w{eZ-_kXdc zE&8cZ6t^EwqMrd`HwO3sR$r;!oGAPBf;y?9?YDyAW_(JwzLsFN&s()TuavsJ8q4pU zo8J|;A5v|5;jUKu9or9oZwuE72%l3nVgC@ot4f)HUqq#n#>$wK2aU^=n#Pwg${KeWE*B==}fey$^h3M|J00_v%W%>XAn+Su+;?TN3gh z4~`L*%{qi-N}`z+jyI9<$Y4Sk+3V*uB%7GvWDLvml-li~EjvagV`H*e(oCFq7+B1{ zXR_INAIQYZvh2KI0wKvh96N8b8?u`?lV>|*1989auj<}b>(3aQ&D#&3_wkXss?MoX zr%s(yRk!+f)xBT6b$R*3zTNXzz`x!n+tZyHl(8NROCu|peA36nu;?fE?K-;rx{E$~ zVRqs9$DVuUjDfdb@{!MOtMr=PS9E0Dv{c!VOeWdy?yfv@@7Ra$rYETpOKq$?xj~@bZ!?I4tTRT39)v7DYW&qr> zG35h>6+;rT7on7kH-rbZH8x4>BdZrNG>}{G_xL0!d?Jnr!6#ScAOFAc2^GGGak6da zZ!O>T|7)KwQW zzqGA#`W5N?LaEa;cT`5Mn7rc3-+g)IncMpBT~WI{P5xKeU46+b=dZkHa{2HF@?Tha z<=38Bo?N;813Rv5KC_VTUAe8^9Jvj?yU$O*cKH0gk38OY&U4i>zA^KW{6}v2_4ohI zJ3rP!PU{OFC~XIZIqSZssF({I|2>-i{^vkjwnI$=M2~F4yj_YOi1sbSulG@%p3Dm``aWIroW6v$Bs>R{2{&$w1d7~I-ec0O8Q`} z$4pno;fjA{!6HBV)*#P7-qWUkeEE_~dV2%cIvX4dvU}i~Mzx{o?;oGg6s+`OePZZO z`>&5?*yxkeI5Do6M;}!Rt1Qs?N*hZ&MbK_9Oe=lt*!5fYhr+gN($1a^>4M%KJkZmg z-v3>F^28HU?P-YsxvO4Bl)MO^#4%IYc47L!m+{Gg=N~8ScJzrVeCx5_2uN)^YcKSL$T82*5l{AKyBIOM;(aR~X@;X+)%V}* z4!tdQ7QfCX+)j)>amICvxyJbFXn6io;YFuQ9U4W_b6b&6_XCcHO&Xo5&~n zB=mQGap~r>vYk7HpY?wDXu~8n1i$ox0rJrU{nB?kKYG@{c;LGr>$|tK!OfEmbj>}OGT=CL!yHuU8)&s>;Z7<~Ha_q?ag)xCGm;NYI#g;$85 z?;7!%)GhD(H649&;)Sc1X3xnduSs~X)_SN6{@@R;QHD0zfT{vb<=6N&r!Hylf4Dup zu(>=2XB{0i=7Pah>FlTX54PK9wu4U|$0zNWSl|r|0D_XFN^!P7MxD^_t)lvN!oS*7kiEMxVTxaq>f9oJ?}h;g#XShz{!MAnsk+wH;Wv!BK%$Ie`c;{>1JC+ff_#~3G5)6-MW9y{qcsm!nh zOsaQR9MTfAIsRcXlI%0$3vu8BFXKSxT;pEx5noosA-_ED*u`Jwhq!aL?-z=4@#YR! zgebr7k78Wn#6jPYTTKC}>M`aKmN#F@b%E}b&HgfV$}(SxGP2Vu4vr*yq==VNr|ix- z!VPt2W9#eAel>6tL|brvG3e4c-&p8uI_ry~e6@^I7bM)HbC2=7qx3N!SznK-hBJ4* z{>cZd_|uPXio+SbTaQCWK+onloXOL9MhPh6^v)7TSOoc%Z}2?{oz$StSx@^5K86E8P0*l)b#nD`ariaxZoCT>Zf0Udp6r z#{BXeVcOqSxAK34a`2b=J(nvjh`JT$5xGZI$X6_WFCGE7C+g6bESPMhwyWIaUQhOu z9eD-67G7j1;!|K|(pU%)Y?;^``!$l3kxFZ%nDS&(hjJ`{_HP^Op zs@ST6?-^WKG9+xYf-i|1V_7Q`(ec-TN1?^Pfs<*|#oZ}JqKh2Fnkm~^lXvBH7b((f zxvtbmIqUQatZR$`jX@HlO?d@j6FsuOkZ|y?PtN5|Cii6Y^`ffJ!^TXNuIKK?qHPOn zZ#2u&+pRNCN?o%? z>ISbrDckp);W{M?;|4r#iRW!TYnP4=-`0uFC1&gFO;pP!%uk2L#k%B$%=k@wCBc@7 z;4vXV-!*cP??N2OrR}t>sQ?P49SJ2djqD}*V&awFEqoGdqn?w=wbD#8P0@<2YCKul z$m_Q%(xH_NF9^1ip@dt9tsxG(3?#zk%h-nKRozmFDQDQ*3l_j?^yrVvK?Db>I#5*M z3L-QmwL7Qevt^2s&XXxXk|)yVWMDUEl>IL0%G&lv5#a~A4)C*LC%rB~b3%@S$dZ?@ zk)f}+jruSHSObJWov8wc%6V;$>>;U~B9~MIAET_yaj_;*t*-IwYq6pSGy5vSQ_rRV z53c!40K2Q1M9Cp-xZuaqA?)DdI|228j5m@=|4R7rKN)Zxb@=T$i{%QlaeS3U5ztF% zU+yf#0o~$4CrWmvHbWVee$*?{!f5G_Z)l9oWollLCGQLLt-q zLuBSj*mV*~@m?Ej+)os@GlzpRPLu#aPlu8e;G^TJ?rtt1iA^0gCr5kC!j3>xTETUx z$3sog#|$i9sTn@rnbdisUE;}1&G|&7mt7jO9FgAdwP;AWS>zahO`n5>V&0&rP2S{& z#0}6&N%8?PW>IEjp8zEz)e1G>B}fcl6+}4oJ!MLXYsIitB=CTHzFp(VNbrC2bo&r`2 zL_=@ShT#miGy4n=*OQlpeHzGD``BKV(L2Q!p^yV_&W9?`7oBPXN80C2%C3$vTn{BN zBaM)W(zIdJnTbZf>0|T1_$w-w=TY=%IExjei%>~NgPn^Lvn^Dy{82W+JtM@X3MvTY zBQxTB<_i*8q|#nOeW)uy;$vL-!;()^3(XaW=aWRmWSt>om*tG7j|E7yXM$?II&#vB zqJ5dp3+(0zz+&K+dqn}l2##-3wA4`Lmj@>|>yg2v(okQtX$)gArW9|zSS^HMCWoNR zu(`s#6~a6pvclf+ki3X0M@YGV5ukVn!WZKLV^1x63sSHpbw7!Z^*Tt9!%g@Z<9(3e zAp(vMTr0LH$EfO=oo^oKA`K_d5yf4TXsWL zvoW8I2NQa_i=i(_q#!(K+LN#ys|tgs-)L>cb<5QqXE_+o4eL{NulNn}P)7(7k)u#R z&ksrL81Rz5Hs4jBR#C5ir14KeXDjg>#A;rE2B4X=a>s zo|TAUdjHEL!82aKeL8715$zJqY77aoamJBlOBd}tDqM{Sk#cqDM3CL7v^27z9IGL~ zij?y)o)D2VD4owQLqWiLWC>=MtWu?EH9wf7*T?p$jr!1lMra=oARp69c_{*&Ff%(; zycW}HC}_B-sk84;$@?WBuyPTj9P|bR-m%sTJ6c7_;u2Us8b3ZJg{m~br7OhU!Qi(_ zEGgzT=^OdWoLEECWIjmX`<3z?AH5HRIjow^=qk%9#*Lt`B&5EViw+5Z?N6emp#l-Y zbyrOb?;M3deqd3uGfuQLnsE4l+O%O_Jvgdj=55Ui5mYDDSrMVe9Wjn6DKquh>(Y8K zhbEyGsc~a`E4Aq2Ilt$;u`T2E*W}3GF#4M*5}u|~H1;*c1;i_-I-r0VPZgMDAtr7vj>&C{ioF72H^kXU|i zuh>9Mz5S3`9`okzV7Fo=MJ=HrgidKKhAlB_4ZoG)H;(o*$$}s z+*~|F)m;CWDUjG*%I(ln;?yM|Cf+-YOy&r}ReaU+x&_TC_OqQsq*wvLT=90yL0bx;qdOO_$1T z26QbL{^gwJ0}Ta<0(4BI)MD*~2}q-`yQqE05u4WsCA}n@Y$B?#+LzWGmR>pHHJzX~8qNKp%Q(-g%fRJX z!_+EtxDTzQgl3p)dD$++kY<{r_on8i+N1~_sCV-%MRJx%2g=hvS&gaFTSvFhTj#3j z$e1oMfWA3LZmdq|6e0PeXJ|e_3J4uM@$E_kIK#bUcY~+*D?q#Rzq{ z0w_0I3Q1-PZ<-$MSay$ClMZjYcD^QwW|8lup3B1>l534Avte%mqdQ^<0GNavV*tR@vtEi4W^nZoAa;p*jbecO%|%bCupLNhxr zL)7$TUXWEXMLo4kHO^Hqte|=`KkSxvnMMl%4tg?95TF{wup*sDPLeMBnZx;zq$RbC zOXci@G5hF=Sr{Lqw!-zOfJEFa3D zz9XfCr0BUqG&5bQx6EksHs%W|wU!*^25x62-6@o^4kDkTJc$TCE?drZ*dk7_@MWT#LdWg^Yc|}yHW?KavHVscrv(_17dt)|)5kD|F!Pk)1Kf&&H zm}`PJO!>Oc#NjKw>&6*#eoJA5P9ma7&?cs(Oim-EqK>gT zQr1i{Jg}hd9SFo!!hCn>lGqhnD*=eJtdEcZ=#DRjj|ZR_g1pArXH_1rz^vH?a50t! zh(a+HN-?tsOOK3cigjz;-6|QsMh~fo%eZ#S^T6q=%L49;%d4uR#7FY9y3edguZrnm zb$~leZ&i~pFj754Sa$^ZYvu_vU#$-tQzO^yo>Xmd=}T4wpO^-AO@uM$ZG_E~z!6Lw zYSbt#&A3*$W40x^Eii^)jl&zmfAoamG8YhVb^hQDWp=0}St(~}5}N5bN|c4mRA7o+ z*-(xv9)7#_pROnlD*2 zOyq8K_lnFo;i#p4sXa$H#XH_nVFuB5k|`#!{icOwY~UbR2RxdI!q(~zpErr`WHz!+ zQVFm?NE=wA3p7t3#tI?V#SAfcPf#aj`Ma0otz5BuVwObcRKr5mJ8$w;N>HF>Zi6X3 zD<2uS^03>en{gDB}!r_jp9R2BP%#!bX)vtmL&2?C_Wyd-pO=? zRp(OeENf=xMyn0x92T8P+Q4osMUn~bC~V^j-=P0!5Ep>=y^>?zlIY*HWUVo-GTD6j zsHfmS(#$7^JZC52N~_I0e`9tun;c?dXlB?V?Nt}jcTek?yRtlAnGk3Gn5`~fGSIqsnUGm!kZC!Bok9FAZWbQIq zlpvl;o!}Arnpx)Q=;lr{^@r(=<|A%y@1bo2`^J8&cBA7y%Dd*8yUzNV>g1$%zxMjR zo3%`}doJK>g(P6ij#GZVC;fCEml`hqQ>k?>3_n?u4y)=)&@B`ZV#m@QpK71FljbgG zQm60G;-!~q!U)qKvXZ4g{@~85w(Xm_<1k+pK2Tr63P{&KO=6sU?8%mCK6b~hr6*hd z===vie*3Sy_MhK5^79}3%rE}4Pky*@=mR^BwyJkkm-C-I@Z4{H=b!x8R}U{Qv-xVN z-dowmSySy>WVZcM2m{Tf^XY#STmtI9)2|gwUe?@%QAp2iG zdF;8HZg|TdEU6Tk=WSa)yl?U=efiM+_@t75<6W=+!@UPz``^EQ%U^u<+*{uN>L-IU`a7Qc+=Xw=U)wjF-euBM<_+-A|JiGQ z{hW9F<`3TUUn>uN{piAD!B(Zes3c>XDh~6WgT*Pv?uV=>%m63nx?p#{@BfqavgzKVaS$vD|!&+7JnRrtib{m+g) zXU*xi7e4V9SC(%~Cm)%w>^QvKe|nnV`P=y9J?DJnr@!%gzrFt_-~Y}hp8J`f`}(%` ze*1m@;iumJGZ+8B?!)hGfA*@IKl}znt@uRPcQ6gSF3xbr>6dC+xY3@2Oc+$y_^Tz`%j!W(rO>{k8Ui#5#PUO zVgG@Jc#dg(-q5)nyk@3XJ4jbz;O|`w_FL>Coi>9DZ5y)24-i3`nrc542*w zJFKtBxKLKt*`~sww)uI=sO_QsML84q2Y0YeVrW3g-Uo*s4l;{!G-Hdt1!LipHqa5# zod|VCpDdVfKYiZMqJ`PB=gKP;10nyf+w=4IWP0%AK56EGeY$Pt3!ga7tUWFXf_d|; zXWIvx#{<*z1i>d;>bmnEcZx-yVAJ)maQU~MF=q9*eth7>)9l|pabw8lRO4o!v^zfG zz!>>|(JhG+4{C2b+px|jaer_(Z%hyEQ5=0jqVNe`W%K>xvOxib4_<&zPMpB}$f0Aj zUv*Hv7Eq_h-IDg>lg@dQbv}t_8@hR8`tfL&l2?M=pHavY~$Ro5W?g5-;>g%X5{ml(6F`SW>Et;T)m- zv$x3Mr$c__sT$-4-O1+;cQ%GDxiiL^LZ{iH4YMdTVq*f98|QATkdvJi;Pkk9$W z;@qOzOdDh~*`^D^c}BWOhh9}?Sx$QLD|>P7F`uoOk^3a)-H#r6TR3~iS-J~2uUL)e z5mTMnQ~7v?ud?^ujpn73W)&93=g zl}8?D1d#(Dbgk2M;YoECkhoUr!Zftd=pSOdKKi<1AE&bdX& zM;_&ukiQ1hA9OD1*O>T)w>WnktMod|*h|j)+1m_jG%$qAU6K)NN3TJ}Watr;=HiLuHQ}gD^vzY>? z7cN1T;n)@sYG<+ZqI}Z1?zDAfXt$3YE1%g=JO1R861)Fgg^brNeX=^GQZR75PnwuV zgC0)F2&-QX@kZO1co~=Moj5%n8U)^!PnfOCtREkkHmzUX^STlz9@47)Z@KQgDk#zM z$rUGpRy^S&`lPGKT5|gAOK2PC><015m7CAfm7Hx(nU?7o%VsRK&(;CRsr`djo=wlj zC*hpeE2MA84?bCV;p3zn7sh;$@`c|+g_j?HlK8}l=o6&^c~g*g`6Q^Iz;&?&BHG2c z%qa0PF6o{4tj^(49tUw8pIlXDJ$_t1X@950W7qE-7G@=1Ho{`Qq;w+9CY+n0m`d9P4=W1BU1y$GL_ z<0O9H(IPoQn7hoUnY+$CH&RaK6Jvh1{kY~X9ZN3z#%du(QIxsS_9b4%T?Jxt`!~r7 zWs~TW&Nx{x2lv}weIneW6z`PoFtG+~>nGd*8t+$MjZcOo!J8hAXFo+paWQ*Cc>L^3 z7+r&$?;UKPxN`G3;F2AwTl!>Lu9)64f8xrsj~mA2B_~+Lnpfz1P|&~PNF~`)WhTVG zTHwX`#gU-`H$^;Dc|$J#&%~JXh_eB=1-&ev7W_8GtWsh<1i*?W` z|HF=ZEIVz~b7ZWLHImo>toKS!-o>Zvt>zFj?ytnbk96zE^{IVeT zk=Pc_Q(hMIdZf@Nd0>)m;r+*BtaFPVF*!;v#H1zgW^i zxjX!TRg?}8H;Ma^uNXe+<4L8QEfoHLb>YZOwfS%z6#1MXlwxUK$kSOv!4EH4MOx>M z{HI7ui@M9RktHrj=YPUecX7v~Mp(HeB94?NH!o8&HULtNqywDywEzY$&M6&Drx zT_(ilfmThKiV1n2V@p^*8{gZ=xyF_a<%yx|Tq8E&K3>!-S*3nY#%#C+UH;k*VQX-k z$QFt<86QiMkUzx{9MNh_7NK~3sB(?GhTFBGYuW2lumtg|1=$yICpz~iJ-34e(*-P; zDWn{s52;R&c2dT)I%yPh+TbPy^P)%)qXFUcrG_YTZgs7Apc(T;W%0F2E{We0J**-* z<46LrOh|X#{|{MRfo9jDWEXXFQkz}6!3iNKsU)MQsD*O7AaFSd`gDWqMz%;VcF|l{ zdPDN;P0x?mz)+yv?CxY(Qc0veD?xrprsd^2jrqE7(ZiF{0b_t0*|5@)A`-%q;q>q@RK z6S;#RzBvQqMZPCiDSfO-opB*9^ewr_JSjvQ$52u_U`eHt_kv+I%)^t$R=vtdT1W`l z1T-nNPW2bP4N3sZ)i?m?JD8bfKi+UxAo77K&U_ zpiz2^m^ zLUEOI(DV_YMSO2mQ5&TGKd03WjwNm?@~b-#iUj%6+IdKhkBa-mCB1A-a9&nK{8H7i z1q>fm=L$uL3h5#=_{{S$ob%wd#LgSLn9M=v07BLA6ysqkN?Kwv&eb!VG#55C@so1mY$p0jW}TzN%#26M zoN=iairB=bM0`BWG>6z`0csY#gTiSAH)G{z@2c4%l8#hngz=$h2#XFCku;F>vneB4 z<*adpd@PXw<<9-Jn3Nm}R6BXjgrf)ex@NDcls|n1HF}svG zRqdcufi!RyMGcGsA3_E0^WFuI)_rI|Dg`)jp*$}a+6md%A~yrq0TT<3+^i9zQyB1& zXFX-q%k$K%)*%E9eFimEAO*RG$8S<*z)5H|?YlOxxyY{Ka0QU;HLzIHgJKh`QZycX zAV?-*PC3KWOM0%tSyqZb0~PjJy-##gi?Te^jPXe`)3z%?PUTKECyapF{68854Ir^@ z#+y1MW@Gk5jK;!FU6@+P6Uk;?iS&qOY+TYvJ-KOyA^4F-zZ!Zz>NVDQ>!Y}6eq@Zy z@@uEdm^G_a{ZK^Fgc2@zskmx*DAKK3Z-fyA!sgo%v%|O4T~NV-QG@hoaF;{uhE7C4 z?tH*{*`Us*Gujm@fer`1T)2We5TL2h8rZcYT7d*rTug&oNCIoj>8FL1f?4U$ycMsX zeGXEJ;E{$hse)X~=II8)yveLxaVYA{{p8V;DatF!jN5BGN|BX$g_Dp}z4}`CD!-4` zAW3-WFdIh7rL9NrG(Z^&2k(CuNdSA?629Z?&stbyu_M zoAd{S)9+wI3kd5$WWj0(OSP?!Hjy432+J$8<5)>pG2;_u0nz*{BY^$o23_mYyyc~# z(dI^AHHB_PfSmd$Sq-nNo2BF8@*blCX;AY>NLt>>K@RD$*+hd3p$UvZfcF;3Xq%4b zh?EGEHtO&I!by6>19sd61~#Qa=Yng@P0ARkCk{2}FfKSJqo6hZ&|C`ZmX)}Je;!S8d`)FY=a+iYOuqTcO!=q;k!G=m!*&EUD^w{B-L@$~1kZ#_kL#6ft`4=O|6lUn_@-} zk$HoVMW*n#4d>J1vj$ug)Cf9x-y5K==4R0;H*>wK zid7=Q_KzVx@%M=^~Er~j?s@jx4J1(!wKv;=QW_- zxIT#{1L$icjGr&2S>2dxO^qd>%~;%Lw(8H5(^wi9UE@u)3deqRz@QO3NEt5@|#-}k@K6e&G zZ?2O8X5a!EZgEa=#vsc3vTOncjlmd;~{dN|?Q#~Pa^n2|n9 zGiv!K#g=Cc3MsV#m;?jGTOxSWVz22k0?7i>e~W%;G?7AQY>`9Ej~-ekj@Yv%%&@(W zClg>m9h3`x3w(~v{S=cHLzmY1(m4d8r}PYQ1s~?pW9iuS4s7ilN<~?-B$I2>i^g6jO-=&v4zqfRbCk7k1s#pw$bZ^taq){iq6OwNleDli z#>`U3O1C;;W@n9=qgRHWN$Vwx)z{<=y_^Q8`HAsxXM2aZN#PuM&L(bez3$2V5Nkyy zl)O6SO%=nkE8Fl7z$mRo4Xy(|gu4yjalGepUQ80APr;K|IdLF-)r8q$PCgwV5Achu z5tW=2rq|&*;#2`;>Q-GRX{I*TJT5M;`5L~}%*-;bpir}7`Cj~Tt=t_|Mz{kxVbc4v zfw?J7)1HNZU%fZWD=V}z%T_68WBVkn3)EM0%4g`wZS~ApDB$r!)Pd9gL}&G>QVVL6 zj979c(k3=2WoG9>+w_2sN!_8hD^ij9Yl>MFzP;`-Zn)qEc9aY_WK=WMQcQatk4KoQ zC7e;_s>R}L)I4H53v)mLg6M^rnIK)^XuH7_U-Sq?0!mOScXQ398uDzkl$OuI?q-(e zILaZyhN$;OuW`-VmXh8KLG|csh%p^RoHdDJd4e!}>L4ugQFdzktMtSf<9Qx|rFHky z1Al*!E;-_0Pyy5=1Tx%69SJ&CE!zyCQp9t0nAF8k)zhuTxe4ZiHa2%+ibDXyQC-1V z#J!8)Vqpf39n1=$Fk(H1%cWyF*2uZf#iS1D24pO9bm%;1yz<~#rqvC|D-_Io9GqP2 z^w<`3y|usAt45jRCue4}>I(C^fMW2{&r%)X>^Iz2a*Nr38Jh|@>3F*694x4jRIIt( ztCCKKuFtuXc)|%0DwwAKhuIvGUbuGZlDxOv+S!84JV5G2K zT;qwUv%gtVEKSN}#KK1dP14gRxFJ@`f&fSlyDFL`nu(7sUuk;gO`_(MwAYj0324 z#o4GGX{G4}tJW-SGk)2k4ey=AcHT5@GOwAbv@GY>-wdALBxC$b3O#0a)>|&8qfPbL zeIw1i9AvUru?8O=KgHT$;NCFjh=cjR+R zljlubZua^yV;W)5Qg|J-Dxvia?g}z(oIhE13tu!~jk)?3(&_=`Vr)XKKA?C3lU&cD z=(Mw1BbAyN{)Ouk^VZ>9{e6N*C}=p}`AZ2mU+I-kGAFF&uXoAP%slNgyl>7h`T1M5 znB2Coy?_3~{-ova+HG31yOW7f9U~xxHBHjwu&!m($$Q@ZR&U3Z!!i{=_KyQE^HItWdG}ZS>mtTw06OHENY-$$m<^D!nNv`CAxO`|YN@V%6RB2>(?yAXZ^`39e-v5mKtG_(sv#;6tj$Ln=zh}8}ld<#3v(37Htab09Kl-o7 z%p)g${lRyA=dYT3|LU_JJ^I{#so(!M|Hn_&pLu9GdCUE+3qN?*PrZ5fn-?m-$=>qQ z8oi6Z`|Owg``T6~H;{3|WA6LxEQf0||FGhk8(^>x^DF6H@AQMy*K{tP22nqy#w%1KDhkhuS_m9_B`>~ZC6})^$$FG?4!^9 z%F*W@{Lg<}mm0VEKdt|9qxprUb9Q|6OyfigTrNPsA&*NL}IQ-DE zX)N_U^b?hPzH;=+-`Sp}gAJyw9Toqzui3}$=8cG<4Rp5c+z!h||NFjUyWeraH{bQp z-P_F9Ke1~^UU>w4hep16+5JEFp)=lh-yu8vFOF`jYMit>K7rrIGJT&O-(DF zyAJ=}XFvPV|N53ouKMNc|M@xZyDFdWd)LLxay$D5ZyEjQA1<8pwqLmCfqQ!ALAs; z%sbQT_~x9Pd+yc(oI>t%pf zp~>I0_Xkaxrqnk61{M~M9Xr-lg{T5vnph)z-QaHxvaR+Q)V1?-;#r8Bau~uxn2?{OlY@uGCpi z4Ui_CE2r@ZRTuIfKdwA6^4A5WPYxD7G5BO%Tj76U zJ~{3d7Jii0mOjBW06q!z#Y!vfvIGIX{GNIfw?_&b+3H|RWCWh#f_LXhgLH@viyBs;~)(L6}?dPyS zZ20)I?He&!mwHi^0^hrC+U0eHv_m%+*HTgu-P@KC?TzP!M-1X(Bqui~1GSlQeh>d)fbBXs= zYWe49*^5#=#f)ETK7DcZlyuju`SgfzV$pY9Yo;!)@=(_@o;6b=;P6L!P4_@Kx5gKv z`-oj);yVvHpBT<9&Y0o*w1Bjco(UIb*UtO}b<1GJjA+i&*+KZyo!1%3(Rs$W^ey>} z*}gPm!nwm)Ge0^P=<)2N;Z|pSFCs&OW%b^Y51m4rInNkY1u zYzAdSHsj_o?=<8m9-YzSo>W>b&gSX-;ssfDFZgJNF?3FmIGk&|K<5ubzRn>Q?;Hg0 z#TPf5LuVjX^tTctuX(fTdADocO!=MMR23aP^-e?mVo~7DrAtNM2-K@Hft;H>^w!av zvU}g%Ttd!>&MK-NZdrMK5eBN?;YT#>%coDoJkm0bxyBqCE!rU7z34DX%nqH{=6KE# z9cjbpO}p;Brpea?eJ?8Dn#Q4UF0$(#mOf^!gnb#@7-~v>%valVPO`toCXrx!oxzmO zw0Vj)97dl=*ZUp^#`ntRl6Q^q^NM-*vRUZmi?-&ZI4>>CFHZfmR!#FiZT6e}gRh(a z=@Y-g-@jeB9$qeV(}N3~P@3jQjLv{f^Q?#k4kq&g!ogZ+{`m+49d1@IAJKv<$nPEB zGtYWv`diO3P4FTxZ;pRwVc{I4cFmcAd1El+H1ij*mMSSB?wP6?4XFileEM?p7hj%l z$2S^tcKtwG-_zLG}z8)74W$0id z7vGaYv}-4OPtk(f9!}APb8|5Zwi8Nm)O#AAbk=ETxiJ6J!6$8e@!*LEg-4%g<+sTv z(MO_xSD!o>d~(k9PjiH;-F_Wyf9kn~tMEzkJU(Hq#Y3oGfKSdiJ^BQrPG8>c_KBH3 zxS#dJl)Nx)uAHYC0PEtyBTz4Vm@E zCuM67>}j8k`8tbAY1i&|dHFS2Hz5Al`eN^{A=_0!iE<6`4Dp?5NF zrn|?<2R`D>JsZZ!R2U}*7QA6mz&M$HI*yaS_%7{XoJ>#IqNyk0tvp$dlgm%LeEPw` z_q2~as6OBR>jj*lnrgL+E;94;_(Xl0%YNaL>F-RB$8q95SJd&m(b_mckYs$X<7B{W zJx(|fjZZq`WcvE{amLAF`zE1!SU#mX|8)u zJfU&&@VBE+e)J@E#xxcFG)}&&Plk_ojgxMlw9WK^g#!l`ezs;VYER!7ebW2)_^wj; z#5_Db&Nz93+IUg=3m7M1?$Wob=#%exoDA^2h10`j2Pnr$iN6%TWP!hP3*`O(``@|D z?^A(3=oQ10sK_#KOK@G(?lj~LXk^@y7_+*lvjS!zqO=Y_9 zQP>R*BX z=J=Fg%f$1?ZbSAuTt3NvZv)3>bX}Rv+21q8#*#gm5*zGZ~ zVz`d=?+9^Q$kE1!&9ITS5#L-QP#obF>WdV}E2r{<`u{huq35fT^_o=6dX*4&hp;YL za+PsHg1t+{Ur8-vTPDhwT@z)}mkGugVA+adyiy&ghxw?376~8Xbjv&&Wo<0-;_;4_ zESkUY;){E~bs29%TSMkrDxj8dJfsMe$H$j=h$GRKG`rSV-^njBBcUwcnZn!e=p;Q?ao0Yl?pYBRmnmM8;{wFL*s=< zhJwwq4+tqD5|;c`iKbgsAx}akDNpwrBuO0j*D6subWt7=m&a zh7em&jQ5ene#lsK@~Y4gcAyj#324>HDH1ls)iF=(i)=?)p8)5&H5ox~7sACNTaEEb zr}fyX#I{0#Bv6$D2fKl#b%IzINCcfkk+#J12|pEZ-@gP`XjF>?t0+hcI4`dtrZykK zKm&C#p|C3nHpa*D>42^|CE&s=rjvZ8%Fgqm^lc@>`nV`sswzcJ3Sy$7wYuy&)-h>c z3R+_dEfr%oDHa?JzdOaWMoVXp8~sUwN@3zq=~P{~1GbY2iIhEQa*P05ZiXPu1-dPA zW1LuD>P9R@Hi9h(9lkY&GAqWGH_Kcj(#LI zf|{~rbHu17<<_|%Eu`10-(@XwEuRPyXuEJ>F3`;O*F~0fp$nd2-=ghui7EvqW26wV z^rtvR)R}`a>XSQJXQnH(XGlW>`%lE@On zzyWOylClkfG|KNgC|cSPsWEM5o%ux}+Cym@`T(KjPcTVx5&CXX@=*&#fB_DCVs8XnA@;7h; zIi$jShe;>;;C}XakwW*mknb!QId)FPN{Eh9#XhcOCK<<}H9R$nax4k-lNs%?c}p|J zn9?Tq771cNeRiG&ajXg`J!vb}npw;>WNw7+trQBJipD6Q*rY{lls%@f&_y~6=+#On zTc3iel#2}W8agsrO(g?Q2*k1uT);Nw@#=FG4lf~A@7S0h3cb*P@<0sD>CXggeNf~< zjM^)At;)_iUt~b5^T6j|a-s-a2-gSIDt3r_$+1_5BdH;NP5$~aQBs-PDbvkVWXk_G z%xLm-H$zP0b1QnD+K{WxVUKpaU38I>S0W}OqF$RSiCmFGTA3cq22#jNl>s@h6)7F=i)NCM%O>23GDO-4wu?Yv{&i?qMFp{|sxIaW!R}HcuR|VX?Sb2p ztw|(TONHp8AjE})SVgGE#*B~_XMs+xN$oTRkuSkZ7I?`5FInIv3%q23mn`s-1zxhi zOBQ&^0xwzMB@4V{ftM`sk_BF}z)KeR|CR|WcIbCO@=cjTn8-V*P`=$DIssFNS`Tg&IX z;EBp*RMyeC?_))szZzq6&-%D*n;FV!N@&YJxSV)r$$y*b;(aL89rEvvaW+-p`duWJ zi}{88tgs31hPjN4q;IO^E8|M!-&npH+i0o}SR;7n1Kg+N_Uo4(m|XPydQKb;*nEk6 z=tl1y5rEgc61x-t@B#j^$j3W9tZ?xu(tA==KE0p|M>Xh^*F#qvIteBxa3P8 z-XXFVdG#NQdX?`}(K|>W8-ArQr||xhfE0D7N29EuLtu(^`LayGXJ&VWT)h|NI_WkS z%XMVGGuDxOKE~l4E-K+E=M@+EF2;Jd3slqdMf5>l+JsNAfqyej8$E1%wgg*Jttpbe zq?B<%FVJ!uZy85*L#FdYt05V~kTh|RL}m-D6RnccrzrBIl3jrH*C2@Y!7`?gUq3Q> zkMo4#&Uk8EV0C7o;4xm5JE7mH9N!6)09;oXk_9EE*TPVP(A70sOu3DO?*UIjnNA&D zKmCM^_)E}Q_68l-ekg+5g%az6b@}UZN+fe->Um-(V;2xpwGv&6E0e(|HiRYFg+#IO zDnq!)&h({$|v{i?tlUP&F6|^$$u)L^58n`W?K4ln^3Y;zI9ZDzR zNZAgyb;614H+d#jx^Q4K%GaRSsv5|In35cYpc zbZ;tzdVD$HJ6dMtelHJM)J{%ET4=QtuzUb-J!xH&QtIsD*N@?3K_L`yy&{xhKHtq} zA#4QOO(uSfIvS5vPwOJ@XdC#gYmGkO*lfEU~KI8-TqCsOigWad~mNBs?neWlzEZ ztcJqMm^F={j86kw5bMQ~`D&)!KA~CCvjeWEjm<>f@su)ZP#w}aidB)C=~n?#0mz(5 zkfE)j*$N~U8@&+ORkAOWY=;qu5l|R`mK4&+B{d&pIgkL>QpPDcYieoL>M5F%Yh0}{ zwv?DY+J$@@Bv%;=q>OcL)|k81Va&WwMd2epfbD4NL}7c1pH-$w(<|nzB=AU1>hY#t z6Pdb_H_fY!jsgP9$GZt7d-)_v`1tXGWxNlxkB21onM0wLIVZcNP|s*4EV?LTGdr6! z7PHw+ra}FMbER~C+{fk!IQj?_L|8Qncx!@z3@oS zn~+lw>ruiPBwIq5jAoxT$c*(JOhr&ScmS0mc%g|si%MYTqicLth?l^^D#TzsS`?>+ ziX_RQk)c!|sKq24e-Yp?TCw3hDq*)8wMU6wIlx>9T@V3lz!V@T0%`^+h7O4trL`V- z8O0WSJnw#7Wm6M!cD`2mpk8%BbVON@Scvi>M|-M4q{U+S1PF6?vqjC?oELx|=w%z{ zL!E>YU{+0P6^F%5rqF@u(}5LpV^M2KPqe!<(&F6R;WgE=K1eS7dzlTXI+ zrW)1YZbM)F1L`j>lnyB5kp$7+c%Dhm^St%2d$9!;#)lsdZMM#vBeijFJJ$tECFmPhCu(<#p%B8d=(Qbk|a zP|{XB4j+i%+D{!H-C50Ix z6X`Wb{AD1Tg2a!89?l--BK`n~XZ?q?8azcW1oeoVO^^>pcaM8hz$j0XT$i>jEBFrH3$XkS$&+48p!Fh)R)qmf~ixd9Cg^KqH^(@RqMy$Wl2qK6>Miy zyNYKM+he)jhnk?(n@3EmJ|6lz#gS@zGf#O8Wl-9*QrqNNAXmsI;Z<9 zb)#ACn6aXsY8rp8rpy4|n<0;3=-@IG-~-(Z)D0?$!bg|HkO^wl_@XX9l<|!)8eC+U zGIN8wAzSj2!}Fp|Rv#k8Fd$&zZ$#I}bD<7JK)J#-`UuPQATt!&P$b2fa&^rjE8bP; z{|7Q;peD6qWfE{xtq$zsJskO|*7T*UVz~w|Ol7n6AWC&E|2)sk3+|;q)EOLn9l}be z!JxO*0iG;Adl9d8NSwJgs~Db$&6|P*C=%l=#gMsUF~JB5Bn4g^k&`r-@DjWdcL!gr zi2OQiJO#;_nkT}pOUx9GVsj0YgpvQ=*xp-tyNtzTs}!{2%@hbyZ!+sbk|4=?n4HKA z?PnCt?P86RCbrOHDGi)HTR}D-%}9|_tji*%HszY4Lp=-uGf=zqH%yJ{`m#6Y_D*Sq z1id=ulyBN3A21BBe?OYPku{SQzo0VFLRtFbu)b1>Kb2|@saha)AR8bH&NpZCqV<@1 z%z_1VGxH{UGlsb?xif2G6&-f9>YmaqTE`a^s)kTa=@K6WMYg2CIyJ{)P#Jj$<~21l z^jR#*(5p^q?sk+9cN2*1%uedH;6RRI7|&2~Vo{_?vH+(`gKJTMD9|3A;4MRmN=P}% z-TxK6s%b*9_0kyX=JiNgZ8~L#K#3qiO$tSgX&L9p=7SD|^Ea-B3DM7wW%pB_Y-kL=Y_y)!Eo4yS=41&d?1H*>K3@@C zt5+xyu*s6~-b*?kyCd(l9xgrBP;D%PfOsY{o~-L)IpqaN39VA8BM1=7qz=RxCfqfJ9 z6p3M*Cw446z0#qkcM$m+4%-x^!k^+b=%lT=JW%Ii9&7Y;CiG~nqM=NOdFSH^32|42f&<8NFO!!Z@Gg3~@)Z#h991 zdBOupxsEnhk{yfHJRegAGAFs-h82a}n_9{CVI4rFiIW6DkP?%Q$blE-BN0hfsq@W9 zdcQL{_C|JCsn)%r1DZupJI4DmU-+3c{fuEg*{lWRagJqV-K z7$+1N1;iRm`k~8dd}ii&WkF{CO@jNo!3(KYQ1MVR= zVvY)to2i(OA2OY(u0Rn%8724vB?c;H??~!~#1)yC_gKw(UZLzva(A`qsos;dQ_rc> zoF{Ft8}_UgVng+f35yK+ZDQewK7z9gmKht#jw=$q8913$%RGM)*MU4s&0MNQo$iH| z5Sv$G##p*fk6w`$V4Z-Ctlc=;P6&5q@`B;~zE$dX_{5fS}`+n3Jt!rjq#tFc^00^lx;Igd6V)li!Pa2)2tq9 zRCMw6A2Pn&#WAyVwhy820OH1ATf0d+_ zd>EG{J;O7}lyzx!q6a}q{(;wA6t20iF?|)!jiLUEt4*M6){qH;dWv?x$!0yxn|tzo zzf*lfI%)bQJlbcmNqk3`#Mtij_J@GI9}65Bm39T(R@Do6S58 z)rFx0ticWKhz(K1N)A*dNeBBfF;>kPsZT9a+oay}nYrW|)}qW@eP+>)@hs#ed#7Gt z!aoL918VpVe;}()FI>qIO2MC9jMyv;bsywURqy)!o{>|vObp-lhNk{z_SGZjg;yL? zyO%cp<*T}vf%8d+QdCd^eL~54rD^J!l1(j3OzSe;HT46Z_pKvl?9twubQ$ZZ(X?B3 z4R9}LAWi$s#9bH7m>z_xpy3AfKz3?2F(KCv^=HZO2>qbAi7$rGGIZEE{8*M`jp2S< zpET8v`${g|`@%4!nx(-Xsa)uogjsry4w&k|)G#-S)ARX06k3j)Og6g1+;wC;arsDI z@eOstpoS+$!z@5l3`BU*jaeJyQ%UZJ-d6eSg%{2J{=a`^c0K($cLT z_(G1lK3m7z$Fg-KgmJ*YSXGE{d_f?R@Ii`4iZFua1_2h(G+>eP<#N;B zG%s*^o8ZwwHpha1a7=hKB_}Q|#3X^HN!mh#m1k+HVv;tm{_rL3m)lobqr`DZ3HW^f zwPx?5b7WyiAK&l$-5*QZ^H{TH&6>4lX3ySdX3v_dY9HJFo#~IRyZP>tS$FB^)>6eR zF=p%ER;Ipx@vATXYIkYsz1`^(-LI^~lhK4v&WJ1h33GmWfTtK=Kk?D$maSZV#gb&Q z!gHv(=zl)DVe_Ty?{2G9CM#y^#22^vFU~yhjXOTGEUxWL{fAK>`ShZnaEHlk@;6hr z{OyNNnYpdaPfZpXryf0Y<+^jaCRTj=!B6bE;Ou?h9=m7ioFymUcqu)o@T!g#r*y3- zuKc?t=j?sYd-{H%wDaB@kY(vPAAR)EQ;z@08L#}@jwQ=(Tef`7aVNZWY+Y9;>X$Bu zVuGf2Z+h*Mcl_1|?mKqVp&h^Srn5f3?UbAEn5Zy!@bu=m7=8T2>({>H`ra)kuK)D^ zIAP0yyH>pRx)r63r<}aJxN=1tB_=@^a4PIMil2!(oZIe6My}^kDYn>IeSk2 z$lX2VQ!bs}n#S_iDJWo?icf{`bVwYLn=&mHruM6jJK^e$y+aqN zO(>L+2iKTKH$D90^ZxYxe{$vXKf34F;xiw(asO1YP)W8$(+SO_82#Ya-tqS9xBSmv zx?#(&j=lNR)z7uR_w*HMT>ALZ;!4g?gh^(T`qZcX<+|T+Z@wLyY%}pzsg#$+*6LMSb9Pv$G6TJWF!&2;bc9f4ILtoRRQ4@tzZWkS~P9 z)vsVvy+S--jyrB_v#FQlj1$W1ko%Ik@WNA1ZENHE(GoG|op%~kyuw^RcD&5z=VABm z8}EAko9_}mlJ{qa+$NhI6q_7uYqrUz!qjhKlb@X_IXK{@hBmNg{?+OFm+Bwb^K_`A zu;iJ05g0fycc2+f?)A-aS|bxoRHQa}^2wlQp;$Un#|i@L>zg?3W|qTl#3p>7oiDdT zm)WH4g>52L6`Rm3Iy?7?HNtn7XFK)^U(Uif^(zP0bBYC#Ic&lSFdV;r;^8(q;cc&f zvz*2A@39GIWjr`GcA&7pCI=pWYL*&^JU=V+n`h@jo;*Jvhko>@hvsdvIL8;W311rE z1fSd{^(X7Ixh2x$>a$rtF=CU)A0Hb#@kFu7!TQ0u{)g)iKl`lE9<0yJ<^80fy3Qrp zx35&@9tWWm^VV8dl}`~`elx@og03&JuINLvZ{2kA7A)}ML)#caY6w5?-h zy>(oWLJrL7*o9p6(RrJ!ru_z+Y^ramW0Ton6X@&D9O!@e;mjt_H1(4OHhDs9LO#5pM8%nq}X^GELF$#;ln54jO0*?A=Re0Il}p~1;jBjo#{8SSpN(xoFp&rFm% zv%o5S0eH1p^==|7LwUg`zF|1EI)8+u@h;O|><` zGOL^7g@y9rs8f-ViApTKX9X;_r30kx4e-v zXv%K-EpiUZyX0&R&N<;Y^~=c|UlY#g;894=BN;A-^5qN>&P9=li+^(qU0KcmF~j70 zGd|#@K6=JTAAH~E{F{Zp_!rw9H-k&fyNvSU;9BJsU+2t-$ePpTGLcDj*-6=ba^_1v=b-S(z;|(u ziJVvRu3YxucN3@j3M1lPm8HW^ZO5chM%VH+rrJ;4=5=LwYXhLeV+BvJ5tllME{y4k z>8pEnbm5MM-}-0H{coH}2XID$>3C51)y>?TH3#=SQa6P$!;`+;2X%lN9yT#o2B-Gy z{)yzwLrX`n$)7(RY$Ccu55O!osfqc-CS%B)*`z~G$%=>Hl$UvG zk6B<7$s>H`Z6fEP%stD!^hIE7pAP5Lm&3tm6xsxO%!h~ANRhx(o>ihQ}I#hpH&vD2~4m!PXSSUBv_tu|#KC_9|ITvrZ z{s`7B?4A3B*%Xim~A#Jm?OCYqHxoF^*%k`*!>Db@3*rbEAdjehVww{^7lmVO6 zJFGJua!*9JnJb~}&qP1BdGo-)W(-3=*(;o2O24gBrB3>ZAatrvrKO(;BEYTH-PMlu zrL(c6wuPT^Dx#LtWRo_|-U!qW?aA{k^g}=C@29qEn2rlYe;suWcEoK{o2+N9%U9p( z_5Cy0K~7xbnX0}i)01iLCtDyS`Ou;M{*F!aW%bbO$VoqubA30F(m{PL(-P;Yq@TE9 zofp8nPC_U1a)G>`WHvGX*Fc00Z@;~&XFCNNvDlIO38#~2KQXR);U=UMD+D*QhhWV1 z2ZBvVY3e5)(r4>O(@!WZvk7&epX8+*b8FR9VJP|3Chw7mSlv7vh~O{hp>PV&?)hAY zhmJaG$&#^s1O23+A?+swQF>f2Jy`#9wMhqaU8W6})c4Q9zuvKbe@9`i{?xvlTYr5$ zeN1b&Niu6c>EHWQp3WHFu!;1O4s4d$1b*`%{p3CL6B%E6>Q9sKNM@5QTLRUI)_k?;M}eTG%zZzbo@{F;MoJ%CvKik`FP&_JMj3#13&02^z46Byw_ZkGl!F; z5M!!=f8mYn^@G0hiTmsZ(DAk6`JjnPW_uF9Z?hCoMisw z$Oh;tf7q0sO8QnNO1yV6lOs|#{){DGYC`^K#+z~Cyeo9-`;gz@3w<<`m9tc61dWcJGOz6 zya62EOb9kJM^K+*)o+d=U<0^mXE4t*Lr9X#!VCQj-SF~snFP#Nmi+w<5)HV_WiV-! z9OWdD>N}6EAz{C0xK~mA!nwG7fK+9g>{AyaCx%$ z3(Gt#OGfOZpkz9WiMKGPwq+X>9k?L07s>{NT8L{KI1Pk^CR`MxjG9m(s0(9^?UR_x z_{>N#e5=**Bc;}mG^7ipnV8V>qqXQU$mU@UuB8B>$t1A^1$u&~E=fL*HdkKW8TFEs z7cG2^i!83fE53{@9s(OzL@K4Lg*5nhB+A&?fVAKQ@_U9x0?tas~ zt#x$nT)`(!+4*Qt2*$;cEdktyNi-wQh019iX$fmcCn@r>9z(#X3%&kJgr7c?rG$Ao znh=b6XuZNOv`GHt;h{7`7f~$P=d!{X$k8MnAlPmA@78*qEh*p4_Q^)qsr54RMOBS~reL0_u42(E`~~i3_SqS4B}aBv82~P(HAt z_#s6Psw=GdXO$^zM9T0o6gis#Wf^AA)bZTfG;1g-NlcNz1vb2Ri_&o>@J{WIM4lwe z<+#Dd1f3S*DT(48d>pkMu5#OQEOK!+7Cm}0s7eV73^tCZ8P~Wc)k_Bb!!dG6`%(sG zXjo)Qs0I{?rFY0Mc>E8hqj&<;8nZKs$x=xplxU6XL-k~?py+X4^Rg}@{g^B7f@jx| z@k74TlZyRDc@t5NwL$^A4gZ zSR+Xz);ZQ?Lg{y~kSq4(5of6G1S!Tw5f7o3)jdu&Du@hxdmR^uxm>pj#C8!VBCjn@ zmdJY3Cl16o3TufZghDHoynuER@Y32XQ*$zjqRj8`+ETQsWe^t-4B+`|24Z6K&PwdM zO@p=qp;k$PG+CU|B~!?i;gnY1 zkW-O}8fhh5nj|h3Jvfoi6opDk_L@u#KL#i3DLDN-6GVP-6(HSlO_D*tsoUbnLn`3a zC3o2&R7#&Qti5u|J7&26$@(H9kl_w}9DBorrst|PuST4uHBniX0#KI~yp(g??v&PqqGsC^1!%oQ%Cb{@6h1MY1 z)>5!FHJ+w@zsMyySsjKGlQFP?ED!jbO}wm&p96LXszWcxh#_#lSH;W%%(jfElB#GfHyL(EQBOO^r)|D5l7U9NRp})4r_4!h^W?9 zlr%^QTUvd|n7&$%@m`Qnp+)vbv1ZhQiLb%wBM%-Oq#~Zc{nA?$i|6@cYFG1pgetCD z-R0n{9m-F7Q>oDYCt|qMV!6L~&FCDSL`f77x8yzQ65n_o$r2*ffI}>3I!DBd9Xiu@zE^u+R zc7cN-GKd>b8u5@O*Aa;s_!QB$C5#FwQ&!S%8u#~4B{$hwX+-mMrs#Dn=;dAg4zt_d z)Kj&!*sWm5tt{;`y)z;;OH<7RjLS1Ak*CZ4MJzFlDGO~xa8gUlsi}!&YEVkf^=2peddx0bz0?E~S<5~i&11A5hoHI|k5gI1Dikt&?rMuG z6>o25s4WfCV8%g@hkK|Qg2sFKcgBpK z3zfi`T%N{FG1f2}mE0yWnmp{$Jwkhs6aC;j%}KZ{xy9`={UpfPn&0iMF)p0}Whyh= ze%vIX@op=fbTr*$fpDNavuY*e{i9gS+Vk@3hUZ#5Kiv`+e| z@!v4J5rhEqdGlnq`=V@XjCOhBJjhYm&iI7gz>FyJjyCBy_H^Rr+av4cr0nQPm>XeU!AjA$>8KZCSBF*jCZf2`b3 z(8iD>1n8}ALd_^6BQO!mI_R>FRjF{~p1|Nj@o_I+w{dQ!qE8wzbTT@b@5itw=NgYo z7b&>UU?~W>^xpMG!?NNeZX>@;HUY10!(p$83JfzbAzpm6XZdE#lZSJW2MeS_c&LXKQEe8R` z5g09xl;YkvNj){_l&wXyO8$l|l%*AvkeVT?{N===@-@S*$CEcm4`Ma$H6~SQ~ z#!&%EOQMseMT*GfoTGdq9B4Q0;mFoZI9<|N`$BnE>_oNJSc7kAH6v0<1HTyI=zZfb zv_?lg-YL;xrnyULlb#WwQZqQy&%Jj|HXR)#vqE3r)or4<(KhKXBFtm3lrHIFoFS6| z^G52=-_mwk`Y_nlSHe}!!X_~grFHUPwtr3R_RO4fL%52B>UTnZ?L zIyk%P{K%a7C+ytN0l#Y7nKd-cA`frygHM0EgJpJ^*b4 zQqw4od%zHi%QQNoP-*p`v=R(J)2zg#-%piLUY}<}xn?8TYoP?-(gchS`B2HTjWy7# z!FLA90;QkNpammZFE|%%uWHJSxYRv%>f4M63gVutN-u`OPvbTcjW1wQsJ#?N^2?={65_hN&v}i zIj&7gVh#(;6In@^76))f2QGZ&nzcMlO1NW>I$lsx!Zx$hqXXuI5CSsqN;k$!o#WxF z+|74Pl2@By-*>q`zqra3O#H<31Y604EjFPunXh<{$ey}XO*fBpD_lB09=~E@@cZ8% zkBVRDURLF)VPmat+E3N`^fB9bGB=={uB0L|qKW=}x!7CY_Ugn}TvWR1i^e^X6Vl6> zI@%t-*Fky0qy1}Xe1SWo-%QviR_`+MP|rqlKbTgB;g>KB)vWD{opIA`rE>o}6VEH7 z3YxIwR~R=$JtvP&*kiv^_LB|+O^6AmE42Su?hSD|WKK!C(;cR3*_z?fEtew2%0e>D zi~kY(kz@sYtnyNan<&DeivYI0cV~_L{K-hkF?gA1gcHkUj5+DGB18m#HblkfepS1R zZ!l3WSYaSd&!f~C@8RSbyFB+ivtzlcoF20K_u3~Cb4D7UG1@oE%jLNDsI+{{wrykv zES-1oV`g%qN_$Al#m?&V-O0w2c)%>j?|f|4H9I#hLzp`0bE)>BYFQIT_t>6BH7a%S?3}Q4!5GF};E|Z8CsN$6Fuc^>z(Xd6&(zUt$XP zuQIzXhG5yC`Bvgbw=xg^TI?@3+e6dD3jD`ps8L@tIl1eaOKT?j@2A^Hq`RoHj4!*G z<+xN=1{j7LCg%LQY<1db&+}@1=zw_`B0?QEdab_cX$2aaCz$R8HR6 zW6BpZ;pWjU9^y^JQo2N`+w_^GE917JDZTsV)t}h7;@cM&?(L7$;H zY~p=u5UmpCJ-}-yi>U4K?`j}0#e|+fb>$cqbgYW-x6`kr&Tm+ox4x)k@1vfuL7>o(r<>aW%w_`<~0!Eg1s zuLqlWbIZo7+s%@-J@+hYZ@>3w(OuUAH!b_x+#fvio$Vic_K*MNdxbAdwjDe4;mWz` zP5-p2yz5ZGefEK?)*jk6Gy0V~mY4qO(?7i83m&buj!2avjy?$){ zmgLjj|6|=duKVcIkKX->?vqc>>w-c0i%ribf7tQ*dmdeO=4XHW_R^2P(Rb++6MuH* zhrf|t^xb9GT~}Ir>DrT5AHQ;Iex^!`9Dj=Jsl3GVv3WU-+K) zCc5#4A5N8iyz=DHp+8t&I-Om6EB_Lk%zpgJnGdWu_PWc~Ui=rg-BkL_QGHL`v29z? zvmrVD-|QiM!^iwrCaTqkx~rXctpCZ~&u+eQ&)3x^kAL_2k3RnJEvJtC_PWpB|FwtC z8ad~4VK3i&KRKg)n^v9jVJ|j0zUyx;?K^+# z(^uI;#hKA>-hON8&~-m~%k&3JC)~~0{PCC>ne>zIVUvR2Hu>;BU;pq|u6_D*?^-rB zF<~zH)>Aw0?moKX8=XHmB*hvcU*Vf zinZNsCojF}o|U(*EUj3-KI8~%c{k6m#gw(F^49=aX9_58U!8kkQ(BgyUaPaGKK7;c zP_~tP&9ji){DOH~eakb-yS+WEuWinen)S2IaY~te_E{~fwLGZC*v~kyd-vE~cg@Z5 zJL9L#?~K(uX2<4;eQ8#fNAK<+1>Ej|`dxR;&fW#gu@rrFU~KkFUz(fixXXNr?BvbX zw}<-HFX3;jE>gF`wbzdEO0%bD{lM90o8;6}$2v2elsX?N9O&pcs{EkotdDJM%{3nz zyVSG~$U1MWyFzBA zxOU&{rcIkS?|GztcDcKLDjOwPH~!PJ>zjg2et%C5n_Tghz-)1Mpg!<=sk{7THenZ8 zy@zeF^?I$NU2KwX(*Q%AoAi<8o9DdHCc1)qKAAS#6lnz63!=O4f=%k!q~2_k2Hkw1 zNd`gIJ7#3Jn}p_RB(%vq|6Kh^Z1U#2&^-5(W!R*SO*&XvuQsU%o76iH;jX&|20}kk zn+$yEOOV}FmwrOtY|nwznR29`%xRkqB~k}1yWao&bDJ^BgS+cYLhC(aV~3vJH~VMH z*vV3V;HMoO*u?%Y$Qm*(;tojL%ygUEgtqmgdi%Bg^*Oakot=1IvTjmdM;g2K2A!zf z^~J_6VRIPlSuZxJF?LB39Tl7GS^xVg)%x{$FKy12?->m^yRYLh_J*pinyCys9`?;X z`6OdkW|LK~W9%}FT_`(@UG*?_8Eis7$!(%z*8-a?9J}i5He!&=;NZdVyF`Eg!MTA_ zM^6Vmhu>j(#ySr@tt2H=FI+M(z}WS3N3zM-rL!{wZHJFtW9COcYR4wD1K1^XreyN2 zeTX@{{4m^=`733=U}?DY)olMFBr-i`pBQ+ifnOybKd)Ic2tMTn-LTPphU`CFHAMOs ziL*aa_baj=GUXc;iN?X-37f94AJOLfD8DGY1L*U$F{84#PksUnaE8B6I%KCy zS&cfgr!z9tk#{i0%p~XA&Q~z6zra{t1@UI!PGmC)mp4}Plxt?v2b0ZsNLvZpTi8)V<$>h~8v z44x_(b4}P2Xu>|n7&*fJ#EhOjde!#{9eeWN6APa=!*4@*RQ5x%KhhOPh_7TX;N{4v z`z8BWwpC^ipQKCP0F6hL5s8=kx4}>L`c>c8m-K89IYGx)W#zxejH~TfBk}q7xase% zZtppPJ(;raBYuyWmiHE`GasFltHO))?9ogPvDa8I+woL-jQ3c8!_&D>72&@?%0G^5U(Q z{Hx@-tY6AmYN}PXBz1)I?S*c(F1wU~Y|LX1(vtr5d-jC8M}2=;w%yc7u2~Gz-CnZBAH^%0>W5+CaskgCW|kyRmCQI_m0*7vF%{c zK_(%a$Pn^Xjk;ZSKy0#Q)8_U2_Qv)0`Xktcxf|4hW>d#{xuFDT>L+F(>ob{6grJT4 zQpkI7znSYW){3S|n>_u5cffsFKM7^mUxks;vG$Y596VSsGXR+Sp88X_GUj>Vd9dxl z2l2{+$8X4uP1F?9VuDScZ=`wonWq7HOO~Hy1lsmsrm->RzS2(yMvXai=pjuJdyGD* zQi&;PG;C43WQ_D?dqc{X4l;RK`^f+^hqra`4TJDUKVhl{t9@p+RBCVE_iRT;;j+R_ ze0ZY8CMNU~l|dZ(5*gFdaC>Kgqb@G$Y%^m#*O2E`O4DQ$zA7_6b}j5DV+@=J4-O1G zQfA)xGM6cC#<^t{ZxhR>VK&dkk7ZT6rWXKG&Q za;HI?A*|ShE#7JqAq{#fwD-?s6q$!$z`lLCO_u+n3`^LgF8ySHuj617H3|b3uy?k9 zeSbe$>Zaqk-E-Pc7TQEpwH|MIOQ?>Nk@b@no6t|p!RP0md;IZFeX5F0ZhGpnr}*eZ zi%n)jKiMrj1THH`zd5@!ynbIHu3vG*BW=X%Y7?btvPsDB|6|v`B-zrBz9h1jiT*=0 zP<}~V(vQ3(vj0Pfl2DJvoUWx>GcB?Ih=^anWMN#BGnpjp6k*z*4gO+oM$$-f-0lv8 zMNkWA+(N{Q#D5lgDgI}nf03faT1|J~7omO$$@T~|A?>i07bc^?sBV{7(rHwl;!sI0-AD=xtz9eFKn9E=~4>b7;rCu0sBK=PY zhSL6>WwtiZf3K8ofhCE*6lmW!ujiaT?;ZS7oTL7e{ePb(kC5B83Qk?^5vW^vp9jE&PHz?CUvLDd%;$LF zP+;=H>4&FKB|sc&d;pZ1@Y<(;WbS*(h$#3CEZ|9DeOndB+!hx)P;gOr23{meBM+3+4* zTZ5*CG|4{Sdf7i>vl>Ymy(&sBT9!*akEB7#ycb4BAF>Hf76^)NdF8BsaD;juB7)Y6 z-E4-8H6ZvnU=mGItOC8u`6Ie^Ur>Pu;nr&Qmd7?l4aY9V9Sl)s6SZBf`bdHA&`FIl?;6oY}tqS{PQ z4~lodXY}zc`hmK#lTUX z<2PCIqJHtsi0wE5baN5^Mx0=pP1HTq>nsJc?DlXYJ(uk)>!#nv*7HMVkf@x!0@jWmATY@C-sJRGHT|@_G>xdQ)mSopl9le}AZXZ5RHJvcCMNT_Us|Xk&M4zTi>@WV{pr2DAI zzDjAC1XjrUa3!tLtQD*BAW|yT)-eJ{%NlrD121dfWevQnftNM# zvIbt(z{?tVSpzR?;AIW`AE1HQX(jS=NRBE=JW6suJO3m#nGk7e@krK1x*IyoX``maqoNT3P6`I_Q=j*lO2 z;GNc`x^-Oqxca-P*3tiNxaz73;U78j;~O*StkB_$+c>|(Ypls3U3At2 z;~KutieGpvWULE zip}{Zg73#A1HTUQ<(2IRDCF8cPDm7fWN5Hjz@w4NH$oC{Eiui5<6E$KWI7Kl^bgb8yqF=+boK!$w=icO z&okHzk^6c2OY_OqB1#qyxcQX%knzG8GJz(vM6EahY!=C+WKClX@eJpmOeulS=ra2V zBTx++OR5v+|8uZSB}VgM%)x4o`FK;vHHAI(sSvNu||iCx{5x%p?}VgeW7I zr%=ffaV=G%Y-OU7dci=MORRBF3)ky9Z~?T>L=!<)zL|oTEK7=?NSpjAJnDHN#i?{VK0mT z2j>7DQcy$Gld|}NyrMny0^W%Pq~Hr(Buh0NdpU{mi8owtESDF2GepV<#uJK7#C6Eb zCBOk6PJF32M4BvdC6c8^u_HV}TFE#|5RgwP36Rt4KN*LT*hJWNP*c3Rnd6`&h?hYU zJ3?XQ$&lbXQzsa=M!JWMCCG=VdzQv2oQ)qID&i$hg)~v8q02~%Si=>&NmCq`FQ8Hg zYmSD|L6KZX|6>wgFtjR?4}fZus|}kCZo8T^FhwY>3~8uOs762}d`dZ$Z?(dT5=kI1?TX&SaiWX_54q7HL?f94 z4oyxHQwg!5=R^q;OR^VgcxR-UR`?caG!ANnB!F)2lr!b`3NJw!gcU!I%u+`K#$IKx z@ej;+)MxzL#!KCN^Um-k4x!^58tk0-a+k$eaMe?cx+d_+Bpd<9<++Hb<-QQ6NJYUZ zPn6IR039!ys+G4v2N2kKA|xV)P+}BOajt(5Vf-M?2l>e5B@ED>G~g3(Y8iAOKzspY z3>$nknZ_xlNxN@_pcBQ(ZUY6C<0R>osGL7jY-l8AQICD>Bqg)Pxv=bAxck)9$lv)y z#>+T54xh@9D3i=KzT4@HaasnSpQTf1f_N_dvP8TPHo%FU66YF-=73bLS~HGMw-ml$ zC52X{zO+@otEEj4)-Qd6g}`Kjn@kGui&nfrSS1d7CB_+Vyi1%ecHBmqr^g6w z!gp`{6ZrPrq-|xvuarB0^pjC9V{+L-G}Fr$^i9GnLO##U$7swFk(4ewq>Kr3GgB8T zF9E=+D~|VB&`~7p4Y|}KiITI#MLiMGLSj`|A%UE_3SNOP)dyAQ@ys{27W7Hs`3S;G zAmlE2DHXr!r4}>@^}HN&BdDY~{6WIE9nwlprcNk~*4}!4QDzfxaXuYfQX=AOC-34#U?UQdsP1@ciDh)l? z)9yIP#g}icm3m~}0FfsP0WLqednvvgQRGEaiX-Sv1yWEHt;kqX6roXx2)#lz_8}0` z`DTYmEbR`U1G_9^mW)KgBlK)em9cGh(wiE8v6&%(h9Vi!oHfq5gisP2kI%p3kI};W zipTeSV%#J?@$n=d8=j=+=rJ~5HD4BA6@;f3RMALTWhC;}L`VGEO$J)N0LX2v$ao~YNgb+^`w$%OMQ>5Ero$7NPI8RP+T-3JaVp;ci_*<93(j$DjHx=~*;O?y%|eWdq7hNbG2zxstrLh+?BRDPAjD3N?hYnMZ2hh2i+Nny-;OfWybFO z8=aH#fXL!F>9+zRy_Wz`Kqp1+8bdXWdNyK^{08y|2sIViL2;gi=h=uS9%mS_)IeE*48Nff5v|u>Hsqn;sMQa5f(DANy8Qnp|C4#WsbtiQJ9)xNTSyJLr2&_gRCH zai*t#Bz4Of0LA{vy5cGuhh`m4UWGdWS8qEuUX{g&AVvW};qs%V3KcjaT1_%kD{e**d}K(Z#C(Hm;@p zZ46l6i#{0+gB)xM@?PkJ{1OU)VNpv4h#6iGc=V`EE%H`!FtBAAC+M-tB~HFPj9^K% z+}q~qDP6KG-As?@&>%BSZQ4Bf!l;f<;L)&eP78mel6ouz zuZZahQ3(~c5-lWaT%xs)-{^*^*-*LcVtSE@s#d5B(gH*3zcq0TRwk9cDUSh`Arw7% z2&3f`OM}CTMz(C70rCDv(kX|#V#e=={ z@OYFFQt}MOXneYpY8wXukkUjrs4$`L+}uli#i&jry(CT3;(L3_NQvw+NQ<&~ewI(% zdl?%nmjX}CqNt!p$Ge%v5j73f&dV6GV9@Y=!8Oe6qseFjw3RF6ZY6WX!$3+f=Z8|d zqrdmQg@Vq`Zp}{5gL&jQ_%Pey80ADUVmYbx;9%Ptyfkt5mt!wa1jacz1`B}VIlyb*Ffgv87aroTD=SS)eNxBkkzLlZq5#xXg>4ySk6Vg{CJ@oj? z=W83%nZQx3m5Ar!2JOWMyt>9zvp^mXzL#ubn?T&H=}$j zOp+*fGCb|G4N?#}aL84;NKHU_>X&j;qd^Nqj0toa&rL))z$y_pfQZ-xo>C~J2}3X< zo};ohYP^!5j|PL-!oJr|kl>7`OvZj%??X-~rGbikAbiXv|uhOGM7;WP5qZhbF6LM_QSP{`B?c;LC6G#iS=m zJLL(|Co(?cd*PrhKLj#YP6I=9CweP@fT(9xAqP z?fm*WpDbO8f~LDAzyIsn(l;?|+GI-Z^BhgJQ|@%0G4$=H@Xg;I_F_+#%Qv5SX1aDw z)YDGeO;4cVzsbbTnRqB!ck!^58%Y{jTuS1IH!}!TS2`gG)fmZ4mnSMFK_>o!hPfN7@ZC-1>+gi6Ir`URrWNnxOf?htc3sW{fpcUyJ-1LX>G)7D z3NMb+ecaJ)X-Q5oHtp@l?m&Q&r!A1PP@VQ(2l<+6z)$MfRip$j zxBT=SgG&onB__5c9#iT|PKaIUex+@4yoEtj;l)qcr?trhVxUkoP6KTpo18ZG*mPs5 zBbn^!iq@5`=J>_pT07y%$N%qDrap7~_URk{;MVG{JJKC@Jo3-aP5=B~J@D%9-r4y_ z-~8Ym-@c{z>6=SOO-=RJs!4HsaV2@Ya^{^$t4*ri)TXF>A-LU7QSXUuQ#*G~nPi(O zd}bO%%wy-I7u(#F?3{{G2guBBdd3I-FnpRPak^v z(1q{6{@2^4O4ErkOO}1+GikcxR`c7d-tlPv6=%MhBL2F&`%`D0b{-+BB=W_Zz4ZpJG*UvEV z8JtOW%!${ZazecEmQNx}3-}rgCT{R^TgyA|zjxcA@1ZmAZ`|f*Di!Z1w|;W(|GM&h zC%%2l37g)3&+bc?pIX2sHaVpa-C^p9=(LL8xo!LOk~=`fBr3x z9P^z!w}1C5pS8_+Zu}NV9OUuA; zdu7TqHpe$jW0QDWbkk?LOTJi~C?p9P%RHTr#|_Kk6y9o z%HKNmo)16Ty=3LqA3pO-kDvYS%TGRb!YwJs`am0)^+_+D@HH5F@Do^*Iz$&^6Cw5U%R?8neaj_V+ z|JQSNq+S2zCTudvIaFeknWLk)xYGD?GFg;c>}pk+Sg0G z^N~)zwJuPf6ZhB?kDnFo7WU09s+V+&+QilC%a+wolN{zs>Nl4pVu^bFM?czIf9|>P z?epQymt6AHQ`cTAHmMIEm>b?K-@_K06bhsD15#cnBda4?3b;Hj#7*#%xnL7=6=lIdni`ay3r2qJ*&(7P#bUa!AseEr$>w)#ve=(cP z&4qqOlX;F0@rOJx>DV;-o|^fRPCP`m1~hC^ufOeWcilxP*A~PB{tzZ{uf@@adrnhUa<|EbnMyF-mW(3d2o+PEm@kzt{?yS z5k8k4bSfo1Stp*=V_&Efu_KRNjP}~kIQ!<{X!F>mHu?4@DY6AJU3JWvMQw6$Zg{wK z_EXu|rS&h9KN)7~YI$JK{FUN^$CvX?EO_zF%Bwjm#3r$xk0O3X2WfY;S&l)@5D9VR z!?`FL7y2IXQVxF1=pWMY1&DY2$*aTeJ4K!gjOiyG zIPOiHk#Z+9-VNXsa$oSJ$#jF{<)y?Bc&W3=@-jEoGhni_UCc_$880H+RaHIHB{5lD zvO0(^CQ^O6{7=KkXF~&-n#DoWo*#Sg zUpV(f&p%n0m<iY!$uF2||>yqx3;T)7i&PS2+NCZZL7hE~lL_*hO z>2jtBQTXcnAowL|Uy|%JS^6~r&(qR2;iu{N!x{Z>&L=OAGe|B+F3upS_8-T?6#eA# zcR4vnq-W)I!~}9*@SKYxcuZnq@~TZFFJ!}pItjhhiS!LueYyJUBAdiDJ*!Jrrx+P7 z7yA6nm%I)c-==3ap@J{`dA|NIK`(K1@6|Kq?cz&aLR{+}g3a!%jPL#H=Pv2#;U(SX zgU`$O6vnQ?-q*Z_@SKp(&Wg8X%Y0T&IcS1`1DjgL)q#3zdK2k_;PVugl^Diq?Qb=- z*cNfmFCbO`sO0R1`hGoR!9+hC<2*S|q3YybE@R8=p+n|Cee~em*sC}!L(bs<_U+rd zH$Tq-A9?|Ppb_A70re#W6bkA|Fa#Q7o6Hquel;-5_=UJ~Z{y^I-LcTVAk;g)G%&y| z4Q|;%NPn&764BvzY>sr#`nAA3I=(V3UxoIn1FU z%`g|r$x)2Jt?7BfVZLaNQq=)t}@Jn%QKazM1;Sc@J_%h1xTdspCQAs&&mmc!kUq1cMA&dQW}cCZ{ex z@Jz4?QtzG@PPr^_UdSfvH;snAE7 zQQDMfFNfB7`M|(}^UF8}Bd0u~Z|mm5I>(}HVNSxlmUr3olQsroQ#0n7df}#1DOVx0 ziS!ehH+EEb&?2owKbh;N9q&7I=)i%|QIg~s9?nLQT%DbTLQ_A<f%bh*vy z$8pw8-cRHNy!I=ErtpBgu{i?F(NAQ0Abj*M^b=%M*~Z3N$CjMa`t_lobf`@pd=RZ5 zPkl~o5@?#otCoI}v-o%V9OEM;%JY=kTw*c5bja&w9+pK|9pRB@$1GMH5FS)OO6Wr42#*mMRQxs zGzVIfrRVz`bN>!fC0{K23!{ir-krqF*R!&07Qa3B<19T^*~}Mm{^SxqCjL1HC=ba4 zU!ufsm#E6&)c<-s2!+U%$AizfyExou75}w7HIKiTKN0e=Z&3qH`xPb5KEytmdo1*C zm<{_IWuGFqv&KHh0{ay=Ncjs1&G)3SYy@yEdn z?e>tK?{m!k=&?le#dqGFl$^4U81qz_(pifSP91_p25p$R=-Y=8G{fKS*6x;<*o+BvBo#T ziw7E2eKEqtv**}cz&x(LZ;8F+2)*hhKtu4CK)VQuQ=FpbINQZ!IU2rMpXe1sfFNb(`= zFp=^s6z0?hxPVo+#aWn@ctb)-D{O5cKP)o65R)wAxR9U`f60W691^futR=V0kpHP3 zb`C?sVx`QdG}PBj)@)xZ5lfp7;4;7A*+wV?@_3%Xtazg)G~&h)pBF&Jx)zw3k1Z-( zYvy_4#Y1*+^uGx!f{NhH!Y|6GxklME+-8KBWijxKMJZ*n2^^ls7?OZ&Nrr~SahbRcL`%TOj(Da;G$@YtSm?6svg>Pt3P9@uj|o=c7}j_Sf!s?9R3oywq7MR=1S${5o*uwO zEH{;MWbUFebxuG4uX1`W*+*F;agjqpl0hmsS4cwXEQpGn86>@vM5k3S9zrlmp*ge~ z4s-^x^D&1kq^m*%M=r?ul~A$|mfHrsVC7dsWf%!}2|Dor9%;*g9> zx^N59NrCgl3p#)`Rs(t3sL2puou-K6G#p%_!9rG20+6C>#k_S!SIM2Dm!_4N-q5bjEjv08 z%;KH06$KWSWOJMDj~Fo(iFmPj?1RXI#HqNAB}D<9ho^(M7dr;Pr|sA*<}!aY*O(>< zR1HGughG6Uk z??Odua(8eI6$J`Jej$*xv%*W|m=G!}^72~(nsXA*^(SFKq6<)h*8Jh-XyUYVxRjzRny zq218;7_-KDBAD@yz{9_6`uWW);&%`;L)5ql!j-63Xo&G=q`|=5W^12`<+UY)hl_{O z#wsyMDkqqnO1ddLkce#Lkj&^e^7wK!nw^9LGv#l^g&q}nyf_R8?5Lq25b0E203?2Xxd*dX^_@sV;U*95;Bi0hQv9*yVoQ@tgZJmSsI>&$` z(<4j87{Uh0&k9B3Mdb6o@%|>OcfRPXu3^##NAP zY@3-HKeh^sT_W7N+W7ta_S*xQ_XuYFZljI%d+fvW71R=go+R1q(s+1<<73$lY%y!- zC)A98;zH;s+9Qc4>_PWxZ6zgu6*0iaLvrAR7bI~q2qc*wJg+Em6s(ExCCO_%^cG`# zsv1>IXCXW{A6zV?CAd(qg}?_QDM28AF7O(oW)iSy9mW$5cYKJQKxFehNR(KQjn=Ue zy~0N&R?08hG6=>KI9|-A^8g}pl$?MQP9BM?Q{3Za1f?<&32PqX)Y=JuS z1D{AX0ioi=_%<&Q0~)#n&k8>Ue265aDlG?VP@7%|0E$nvZcxZLMgu|zUhwQm5(>;0 z*I?isIYmq)iye3q3SgQN%MJ^hnsy3lXUk*7qJ_v3V=h?{fsn7LDxefA%=yniQ>#Qk zhk97PIks=vQ$Mx6P6u8B(18$|MDPuUT&GH%3^W!f&{2#dgpT{-9aVIsBI zy57Vbo7$;zT9Ylp$Tn?RVJ?ig4M9WkgGZ-59^ODrx;T1~DVaHO`?Qsh%dGM-8H{;# zMXG@&Ca7a-GMP@k6D!es%PV%ozRlZ@CwhZ{1XcE^PL+CrBTAd++DOcFnd?;W+z#00 z=o=&<(1^o%V}_$oBW8`0Is+(UdfhO%m*jF)D={QC!HBS(X`mAB(8y%8nS{7MS zkyY3n349|lYJ?=9Ch!>w=_pfBJQcUn@pP_|C*H*ET^Gfj1=Jb@^rDr5kUQs%P9Vw& zi z&TY)-NKT!x){L}ErP~D~d;SH4cLu`00Wl?eVyqX=aXt?rpak`?O68>C)7XPyGHURF zoKa0t!|b_pEOuanUgD@DW0lx^>7>qOkc$#u%px$-@|2;08!)8qe8L<0n(LG$2G8L+ zdTk=nZf93vG8>H;7dsO<(M6h`PuNLUGd5v53@kNru;~ zNn}XG9;yOMcv0ZS;Ti@Iinu}MLP$NZ;^)$8N|vCW;R{=Dr` zXE)e6c>bD*8_tqsII#w#-nr(Bb!(&=RD4hii(J%MwTY~quqLR#{OXe>Bk{?^xS_Ii zLTby9=;_2W<&)WIYig0RZS6>bPK8?aPn3UZh=OElAys8SlqaS@g(o2LN}{9-pvZKM z=oKofU&C;;J8ttpP9xzAq>Uj3ZU&wqYXTlho0tp!U+Ufm%JQSS@2ubN{krEjZ(1|2 zN3GH5FE!18nmHIZ8DSG_XR4cKG}aQkCDcI7!VEUCu}_vm4k99s_o&{RH#4o4A{u!l z92VmiE6jLskYY=A0ts#r1rs0Hf`B2riwyDc$$E1VGOVP-24nSpzPEnA_ow^K9~r!7 zbGu(v-CMVA-Ktwvzdx_;D-CZlQSCgCkB~ZoRgDq!DoW^j(jx0?GD+sxK{u)&uDjV6ETceKQeHuztEFU4mvI)s#ewBc(RyD&JZk9SF{QV z1>V9skTS~GO`bsazOf)tEX%EkwSXEHyht&EZh~lq2Z@7};6k0%Q@tki;^r1A%Ita>T8ODZi?VnKS!`gqpcY|8Dc4_kJ5<0%{VOGJV-&W zq&F!vvcjXq5G$OKIJ(^@?8=|{C@GQ4h^`u{-UxN1AC(b783t<#J;F^YWugde7P1Ob zUnYKUH1ASeG0;EYJ%K&yrbKkzA;nVxLaVV|DadSOl`gnAZ4xNPB(b1#i}qTJC24vA z5@MCZU18Qep7{u}mOb&%_^Mu=j(1PGJ>796=J6!cB~!LwteIcSWxqJFvNDb8yIfx7n=K>x1)j!A8z%TFOR%BZ*F%i?HGT1 z?9CNWV9G^$r)oAy+Ez_25ZzM{(J(RZDS1b#rx>nW1pZB~RZQi)PTt;H1P3}6D)26L zRn+6tN7)9K!zp$RPvT6;Tnl+%zVTF_b2U+{8_ba~Ce>o><NhQnXfOjdQQU$S?V&VlC!s{B&&(DP5JSO+8u_>Ms z`JtFEdy2r>tIo;}1Y?~}H*fdVsYYzpb|~z!c4dQXWr}%%A6mN_(Fi1;nQMI9rJgQ$ zjZ(Cq|M2POmkxaO^zm-D*k34qejy)gzz0Z8) zGxzV@eg7$DOrAIJy|eaZzk2=k9~sZLZ98@E`%j+C$F`kYIq>W*|CUpY8y{II_iV=~ zm;L#jH;n)6^}qF&|KXobUj2=)?%(svFZ;XiI`E1euesvP-^~B)i648*(Vuyl|E1Ue z=ub6&U~1yPm}~9c(Os3Q>b-(6Te<%cd@RTB_B4@i;Kt(Y>E*K3P}8FF$2yiVb_F)M zvW!>GHk*&`ajRE8yWD*CP5up6-ng=I`x{^O#icdV`FNx1ippWqU2J?Mb&Z6v4nGcMs-*1NCdn3<#zkdh zcTdS@G*32RaP@6s4DI9H(;aNq-uTeYzwxC{e&wd)C%T=i!#u&S5u1#m|9ZAI_xlfj ze2TtbMsim_AZvXnL zU-Z?6f3#Wd*~M~H{KFqP_(MN^{oXem{VzM3|M{!st+(!Y-7g;ap{rl>@aO+#{+l13 zdE=iP*zSMnr#^M{TQ1u^)Px*VJ69!F11{4-BZKSW!`oBOO!+vD-k)62_go<#VZ zY{DolZd_SDeI;ubeR$*Uva*T0ZO;@o+1;~Ahc(EGxqXap7h`eba(??^xA@wn9p$64 z$=hCb^)I$&7GHE**<72N`NCIUQs!&eWSi>xUSMLf@zjONkIgoZDu0Z@koYS9s-@(g zRhPw<2IW<@_msV(iLcHtuGpnpFSe(SolUX!$~K;1zv;6q{9jf9Zm`x5Pn=~3nk0!|r?APZ_h+9|~RnvhVF&`+}bm-7vJ~m1C#y=jg z2^)lWnXlbBc;`1Z*v6aol~Z1Q?ws zQY*HG&mEG_1l|bGOsd0x$|m?7Bz!o0*PS*_>C?nl=YIQ-pR#^t#1F(~KkTu%h)>YJ z`ObH=xB5M#>v`fXJG-&*Y_iGhMrD&{zxmDYephmze?Ix3)^+T{Nv2LK-X%xf{|@KL z#M8-_dax~n>E~uOKecw%Hc8|E;HI_9Id8>Y|5oeI5jNqHDHyT|YZn{Z>$U4U-+AN_ z+2q^3wToTv8_zN^By+Z!9}5fTvk4y1Lu=Rn-)yqLO`z8g67`^Z3kn@lK|d%4%nwm< zg&VQPi=yYJ=)U2L?S*^-C71XNH-Mi@c=ub7*T&Xu2i2fmx+_u88BnZd28 zW$3#rog6y7T5{&xUj3~8{M*eRvixk_29@I>o15|WU(d=0By_5TWi1JHx_(LwpuTgT}7m6dqhZCO5e^TYl z-w|Iz9xrP7DJEb3l?#8rd$NkEySV=kh~TxmuUnN0YvhZziuMl5XNty)ERZZ7uVIv}aF~YvuTb7v)qqoIHQF*^T+Q5%iNzcq1atoEy~*C4Gbx;|`7;%8V%)FKu5J+A92 z+@c%mCu(Ot*nBPYNMzMI*XJqU#x;J&688>x6*a#0HCw8XjUOO>>`QLe7OzG8Z@|yu z1O8;c?86UNY3b6}ts?fKjkA=qJ2TceYB{R=xa3!~4TmIp?9PJ+39B~s%iVAT=?(4( z7xIlm2X9z9xa&n6@fY7gN3+SFruvgoBf_4K+K9XtPMUl=d*#HT*+b{E z$>h`N_g0v{mGI5;MBiKKUZ{F*34BZXf9u(#hP{77^W=_${H_EoU0lQ_0N4EY5PkQK zgZ#D!u&Cdi0Q5960xn{cRAP3Qo?8xW?E1B26KTafdG7Blt;K@}@4vu2Sy;&PJMXxG zx+lN5bnr5yjQucEMLPb$!~}Pds()baZ`RQ6GdC0e%J}5dm;Kn}8V52JaNDL%jcgb+?GH4?fmG{4QH2FtKF{4@Z)|C zn>=%F1DhN=RM})L52njSgQoa6OEAT*^6lG<%O6pE%IC2=YgK#&{)k-Ovf`hl{NDMG z^|_2yIm+LR0NzDb{1rX_Vjnj-A8gL4o~c(hZ$2Wq_d9p%Kg#zR?SsjmkqwVtc=4qw zuFgRm{}xn(++=W34u(E1e@5Eqo5K5TrEcN0$@2NqDd8s)-t&KiZsotYiC*=A`bvFL z_gyUq`ioVr#tYx})OQK+aW5wM7b?cL&*Clkll}aK0Y3R79$u#0e5R%_s-yB>tlQRj{l{laXP5G8e@9|}jB#?ZjuL!$3Y~h!McSKL_X_$Du`9QP8|5~wQww5 z8B95Fr3?-0uo}8M^lL$4^i$jDOH_@S)j+@9( zO+pA{tSeI=AXqpU#2Sf~848z&n)H2&{YW|a7HXezOcS;Od7!jf;C!jWnB_w_Yxn%Y zSVB^qur^dd@stMxXJ=e)d`V_su*49O1IROet~n>{ex_XsfiLY>=>- zknlleeZ^8M5mUm#nzl*Gg~_pQPg0LvEH4BG+T>HZPpLdLd|#e@Q|PnEbxq(c+!XZ7 zld)ecx$}y85bKmriGc}VonL3W)!l4A71YxxVFO{mYx=1wI}EUWugUY)e;&c9ZeQna z(XGxH9S`&eeJ99LSNoi8S-JO7)Pb&2m$SP@;JrlzZ9a*I>Y=7|5&li<70WEC39XIQ zfjLw>!A+B%x9^`IYqO8?402vke6>ms*x$tXnqCX7am7P4-^-~|L@71ER&`o*eMmgu zRh}n~Rm1vRn+a^Y2`N`!>kGVvs;d%Y_=SR?Oh$p?NUYT#U`t>?ggGV>&xz#7Ds@u> z_dS!Y2mv35g(5@>cO^jDz#I_6CO|&9?-Xmkwccv!m&Xb(i5R-Iun2pgib=Q^`63hE zMb)8c7>Luv;GNXOhm^ zhr;u<{!97l-oaDwzBVj6AFr~4<815T>si*z;uh(_&$;{*{9)C(V{B8&gBuIHgS^vu zHaRY<|9psO>una~MKxrJo%MtA^pU+Pr#&ZFBi9p0KKt2*d6-z>HIDDYKNV+-Ksgu? zNt`3FYFwf7Ti6QBCqSNe0vs&iifQ{`A>jd&d*ws|Q^$(YDqr^#e2A}9CB6Xg>fTt5 zB{)W1#;A>atef)SBYPV|ehdbb(pytjB9{pVH1s06sSXI%KIQPb`S^cZ@} ziCXJ@T!gyUUS;RxQJCR}Avy%~(K2!{dj#3}_ZXsNs|O`Btsv=t{ zOH_fFt-wBu0&hM@+=SO9Cz9VgV8hHnZ6 zR7}a}WM~E*gA#3Hmkvl}I6&F6{xEcbNELjd>r9K6DoXZRu?nzhmYB=OnG^cW`>y3V zR-PyJ=WL^UN%8sO$H~5nU+bKRW_yPH3{@bFnoIXtHc-P4K5eHZRkhPe|Inz#eyPXJ zUS7oLXG{+yI~O2(*wV)SLK09UfrJ=BqS9BbV~D`#I(#CZ0f3JuTrC8aV`Zb(=>*F) ze@u9u7_1Vu2W#X}9A#8-4bc^*Qb^{bwHJj<^`wQ0YcnOrSac)tf_kg%+Ka_8CgZI5 zyweqxz{UMsAd#)*76KISNd^WwDlyorxiB^r=&swc`Rx*|SsmCan7vY?zWMSZLUZK@ zBvjcc^qD&{9ubw$H@P)3T1CXmlv06JZKsD~5UElnV?q@UBoi^yv=U4@JsAciRAbA= z26U)ZU6!j>?A2`-V$4^{Kj$mn zT&gV3N2%woy&g`}s)Mo}rjd*KUDByvSyl(JE_S2>{r6c^mv$&kTtn{8R7vzgVrlb( zwmA-klUzN*YJ{VJi@K}SNq{t|0@{#Lv7?Tl8ICn0s$@$NX{c&^oG3xlZUb4dACdY3 zMj{o50!BWU0x>aV){t>`l_$ku_V&0~9AiKUY@JYZR8N~epdSRw*P>mM#1XY?jSCzX z?&!v)r+{;wGw+J%ymWHzr=_4T)~(e#Vxw^D;9A%BQ7=Qc-Hm(1S~ciJzlX4n-|2I= zTdPRiKJGl(Feja|{f1Mzg23P@y$7pAfM%eKDrhj5>Do4~Rw34D#G`W$iU?6S=9-qZ zdpSyIO^Fp{+TzH%#h*@<0%%~hb`?x(^=i5sLrU=Q0ntLG20%(A=-nr)OU0^_5_^>z zZ8^GdH!0U(K+)lv*o`u-VFKm<^Ou*n1LD8Qj@3LaH~lg1k-w^@yVl&;`1ntFw?8!R zLBg`97@PrY zH0f}%)EZU+V)+l9X>g5Na{B#V@r;V%DB>{9o62I$_%I}x17rN=o^i2=Xe2myj7xT1 zXUStn)w0-OtmPOeS97$2GrtOU#5&id6yuqX+nwiu%S0r}qQ<%6tk09}bMV-WU+W`JiXDU_&o01eLK>rfFME$*f@8J2}$| zrw=In3;aSJY&^`R*3N-3HG=Xu@sbNNSAj|0D}$n-mtuTUeS0~0jkyxW)f|*rY>jo= z?#S_?JO<%1+H}=2WyRmj{64FK`+V;q2pWu%fGYFBoflYd1x(i(5Y`Q5f|oKi;Vc!?3<@}ZdrNua`!S8Dr~_WFr;i>QaINz;`o>R z?asa3uCWj}T@r)1Mdc{iu7vvm6mVR(gAmWv2g8t_o~Gep2CG$&YV0A&?n3#EFsYLV z(iH@Yv(ymsd_`B}q0*%O>( z4ydD?s_`jVg)!C%#jDf_p;OUPXMv!n7cDMJCo99a>D}XqMy?=QsFjFRLX47vijbNe z1~Mc!MoRsaLHz(k3kL$x`B;^)&?qX}6>rT&)uIHKPOnQ?ta78TdLearQn9ZnE1UAW zi!Goxx|HGtT$5^f574D` z##pf2Q6}X#prw?XLQ2lGuc4n31tCMwRa-LEODZ*q`u zY29`MnYF3io^n^asbbq$jERrsrHtJUuTNZa`3nRme0>$FV8fa{vlin zC4YCZTeq~jz^7U8C|4V9f}K0v&9k}b?6w18w#C!t4u0Z*qgpfXiR1 zhU4a_+NbzLNusK{8OV0dTPWY13d+uKN90Vn)Jp|I`SHVX9*D3Bzk^7-TkZ<8kP5?B zDBvHMqOJnpHE{J0_gm2-0zq-3FR0zOO3f%|K0tY#yaUI8mxWB zWc6vruZ`PpWhDHr)5Y~zfhEKsQ%{q|EAv_Igz^JpTqrCvx+sp$>ss9@_ICTGUcj^p z{3OfqoL`DkV=1@YbA%zZJm_k2k9#n>^#}E{3^&F~|D7)*wMJ92SKQYvTRY+ued1{y zOFMV1{HrQ>dcb&zm3~Ins}*o;6b)A%iI}ZKZ`UkVN#t|DCwPZn=X0woDpGdg>UW}g zHzri{8j>_ZrVwvoVbc8-ky~Zx6x3TzMH7Qfn)Fd!@Vs$MdS>|You)h!Ga^70r1*4) z^GER`?#biZpMAEu{FR*t9_y^!e`S013fLtl zyZh*;KKZw<-}jkUHCG_D_4$_{YHt7IPrmHA zv-8jW?#%DJVaJW~ozpzo_P&q3xcSI^ZqEl^@xTMGxO`XpiW80U5r)FliLzYVUA88r z3!u(1STp3f#%UDczUIB16D~UmYB+wjvBPl5RyzBqIMDw7dv`uC&Y^z!z1`W#PJa2y z6{lC)Mc&3H@Q*iWxXR(8>BwUm^YFBa@o!wnl18qe`cy&(V@ZHPA|vP zF{4H@y#U@$1jj!nSr+0qv z6u63ElepaOb~-D!Kf7|~E1&$t{VScvF6SIb92TSUfA^2S_AjshiC6#bjm>y^&-T`y zd-t5a7N64MioDq^oICliX0P6V{k41U+VSj{n=iZNli73s>BzZn9r>LnI6IT>*ojT9 zcyaf|`9t?@Z(aF{`%b>1wd?fM$Fg#5wVb^2L0(y3S+;h|Ci+mH!5Znz+1eFF*u&bz zMPXaj)^;14h=Fg9HtXcOb30R#$Di&h<*`<>ZI(~1Mz~}H z*#tYNPF*mlpGUYtHp%_;73E4-Hd$@1#PKX=o|sMW51V~2#lG*5z1TM7roEn$&iP)7 zZgQ<_#~v=z7lezVe2HU|e4f^^S|25SY2vjZ8X z$1Xs$AO7LlO?nM*ehu8ToPENea?&7#LkoyyN&U8-I>NUHW`xh)KeF> z$5Z9zgV9IX|ZtmBT854K(WK%Zx)Vj*HGURZwHsW zN>{~3ukpG~CH2oBPde`%^pn*2jrcoOZIP%K1P8hC83hvy+2h=g9If-lCY#fPICNW_ z>iDLcbc-|Wi&dAkc;l?bqmXXTIBXy74c>kaoS77xhl$rzwrAh~!{ znZ*;D*V1tKH#0pyhIkFl@4e{FmC(?{EL%%V0EH)G=!pH&#Pym)RrK5;x8!o7APw=^WID>s)Ly%QMQL zO3jK%bzDsYuAm>PW-4C z?zm(4w`H0EBE8X^)6;+T7PcO(Do{b<+kDPq?VGpRuMzsq0fBq);X^=mPGgo$RsM>^ ziC)KB{Th4urOMZQ=Z$%8d<8WbO4P~~+r+6yA z=GJo3=$2o%ZTw@YO#^M7llM#5(JKk*YwcLB_xg;hM-91K=kc%)gXsb4f9$78S-nZRw~Q28^1?yv zXNP{$QtJx6lj?$X3l#(xLPDxYTs0eyY9IpucaML7>|S3X-byR5KQ?*YA8eoGp@*9V9jI=Qe2Hm4q_38%suLuZ%#o0c zdp;Ah8>ur?Y^#PB?C62Afwb@8{Zx;1o&=ni&fJ%=+D}%gI6(22AQOJN^g7TQB~$i@_Md(go+G`oVHRG$riUX%oT1)ZeN$^6`}h+O^Yz;(fj3 z$V4T7OPzHuD7b_rqoDs@N6_eJxH6le{UMU&!2D zvtz{q8FceLUG>6~xpIYJz39LWo&m1^Pj|8Vhy1`Z+0;N5$nLLT6ghR4n&Hu}*RBjMM-t zT*tY6Ew_-*6`mR+#5a0^e9f)RO?CrYu&LhVkWM=?g5Esx0O?xC#^yiJ9f#x(gE|zP zGnXs2FKPgCLog?L=5~iNP+j4ETzG=UB2Nf4;*OD04U{t9otTc?gyf+``zK*6rCT5g zurDS+3bFgLhg|og3>=0+G0zBW`RVcCjfv*TyM(qzltM@PB4;C^GSf6U?3PW>1rC5% zPGw5ZzJMbEgmOWxYh@wmJ7M8ILP&tT+Q*V3VJ-@Kzig0s?acv#J2vH&s76~0htEi# zwOlBVa5_nz^C~o>`ldS;)MWmMc?rudpS65i<)VvlYsZN%#N3Af5?X;*+1gv<>>AF= zCe$2U3_&BAP7UA&gz1&H`RyRLYMV)wKVu3dosBUMXl@VC;!j;i z$|`6T3nF+n-VkjsUP*{;$gb6PJN}(@P|6@Y7A@HelI={I(NYBpYpX`12dd$Qhe&EL z#@NHGc^w<59w8-2#dB0@Fvwa_%mQ_Ybkc1&6;4xmFgX z@~XOMg+~O+z==KgRLO^N;qkRXaPEre*teNYJ3y-k!zS*Q&R$Q$#Ts$Un;5|in7cLn zftV||Mwi)sQl!OzG@5dw^Az%TF?C`@f*_BQoORmkE_&CTN7H~wd&Z~|JKx`HWyi{u zZPc<<3cSyY0hDB3AkZMXDnSv11Gy?riCLe6(TJ`WApw*lT@KL0cakL8QO%2vrOgUE z+6zg4mLKzz7L)0z1Zh0MD=YdUYJduoItvN8XOl#Ub6G8-XfQF?bSvY>xovSBcB6LQnU8at zPNeE)xr~65jP$N^fpYWI9m|(y$4I;F%@A4kEXO0>f#zu`IqC9v6{lDG?Z-?77s(dv z{+G<6l*~hn2&GKI38Q+ZYHN>}7agB?;IAQudDaj%p#IiL7Ge2^PPvBn({0?3yo@KX zICLe}ZTAE^23?4~^_kvHK{vxEK&TWq zq8{ZVy{h~Hh*jE_sp(j{kIv3OoBk*@p0;Lo#4+Ou7IgQ){X>4>_58vq({(yFTrBPt z!-EmkbZYg!qaXvgW<)Sb0Bv{JnLETlc8=gHK~z6;7JHQjYT*Adpt z%1r&kXWQR}-HQm&W>+>!Zc~NO9Yy(4Nb0*;MP?*Lx|!59(8jNI8`r=!x84d==tFt) zn$=7t+J07byTkxxVEKJ7&$?UM?N+l>21-YD?I(aH@`Z|S-~+y7pjdp zMl8bk2%DrV$EG-J(UfXNH*Ug(>5M_3aO{{zxSHtv=Li6D+S$79 z^iDee=VkuUPDC~3G!)c8_e|Ir$)b@g%>T^C^5jGNR@K~0*BDy3w!Ww0smszwyWU$P z#6Bc@R-{O*PYRT%ASzDHw$Vk9nPv=sTXPVcS|V zhK3C?T5a^116yEbH1$Y>X>!+1t#UDvB|gRKF9UDkxWZ6a)?$hmiRE1;A8Q!sUn3c?q1chV$CCN$2E27kNX0N&|W{khq zOklWS+msnAHpRg1zm;M_CVn9#DyX1cx3t&fI!77lisL4tjN;J6s}mp3I69~*AqvJI37a8U z9xLAB0zI8M|8{CHs{~kcvI9g(qBN_;n_Y(WT6GJiTKql^?{gNs->-ZxuEK|^%KRld z5SOy$_BoabiY7pJ#L9}aCI&?|UZE$*LzQsX8k1r90ui-S#_(X_mO#q(0OoQmD~Mdd zRM#5GxY2Y8E;{b%roJcE><7-+0fpPLIu za)I_Bk~=2@bP7MIA6!O|Cqoq{~y!7Qcdtd0NdGdT)Nv zMAjU2oPWG3LX_d(D$S~wdMU$H)r!#rYR?1sZrxy)Nl|7qGaaH-QyYlAlD!RdBtsCv z#nLkc@HO?C8!X_^WJ6`sGu&K_kt;xV1cajXcGC826(D#%$j<|jL8#)W!Ymyz#w-@M ztu)n|^pH_;3`UaeP0%2*S_`KMQx_OYpg|!@#a5H8XM7K%T?6Ui z5<@r!l5O2eQB@>8ve7&LvvLF>av^n#wTE;!Gk#!m0R&jL+ zJsGD?cXU5>*M3TLy69kwW9Ht>Dw((2{@PZ#FYiWQATmlN_<&ApiXU8Y?R!rCGN&&Z z$%6LnF}igYu6B9))|s|@cg)wQ(k^5$@Iw>iTR&a(gI0iG);jYRSKkh$Iy%<=y1trM zcsV&68DQL~cJ9lzxpB8I<(8{mCE6TTOiyY|3_(_O#$6G9$j@bO_6^T(T(lNC?r?P3 zV}-=FoA~gTMYC*Utu{qJz)zM?&r~ClFR(*dtF+pZs2u1XJ9J@pZGJ6wws#A6w{DL@ zm7SO@j8Rc+E`GuJPb8g{pNTZxq*m^xO$|oqNmt z$4JY~$Q?7aaRSVBi$xM2jmVCUF7Ye1d*ts-R36xN_K| zo2vjpz=84$yIQm?^U%yq#B^T=#znK6mouiS5mJl5)@g((1~oQ^!yJ z#oPYm!yi9&@}b|pXX3Y};_(ksUV^ig8*lvZ&MPMFy7z$(?rfYYIuJ#7cRhPrzIN^B zj&p|L%RZ3({m#m{+uD!gH<`-y=gD>Y3dZ2wcf~K?=Dv7K(cxV?U4rh>wU0MEF;lTO z3#YrXNxQLf#iNX$@w@K5{v#hczHR)Z`}z5{AD?h{pFUl3bKfp+`|@&m+ss;3Cw5JB ze{$t3_ucTXfA5B$e9?DazU#)%;E8$r%JLhRWBakwILV!AH|dLVyjh+o^V267A&)Ju z-2RoBFHP-;r)3kJZHd#|$u@03P0f=eH$S0y5>Gz(rGw!u`z5iPX7P- zot@WXq4u56Kk$){f9|1Ezt!!=sg=u_CrOWAn|;)5^8S;*ywW(8x1l2z-&6b_XTEaa zH`b4@Jo?7pc>HzPLkD>+}5yLnsCxttGH#TeEI zqV88b|0h@9@VU?Y!2fi^cOJTC|ED@T-u=YN%o~^Y-Thd1#hq%%CY=&r%M;BqVw2*z zeC5x+;&*>#$7!>PD_6M#t$em6Pl6S*joS7~vnx}7yP#bVX2-5`V-LG08&5UHMlrss z+QX}T_M9Bo+p{_L9KLYWu*=OJ!k@24@5@+RQ~KbpgT3)Cd}&wXsp+w-?hld91Fg?* z&FJm<98sURt3BHXm(=d1CAl04&blRfWy58u*hK4^Yn~e=VIpzk2Zx81_T7(-vA=tw zIf=I-n`8X}o$WY1ZCoiZDUC+jle^>=X9w~Il0!B*H;^$hIs4poPfkwWbW`K0XGYs( z*Q-p%p@mm|i(S{fmNXi4H8xo~I5swIw(^_gn@vi%hQ`G~cAZZ@yyFv_m`9+k5q7&Y zo9tTBu;d)Tjq7ZDE^%N=()>Ht#tC=LHAB0DtJ)j87(oZ!S=og98cye=|Ie*Id34gw z*xPvbFOIg!!a}mi!Ci~kY!v+L&l*))Y~Z_j5jgbRbsL}l^i4P2amO>yjbeS(#;eQ@ z+GkIX^lb9XGwem@Z|UH3&n25|DxEJHfdMyc6V7qGnr^?z=}noow>nJLPB4 z_cfrr$zNE|esrw~M-Oe5ned@`GSnZV_z#U;cW~@so!HtKZIg4aG8q$hT=s_}*RGA( zLwEz4Zo~4EO}4IGoDDm6%eRJkM`77#w^A?7CL7h-b@1SI)>pl?t5&l`XO6ImD^w$6 zP1zf7defmp4?p~dH_ZNM^V4=_+Qv(Mklr6*6HarpdX_eh&TiG2w;$%yhksyq>R)h6 z__?{|)^_;jH}fu3uND^i{)pdz2d&a`50$TjKW1x48F+_{jf8bD{aU zer)G7_WT|De0#P24#<@}`9HR}8BYF>bqt@Y^+J#TBwVntIJHbfndE2q4rjiUIujDQ z&P_}Jj$dMZj-qY{THKQn->vV;j-a!(O*-oS4M=UR<9FbPXlzMsrpAjyA_ESXSeY4@+<@Z_Hz&ka)h^ip@CFc1%<$uVzj8%+( z;_|!q7SmJjYe^?`oQ-^sprM-TtYi69nr~&QNB)!eF}j~faq$54%Rz9e?t{u-^04UA z$M|k9K1aRQmRhdXcvEpBdEQU{EYm9cxt}xI=)m~D@U?25S3HxGhyTdo!PF~~LO?aKagl>d3}NKCi*dv0O_AFy-P zd5Xxc+Guf4C+X44BXMwvE8Po#$xrLrzOlp#b=#90cCR(E^iA#=TbOUUX~!qd;Tb=Y zX^@!oLNp%iz{VXy~bL>nNLC^*ePjv&qtv-*hj~Cc9iZ6SJ0cu{iz0 z$Ho#@@g=+fN8X1@#!XKqn;hJD%U^K4Idn0()mV{Du=yPuNT*13FE+Zc^=0eY>R!I$ znK+cMTxgzz*B9GV7k7d7yBri7vdKVIOzRQAspR>$-JiKbmC1kbh^*ZN7m* zY@Uog`8@U1kW!oL-GpECrn8n-#p&5s^JH@J!t*5A#65Y-w=QX(NIo|W$>(oVr2}a0 z#W!A^aoD;)_Y*4jfkZDJOL4;Gw>Zqdrz%&Muj68}Dt~#3_xx|ewmD4_1J*gmaOa8Om7A#J%7Za@dw)_#ccUp$8H^?8Yd{){y}P>ypO{V`(vA7|7?Cx1o3a*C~7ME*Sq zH$TQ@^6?1`L__oeJiiCz{1DEcwIwG)vHstZQxOVceJThR6YAD9+Hicl^b$UdsZ*x^q1p|82q!h;?bO6IhsOh;~r)&(uMniDxy^KIA@aMuh zDW%oaVF&}L(u4Rw*2R-dY?lwQH7cw%L>)#{B9#iHkl~38Nb?O}Lo^`UB-=`PzS2-8 zF=JGzA;?=-{L&C%5IL_2dQ5?o?_vGaU~}v{$i$O{9Ju9)vK6d@t!()#T43q*bY!*et9{X#mq@0Sjm6*j{9G!8~XQyZu3g&xp(K+Cv;cOc&r^yT(bJ%QH09yEOv z_8}-~ff5&nVA-n`Q*E{yhphJnJDK71!HNn1G zrBfwSpPof$K@6e`L9D+iL24bnlKR^l1)?K=O-(4H(w@M@eJWJJl|PsCsPTcg7)Xyy z`XF+w>WW?%a14od%32ok$f0w{$tIvjKHkM#x+FCrh}Y=o?k#Dw!sUI0{DkyMNf!SV zc*+`tDwb4g9e~(R7lEz{)>&h7BDY=#Z}Mulp3dZtrwm|@4YZ22?2ZKjUHJ67#ASHA zssrB0Uf+m^UjawJ3JNn7!2kslnHY6tB`#O$%pTnCERp*_zRBA2b|nCB;ie$fEaJXRIfaj+ zP`mMfFrK(<1)p!HrI}wn!mHM+U0h&TEowrWipEabT{W)lK^RghYq%Wa9Gh4*l@@q5 zA)@0H?OpY*i0+sT%Xzh*tt<*Dm$@j#sZbCtlsAw@$MChh>~9 z`F9A-crhJF#r?KGZI7_GuJD$}hSdBRDPS`2DqV?Cy8Tp}xlVqS_7TRU6ga1FVTe|Q ziO-DJ-f-0pcR=?*0NAb}OSxTFa1uvKUNE%x<^vpTO#z!6pd`Do88f=+M8;se3vYSv zJoO*ZVq9|Hp1Z7cCo->QWNZ?0#r9SOeCAtO=~v8o7j6VX!nqJ6BsMjWaqu5Qx#)c=>@^UUJz7(?!6e)ih3ARN0A7802H8w zE)N85KOZG*VM8Y%PX!944GfPdEox67vg#e)A!YYM)sUPo5-FlMG;gJ2q78=Rvh_-( zy#9S+_Wah5b8E&J^S~Tkjv)HfYS>avfdaL%wdnV|S1{^9qN8X9yETlUy6v+Jxu%VppH^H~ z>vp^O@LR4MpkUkikc%hsKO=v{Jnpv)3(y@Qw0+#o6L#Eo@6|t1L~aveWQK`jna^}2 z($Yr0XAUvvNEfkiEO?R0z0`1m39{_Q{H*tsA0uEtARK{u3zOol;^_Wf(3Nmi zS7vJChY4oY*~!h%60Y#t26{zn&U^>$cX7zj(<6eoD_{Xv$w$j;cbDw2vbhj!Nr~73 zS*u$41efVMt)SE}1Q#Lbb0JWDp<)P9k`{2=a*IvuKr`F|r#2#I(M4J_Mlc6cD0-z> zx3#@KXSwCR9oAq?PNK#YRZwujvJQzN95zOlJ&dH^Q&rtE6ITZQh=h|E0kUCaRGfuP zMLdp+iq#*K^KK^3Bhku?i)+pW#(+$Z*bccJ_MVpRH>jlxPehm|6yk!WM~og3oi&(! z6G~w>nNAQp)WX#^|7;{9xV2>}jnl5P0-`lfC7sQpYeON@AV@*LTUZBafCvjll9|m2 zX~LhujS*!cvw>3}qg(ScXQXWhy;tH#X%1>r1YOtE75RY!RVOyf-SB(Lx%?y@>`nYf z;ne=_8NTH|;W%p4x&Fs`H5+56WV-h1nN;;6Gu2q@QK({6v`mpBq#ohLvt}OwP zAh`U-fD4|=k`7$KfV@-g$qUJzfsgBP3|taQD1m%P^oH68vVSIPEKip!p`e|9jkVgY zI2@r(>(mTt_YC|zL_}%( zXM150!$V4Q=iz40xc0L3rs_KuA%}d9A2^OhTTdW)ryV2Bz`v8m*;OdrwCCMOG@jzrGuW%m)!vYDmT8Gvd=l%vF z(JHdOw%lDlbPC6Bi7<=pMalNETrGO{pYu}RP5a$+^d!=}%F^E`YW<$V3S|It-$SN*sVd>yN~CHCedPYu zvQp=SPM&k>#yfO7yNLUbO~*iDmB*`$uFm$l`FpA%)_BBm<<#l~oQb-}+du2N1vg&~ zPZHYoE4Ov<5##}aHI8L~KduChhg;<2R7DZiGP(f7OwtkB;oy{zlah^tc z6s*|X*ppSNuTq~t!J2O1XM-GW8JyALV%<)09Tld5|u7D%s`3w5~;C3p!|9 zjaJekJjR|(ENWJ$KQeMwnGKRevJSCxA0k<%W1qA&CFk!#ri=Wwl^+#k*&~>kaiish z`6p4U9g^FAsHX~wQLZYW1dwU96E*YKUfsgIJUI6S&~-irJq2UJ@wc-_8;&?pe|7HXP-~ijUmo|IUTVjmMN$m5@WhPsoJ5Vkr1g zuu$>2Z9$oaZ3=>sl|2Hi;|2?&E`rtH-#{fU65j1}kGFgmuf-`bClU}`xS2?{G&ShD0+Gs?bqlH{@ytuZ?Wf0$Esx}*~X2sH#v=LC6RDkGPxcQf-GM;XfPi_DiKyz*m*# zjUOvLmP3x146azNQ!h9+(UMiwmbq8bE52oyftdSS#%9wC+U%IQ!g?2+-X!>A{i<@3 ztz$tUa)_i_P$I{O9&t*G#MmVnGJ9~K*JePJlUK3Q2416+|MS6sM78On-n#s!y!^Rd^=yaEAC0ZY|EOw*k~L8k67)Ne>z zwu=jkK+V{TD;cHhilnv!Oc?^xA_^Bo`?sXhHSkazCuPoBm#kUpxZm9ypybZ7LFS;*t56{|^xp~wPM>fnYn%8^Bc2@44q2s#71tU{yZ(YXF!5|8;K#4x+ zS}U+hq9w&QXac6{9ZkSk8^&O513#o)5vwrE6PmD%N5h%nZDLN}#boAow*6HlBXZzNE0BqMv+e0)ICbLDm6cV_96WXRx2Kw&@e}R4i`5m*_C!t7 zi_v59-2HbiKQxuKF5kHR%d#aB-}*J*zFruO>pqoCCXo8oq|No*g#agFmB$M5>x z4}at{4~&2Cfm$!;cK!jnSQ+?-z^ZE7I2fY4F80N$szZ%QZHd|Gl@EPpeC+t1Z|~fB z?v40%{`{TKKmU&o{=;v5WaT@beEFZWKY90!tN0=Es^!G#mF4j+x3IBtqwS=L7hdp3JlRn-RZU=uZ5qK9#F&veu4kJn5Zxo>-sI zQ5&DS`a|1J9Y28|U__5?$TE3%e+(bJQ}?&`Ux_>%=LHPYxFM zrTWHmg<%K165et*CMVfqUHgNQVh8HR($eJ9mODDI_Tky7f)|HNwaL+4uR_?CzPtQO z@^e^NSUPz5mj-PzJIh%>*ko~W zzSp?+qpIbYO}wx>?$9r+RDchm&XDZe^_fNO{=c|QmhhUZgx@v(H`9+QocB?hW`&Z??&0@2h29dfXr5gJt?_S8bE$%_akD*EIat z#C#chMH@$V;Rk$io9sG>kMRXT?~~J6h0TTXbLV4SNbfH-LcSrtMEM5#o-ZJ)R`O%q zt$fe9jKt^2|J;JxeTLgTz6@!p9YrOFujJGFUHH~j=YpNbXyw*buAgsw$TJ_n0Xgm) z6f?TYCEG&I}HBMg^N%8HNDomDleVPCh})|`9ywrSnEC}pFCmak0?Jy zJF`#^H$A!@a?Q{2+S?2K7MEvV&Y70*AKCj3ozqyTo&_HBC1;>qw0@D_B4-`S|8X~u za_CXZwHP_++{apu^x&aUzJZl5;FWKy%Sg{bsLE33Fi_TBOH^&sD+tp~eu}7=ztfpN zqkE^F9a*~f%`U%so7-{tec+X@@`J4U!d_uqvzPCUYB|U?pUrn7SGv+C?|Zq$$)B-I z^{LOB(yT7Wx4_e;sjd3MzZYQiO~I}uJ4rQhkGR(R17pvr2zcl)8T015` z-8>3eX~S!ln_Posg71X4z|-m8E%h?@nHK@6n|Qa>p^`88!RkEkgVrwbjHt6;$ANd% zORL$W+_mfVZ;hLD?{g2NcJZZ#8~QDae=?B!Jtd!ds_J)r^U71T+bB|B;=ea|pVh16 zuWFMgpZdPogd3jPA|q|`-aFIT(fkg8Ivbt~`)&Tnow`nHS$S$&i`&72@47RUBfJ1? z?9w^NgTG}laoYvhUr-iTX>_uEcNwnamji*Gny82Y5 zzQ1eNyMM7>yR2Q*cfo1mu6k>=c9l<6Yp9(qKSIx8t*f=m*2$E!L+=#6FTi=FjHiM7 zWNhMHWW0#}!q+Z-VTQJiu*t#3d2BMe8Ft~%`gyr0%{hztfk52zFRc6)d;Wz3I1+k% zHGe-g$-L{9A7$VFv6dq~EB_x-z5Q}MJ!*YkDt+*0bl3lBl}CC6)NQF_SStU-$8B4S z`88UdKGBPBH3LkUJCWkrKe6Z6_;`)+*Q+zDN?tZvO!b>SO2;E>9{)3)G?T=Xd6%NIbeEb`AJJI8-{2=>y5y*CK z8M)L{mp@+lMarM?Lgj1!N5vj7@?pIGN0C*f75AYy!XO7yY)PTc{1Ib2ywn9S`88UM zKjN{7O#Brg^JQj=hx{73#cL1H_lfZjK7J-d_}7s`?BDy&~h)wp--mV;8ns89s1ChYnWH7L-1PCvAyf>5V8+=67R(Tbbr z)!*-tzPE%wZ}F&{JP<@aec)$(`$&v-c}#?3iqe~R5`q0&z=Zc|&$=NZ)DXqn>!6xy zk4T1iI?AyN#bUyJ!tG<(y&wyc7kY%$0jg8A zr;j1$3-&IYFXsi);}-r}%`lMT2hu~E|FV8gGJ(FT9EO-!QlIq<=iJ;d+r_Yfk^`(h zkHVCh7*ZedUcz2lRLU5S_zb*fko3gq7&IVh%~zt;xG$rF&80vI_B?Awc$bGL)Om@Z zm=_}0``#4yLvmj*#DNk$B}KE0((H~N0ZI#!QAwwMs4;62RL>_?6S>ZV)YI8}C3QJX zkW%|Vii)y1%2HvX0cg1p==hKd>43f0S#Dv2S-lj;T#;$B0Bog%kA?M2*X0HJjdGHw zr8%fv&9bsRdzZhkpBr_vQg3A&&Go zpQHeVtqJWq>Y%@ZCtEWETBeB*SgTOu{^;Phh^GNjSpeZCj zNUUWq@~4t(e56(s0$s4saSQw9sfN49&ud?3AV2K0yl7z-;ykv{cnsYm!MXivT&1@p zL7I4nZJY)f1!?Jxd9ciAp#=y@nD5cnNU<;4uQ{XHaO180+$t&r@?!e5A{9pO3gJL& zdtS7TP^tnvHl!Nw7uk(NEXxRvnUI!S^xCl0a`T4YO6*i2|63t$B|&+q+gH)OzQZ3d zIa6W~xJ&5<2&u=4URD$>Bo9Sxrtv9f%6W#2fp*G|ZO@`~$89Du@H*_J5n7fKq|ZAk zT0`24LPcU3`$}S{Ge^ah75iCz^`M1l=*;{v_`G-}*L{F6@pXifK1N0+7P@h_kI@Co zpvk*~%OWh~GWSy_O_Nmlm&7b!hJyF>5j3@<9fHrzg@|8{FSj!kwAuC2Ak=JDTa66H zroY=uPYU)%g&NHQPMWbeH|?XPQ-HFmy@oPuLKw)cGQB!SY$m(zSS@i?TG803wwzbn zp-L(w39H2qC?*m+vMOO3P(3EJ^5mw*S8|B7%h;h`Bort=@Ye^H-z}h18(#>-n%PSW zzfkgU94cdzHJ+xXUQ>~{tDs}?SxIquyxBE`#{=0sO87{FJi{GDyf5SaaF$HZFk3Nx z?^nbPCB=9H8cyaimyYP8TZ_i9yb4ov*~%G1-5-3;;(UdlLVzRfxSiuyXPdkNI0mQN z`JQ@Ih;u7=NUfM~_ zonQ4?S*=~_g{W!Z7|f|l$|7QN6(a_Mg|0BQ_2n;Xmq9XeacdFjRTBg+J{$|wyT)K? zVeKfv;O+?$oj}5ut%7h_$L|uSu}F%cc#@v8)TqECoNU&JVV-Er4v*Mm3e;6fD1VpC<>;Gv#4He?_DLYP?ZWK$Z$dPNt3>L+l3MQZPGp zP|4@wpyQDR>OGH0FU0MGAUQRZ2Rd%t9SNCcj8DyI#x-T@1ze)V{MM?4UMHzf+_RjN zDBQpHXSYwE!3@Q?d&fHJ1(l4t8kKfMqV`T?w7ppKi_!$1Ko2RG{WjMD;!Ai>a#oJzRMj8j;ozu(e3ljhp0h0O^_}VHZ5Fm zZw|22UDF7$OA!^g#Sl1|CO4irHwJ@MLwrdP2f5l{s)A2VS1h!O!GKPyh;E$8UGvfZ zK-WToZ28!|R;JuL;p`nnqczSAFg6BzC9_y3=BKi-pCYGV?Z?Z5QS`G24P z`MUSM`_8$SGt~IdBteE?G#;Ny4$WlBsiR;IzQ+l&uv<+}ng)(3*%%K}4f8-xd{J9< zGNKti0!iMrY{}gdAot@$+0HPAGpb(nBdQWY2t*}|WyTzCI_#8!W+MTTM8_3Sp&_?i z`%?v(l0LL{;-g5~1EjjN=v`vkCNX2~{WvO{si5i^o+{x)w;{JWKMU@BfeC`EiMcu_ zQVs||G4-t^wTW_29CihZ5MtrU-4|=pS2;N$Ib7n9&$*3Q(RY@0(BNq(7!G4DMJfE) zWwHUg--W~xJ0E~Q9Wyk-NfD{i4p;#WB6hqZhvRJu!RbuFcyd92{v8hyfQ9QQIg!90 z?*kX$@U?J?LWEBk@{%EWjUvmD-Xw>Wl_pS`W0pE3D30!q;7b~G92x4KSRZf@Eb=Ta zdJcyMm-Fl#0dh+ma~y|dGlbSQ$Wg8|4G6P<5Bw7a%;e5sA8PIvET{zbpeaaZp|mZa z32Qo1O2J7&hbV(?b0%NI$0CSeI>K>fIc89{K*-igZ#08C1#|dlsZRB=eI6Z54V?VT zhXSY!_%U z8^(IWt-uF?O*Q5>!c!&gI+VRys~;|V;^wk6nyL} zA?}nB$_>Q1vg{l}k@>1Zji?A#D>zVzx~iKZpotORz$i@Hn99;`>RnnkbB`IR&pQOjh4J-EJ)BEbOms4iWIJnqM8rV44d5thRc;$2+=l4)WP86 z197(B?~RO=IvWW3@i$h_o81sV78@>UE4PM z(@qDkXoU!kf`*oFzj7jN#JPa)&OU=Zq)l&u?GkxP-hqdZY!2R&pIYR&wNaLxrl06H zfG0W=0J3iw+IzZ-2t2W zIY+I$k#=$Q>~&sHlK75jl<}!{k+z!6DO{cxau1+g8=gJ-$+VW^suz-f2EH?%P=i1v9SG#rQz+P{ewdHG z;r8A(lsqabbw+mZ9q)YwwoQ(;`Mnln;Dwcy@n`*~9`Y8O{(Pe?exY~edmee@(v=g9 z;|KFU^#>b=QNH;7B>KeXX$Q8O0{aAmqv#X(6FtU(q1HaR()7D9P7xCMXfq&aY|yBW z;q@Z(cWWo}dZa zXm*8GbLA8JD)S~YE7V1Oc`=L*gd$%g% z#q+sNoFHq5i(`hFTtKW|B(-FReS#&_+J=8meeyK=jCW9lf8ZM`oIReV84%c zu*WsK>fbK!dy;*OU$e6Rk$$-kvbKK_Cegp_i{yUE=!auDgUi*Z1G*0KUPi-rQR1|~ z_c1DyllO!K)F1af zf)qXap`7vH8IHFVWvW4$I&*{s>V!PrwbGdI(>mK(%D6McjIyN;h*kQeCHooaA=D9c zmhVB?@!gZcPv8966So||dmiEJW@<|v^7QbVyS*0nKb|BFHrwC|mdkyUugtRdMZehZ z_!_MXtp{Otb_kcco6cEL9y*Hm6mJe&@kRSuzB#V~r||}0lGsZ$j10#)c~9gyeNcaR znET}8`JJ4L|Agrlp#J)f6?oNNTtqHr*n?Rs7hBS5bo718U-m!4B1)Kxjo8iNJ;I~$ zbXQSX8Xdzm!pO+j)7-lquE9hu%C(p(W_b7m`(*2VZ{Iw6#a0)%o7N-xzIFp|Ib-?T1o`WByIar$&s zx5U{e+Rmfsk=V30v^r0!Lu}9tBXFB}viKtB$*KN%qTfGW{-dE!j%~1=cF-sCKF3OpU(`H7 zQRhETc0JBM*=nA!F~dCJj`T`|ln`d|yp7l=$_eQ-X~udS798GYUwunH5al-o;{nWZdT{`xtRE>cL&xj{KdTPPwaWU+FuUd&)9l>*U@zFJ&eNLBOyg6+JWQ-}k-^`a`3JjV(HLdqHOLoDNvwk< zL_37=`wp}@P~oXal_QLhBo#t6mBAkot8{_8c{6WZVWs>+8u=|C156dB=F+R9+BtHD zPN)W`oO7h9L{^#%*{CcdWLYWaitz^wpsAom63Y)#*o#|RC;-u6SLF=get>g+j4&fy z)yh{1!SUjc3KL(+YapXcIO;70&QAp3?yCP1IKI@5@`1c+JRsbhv5ASRYI497fI~rn zOCy&JT`qwT-X?BK%k8mpq(t2s$474XS{%rrQ-rLv##q?9WHout8WTE0`GwTrM+bWI z_*9r=DS){;{OdvF@H0*nytv$NV^-89bJZ;KxB=C8INw1pMPqG6Z#-k*5*t6@ zwP0*2+O(`f({tcY;^bIxqy%dMfL(C_w){er;#cCJu;(ozhu-E;71+&H`nf!|i<#?} z#M+BA3cbmURSwdD7P8d}h)td`vskkW{bC@+3Q<-8?+d~O%mteSaT1)Q0r73^CUBMC z!i|y~OzaatYyvX4DCNz~UUAqYhcL(4CGXt;Q4B;8Az4Rt74QODL4t}a99{P2pc9R~ z8uX_zo+=;CouU2&x#~a)bRfCI0!)tt09>?<=;Nh}yw_$dMY#8Plhi+D86A9rrz{1Y zX588Uqyj0{aYKe5=8f}-%aSRdnyHGy_NXsZ(%rbK!g0HyoOvsewp++Cbgea3f{T$^ zRKvI!&;cx0h&Zd}AsjPJ@OT{}TT0-E*OPE$L=!pgQDPW2JR~#%z^UaDdw@6Q@;}N{ zm$Xfp)XTfn?!eH_UEVis_VoI^DMGclx)C(Du}@zx2N1P7!R zps@h|4h6Y{8f)yhRZJB)Q3DIToq>az7gb_}3?H;x1du3+OaYHDQ^8PJhI_JB`No2l zmnI!ie>#>L7%1SQK^hJ@Afq0k%(-G!tuP$uM{GTGI>uay^3@k;hfe{nz&1mQh@+Lm zaxNC$#jqo|xQ|S$jNqNrJNH>iW3)LY0+vvsF%mM6qrzsl2W})W(h@+~URa|qb&@5Y z#)1PbRy8HNWfL>#^9FH`LhHa*2L~4w%m{2B)fG|_(4mDnELE==wX|j5%Q1VCDnu+@R8-Hj>tPf zoLWIFb^>s`H&J>H7Jl;aVBo+@M{{e$kDx)aRg>YY?{IUAEYH|G;xYF?b-#q5pkkf@ ze^H?Kqe6w$!vgM3SdU|nkduDZ@Knd(4NhB_MWj5IYEDlhoLI8+qJY>{Gjnqe9B`wC z%Gv7hkfly&{MN*=+L{Y`>)845F>dNa@viJw(FKE`si2zpfLqBUMPnBR9)9=(9w`W9 zeyA&OoxD{MQO)BMPbiMhI8Z=vgeW+GORLoiOQ6u%2(4zyMd9dr>^~pFVtjjzR zl@ngF(3IZt0E+S^9N6B<*cAo5w-Ka(Pc>(15nligGp>i?;h0V=`AE?1&N3&xhNuZv zFCSq|Z3(Amk;B_1)$j2RymJ7GiNQ#&&Nyj&YJSdon5IuGW9V8{ER`b`ob#S3D*&*F zVLHcaDuAoj8mf~y+o2TT9E(YDeD}ESq*XkIWNWNRl1LcC7Fs)l4rU#|rEV@5EFe$g z5f}I~Xc~u{A3}rigRe8T7sCCpDj-jhQs~sG7;10iK&1Jb4EGE%OmOegav>DpXoV|WA8;3WVvl${Jq2}c+!HkC zKr?397{@AL+(}g^#Mo32KC~8;)C>QKH8iBeZcri;3@!u!^biqV0bedu_y@Y9TLFV4U(r|V(GHQify(+)5x7f zw($^1s_?LJ+<2-1xU{+@k8v15n|N>%woUphez#x6pS(Gy*~#qwEu*HJt)QDX9bUzm zWnPv>z_$Q%goL%G;3F&v8Z|=UUKGltpN^6dG_uN~(;(?L2z0>?NbCPL=LwbpRzTuL zEn@kJ_C_|GdoE1jJdOI2x7F5z-zDl(JX^t<%qo9Dv%+X7(0Bu9wSf|$kWk;_6N?Y( z+h;Ja#yG6H@v-5>2+O+FcsDmQ*MNep%0Va!u<6jRf)DwiVWp2nsV$mxpRBi~N`>i8 zkr)H=zQ}n{D!mK`6ic~FrVnK{FxGLBv(T3Vf=88$SVbROoZ0*e8I)RyBhkT0QU+ry z#P7-72}E!3wam67jfqxi>%@V;zoWZ6>XRS@T4z1Tl6E4V9Km^yX9FS05{PaJ{eFI+ zk?s8#eX>%t4HgSw)rdR%5vFm;#N08dfKwc*in&C3Zn_7)HQrm~5H2GlAa=(*9+yCf zzS1tArw{;>^8*KfMY@LU31j{xaEnhYr$B;ZgrWM-2_Q6ar;J4NV1Vw#$zTFh5Er>> zgC7OLfTDtv3~ByWU`h#VX9@hU4i!6)>U`b}o5cx!7fiAvTG6N$atAv>=L~?@5j1zQ zf~O~Wz0pG+!ATkt7?DmK1~?Iq6#f$ukb!fakV2mUYLGxYJ{6$+MZi4#$mmhqIZ0b&=D0n^3NmBLRGq3*lfk` zSI+{&Ge^S8JV(3^zD^EMQGVq=9T08D5K|uy`_;aPPPg+Qas-Zlx%0w0ur7eU!KqA1 zxzCaMu^-S7xP-12Py3yK_tZMsGgHV~SqD#7AVZ^`TUD622g_D4g)u!B6DD9;-OixwaaBxietd zgk|`9G!L{&8>qB2P%ACB^8`Bv}%;MZY*Q5S={ z==1<3J`cj%%h11~*C2 zIxY04gHXXU^TWZf8P0pQ1(z%v5qRv)bZARl;dt>#?VSJygoj>ocBOg48=rXY(((J6 zUBrPtAsbH-NYe~{hlcOdJ%Kt;P-5r{=ur{%(j0h(&rocT4~+Ew>XL(h5a&s(exV=j zf}r5HB`!ACo>6Thc-#;drCh?tZD+d?B57x1Pn}aqH}LZ77A3p%sUw;Szsn78lg+_lpA zQp2}zLHy99^3H(eQ}czD&YxnQEDqn-!@k5~o}f>B7h>!o<$gu%a}<3i*-=@C|4UNnOYh|GzfaC=T02Y( zE-m&qhW(Dv55K=iOz7|IF?3zDDllY;oV?Gnwl1Czu^U*o((KdJ;F52ZZ=>5ibz-`jv9oyN7EJ+2^=j z{!YjJi<5ZYqWELG*Zgi}f2aD#P`K>cfbXb2RKg>Su?G@gxFpAWLybrAeAKtZynq1s zgG5^T)w)#L;_~pmMeJ`(5xdF{U<>CI_FTr8Sq?fl`dL6BP1(>NhT>{9dS*wfi(hQ3(0(s!!1K2hB}RoAFfbv@m2UEgOLJE}o6C zROr44WE3y?8yg#Y`i2)4FgB~8`z|l}WWBAc8g;y`$6afEkBq3RZ%bYD-?mlhSJdPK3Ajc6THiL2RqaHgD+|B%Y6Fjqep-2 zTlM|B#^}4lf9Usix&f@OPc}}UL7!|oUdz(Yh4JCD=Ly^N$)SmI_T?vxx-E(DYpP(kti2XXV;R9xqc@4bqB|R9LHBS5>N7{uTeVN^Pe7 z-SUF}@Ljgw+d%0#dWu!4RtH^B)x$P~0Cj%k?l6xf$kv^NC2G0cyddSfO&xKylggQq z5}LoVMQ}uv8(HzYe2_p`mshFLYpaxc7~~Y5Up#^%PzADhU>zt+^n68i0QG3P(##FW zw`Wv4xQdHqGKtLgJK22Rd#YI`;S{21F@nl4D-jnusRhap!2`1z%+Loy>#T`nAn^m7 z7sIeMqkkkFyU8AeP5!$f%Kv;ohYTab^)O`y-^1e0@TYrQAfXk z|5}u*Hp1Ld;(}I;o3s~Ri3y2Bn?IJRT&r0U0%4GBmJZpQ+<8yI=5iu#wMab(^G>p@EaDlQ@{Tm}OfzlFo2PmnEuj)svFb*>?+G9VD*e z$iuPtPHcs%XvtwUlTg>Ks@!MZA8_XS6n02jH>oYNtOl;%F7PoHoDoPhLrW@xRItP% zTQ(N70SZEK(g2J~#B5d92`lI-uGeiTiTyY%7O+Ws*h0u7pn%muUl9n3m2)8qERzA` zcE(DnM@Rvj#-K!)IV8j#o!TIZ(+Z@6ROFHr@;+ob(&yBQN=5DjTaCcx!c3kURwK)#CSQ}&4!IdNktc9Z-6 zx9dZdvMLUuwu{Ktd7l;9A`}+{(S@s&RPz>o!%;o`79G#=(H5@gR6pT(qME@euN!M% z%g(Lw2Z^$8>#~9`N9DQX_)1I`y(If&gZHX&a!4oTJoaEZDV`rpCy*ERcn=UuishH~S|0qUe)Kzjv9U*g zr4|!)#7ESHKSJg7sdD_DcC(YRn#d4q8ghAWP?C&WjfH%v(e|nyLlE-LCFXojkmh-slQtga1TQHbqUXRjX07X%nSaeQ1?VsL zX)pYO-|ISIf6hy0=DSC%H{L&^{Grcw-2x?_>$<}sXEt#f3+*Fkqz9}4~_Eb&0 zInigdxzbkLdW5A`Q4d%0Dws$ARLJen7awByb-yS;#;>oC1zI4o5> z3KB+Dq8cSf%1z=}DfxJX?i-^wJjn`D8kC znJ1s|J0g-QCSOIRUslE+a@BkB-r zutkNP!374tePrNMhYtkDfO3xd(EyLx!#ZDBx%9AesdwymYT^4>Vx|g$0nZ%Ogek zYmg|w20Gw*d>nRsmz75=m=?;V;A+H1~10enK345TcMG687ej1?-g!iHx; z;;CsoF)Czcm~%GGvA#1vhHn!BT7ne62nJrL1N;D5A%`!%w~KBp-V>DTX@)No(o)#6 zgCNaYXY)M^@KrK%hT$ZU2A73%7K4r|jtOIKd1|2ixaA|makypP2NOIz9s&!Wh>ES~ zVW8SDT&0yU{ARG0W$rq2%?A(WCrpP<<;WposIvxAivNrKs*s!l6J(hzmSa-0&PppJK*qksCzvL- zFn}nu0x*Y93BE+Dn3wv)bp+1EL4em%h2pXpQa*4Z*Mg4yT?Q99q0TUJhMEEz2Wgps zp3K~IJP@CvIF7n9gelMpMQ(*oxnl=lP1?5Jq{u;evVchLt+)CXhRmz7rqr3{V}TrJ zD8YL#Ig(WItV4!F>N|2jMl>=yNWF}g%YKe39=72WfvHU~AY?_ZT=2CHxg5Df$$BVd zD)(3rY3Y3pUeOA0??sXVBXoj;oHJIyquMxqq|>Uo65B{hRsyOhX>tf<7$cOl@ zR$|jNGb6KsrNE!3K;}p0fh72RqK5>q#&flR9Mgz_UN&5PF8gc{>w;={%4QJLZ*ZO% zi&yG_b8hfKY&TJhZQ>m;>!9I`v<%kri_AG6%qRpn{0V5m=to=)fRT5Qq=`ky_}3#V zIMiyHeW8Y#ahLe9Rk<*V7cE8Gc-zC6@Fs-kw&WdE>8A6z?&`p@ z<0pM9_B&KMc%=fe1Ao|qCf-KkgDvuY2&|ArsSaTJfTd+cgySUz-I3@`XU*c`#~aUw z-cl7u2C8^01ZK$KWs=JHWi`IezP zEn9OQk@(Jt%<7JasG@z!f&nNPU?pN8`kqVP(_|1yItQMY00QEXhtpaY74)Dnp3}^? z5Kpp9DcqTf>!dD1d8UpD9Cet%0^sEzO_b(v(=iP^hb_gQhbQxjG~*R3`6L0^-J0Ww zVu?|;3g}IN`S8AaxyhCU4dg3bxbm5W&)o2uGTw!-D2bs2|Cb4AcxatB`52_3U3DME zf>C+f0s)%3)pQRpE9~xZ{g~TDMf$_Sa{$YnF`|~P48MtzNRjW6I=~uov*;YNqLS<8 zRe0_)IQg2V0KWLl2fmsO;F(0g79Q_SDz{r;FAwA!HhXblvXF%q$-G1#E#OMWrZZER zBNAlpja@U;Ur%{ifAtsDme)u;LU!0i1vp}!3C)YBLvdz71Rm`~snsyT@ztu0h?q>` z0|$JVpw3XxUEv|h>6TeXWAg>zyYXhARyw6S8dJ_GE!LyPYpB2ZEt8=#jkTuf=EpJW zhTs%K&>`~%(MoG#C|Gd8NU{-Rj2K;{y$yVm$_SSU3&AK&TRbw#G=ps;ij$!Xd}w&Y zeG8_|KC>^QP!cIf1_Z;wzyQ~K&*Br01Tc&pQjKx66=#<>9%1oLOb2H@w0#%o?w=k@ z_u*LK5rwA-c#<1SDi)=9OnpFNE+mdg84(16PU=vGPw{;av81hAtc&h(j4>Z&b4vx0 zS&M#vu_&MwNASIZ*H# z*7?Oh;z(OG9elE+xHE;0R`4+=f^Za)Y!%=7@Xjl{CW^Sng8Gzl;KI+3IC#YYIL)8H zz`)oEA*`}gpY7pxS+q#uIJo!5(nAJqbe2!r9ULps&hMQXU-b>T-uJ5wGm_y@18arg zqt6u%LR&!mUUM-9A&SD&-g%ulH`NCkyYaS(`VMkfKR+5gFw|yWWBpwG%hk#LxV@dd3`c5zs zlR_hci%4W*oJJOJwUJ^N$kRl8i!`(Ji0c@3JL)1#s49ZgkusV36wk9#08gR27N6&}3M?ZiqhO`@_u2R^?ZD`@Dz>55D* z|0+a^lZ~VWqlQpcg%B&AAUsXBwd(8%xq_%FnrvCyFcTL^zKWRx>nuw@daEd6%E}R} zg)&J8t9$VS0uJ49=7;dZK<3elU32BQ@Ax*<{}7i$XsjXe2O4Tf zky|8ahj4E9@KAsUpM>N&#;(9VoR$%LKErW+4_IwacL3zL@a;6SePO18)L2;`sd1Vm z7C7cIz~hfS2x-%dG$*G`>z6QU_!=}s-!sO&0hRq#T(C6#M1I5V=HLTnPbYY48-87w z$}cv5cBF#`(M}&w*yM(?KD$r~q4*ry1)ROL~HM8@8ro9lj7|+Fu>6y>5bzeypbjMzw6K5 zxAdCD-+ti!>!vy*iw7Pw&65UNPj>!IbI-|pFS_^SD)bt`zvnA!JW5DD@W}5zvbQmE z&wVGmD@o(T(D+L4Bii%LL~6_LZ^B1rw*9F*N+)!!zo4?JRi z_KANn`oU}L@-Lf_Js-iaSa}Dzpi2F$h5;Ttmu<$Lgej6eiESonpbDPhNm-Sy{Arg z{E2(mAN(*L4{?HbHT~(E4lW)>IYN)6X_uF{t0~{Bn|9l4rt3|EErdStLs|B!mDKD_ ze&i?ac-Jrf(z}20U;2aZomlf9ANt_4&E@a(UY>mTM1J#a{`$**_l4%c2Y&Pw#>`+U z;wjRPnf6k1a`Mxke)!=HbL!NorSM$n**D@j%#*x%aZXqq!h`JbjP{wuF?{P7dm2xK zK2tT|bMA#+nw`Dl;oBY?y>aQr>Z7N}Mn+Hup1c0^&`{Mb;=?mDi=U!Gv=sXU zPy9w(j&0v3-`tp;HKR*2N5>9fq%{{7>hIjav#K>d^vT0_Ja*fePcMCXV`J%52-=Jt zIwXBEJgo6Ve$0mt9YXtj5q)ygTZ9+-WM=02Z-7QywDufYyh{WwbB4ee&4G($TkW+<5fp#?r=Zx7~L1{k+Cf2yK8q zIrTK>$*EJ?Cptc6hj!K{N546`G`lgnbm-{whm1LT^w_b1K9P8rPMtm-`ULZ&?33pY z9m4w+M>n2)a`Qepd*~3_=ZnuDJ^J~-khnvi96I#l-vJHZS3hv*=v7iis8}`IieJ?+ zXV1!W{mrqaPU+8oXXu+RMW47u9uX!d&79fYnah%m(TDHYxN+&WjZ@MmYa6FFZaZ`4 z=v%WS&J%t1zj^G;r%sLSlRnX7m-dO3c>;giz|o=6CA?l>_R!+<;n-Dw9{}G6K^N?k zaO}c7DV;t)GQvK=QSX~*he0?yGjkNjuIHQ0d-2;9AoR)b*^53el)3C*%^bbzw8#dN zN=bvl$m#EsPkn=ZqU{iMw#l`ezImd30!v)b;)_|jaYp)NY4#2|b{(C)W8=2b(W7s5 zt(x~NP#Km2;d;!1W-bskaa{;l2#*1bxvJoY+wS;pH5Z!C!jAoyK`uFHv5S1E@e*)3%zun0B3bgr}%~HIwZ|`Rmr%pXq z#)h_drg$%ql!!ZJ@_wL_54(L7X&Y!=>6`vgCS*ljc+R^#mJ{^nk-vuaZ9aaTUIfB&8M=76#n-WhWEm-hrk{_QiS2RSa+Rv+LUn@~RN+wVkE zSM0?O-vZ;ic`{b%F#I0jyLsN;?afRh2W?)NWe*v1)z=j#Pi>-Y>odJ~;(9;D&A21X z>4<=L6Ulpm;`@T$ZoIS|?D*0cz7y$+>}{F8#|MUGT{O17a?*F2-fJvQ7>MmP(}*d& z9|+@5{n953zssy&`TAYvn!C(%Wj<`KLE9d|MPU&i^$E8vy?evsWgL@u`-2(HE>SMi zW9Od#oUh?{QrZk+8#it&J^u%%AKF-Y^4EZ$GLN15=c3g&-}^0RjlPEne2HV|i+b$G zY38Wvw%&HbkG<_z`t5{{zGEJhA|3O<-|nRT`d=A-dgz-x&noCu!0hbo#sa3QF*n{g zdIsmA)3H5@tAthFGPNzrPoJJW&ExouH{v?g?p8;Pg`$WzzTlV|xM!ip-e_rDsJ}bw3hB@-Ww|@EE zWxN$Ewt38>DAF+x{MpT$CR&+)^6n?mCq+x6wXVIEZ8p21@97!rlhb;h+ufZo6KPWK z6P#b~VBbJT<0#6hBWw6w17&_s=83^PF}UX7JURXF>_g_$Quc;ndv4h$qf7d3sHija zMQsy&ZCTXVFTFS0*k9CJ zHQkA>@s53hS%rDR`4Q&{>@|+kWx%vYtvM!r^1YZR2J^(+HhTx>$>}@FKH1o&Pr~(K z=(n*kJ$97yBs=_>-~Y*fGEgBhVw=Z2Dn&Zxfxlg!{Nyh`Id=AJIet!`4%elpH=if* zdRl(=>E>CzPvSf&`y{mpB;kdH=JH!C&b{e%j{LZ<@j;RE!b9{bdj&VAvZ#Dz!6AfRsjfD-8=ZO*f7bG+$D$Nh;7Tc->D zV_WdQQSj%*5B%ly|0l}NzR?su+HhVjDX^cB^2UD*<$t)#@^SIhb-8Drxn;?_ZW<)^ zH69_YH+INS{mNcJM{Yk|?lXiw3N+lO*h9Xyz5QYFmpNqE+ZXfA?b44&KGxMAk9f49 zhbmwNvPWI2EWxi)PX4%EhPaJ=iDY1(;WU-gUO@|=`w<}?;B#Lh`IUW&)7In8ApEgY z;=aeYA9Cn)o8=kqf0X>Qny3E(zQI2ij6fK5VqVc_iwjUs+Fwbt9&!_~Xp21K|3V=L zxed_wIkc>p|2uUeaVWZJYB%L>#*7hDR+dg|#FIAw)>!g_og*HBJR6DFBqd#7Hm*1- zI1wo)I3u`T*u=^xhoWl83yG}?gex2;>>_0W#IRpyx=`f(rP3s=QrSSnTCB!VbXgKu1+##C3z>z))wC za{a8(IA|OA8fc+@ZPE@uAa2HgF}$L5ZDzC^Ig)~-6c|AoOGs7&W)r9SQBve;;R_EU zNa}HWGP&2`r2+m78d~0O;nDT;g~7w7<-OlJ;72B@g|D;aE^$ArM#I2{AFc!=#lFR@ z2#s%wbRDLBNhicBHK~X=fE=VI@Zw0baBqvz!+RbJ|0|g+c;v>H_i>ZkIXZ#vR9G3!gFc zu5*SzMA9A>p!kPXFdztvn3WF790wS?$r~{BkUPqd>-Y#o)5HlY$0{0kFKzfCcu5yY zi)Zp3KF~v|`M4rNvk;a*y-am3``civ9!lS0aLztF<&m1Qrn!Hvc;8Dn9(51;RqD4z5t(MD7vJh6JC(ohj;I@_E4pw3o6PG!hk;b5G zU^my1mB zfW=H|DTEXf*?qYUw8wI`)MGSEgE5D4(|K+C)Ogr)gx0_sC|a=O5JjXRI2IGMJh0Tk z&7;Z0f<=d{I%}Zq@s-4(&JHUb;cj`JnzX8dlz;(_HL$ncj^&Rznrss!eP?G>f9@@fRkTr7lsjAer3t7o2K@j2Guyf1hL zzBRtpHc`otknSX#YYC3fCpZOwwG!{AcHD((gI?c=rBWLfv4M2 zX)bJBFQoXIosvP6?ZJj}C$VD50zvV93hA(Mn7X{YAgua`W%HS*5g?zklA9ULiZr)a zSVk&#K_?Wb2ZNp{&f_?sfrfCwJwgdalxGfUQ{ABc;ZUX_?)pi{tY}b=Q2GF2S+hF$ zKt?@pd|-Le#TbPT4l78g3kMY+fk^?uTQ50g$4u11GJlk8wGMtr3+iytf}PJ`QJw1{ zvUJ)sQ*Vu(c+{2+1RbYi7&8li6DrQ5SrRoG&Vq{=9aC*aD&bUP5{r}DI&jlihurZF zOqeIuD5MAid^X~NgaM&)o+&RDq-h=Q2$eN^5#IP+2#+@z^TQ{n5mf*_Az`v0J6MR7;D}nsjS^y+Vy5I+KAZ5$1pq!h?Ryn4t2ENhAWZMgM3Lul zjg)8B)2mcFpGI9|I2v;knBrqq)sr>N&JT4ORM~5a8b6wuWRu5>s zhRuceTW>SVBgXz*dizlRD7s_qhhJqT)yrOFN2HBhy3VWLw4Lrw@3jtme?nUjDBO6- z3}O~=T`l}(R3Ys_4zd9W&bq3Ak*&q24%ZG&f4mnPA5S=}JRk>m%_SD7f?geBgoJCc zP$sWzFub7Se1c;*zUoY_nF$;de>PlqK^99_Pt{ZQ_zbuvmqL0d`+c+(&Zj zeCsm8@Cc^-B9Ou%8%i7}J)bqucxZBbilQ-4eL)MRG^*q>%&~mLq5c^qsoCW)aI@5b z=wiE(MZ+|3)ri9YSs2kdjup7D;&m9NN$RF84lkW2a194%aA31(v^h>;W8=EJYRbgo zy7|6*h>z}oA_1GDTbWOLY}pE+nS3hIb5P+B&}J|}VLf$>)fr>S(JG)?-h0plFR3Ix9!x-?$s1Ea zB=a3D0AaX*>`|M^YejA4(bgLr7%W>oO`O?fMK3t$nJ5ghk_wI*q9TMj%O zM5!T;^%oWiS(fHz9@Tk$R_wClhO-)^^U}@cCustMLX4U%(*XeosYKk%FOHH_}oL3jI8mh~d##Nq;l;-dNNO7ep zC+|FS?1{2BR12w7%((&~!^`;cJTyuru>|g~qXy+$!6pS1s{D?}F#~Y?3_DUT4KyyV zvSn#WFr<#mD}eI#PkFqC$`}854^ul_feweqw?l?2Zj4>bT+r#l-t8IJG43;wbY6hiYx|Yd3=udaP7U;{mhqo z*l@O{0dQ*^rU}lQiI=Bb;Ou5$qF-S6R5XKsbP*GHk~Bj@q8ud*zSHxo3?Xtt-i0E8 z%3UI!3BY@%96bRd>LX+8oGKDct8izo_(1SU;ih0c*}m43RYhDGj^hATVa1RNmIKz; zxP@#GSzpDtxwmajiXZR2Wzc9TFIh0~RuEl&!WOXyvUy$y+@CcU8vpu?$HA=WQok@} z_;ty?&YaArc>lP0D=bq#T||84NOL&jMncY{)a=XiD~B?3pUF_Bj$r24A(K&zU4}Ef zOisHHvr^H|xK?o&lvbgs>?ovz0Fl*J+N1qE)aT(2IpN|lRGJ=;oC{#OCG>EBjwRt* zllKlKTsp?_rk8&W8P4$mwCv)#%abihNavq3)4O){%o;ACIOaXBgeh-$Yle@H>^JiZ zGx!q0uS59uaFccBro_B4$09s=B;{9n4o4zDu1YOjO%5sM3Vm9^yTQW~kyVHXWR8~Av zpFu(d;3W+?*<@($kvDy79yj2`lW2~79$YGwEa8`lg;Y;=B~LLgnQcmIv%X~bH0$E- z>!nd9`YNat=xOME4B)qVlUe4hH5v9|zkzxu>_leP+dg&FdGj0WcsFkOU{C27-S!f1av$~%?%H+Y1op%=6YP<@^opyme(wiPychN8 zpwn@MB6>PchOl?;qfa%>J-s1(dGZu3rx-*FE>z59j7DpPBeC|I7dONdDA#{=g-B?z+L``#(C( z0uhJ#$Rk(pJ$}!Ld+x?Q#WsFQ`^fM8ACKI3V&uKJmO!7RXhYFUhPoJQ=#!xb(I<`G z-Cayx9Rr>V zKX~~stfWKJOK*C|&CQ=5ns_4@c%SrUq#(Ts`=v(V4twuvaIMfwqsP!Eg?UZmB_bLx zk)OiNy}z+lpOpI?3gt}@G#4uTG(PMTj#l=`>C+pg>=W*J==^wSmcyivB-LiRMqmXiS)Z8M4LLS#oQi!?9=itnqzvoO z!XY_!UG#a`cZ=qJ8TJ`&V2jMA`=mT}m3^|=v1`t>E~Dqx;y(OTlFi?0#(N<5nMK*pn9X(ffzF?y3iTGS zv|e-UBNU$OTLho`3Jq@6MtPCHiu$*k@!x_RUqcVflP>klIw{yQ-xvKydCVi9IsF9v z7!Ukjz8rM2XhXkMi2E0-JjIJxhb9-KuB;>KF8dKBCXKx{g!|)&U-v!6m|}S-IJNQ< zt@?xg2W^%=^Ex~B4~~qqZhoD;em5TnZDP*C58%fqQ{Ug%3VZGTnel%N4cwz?eU|y{ z_%d+>`x@_Zt3L}8G2%N4AnxJg-a%`O3;PsZ+)D^O*}n+CA#cBic5m--zoKc~8Te5T z{^WK6^qHf4wF92h4j_5tvwYUQV#jjWhW{63)4Di3+S0y&mg7B3)@1;SGVr9B6fy3j zAM8i`8J2~L^WiYG3%TbS6bw?06~_4PrF%1J7wNY<|I?Y-leT8^>0$gpbeHj09tnFz zLq5)&eB8jr{>D|wzdq@BOmVU!2k%PqX5rXmGri@IXDP48b;IcFh#7pg!_YTJ=Ird>>RKge-sycl^AwO-=EV%-`<}AT{x}rRKH-Q zkIpPEaj(>lL9RJBmQKUuH2!e%7BI7?nERZ6-3fj%fNT~yuE=I*pC4P$GTz4L2VBqn z|Fe_LU2i(%H#T1VYMxurC#SdXlRdw&<36diJx+ddKEsZ%^QbGMoE?>|`$hYV{?h{8 z3fZPlHu_H!eSNa)@k5JCVPtJpM4eyu$p-rbRpgb}2Kt10F0-k_1Ox{q&Axi$JIUW_ zpNyTB9lh^fdWSdHUr)QqqmO^<5cJq5cPyb#Hqvs+SYoTKEVTHq{Rw9eSPw#Zyh>X{XS6WZHW|p zvaxX*e_`0gK51czZ!76eV9I=_^?SUoH5)&*^y=BKPhPVAt*^uB+vu3b+G7ioM<4x5 z_Q@H1WBK`|dmbK{-8axDcs5C`Pu}p2!MW5IYUqnoHM@B1y5`5u_t>>$Fs>{8ICM#0 zd4uG(eZpf`WytjP$t{05bM$=PclEM|#Ci*I}f=S&{EfO4J; z2L6M}dEIaRpho^bYTS4s&z}EL>sG0koP8>E6)mnO10uQ(8o?;aZPlp6qqyXVq3@$B zWJI?LDm9mHf87bjE<#wCOZRHQ{yGsb`V=r^GNYpeJdz+sG%n&<++*(Zy(p8 zY8mmYP>LM2NzKT!bxz&aOGnw7tDTg&6CEARJJYNMP!ff4MCy^s_p4I7j`>J#-H%b@ zJaX5VI1labL)Fb^gnXIZVYKR@*pIlCmB+Wqe%W*V45gvx3dt(5s$~^dtv=4`C9>wO z@bG`+B&(c4 zGAvl27mp9tO%g4DRE1OV009=wLb@Qz^+{T6yscRmUd>|g*^0R_KlF_tu9s2T>;$WX zTB&!xrD#=E>k6SNLBUg~>y9(cR68-OJtW)=gvAcAO}*UV!%y|qcC%1~KUt*CjuU_> zJZMvSa_|ZOILhRvGWc8~m}C|LeyZ^*&TgYK#7hO{l0;3cXCntUqp20-AibwU$Y*M%8NW zK=|+>J^<3@ivw&Aj>CsJ6UQ8|D3$Oi&dA4Hh2Jq>G&r%;lw}aJj=9&8MXt%1$0{C) zMWVIFW5`qFnUvs_3x>ykDgrBQ?gTe;5G2c}2b$EI!@^9pGO7?#TjU8aEWVS@=IUk% zBuGOuBYi4eMeI~APKUh?CqRlyEY>A#`?9!C10 z&X7g5D7~&^1F1QVL{6}LG4Nf;k-^qV=&@kL>V=Q#IA?)b#E_>rblYiA3ZfiZ0~~ZF zN?;!fxJhuVwICAZv@{>XX=W_2r66(O-;QyD0A5jYd}R~*fFs_aA-*~ z4$Kp-lLuIQG%_I__9Xzpxi`NK5}?a3!zJRRwP(EOQd$CMB^g-N<)}+s6mqXQ=xK)p zfSyAN$3l_D9t;E(NE>aZl`-860<2BFKF$+*=m%S8NM&5$#j=W0u=`K?6$08NyvSe- zQ4!rh27*xy;ahM7sRmCqBkzJbVu9K4HbJ~jY+CB(SaUeWD1$s_S2!x}0JJ|u(Pb_~ z=s@!W0LQ5g(~7o8tBKeac2$WZaV}F@xkS{cnJm&kfo7v`R6LXrBs=WNnWPo} z{m};H7#JFxfRF_#4NFW~f=~0nb*(C6+Gy8Wp$#(2zPF^M&zX}TSV@t1d@MTHiXLr1 zQD01=9azd`W|;t{H4CXlp65NK#EzT@rK6NANrDU$ER#QuGtZYTw zD(;!FRVwPrVoI=*Lc9jdTI$75jB-*`G_km(MrCAybPfTU&#pmnT8|NvedSavFQ6A% z;6e*rXn_kYaG?b*w7`WHxX=O@THrzpTxfv{EpVX)F0{af7P!y?7h2#4xCNRH!Q`YQ7K3y?VqDbMdfAB69Fk-Y!HKp^Ojk{Ub@T z-)fGBF-S~OrkApBc8tNQe&dg+2m8<_tRv+ywhCYLvIkU-a`n9@@)H*8%Ac~3qg(`~ ziyDB)J3Txye+>z}^()BZR_?*Bwe2!!zNPjcuj0EvFZjsn_Cj^9sQ z*AXq>#X@Q`@PXNNhXqp~$&v8>5q%E|ej)-NjU{E`20C*K{o;Knf28kA@kZ_0h8Fq~ zlZRe-9}4+*f^7~4``y}>#$1#C8Ct~mt}&ET-%5@|f!@vuSt-Sk?FSzi!OeQVe2`Xu z!K+jG{gp!M7Pz@x1y>LSHrg(Dn<0hXX2MN)(3dicf(r!7Rt;RpNx8nzsa~1@^UwiL z?%vygBdC@>W3$?N{7ArihNx?X0&_RnQ zwo1qMcR6}7B=c)^V3Xz7mDs)VIK$uJ0!=AXshnSa~Sfyv6 zlgmRp<@^tc$ShQ4qcax$5f{kKzBOojofX2ek|NR55+$^MrG{RbQq3|^NPR$(koRSK zPwG$0wi;=lP9%LqYPr_1>K?JBu?Z{#&1wd07KVs4J}nTKg4Nhz)F?QL(1#Qi7vKuP z#Fh$*ZIKoummv`n2@J1E!J~bhtc$@iSgu(>Wm;Ha#MQ&Qu@V@h9FVMffHHIxB|(7*~GEMM|kCTInRxSjzzM-mR1Z30DQqD+EB ziO!J&F>?~mqdcmoe8v_KXi~-;VK7Q6C1%dGuoyNTy4eUKrlvy@AZ4EPAf+ANXu>%+ zZQPv0dr!z26A8Cux}ZZYltrI7Kr|;!7en94to6{IHy$E<@bop7oncYmeCmAb0A35> za*q-q&7i{_{1BOBP6$VBJcG%Ca(LVuLTb2WJQ*}i<=GTC)u%X)(RP6Yi+Tc?hXOq& zCm0_P8FnsADz=%|VE5vDB0)P^oD*D-QoU7_W%2A_a59+V@tIWVFu@wo&@K>o<5(Ub zHEs%-#iBFo1Ys%~7Ge5%K3*M<$5dv*J2?nE9yHY!8F18EVS6dTyC)fb2Xisfc^MSqq{S%M{#-U00ahK zfMiNd00-qs;4L^7C@pUvMIPKSEEonj^2FQFQOo}&Z-knXoJjR#8e{Ww=oRK9uMB((4BE1 z_Dvqqq6I9wVzHG;OMuma%ul&}$k+hGh9fKU6_0Q;;rgx<)}SQyK?H!zxQ?Ua0Mr(V zw6QW5kU2r|PNH=Z4(AB0w)e72!>JJ8jU8m*4T6LWb{0f32UOS9v^^+Gj%R{uBR*vF z!~-1o;V29Y7bP(tU_?R8y&#$b4bl1F*CEPOG$e6I6N|)!4>Ez+X6z6T4jvKWkU4xs zch+QPZOBQxw#-b+Oi3HFmoVHbKnoPs>Co^W=u`?{}J~-@Rb$UooC(qu3q1Mh}M%( zHw_KAq_nXhj3XnkoiRg~WVz|EOd<#ZVo%b-O9=7q$7|1E!)CIf-s^{22!aLEv`rG* zf-!N^P6El|#A6aH197~W9zz_*nal>8PsX#!WIvyzZ6Ka;613l6)xGbJq;9$!&u5Qx z>(8lEr%u(Ws$2KII=4I}3OvW-q#=Y1iR6f4q=YF7{K91s%b(QLqVW| z6jzSaIhsWxa<>A8%wa02PY40HZV9nt4*~@*7j&akzy?>2CcfG-0msGnhw{K7_v}mq zVQeza$J`aFC!uI<8;t53{^#8JT_LB+AiNfAMEJFM;+8v_HKZWxOiYiwLviq%nGO|> zNyEqo&Rb)aCQSm8jt+n;BtWh|ED!{()Az9*y!gvpmWYt+%AI178Wn$2{DLrT05Qpc zbxj)r!Ks_+CQ8&hNpg741wOS4xC>U)1Y&!jdh7d56OtzC_9Td!Hc7)cQ4}5lLd$wy z_4tTdPF*hUD|||SO1#PFsG?OcxX%Y&z{?XyHv*sfT0ryJ>XNg`|FRf8ktPuKI8s;v zoe*VMAwAp^1*p}sPt^RWc{(Bvv3iiWp9*9mWxOs*A(Jdp>>=9(W6jw)nMjOtMn^CU zO1EIsXf0G|5(l%Phpb1M#sygEl^dTru1B*^6E(;9L zTDos|*7VJcf6WiGkk=CUKz)xJS%k}iPpz>mHI^yeo$eCXSV5qSvS1LHz%Ah&^a2GZ zE4k@Qr-Kz)W_D@g5>&Gn1LcrIkJ}Arpel&=AnS_Ss#6-s<4fSgbJw_ zg%}RcH)c1Z)C={j58a^ptQo3gwOAD2=2oEKOZE*xc)q_(`DL>AWvKAaq&ZU|OTpWu zYY2^qHiBShC@qAhF4yV>rN__WB~Q@;>i1D$9xWC1gvxSDKizJ|(lIJH#M*$o*>!o1 zWqf@qUoplxKWH41Yu1WT=8H9nlT*C27d7J-my8)B-oa8yqbru{CBNEJq9opUuKcDJ zLrJ&*Jl8UnB6B5Mq0qeP@@YeSPZql(M}E`-;h3;dikNeq>pdvg%2OZ<8C8xC_)6nl zhOTMMwZu;i>fAn6Z;vdo{uCM>%}aig5lKTo*M!juaS1_+50MN%hC&pF55k9<(f8t< zo@U`#vk>DnCp42ghxoCfh`%?pX56QJi0Fs{&IK<76KC;VndWFJ zYfXJ5n^LmC>f{e(%$)ws@DQs2)@OA~%$iV@G0IDQVB6+Rw`qe@Xj3RDG>PJAqF~NF zrcF5TZ9V2|zDXTvCjnF4b)pK$=jgcwhuo#`EMQW; zl;VkU$y*EI?OpK$l z#JV+<$BX)&#HLveb!^gyN$E}Op)4X)#(1A~C;9G35%#sT1>TQw*U-(DJSkTwLwIi$ z%RP*E=?A74s@+kv3V1nA&V~Scl;39yLXn4?%m&OuehNM-@(j_oqvy?fn33A3o&foJ zq0n?$uBi{3hSB8J+t+$C9Y0pAUl_DhN<-I|^hIDv@pd-~Zzq!wwMr(sE$nGviYPtzRnR+}FnR`TFLyc%gfGBN3u(?I+g-i>B zG=8LvDU8ri)i~(hn5W|_#xCDui9pDI0fYA}4p)=rrs1?U%mmiQ4JxGmzl)16{_O=< zf3rcWB9*UjHlEU!y^8a#zPoA%_9gr0A8LT``}f~{>$8iG&YXW2XIcc#57cU(s^&9S z-`!eX7<+o*u^aFCnt#K8`>UVZx8;{w&8BH=+Onm}ILZE(Cpe4a;9aMy6hLhs14iX= zeoE^A#aA1#n#7k5EP8ID3>XnW-v8Jur!BrbyZrq94RFfCwITR|cj?jOps@P9>C;W2EN}X}%7BCcv9w?^7Qp$Ubh7_}#pWgRjr$HZPD_{5oWsflNma#*zCsQH zN%JEM@0&lIWs7e=@3hhCK)rhFz4zXH&Eb{n?mhYs3x9R+*Z2aMyWqMlkHSLrOtz-^*RC6znYsIb%a@*CqS1@6i-eY9$qw@eN*6*yALca_-fWLp#dcCng8l*cQ3yD z<73ay@*|#C9%XzD@JcUrlGdMCG}SDrsee=lsDSuHy(^ezbz}(VogA2FGaI^Do=*l3 z@+C^k^x}gk=%gGcjf!$5&GQCo)!L?P=jB^!+pk38|jGtWHuVCS>0woH!nWkT_t*wNd}YVuI! zrIM)h58rHNSD%@le(6_NpE>&O)kh`{ng?Ur%((o@bY4PuC^HvlN(ES

PF>I^V&K->dbmX_}KQT_Y`~ zbz??H%RGhOQ+}D&(Mhj-q#r{k0|TdhX1z}MqVwU|pPhd4rJpdD9et!nC%aVEbJLaE zV7Z|TN*{b7o+F{KU}9F^>g|Sl+8sNU@a&FwM$6VW>_sQAU(?1D6Q`z=^|HizTAprr z{Th>7dj1-HQ!nkt?NRDvt$gH-ZBoh|{nfpDXJ_B@_j~vD@`m`xs&q2_(od{D!?_+m zYaS`b$=+R}eeSmBj;oVhyW)8(C11Xo-Sh2e7HzLvC#yTc87=0sU)akyr#;HL6@^Yr z+=h(Dfi?6U%Ggw0@qplwa&P)@eF`%H@0-XNsV~fU!$Ka3@y}Jxr=9km~B%tbcdYpwCfCzv$UKT z`kYuRe=VFnQs!?L82bM-XAgrxj+kD?@r&`X<%844tmsu<2iN9tj6j*U+h-vYc&3>( z^@~-e_|XEiO}Oyty59(28J*6*G#T4$_f2j3cy0=GYRilniVtapMaOpHf;t#8)p|Y~ z`kDOUDKnnccbZZBVbWC304%F+AfWmcI*IsOjrsDP%l5UATexL4J|Si38<1CjQ-7Zp|&upEb6LGeykvL*bo|eLnDE)pNV3Klo+N zN74GdUA|Wv0MX}s70E@j$M>U(TjI!F@Hze8>P!?Bt#eTDjtRFEJWCmg2YUP+W4C4p zO8>^z!rRAm4hre;O>Z<_orqmh@thTvvolY37v=5#VAiI8x9CM@ql|;9Sec)41E0F% zVUju%$$9?3_tKe2127eY@A|Agd1(N6vi+90q{feP=jzN%?a6>G;$0LWxa05@M>wX7 zLney3j!*wTc=I!t9eHr#k=50{+8wLA`r7$Rnzc+$D1PP*dk2wp;MqSoA@bKj)HmLL zMA@&nLgzr}ge#r#)N}4xG0_jcAiCQoCU(i6oz{A5c6PI2 zbu_@Ka$$b1ymZ-R%1>VM^93g9WUoSNAhsX(^u5Q|$?6rW999qt7Kd4m+9-7LZs}xo zb=NC_bEGKhvZkyPik^4>-Y1{jdvx{X@179(>mYh%{IY*g_KDRW|8d;|XJ>U5TF-e5 zMLkNLT)a#4dw=Y0^uO8LcuCK_Jxw|~;mDc|biyeQ?^ZtPG5XQ{$iSw7!Q+gR%1gDl zQKisPcV2~em@CZMadPv6mpwCa^F+|e9joKtuW@o!ZE&!5>807GwK9Ca<9*|1MLe&# zLg(qIy^cRl%JVa#KRc_P5zR^ObPC|W(XhZ{oahV=t#LZzL?ck;tQ{whF-`{edL{Kj zp@YgxdylV^*()Z3*pWVrlR_t9?pj?P|2~bA;rG{`9Nc^9rI);|SJ3Z&?3M9xbO9XE zI1wCwoXpN%thEBo@HS*)oJc9GvpPD_I9acgnj=%f0zX+?4z|w?oi~5adTh6r?m0=quP~ZOw1pF=dA>`fgxVnJ(j*~26ORy@Yp`3x9ufM zTfyqLwI59K8S|5SdHJdE1Bx9F$Px0?T=4HKWJG51N=<>kueKY4w!I>Dj8`gN+ElXG zi1{BV>P}qwRR<%#ukW!;;SLXbn3T z{PT_V1i<66eEW3Vck^_#{WA;XBSU&uVGHh~*aTv~D75St zqYr*J@$|nR+wZ0?Z3Qb|K3_X9um$9R@2|F;XwrM+9uLmXB_no-lGQg{AtSycTbf6i z(nmXZag!aR#V>6tOBv+P!4ZD#I*2~hZGn9MKH4jqg|bc8`se4jAcq%!(SJp`PXty} zjbnhc=-X*=BWFfDb7cVEc7;zU7^Z~{n(J7MoS6!IC3h*i3m7>irZ-q7 zr%^nsczi1zc`5GX1YxMSp4dvTF_4MQt~NS8 zvqCk;CgQFVTeOG7`ZB6?U4_fNB}950jkgo4*ybYNk|xdwuKK+)_?rIrrR|PgN>@E2 z(fVe#J-N$R%;bsrJ?8LoixOD z=*{Niu=KsyQ;oe=4_H%7>W*Dd$tv_jZxOTHh^D@LMpwq78?a&#IJ4sATR8;;9-|@R zu?z^!548oO3w{wa{n#R0dSPW{SyQ!lT!j=bp5*f-UF~nm&};fhpm4{clQe}yUNqh~ zd2L``9VKG9JeTZ}7My3VmqfB<*7)8Eg7AC2=t{2SSEa@R2TPW+UtsW2H+vv0X89}x znO`z2;t;x^6T<|nhmaa}4NbGt)L@jQd}MMa3Hy&#V11e&jg3q6yFfj0hS$S-nIm4= z46ltyW75)&T7F#TMYWj1TwYL9_-!(d5NHr0fP-Vh-TAy-ZSIH*F%q0(##fn*CZX6=#hy(AOUL-sISR&>rQ5Sxl&&;Qc*QN?c5T{PgB!{_UctAvU zYk30dEMMAC$wMwo#a zBoL(tB#B4v08TEBM`qr*BZR;q%TlIZ<`phrXwZc8=1ih_AY~JfOHza3^jw|#Ao zeGIRQMS(t!=M8dkC0^Yr@Vz>6M;#OtfhQl6?xsY&vn`qjZ2`FCi+T)*5KoLxGu28L z+jc@jD;y9Z05bTAEz$DB=C(XGkm632;j(45V%|_L?JyEMW2k;+bbr@24IAV=sL42fqxmM30GmlGW zMfC`6{mFKvh#eQGNoF z35APf&T3LiJ9ezW*7zp5xUHw+WH2OfLz)&?&@-1{?&6t(VB;I{r=dA!1^yB;1+~eK zRrAbRA)F;ii`{Ob)4e}aIts7LKEpz@*+Z6TuqPuX=YF3#5OJ9IO=Y@YBA%HugY1|U z2LL7#$>GJ>z!QSQn1!XnGth8FnfhF1JSk=k@>}vTNHtmsw_)I0?cgZ|LN8_YV(1gt zRE`8DPVUt{eHZfFLomwUS$`-wt~y+(RFK%I;R@MfT|-)SdPZxj>ZVVPUXnmft;$Xk ztLzqp*~7(TW)%k5;bQ36^aStd?m7FY>I;@NAj$`9gQm-0tc~Umo6(dwj7MQ$IrwbZ zEc3N8FIYC_Q0jAQ?4l=Em3?jMSgHLS9m+O6Hl&`m80~Wl#5DqQ#t!1zMD$!+mcci3 zGwQ=i(_~J%@D_(FVgDPU0Nax?bTU5Ky$)B9jJV4+4Hc>=X2p?7j-aPFbmcwwe(J8u z8!ARhlj;ZI$+sXRX21($p0Nf4HL$a48OBM|Pc3q5UR*HFSDLB6i+a`aQCKfn7*b<; zHsIt4)KnS1*22sTmd{U6|HSku(cLNLP^eqCOv{=yo2xr|jmLNjtmm5H(*54-X*%z` z9fb#d&KVmx*ZrvIGPgO;d;;zL6vjlDqI}%U;Re`dgJ-EDkW6J>zGNFQ4R8TXaaywR zi8x0>fT5qU;ZdfHAIA@~DDyWADBVGc300VML!;0-D@AULpV33)8{>+yO>(WF8)kFM z4lLo$nY%EM9$6PK=G7j3vT!V&&9D{k^}JSrbTIr$9%a%v}MlMX|6b7cY3*kFc;&W zt>1hTVNM7#<6V%ROl}ady-RJ(&zQ;3kf(opQn@^p$_j1;bY8iHAm&yaciiO9i_hu>^;h0<|!$Q%}9f>7^{*g z{P$&{Gl@sG4P25DDxv6)tWrtm?yk)uAJ82o-+ZSzn@*DrCs{tEY)qgn=*THnl)=S> z)y=KMFF{>`LcWa1|D!amPK9)`GN|ukQ+F@P*2CTOCla;=5#5a11_&Lm6ob|_86WzQ zuvMHAuN^D-ba59hcx*wOGQISb#O!L!2d)`%Dj{WYmb-0tvGLjE&S&s+5 zqT#laB=DtNQV+99K=ME&KkU0u;FlnCtnT`uCrWM9@V>q|pYC6tWR#+W`!|~g%sf&{ zu|c_|oY*HX!MP}^T@4s%D{kNkj~I|&hO&A~!IBMrkgMba-C3^Ks2g&fnBzrOWegNu zHN=Gr3h)%DjztrxoU&}gc*;#hL&bBc8O@vp33xfi`{*mm(&y|v>$j8HWJW=bXCry%=<#$3P$To*=ABqo%(g}}7wv0^?5Y3*5;075X`j`Yb=aTf6r-@~`)W*}j1zz`cndl`pzB3qfLLo6 zBP;_lZ*1S5LLV;RGdDwBu?s6pXAl@mEP^ZiG<89{G(UzwBXzUnld-u`$}+<%n^E@5 z73s*shpM@agzX{;!E6CO z-mgWs<4j2b3@#TeJ6Av%7clJ%MZiMF5UAsY5RuX+*ac{lITrAx>lysSVm!_L90^lQ z(gBJ_F11}?74=29@YY1vr3W(a@B+(B1U-39pC+vbLwrN9UT80&GXkY-rN~MQ;0$Z| z^^g?rgnXGq{~KoBE~;8$OCNM^3d16NElAzgi)ti#EX@VTwIxHaG#l}LDM^;dJ+g4f z(INW+s}vVuIu$wno)DWqn}0W{o{$3c9N-Ie&0O62U4!@HGas z%-Q*7W8ChYw&iMbb?aKge8~4Y>kcG5sPK;6+3^=?$b}2Y9)K@^57SyH3n#1o4;Og% zdE6FJ#x=K5#&&26?gFDMxYVHBu3D-`-e(^^G?F}=y!~=+Al7eA>YoC?v?X-5c*|W2kDr+= zozXNSi-+7M|BIW_77f%KUaZy0G*s&3ZT)`y`F!UO|6=ui(ksn-KKuEKqqVW?FMPC+ z)&Gmn``>-@-~XoOKBY@^`SN_DQB8mQsXssX{9k_R#XtGO#ecZ}H^18YhsDEx_w_?Z zzxHPz@lSkx`T1A>EB1^FU%&U)8_Ur9c|UyKc?YZfXe6DSv3aT52s-I&V0RbBL49FS zYv@h1MN>Wg)qel<{pNFrGKK*iw(^Vr<$Hhq=w~nZox6Yj)qBUT-`V))#}EAWM>lUh z_|Yv}K02RP_V2G&=gC%K?h?ObYjg3yw!CpB6_nf>2cD~ey(TuUW`Btlo)X)jW*@1sjd->%>d;LX^mNH&7wz&KJcf5tRi{+O(MI3Z8 zzwgbzaPj50eE7{j`(LiC-Tw6-p8ER7YqeXk@%;KvZ>l|i?byt97ask)^n#B*`cE3m zWbpg<0PevD4+D=p61ORzF~Q#DRliyr z+(Du_+-E)%$=mL~8fXV!M__zcZEwt8+)~!_x_>?D`-7=eV%9v`j zd#+a}1GANvW@dJE=|sEgkF68O%aA;qT%!}ZaG?|Sre-4sr4)Ox7oL1Wj|d%|46Nzj zrB03<(SGko9*O1>6BEJSZFTRHJ63~E4lfo1Wi{Ad$QGcdfK!ZMQW0$`ur}S8#Tjqf z7=Pl}W9wwsu5K;^v#-3eckiyEk6>SNn`}aktrLE9nPg2l**#9g@9<$=hYx27sU!Rq zI?3PBYtq!2yVmMtS20f3>tx4{h1I=-I}Xocve}?dY4++w^H$V}<5}KdW?Jfm zT3FR2+AW&+I9RUy*5i$tDeW7>dpTa>C*!OF&&L*TrNftvl6;#|DQ?*b^$BWc^^YC#1~yZnKary|KWTWm5+hH0G*O_79qc zx1ZCWZd0AXyD~rajkoVaX5!%oI>N&gymKep)w+GjBfG{AX8A2UO?L20wJTu-U}wma zVKF}l@i_5di-g-5yFA_-toXb!9|`xHBYZkQtB405eC8RFOl8PijR-$%%nwf}4tz6u zvw=Q&NVZJ_;c+M8qstc@LV4Y|?(ods9Xq(wwrR#^*3K2#9o_WD4Hxq^+$2-M6QjO0 zFspA>uyPq)W4pG7412BotYdu7AoBFaudEzpbCisMw8ru-uC$`h#{*cA1vvu!uPrY# z=9s`fq`CCDE}cYKu@3{fb%H%n$Qkc9(upkj+B%`Nsp!Nvzb9+}8@;HL(>^2HrVVtm zYwi6j<|K8kAz|Bivo&nwEU6w|aH5=bn37DyYy&_nIc~V_AjYx%c(W zmO3fN$;1(@y*fIXoyC@QV()6Z9$BmiU-tms^Y_xp(OnVOac|odZTC8u-q1@g9bWC$ z$u5jrdnqcjz47D3*6751XyCLBb+Rg*%&y+Xz4&-=WcB@b98V`azWI=Uv%$JlYpk?b zX%+q&o%m;;Wok2K`4#oS$~v8xBX_LRi7b#ibJxTXwA>jd>1<|>ewVqct&_hOH4t=i z^|zIK1D*7@=_BYskQ71=H2rALnBlxz8+!4az$z+XAanhw=$GlA4*2qHLY=2*Jro{%jwfGH zZ1TqNWy?2L_{I|`(#!J{eQ};+X){>bHJ0gX{e3#WQGAMX8kLV2G2M_S`yDiCD|D#Q*>0cPbSm za3?EA*$gL{vHTe~W*=GGnzj%_T)V?-=?b#8x2862Jb|;n*d05`@EWak6|*K~4PPJP zzL*p`*_6u`*d^lv)q2OTN0k_oEdS-4O0?&W(*EsM_(d(#I@mA$(SHSav-BML_VZNG1?r%%%h^m;3@OzP9VeViZfD zuMdYziRzyu2`n6Ye2JJuj)0fVT&i=)pPb30cS_@;?J{RZ*m>E>BW5u+D6%ZM)3G>* zI#D*Sw1U4USOk$95O z;GK!NS{u2E<0~;_Ow-kyGa3wRs-3fYtaYt1w|&xHJ9i&?sxO=5V~mBwRF#?P<;h40IZJLNwZ5hH zFfe5AvN3Zbt*$W91o@NV!S zlA9l)4dx_`#;0R}&o)6%*YUjK*1y7s(v2#tebulHC;Wd{>)fJ|zX3$X>Ndp#E-!f+NIr|fon4R8Cc zvG0xedSb_dr0t2rocp(Brjz!4DBU`zoH#0TLF3$9ka_h!1VY%NR$;2~bUC)qr<;+Y zYU+C|3r#38s|u>6^ctHHPWyq*N5G_su}njjhTD^8eU<|qmh(*0MV#XCJY;l@0_Y5C z9&syXE+vHb<5se$0kBbR;aRQ_NUe6Z(tVBbDNdSJ(!s#wog!Hd1h&M)C<;PX+{YQr8V^{qE>Xu#Csh;HwueS7j~h@U?P)S>jTo;8Z*6G zLE@!;yJkcIQ5ZC-3PJv-OI_p^!V;LhLc0vYqMil3Mu}4`6X^OZu|DoAqSGC;m5qya zw#+9(WpIIB=(UuuwSh4f%PT#rC-qCrJ$5HIHIBtGn_am1dNacYN-7u6cl6p{NJ-`0 zhIN9`I)c*+#VP{D3hJrhm)(Xljvr@KTkdrADdje9d(pzRe@5(7p!^}!I49P?&ggLi z4Au5TgGesm>ux$UQTOi}N*RRM1%V||AJ_9-I+Q`vcgt->-b%2Cha3DXSOypM$>_J5 z!34~AV|cbcW^B3;aVe&QzlGK6GCgMjZ7!JQO{X44pH0$hzBavp8c5^c+oq~(Ml4PM_G&3%XXvl013>Z3nptQq z5XjT)eSD#HXD!F7QZ@BC6wA%v1)iH&LWFE5>v*pmR%dncaScXHLyTJB*!*m~suM_1 zSn9x1M_iSunSfM84?q^hXiHE^sVJ6_&*G2DP6TA?t!51ky~fIdDp{jpMn#&ZnnNs2 z!)G((f^%jL7toDIpuQ^zZc~d*Xsj^Yx>~G*%(x}WF%O}MStG&08oNio-{|2(0;SX9 zMq$(uCzGhotW?vCsM82`eP5)rOo@Wab3sK}&H2nCYVkmmPKcHafMqPAP;feLs-BZ6!V8jl|G2%R-p8KXrn}4h zmV?xD)!AbC5LN^PgVx|Sq=bxq={YNMX~Eu4(V)YrM$6<%hlqK~gv{7XZt6#Z)Uu=@ z5yWyi<7J8l*!nKKu_7YRc7?lxz8u?>;6s87b*mErrhQg@5V$#(D9Rarm1 zZpTBXT{gDn8ToHEj%;wziZ&xC2Dl6VWcSV*zv|ah?&nJJA&GSy6wo9Y=a8mJUwxbg z%Dknm9;_$vzECglxW18QkSnaaHo%`uPX!{ zhuUUM1yK(3oi|vSVZn&;m*Kn%Ei1hzxf`-y>5iRH7{yZ-b&@C?5>sSK&!$?_p%PxG z5m8weWD6uL4WIc#*t)WU*Wl9G_?oEH0nM=CP# zr@j`3o@Xi|kRBzzSKRoM9h#8iFZg_OsG;By{PJ?Gr!5*Ig zWzqPaB&Ij=>audf!iYc^0YWqk1MT7|I;u;}2ZqK>rc^bfMR|2QWiFw+xqONy^8qhg zXJ#ioxY28v98K2pGw!aXB-e`P>gzwlum zz<1%FfO;7bUPh2OhSiY1zu`dyEZ%6SP_F*@cIK-QM<9S2nAcpEbX9qYVGDOl5MP&* zmj;yx=_UgmUH1d#jTdBo4|9K>Ke%T*r;m?dtYnRurb6&?(y%esTo^um;GBbxWkI}0 zpZIZ6GGUW?vTrw&Hklv^kn+ZXK<;>ciWs-YOy_+rgFXlrv0d(#|GO)4f=#z-d|LL_omg~=LxjFOTS2|Uv~ zht3$44N$QPzDO)Rp8W~-*L_UpLsNxv3IZ5}g&5J^1ZBfaIgo`z%`HKdqdujM8=&wM zKKt7Na}o}QHSiDJMP(;`(4i*hBMaZKp_JG@-NN~R4^%#MdL%8x$8SRx(CsJzYrs)p z0nReEm=Ju3x6#}(lP&O5k-DdwX>_BWqru8LA*VPw%>8N~}yzYX%F_2C=7HEe#> z4L8%TzUR?>*EXx4NXK{^Gsxm)+4T98O#*O8-Z{1BOLo*)kFhgJRdd;gYj+MWi<6gh zvwr>qjx)X)*l|Kmn@UR$4A=8!E2$<8-iJ2)CS%4czM63W{Su$F-j^hWI3kX4#?58u zME$xR4Y+z9{&E;Je^{Sk^*+_&Y6_wKvU#TUs>aT+H^AGer(JX%@Of@;fr+m)f8uz zvCgNrCo?Faj;4^d9EPl-kbLMKO>2qyLI0~Y^DiK|YQdUqGbs-#+s)H&uYSw8ruiIm zD!ek_vaL(@oqTbC*F4xa*8P5XT=;apKNN3##c*b(xu9+;64GQ1_?ZQn zXFfp7&`87t!3|D1sz`tV9Yuk> zJ<^G<{f1?uCPQ-o4L1kT$COHBJye%x1wi=Df=kKQZuu z>;N(i`$lzNtJQ4yX5*VXX1?)zkFNa6KmCPQ|K;aDeA(@xiT(ch*|c_a`hul{g-*h8 zjfUc9^5)mREv&ZmiJXB;DYkev;Pj9)fAtKXg+_re{hqpcKulej>FMjw>4;}bp z|DyLy$BkG1deJ|9=<9#_^1|Y`%%NwdVPiZKQMPsKmNeZ|8LoN#-k81m=D+^KAN}5+ zygSY3hpT+bC@b2i5_FO#+wQ%0TQ#k0TK(>;fAiL#diC93|H|Tb-t&c*e(Dpy`i-+M z`|9U^=#^i3y1D%MzDAX~tD0qfcU=FU{_bbaAO69m#oFT^#g6l_%U@l5>`x#4h{R`D zZ~E>>=D#z2!PP&0_b^Ky&Re8BHCW}7pE&!x`T2eGpWRoxPdd5#Q%~$$n7{WU`GE%( z8=Lm)TuR8$s@wqe^UBa``#$EVEsk%~Oo&eCLXGEky!#vPcy#3xKlS04fAp#A{^q|w zw2Y9xHUAJgnKCo7i&aK+V(9!nxwBSV-tE)<4f?h>^Npw*KR?!@E>GY4Ltvq7G;Yne zd};UC%(h!^soi{ie(m+i993r;|Iqtn*Lcl4pQzPdzAnG!nxImXHtu=xoRuJ8=?t2D zWusf7I|$!YPN#uDE*-n(yp@C815WwLwB(MVs?b^Nn0>V!`=^oBPm z$LcGyPp+=M@B;7F(m~xF$~~;dW=A#KbZsimDKxLV(vFItpey!ji*NUzN{SHtXFqVy zi$y$mho4+vg)}`)cPQ>zW$L--#!&x1$R8h9dz+)H?9~oBS-s?Cl?_w&bYu6xwrkT7=lfSHCBoKUZS=cJ=O?uT(13a_h$jR*$8V)8AO;J$b*Q zlZgp*vbV5feO)@~-jn{euvfahf4*BEy=4TQoU?NKQgvFM+rAt614l#k>SQ%&xGdwzCuaw)|K|13mOvW--~Ri(yGo4wSJ*h; z9e?h*m(a=EzHsTK8`=~=y7eR7^d}d7LuiW$#!1l04vZY$HSq(XFL(OzMl3_Vg07uD zG5ZqZq!=3kdvZFt-M?6GGb1oPJ9=T9yN<6Dv&wK9J^ddI<0R^2(;tLql-1SVxoba6 zV=oECFn6t<@ypkIr&DIMQ+((%Grc-lH+Q|n+;#qMTzaX-@J6udV;f;l4A;>~n7is` z%V09wcj`K!PrV{*#S#krl>6sjW1O(Yqj3YQbo|X3;SisW50FY?ImC=!;3pS`7Zkk- z!-bJ7e;WLYHp{7JG0Si;#q@`gmWLwbj+9GLstv7gqEL znQbv0o5R-dA?S$*I^G8cx-90A+h64GV2&Ls%cxgIITKQK6z@q>e>+c+yWxEXdC$AC zICB!b-uwt($QI~X)7B@1zln1hLw@WMX@f5z>&I%?H=ny$&Q`&ZPIi*ATTG{JciEoOZW2D& zO9p$$(hiawXZ{=IJ3$C#$&N8A>=^^^@r56jkIdV*qa)6oy#1oAdN9!S+ESh^*>Ay) zQS`Jy@YN>a%u45PfbX_WzWLC0HyJ;?C)$dhQ}`inXhX?;J8!9|+q5y?jdS9_(NG;u zG&A;xw(^~p_{%ZKm=IENid$D-ZD8Q=V6BGT%!KDW>ubIvyLGIwXE71NbSpCDk;qgw zS1Pr=FTHg7f8bT=laD=Sj=&|3UIG&n{ku+kPxt*iuJ8JH#e4aM?+R;%IG9a`(XauG2old402OWO={FXSOPvfHydf zuI=K7CBu98m}3M_HguXLZ1)bTVx2ZKGd?5Afq}hd`LVZ|C*M(=t+qxdh!Dz>PF90X zRQBrX_22E)Nsvkm(TU+}7JaY$GoG^_du;H@psscs&(7X<+h=;tY>xN*7hZ_>@^{=3 z?)7c@z;Z+9w4T-Hh9ql{dv{5e&NocukPM-4m75KkZ0x@>mW;lmF;7{^I*Un|B*rILJ6#P?~4rVqSC*$L_+W5Fyp{*0vF^rRS%=`M1hfZXic;{_v#9O|* zf=-s&d|IZ-{@xb9u*&zYolpcSl{ikOr`g)@k@L;OJK{Z_*6-6 zZu+!rgF8CujNF(0yJo+>SKjh%+`hpldv!7}Fg^Xyx4U%`*I|Q$aeZ~xPoAhwcD%T@ zPOlZ8*`)_>ntiXo1a)l!9;TWdSuuh*6Wec#BQn8B*#Ue2jQLBnV(&Pm^s-L)#FJ#3jr3Vz_h=eLoH~hK_Kxzif)8zBL);W}w57_+ z(ob7_pkZC%i!j*e74hJi^P`8oq5|FahrE4eu~zW;a^VvfVK|qu%a=W(@XCKv;p4UW zm3)uq?}onn9LJFV%Spcdq;(SQ3fpz%?8!MX!#>gBuC-f~og-)?e~ub^=;#UZ$L2hn ze$+Pjrm(&2*j#dMBY5$X?3F)@e9RyIY7X8vA1vdAzd-$WwEX@bN`h{E9lqpLbYYv4HD~38xCMqW*O+n>? zBG4GI0%WD6KXYe+sfX|I1}ZTW2a%Q+L1Ez$jtjyJ$&n^5pi6Ku5(+BHAt}{+x>JKX zyMCwH$V{z$CZ+(2yzoLo-@qlQ~j$+XbJc-cOqaJ83Sk#@KRAm6D7IAOM{m z#3Q~Q>};LknVQ5pDYj`zwSoH#3p~>h^1dl7P{0Qkq}ACG-o`o zLn+NEUT+!pXOm>=b82OQtxW~rxos&m_PHCj(9R_fD^qA+ZxI$qL16PKB(>(I>9A6% zDFq>I#umq6XaZPsmQ(`TDN(Ol61MkZQVLFcVRrI9eGkb*1=_1(tXdb}2}4Lxwzbe( zQn8(E>TNUWP*YH%kbqs6`pr^Nn$a>OEx}R}1p&XgFgt>)4VXyaC7v$cvl4J-XH0~s z8bV_|8i&$wT>ekFG9j7_aPX?qk1mN=l6M`q~l!cQaUGS=q<5Huk zp86$6KlvRpqoYFA!h|3K?fGJUAYinUOC?*ZeHhF+zfT2;J!IrzI_w|AUsh0)0YCZ0 znW9N1Wi<1_Zl+=h)}Rbf*S!fDm@fy7o;GtcJ>>43&fw6;U)5)xa2V+QBzlPL_URGk z5C7x31tQ>#`fi|b^qFCDiF-8vQrm{^wUew@g9cKE(*cbAILnVxvS1b%6Hv2*i|i)r zr)QG^Nkfc=JF7Xjh>Lqh_ziE3xlYC{#~V9^;F6G47fn$J?g&rE(O~R!pmwxS=*UV7 zK;f?9kaG_qhDTOe5*LII$#|im;b|uszZVb~ldAOMo1-vD_ zZmK`v5X{&LHzqZanyW2Clb~1|Gtw4h>%R+#Q*f+=%FUhL41clZ0s}F>*4$4asi`kf zJ_H^qRj?qP){&dl#*`)!is7cvX^i)px`&ghWHITq2E&7q9CGItHrDy^{Z zeX~LRO>DK0fSCo=!0w&q5@z`^%E(5|VwNZG?ZdMAPASUQM`N!j8e+j&8cHouMW#C3 z`U9)nTjQYe%OW>O%sRUDKM`#X=T8Bxy7(h z(DSF6`26WSVRR>+OL!oua7XbWSUB7wQd_MWr~(v}34XwoIejdKDO_i3m}-NAhEpm_ zr%}F=oZ#Shgg6?LCV4;h)Z~E%|A;u}Ysom|Imh{9_nzGpi zN-Z;hq@Qz?6=*}h^3+u9`O7DQ5-d>-I;T;ycKd|@IuEMFXTz+ zx<0BRtA@l#AXjkON#Eny(GylB5-JE*KTJh4dSC(GD?n226j%#cllF^94fMXiqhMtk zW|NO;1zNEJ6C0zzml-0l$?$Vjker_BcRYiC2C|@J&WBPJt9Z1PU*W z5mMUV#uU7aBb*US*_`5l3$8h*)4wC)wcRXam5AGuy7>`|J>qh(5Cyyl+}j;Bq}QcH z1U8wDbcoMAH>HuB@S$#a3K!tYKo7PZX(v0AI=bK35jvGrF@oLQvwh=3f;EK1^Nr4y@+eMUUbZEb4Q*QUT9B2k>&ry^xH4+D zi%1wb1uTo98RMeUg@k}8QsteTe9E9)U0?|_eUvRyrfj*P44tUY+Eg`H0kNLha1EWW zWgOT+(*`n?ROBNi<9!G91&Hu}Y}h!l#KKt3n%$uGLpo=s#_Bt5{e3))jP?J(=*-h@ znpuJshEHolF8~WXZf?`6RFuo5K8zK4TyJk@rFS3CkDeg&t44i6+Y#{ zIy_fE3m(-;!v~uvg<&$b`!t>?=Io4}$=#j5@Yb_=i@g2b`s2p^(JddZZNE5U@2o*s zHA??eqvX$6*O8Nu)@x>1{Uk!uJ#OARcHzU0WZv0i!itjRdi0}&zOp>cE3)?IFJk84 z`rwxQX!?lI8Pc#>T=F*C@9zvmJJxoi`#*wCTCh*j0|(Ga-{ywOg8x&ue(tIF|J)D##Lw1m7R>qkzjXR?aUZo+i zG3UGc<(Jb#yYok5H9}@`>z5$XVH7(XAu`}5S*=Dve$!LGeD71+K63D*N{IBhp<3tM z9zrMK9H=cGXy(cM7Z?4@`^M_K|N7jgE^^eBc>0_Lz!H2Pf z%o@Hr*j#+#OxpVJ69*RW^7H$GPQ0mv{NNh|AUB~-I!iM0Lj^*6Gp9IoAwBU)+M?TK znK|!<_bt5nx`B)GKfnDiZol=z7yjAbzIyrPw_LRA@^5_SzukQ8OaI#^x19G|+Xl8B ztYruIvXN=L;i=18TPpoq`gCigxY`q!)XZ?dq3Ogw`Q*?2?oYk{{cm2qF|9l?ln?fC zE+h3wIG>S0P9JI@sNt$SaqZ&RwQok1v+RjUmo+w` zPJRrTe$`RWD;|L~9}@~~PXL6{>1T8Dy{`}#l3soQ zowSn2kJjsl%x^E#T#Ku#xBS(mfSvcH|}Qh?uEWrc`Ug(e2H&%SG) ze1}cg$K8qch6V@2$vsDUv8NCli0$@;RkM63{bTNN>Ei6*e>{5WuF9qSuse}$^(!|I zzS~qP3xT;CzfGHKIlC@+?EFHxJi6WBF##gWQOyT8)GoLFdJqSx-R zlWX`CerN3D4k2tqWm&KWtLSlcf+c|T@w#<#bTzgkyWf}p@%raX;&y*!VBp2)FWvRh zr92Z)XIt+%GB6Ny635A9dg~>f^cH>3J$rj}g2CzRRd*c!d>QfCwfBnEy?d|!rotx! zv#Y&!kDa_{YP`NKSe=#a!^!KU@?5ar=xvx&kmM*WqHITxKK}SW&OXEBB%OTjmP^M= zo%COYPC9c}|He8otJ2BQc0Zb!HRz->ZjL3|_}(ifW@gU#d<}{ue?8vy$hm4I`;fZRhs9nYiFjaUOe8j~#_=_Vx z#D^yJHl91xWc$5c!N17Q&oZgyF=slw`%dB4=2P&Gd^+Vt+d%|afp4AiU$oJ#v74Tx zvpvp9LcKzU-N>vL5y9uD?A?^n&6~Qk?HqFzfXtQAXa`xrZc(LOj;Fo9~eD%3rhrHiC8XC|@{hkl&VkP{fU`#<=7k<;qSQU*6d&@`*!e_y5C;dEtYi=eQ5_7 zeCOYD(XGMm5qm~tD{M7$=p+aYdnF#P2-?uhPadbd+P5RwpOZd&4r2N0W zb??j_-gxeGNA&ah^z?KwN8fxiv;kO}6!&l00Ii1!+0p>ttNG<42JW5nd1FFIJq4#Y ze;WtP-%dCWZlXP zle0%8h-?t=#;>I%?cRsSFB3`B$?AZ=W0i4YCLVv>jNWz|bJrT3 z7#3C$Hr9#eE}bdg(MhyVWM9ea(#a9dqE@-*9yxrBxogKcgDL^$`Xn2wO^H4mkM!*` z3D?*oR^L*jm$rIq{oOP}Om*ElJkb06FJ70=pj zMJ&LlZSXw4SEz^wWVeH@9|aj~_beV~7|ILwhzhK=Lrk$>1Z~!yw^+tSFM={(QrJV5 z@gARY%XoKwu{VFn&d@&zp;K_8jEOtnIOX1ae&EqQi?WodutyYrP84_jsJov)W`NYJ;5)7oL-4p@ zV=ClD=vdUQli*_!9mKj2m2pCPIRY2l<2dKChFU}Qnt4u$Ue8l&puo6@E@Ckv7vVPo zI|VlFq_|>_LmR{S4V?`UrQu^I#A>5S^3UIM0@YaD17?#xn7u>>eJ+U%nV{A;_ zFhiLUf6Kq^iWI>h-+J^3V_cxLuSp;2)>M&P9lRrK!JG=j2AA8_^smW?R)^en=z21D z;R_0O19oV;LhG@@*e;4=2m60NrX5EQ$4NRi-;Gk-M#$I3wIJzg8JD;iL$1KFD{W(D z$E-kC&gB1N?`_~LJL)>`I;T(foVn>t-=68240)rbcM>{dz=n<(TxDvSCTTHZ1Jff9 zqBDVPu!^mL2CiSG7Jde|1EYzT*!a-w z_l{fq0;_t}A?U#A@>IUx8xh3Hj*BmAm_)-{mAL$}wGpGS#3VTD0@;o?2|K8Rvhs8^ zRInR3#TnEUcUwI+)Jw~#&YS>i%XuqV7M(pt>xyxOS$Pl`vxjnpTBXMKIbGwX4kN1^ zeVdd)oepW&3TT|bM;zX9Sw>c4)Jwep+9`g->!nbb*AQ8JV8)7%-+4*5mt%}5^qm-l z)A%F?Iu?Q8Wd9MTWegx)HhwNc3-F2OMQJ6M2qm2bL|x`UWkrzpm1{^0!K8@c zo6PPUgc5h#d?RZk#YI|`3{o}vwZ1$51@-04rFx}`FT}WnC0D`7Vu7FBBFCMVX>k*9zn(fGD&GKkPOGSf|Xk#47iy(BI%*{e3jh5vn7XAyd0ZfGOkdizd z0~YU|SL#2=pu*QE7TSv_%sZ!NB`m8A?S7OCkkz-Y@6DdlQkFBJL#Bs=EQrh|1J#0x@tE(-|wZ#>g)gcUioyDa%zc0z&2^U)L za~?9%xCuN1j3oI$!T1I%16{8TiEF7-v53ej=LFjsgvISd86)t0Nj{fU)QUv9#rLrL zE(1}QbTUCm%c4EEo&+k+p*oPm0l0-HOBI#XMy_dHigD&7DRb8OSthSz?T8a(s z%==W4A?BKK;ZI9ojm~EIZB}PL`ZZ!G5WD|=QPB9P#7fa)(N&;rC36Ykwl}~7$?25VB zMXw5xIuE}$xfZ7-vs46u2@4; zT+rxylsw|KQ}sTOUASl1Vq#P2J+s!{qh{l{S1o9J42qD7gOYOzZs$m}a=1avB0eiq zu9X9OpR0+DEqV(Ar;HGa&03w#N)O=aP)K84vXIBx$_^~1GpEt?e+!Yed@JnX7G>k= zCccad>nbrUQj1R{%g_>wTHTwTR5*W%-AG50tM{ySyC$;U1Btkjy$7cOvv@qR2Qljz zSc`Rw7BLN9v~-X2F?v$MSV2)vNpc|yA$B4p2Db>!saRC@%koLML>X)?K7JzsIP9X5Ke%!_hxLPq z!IpOU;Jc`G<%r%z?mGtwweOrs+4L9kVx~l8_WQ=9)z+45q10OwW~VH-)q-{qPw zA?KuQo5&_gdyk<5<1)TN!lQnW^(E*$sS_|^MXEcVUo)GY-L5cgi$MNl$w(#F09va?Fx-kYMa!cEvLPvXy#i#Bo;F zd;6_&v`HrV?8HmQaT#e(AT_~{4akpuxQao~)3@-_vKUHKq!gmUxPim-(J)ly&?m?m zStpu-??diDCSOfwaW(W!mglarFWft> zdS=nlVlFYb4s^S!=OkN`J_`$qq*nOg)OuLn@kso2xs;dR>I$^swk zQ&|lv`HfNRLGv33@@F7oK`5% zNF2GvgZo}(%X9OkWC$xkG;H^&ee-%QIib$g>Xmp)v@{w8;n0^+>eJ}NXIrDJI*d8) z1;a{foTX{y`VtqP6W(yP&CA7a8UzzrlCMdmacHZgIDIKc$Du7ocX9+d+Phkjf=s<(&}^JC%!B2?JQ>3{I5yiDrZ|cocD^$W1I~ zVMc~2(2wt8s`@kq}4&}+Eoq>!Q_Q28HHE+%KU33W}OD| z$5pBbR-)%$Hj+H&+a@OU^~00pSLq|^%SVxjEA%+opX{G9>8R8d)+G~C(xpqK+ajDu z4EL(xm;S}v(t)9=SAM8;$BB99U{!sLb2il%%0`P2#cv(##YI0J+Q7!*6SgotH0$Eo z2BR&J(rgyTr6kgk%{oyy?~0;FF+Qi%qV)x#iRF&(cl{0~3Y-{bCFWivhw_JTikj8N zcY{zq(I+P%J$WS)i%b@Ks`@PUZiBE0Gzp#KjQ6Vkwi0N$IWv z^4PdI>$b94K;0_mT>w8PzlZ=HR^+*p>v|nsp2u;_`$koyy&xJmq-|9mAAVsx|B%ce zVdus@1UHqI)I8pQlH~fX#yHiK$sGHJk190-aJYG{lJT^pkM*TfNK_U8j!9#%QchcI zA(EkPQHGzptcri+mY;g#8*h2bTW-Go=9`Y({LP#H?UtL~_~Kih`qqx~|LZr8JZtKz z(&!cVov$6zCm1I^>YS&3Y4Vnvf9kQLPkrIJ+urkuAH-`KZ@&5Fw=9>w@|A^=I30=X z!X2pXHk=Dfd4XlL-`XjBFY(jpUcp}=F_Fp?Cy~hASI^6S=mItw=nG?N*>z0rG zBoIIIsc)ti@3>*lvyP0HuDD`8-P4!%N%}8uoP5`_f9hLze{<;*0~dYtbIVUHJ$3UN zUisiT=o3A3$z{72X0aAD?-Rg6IcVQ6yl-evlH7Ki>=O#R#*7oI=pAI+q_T)2eQrVZ;T5x9U%J4{AOCFW-j`f{FZMeZ$G!Roq2H1Fn^Gx0?*RHFcUD5t z-@jwwE1%UT-zJrnxEm+<*`9Mwyz712l0I283bE|*bMR)PE6$n!%FdCgaa2hXW-i?E zT^Hk}f_*POP`doOZI|7=&-Kadt;f)~Xy#V<(8K@x;m<^~eG*0dwmq^Wi^< zubSxj#*h8wKSwW7V_$smpT9UfoIOiAfL&0HO<_mC39(W~j}A;P$x&;5tan*`S)Lfh ziZeZ=#(x`6&?ll?*U5w3^&B40#WSCcUGzJ7zM5xndwP1GRMU7QId?}mh`E(QSTH5|CMMJpM7|A`=Ziz0nznuBFCXh)oPFJM7ykHo z&qJTGC*S|Cr(#ON!D}{L4w(gS7isrNbbs*F?_%5;c$O$2zXyHTIiur6l)o^R#( zYV>-aJb19SPa<2)+j_jcJ{cHjwNGSigzppdi`3t@p~*Puw}S`&@I@yL=B`I>__L3G zTIwsrG{xx8Cza`?mGAXt=}h4Jkk5)(z09InVH)4v0$@(zrDE&udgb!C9FfNE&1xJ z-Fg)_ceT?eV#OZ>i93W_LdZ8B z>QLq5GDKY*%7Bmdij(J<;_AAHTv&)c*2}p%N&1*h(mTb+xwVy=aWhv+^jc-h@WA6%)IsuzkJ=R0 zF~W|M%Q{3jw{{Rd)(Cp}YjB5iBmvrdt)F%6eoZBxn-FD9q3FTBv$xmfi?EIo*8tA- z%Yg34Wp$Ch4U@0)r4A_bDu8fhydh%(`2{04CJ%)+piaUH`CZ*&$%pvF8&GH5qS_<= zh5dM6qnUrxevv2u&7-+s!qKuTL)B~hIi0CP#w?1IQEY%SI#>wx~SiM zr!)B2)mQr!h3jClAeEGjw)jwE9C0$L#>XJ-r=yX)E3)3cJ3#d>on46G)^wM=w)?&SEA8485_g- z*r}Rvg1hv%!+>#;_eK~G#hwXr=s)tzC#IhG%dxT9d+_#7jFbLTM~}y|r+!7oNqCH= zx+Q*`-0}i9PL^@iW^Q>9_at@DY1Ah@Jz-sA(5&zG9&d1QSzoP*4@LtDH*V;jTlluJQnGbVd^=z*f>?XS|_0_QOErQj) zPsz5qUaFnm2enI(uya}ZeDH%j_(ge$e^84?Pt`pVpQAQi{b7g)-{-5yRoeeNpR@g~ zU!Q2lLr!m7)+34}U%!ZTiB51Vli!!=W$$Cm*D+#^rsNCnbIk4Ze^48X1pgjLYvCiN zVp+#%5y;||^^B6bwcUl!I&Jm0?UV#%z<}wy*_63sXSYn@~y@T5NS$OnJ1LP$ZPP8^CM zfQuI0{ZtbVW;HB(xun%`4f#7=*k9p74(;t*Rijk>OwW$HR%C8l;2zCUt_c>cG`@7} z>DjD_V)cY^97FA7S9Z>L&u?ww{Y5vrWQCj?NmjO43MZZBMFt%P;?f$~4&!NIcW*cw zc;1T3Y_hN$NeD+ip16{9mY5Zbn8_qTFN&UM70G!mJvPviDaRuOtx78)ujod}h|_c05NB#-RH`gDd@IFxds$s0 z{~VheF;T8kNZ*$cG`DJ00g;=b>RMZ>}MiP#BJg>Jy@92A5*DJdpNw^#W**fw&tS{7N|JRv4KxfOLMC{Pf2MHB5cV65jyARUR%Urg1a zI-uhbJp79#jT%z81w4m5?@G7I%1)u3SfR%)BzhK`S%^!+>8z`#Pi|rBdD@^^s4HqG z)sv4`l+vBcJRiwZ5#4z*$eQ}5fricG;^T9#mBO*^(3hR!HKvFsm{LX;UCB6bKm(cu zmo;YI5kdYiIBIrRtz8uJO{ML5=g!f-40Uc(gWZut7$e+v` zWb!k({S<=USyu_cY2~qByfhkFywk8M#rt_r4og<_8aSP|60KcD&t-Q!ki$8xjQCc0 zKif(h!d`aakBLHuE~`s+E*y-YVKz26W0e+4+0NmFMh1sQ+{vAAPRV=%ad4=8cERLj zvBt}MQCA#^w_|S8IG;vaTpQJlFxB$@6{Tg3f*RNQ8VzMVugmzsjZ{s!6~RdH&eany z{fXtl3^k5lDn>U*b+pt7@56qnPWNFT`NLFW&{lG-gR{;?UXJx~JV({}njlzoZE}_? zn>f+Zc-TOUGMA!x~Sn!IcZSDsF^f7 zQ>=(`XA+ZG9bW0dK`cm2@m1Fee@?rAG%X6jq33XMsSk`? zUXJF{eZv-$DNN5E#^tGYyO6|DcKgntPOZA2DZZ)AwByHXz?s>YR#UBBYImWxB)t83ci<|Cv*34m~BUFi|Y0XvQxd?WFF`^s;d!@()pyBKM( z)pCOe{j9+}^7Eb3$9*&{rtrUCDiAIs3n!!g2Ex9`SMlwQf zTtFh#t{{cpz_(YYw-=reDAo7N4Dw^@Qbvs!Ved|DPfkpX&fw^Rc;-w9Ab%wcNJjdo zqK6|0oJM2Bmjx}*nMBAy32FwceZRPLRK|6z#W5}Zk2BB#ldCRY$kZMk;!gYgylJ{(fo_T7(!Rqq|aHl_@?a#{i-*|`Ir zYF$V%WB8q4w4D=1*#EslMB=%FRorfjcIN$JT~coJ%I6=`I#vfJcYN2U-q@!{rc!kU zj`4%J0Ze|*I2OdfR%G^AjkKvlY5amcYAVvhkLvv|(tDIF9l^GmImZ@Piq1DtY)qaJk zNEw6odWbH}IVY!X_%Ey7BhPw~+yWa;`n4HRQ-5|i-Me@6C9gq$$$f_0uFJLR#=2D0 z+cn2U+Ss^!6@5f6yrB|pFI2{l#ANNP$%s?j6hCpIda-&?p7PdUlZ+Vb-$Bg>A~_=h zE7?d0l{q1PMbF<0#9b_LI3nQ_9F)<+Hblk0`R1Sc@z?$M9a8tQ-ff7!9))kj9AroZ~ezxuA{-~1Cd z55)`6$C^2B9wil>6+xBU$K5!nl8Tad)_E@7<#X|%8P?Ke$zpftMxU?!E#9|yN1w%o zTjsJh;AJ=;npb;n-Tt11(ueL$qqjaezwmcMBPaLZYX&Q-p>ENFolDeAFPiS;yG!vM zSb-U1Fe7d;PKNsB;JX{w3kmwzO)S%sN!p@ufpwLR(?`0rOVV8&LFc1STp-{> zde1FL?8pt37Rs2LP`9~EOJ*0oa@EMx5oJ+2>Ky7OeG*4A z394#g0Y4kDa0mQ8^qh+)NngLhVRtuxCg_v5rS_pD%w1w<*3Lm6XSzOr`Q^RCZ~3Qh z+_*cneX$mGr2wQ*m{>fFo4yab)FY)w;Ze? z$`@s}lDB{K{^66?sFUT}#|Ey^llz z85{d${0>5=YcDFb85n47ZC=RnA=P{Qj=%cL|B;@YR7-|DK1gn#JKI4t+8* z+^*_Jh! za^K}Dv`zf;tIBk3mUW4c@2rx$`!rd6C-TXIDC&@MdQxY3uj9i(Kg%yF8AG`)!8JdB>#Bj}+ggi5@jJzI%AQbip$Q2k?^+)2cM6mi8z1rzN*@ zZcWTyJ89(u`m#e-B(P?!CWvIFGnM&m+!T_Q$5d$FN4|RFy_150Z&TxI4M0W24tV%?18m?M0ICy`dPqNgE zeSiPeS68p>&))5qn>hZ+@|ZEoNT1*(g{a=q2e8`Il%F2@9t&inK&rINGr^VtoE>`c8Wl4YHiGv4!@UI7; zTr8*9Cl5Rz=c3ilziTs`eH}a~ed1+Kt1!-v_e_uND}CrPnY-{~Ht3Vm1H;4RMf@a% z8y`6CYsq(?mY?=}{Bf+%L!S%}qfh$BXa9P6wsgr)j1A11ljYxAgu)qgef~>|4r&0V zSzGI8zUY+nNl#CI|E{0Iu3j@HT#f=$%w2^($>y%i{NQ6)8+@v|PwLpLUzIH;z4-6f zyTT;{i&2uVnGEq_Ihp)7f*ccyiJTH~gX*}N&O07 zFsr7nOkAO#U2cTSmX$fGBr7r_&0Qu{>G)vPN&kv8FQ}idf$}QifzPj!xUos6VHeIX z!y2|E^j|}TrU`4eu%d`HJ>Rv$+NKiV+k2cC5=cs z{U2-wU$U?6ikj=RvsD#(@!wQM)+=aD#ZtKGnn{W+QbE-qB@0*gLshR;Y@#P?b$n7i zSyiSj6C4=dxTJT@}mZz`CpQrdhRk{|5QTRf{B7pS~*skW9 zrTe@lH{tawai7qi$7p>4ph)!LqiQAo!K^m6A$YRVZsB zJm2lwop&W}yi}=ept9)2vwvbaN24P88zp4&U?&@6VkfDbJ+I6x3fRxHm4PAm zO1&U~hR(vl4@q@>XR)Y>8`jNBs%tJ2uE?D{V>R`T((u5rbs61^YjxOxgE3c!SX46B zK0zxZGAwl)_qFtTpq9_vqAyZ>s%HI60=XYD64yRYl@^3s#SL`)omQ(YtO4I@rixz3 z9{fs5A>=zGzn(GG-BwWD{@v77U>T%=sd%e8 zQ=1y1!LLotVom!><7fiiFqLK5wvu5_GXsudUU;O7uFYsxuz0dQIdtE zs;?v}&dR2$Pb8YhU4$DFAOR8}0TMVp1oY`CW#wC;S^c0FQu27XtjPQo z@{plR{r(rNf5XE1#PD5D9xoKNLN50V>$yhqg6{l7A}}~_yHwr&YfAlWA$`k4e`(9q zv}r}Jxm{E&RtP8R=O4t1VJ-2k=XPDa_3GTH#=qdk$=>1ePxPHgF2(!*bR*5pE${jE z&0W8CYWHuaL_2xq?B4g8-QS7d>9FnO-aNYHj(@*v^R$6AApsH~0TLhq5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq z5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TMW~1m;wNzpdlSySGkVo7FUS3bFEjGwscr zzUz6Lw{GiIv%M+WRt(O{}p!a@= zovwDQN8cu|I$gCrbLF^8u=48Vughf`idYXjyMMY)T~E}JQA7eHKmsH{0wh2J-9^9@ znp2DylGh%6+Vz=@4KHc!b)^LoI8y|+e<3T`oT(aY`f`h8it%-CK-sRlNg5;p5+DH* zAOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*Ab|}g z(6c7{A-DJ;+={{0f7_!StF4qw9TFe`5+DH*AOR8}0TLjAE+=5xZD0D_c5_gl1hzZ@ z({2kmPTD0#eG(u65+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH* zAOR8}0TLhq5+H%K64;9GW|TJXT3Tz%H*tQw9(60O87#)vql{V`d;iAA+bT)d+SshI zcHYgn9`99LFAjaP>t$&Z+G+Am#_Afc$9om4?X4wz(Wg4d-9}qGu+A(bKmsH{0wh2J zB(O0AOkK0}rPZp34BvN`QVZg7E{X%(C_wXIc&j?Jz&Z7`zKXg;i84E|{>dR>d^zHzddRwj1V zRoygBIwQbbBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{ z0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JXFGwdw!X3FOJ_xo>AJ0~FKw^_vH7~h z<{EWtu|jy^M^=c|F3@W?v7Q#T+WN*_|G1v5-?X;szrC=&^o%!RL&nJ_ZR;6_%?gkJ z36KB@kN^psegbBlid+Xf@jBR8r`FI63DgoWwb71a>tH8d2OAyNpBYJj1W14cNPq-L zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1V~^@5STh6wJdM8 zSLdA(3Y)9Y3(jw~K3i?2W~=SmIK8mDiyy+Rl(y}@RXyv-&h6$)NsRIf3A zgY4_whV{1BpxP_Mdp^HHv}FbDJd;~!WLcdkND%e*idKv9LOxrFcM|=tK2wvDISaK0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBtQZr zKmsH{0wh2JBtQZrKmsH{0wh2JBtQZru$2j%nRjh0Ze?Vwd)oxI{yRZ>Zfd*H%+MBr z_E+G=Iuy`;-jH*1`CI>;AiLhYxrlaOZQ5UzxcAELqp;OmbpGDZg7*6}y&tRPuYh_igBP~>^xdt+{P`^z%PFkpU0SBWbKmsH{0wh2JBtQZrKmsH{0wh2J zBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{0wh2JTbMw2epvhvZlyWf?rTMh zIwa5?1j6&f;)if6Ej#btR93v(#h_ z^+jrCMp^o*XAyxcUG}?N94aKkzBsmE-~tp011!) z36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@ zkN^pg011!)36Q{+B@nGxv$PqS(tH79bB#0KjaNA`bP0X zxRsWjcW*0N)FFYho51Eg#y4NU*j(f6?pL;+1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@ z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1llEVQ9BQ^wrjjq{Z=3TZKRjUv!>|PiY+uZ z*R7FfQZK7Xf$3s=wbEKn%ioV8)^|_)d>c|y%T=Ocw-U&n$z64&K;gOFT(?G^NxiHl z1?YB+xm5{y*wGZ|6CiFFK0m4N2hk(U{$P2x4yKxyef@qaogeE`Z@A zyT5+6@@}QwYkLAXg)kW8rR%G_`I@FpbNPq-LVCxew zo2LoAmu{ZAuqGr>L%`I;&S-?=kS*CzL>+ z1lCGm+qJ>M>0EGgR_*0(Rb-&tihu5#ThUr?oiYfRUwsz}E_$&@>s&{~<-&dz6Y(ds+@nFzzq}NF9im6Jh z3KnX>C<&0j=_X(r7N{Ghbe7POy=~voSz%3btzH+?B=?z4u3x|U((1Z4*QnNR7*6hN zm~=KJ=&Z59U$3@zWbcBL>s5S>osQ~KV_~fkQ!pU$APYW3b)9KZTGT7X>zZjU-22An zI_s`s*4-ivb|V43c^cJw$>ymGYeE7fKmsH{0wh2JBtQZrKmsH{0wh2JBtQZrKmsH{ z0wh2JBtQZrKmsH{0wh2J8%5xIe{G{I({85(?z+FzoXodT1TOrSjj~*8*VINCBY`bN z;6*#?Rk!)Vx8@qbZtI#Mhxnc4sFq8R3hpTDSX7-w`>-*g8>ib-qbKCCBviHE|Y)9ACs&>TL)!KK#H&#n+ zoYp;W?A?4V>3_m=KkJu4>umoEeimJ`*U(Z_&Ix3+=O zoK3wl)}^NH?(hAt@l|OzU%dvjEL)eBwp?0kilI)yZ!OoVTCTT)z1q=Wl*;#o+7wva z^ZZrKHcZSdHqy|I5-2AD5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5;%(p=wbPwDi@%;_ttqmod+r$2<8@&Gu(O*f{Q{iWtQ8=+x0!stfW)Ei-R zb(`tJ>gmPQR2L;3#y9R<$#z(y`q?(Fp7qOvGPAZE)D<@t>c&Z}rmR}$R*f{)(}kpBypY^5+9+R9UW^wFhV7B8sh$J0jnit=LqM)6|4V!Tm4b-|(})jdWQ^XNdo-1U5R`rVcit$Evit-Q-zG~o_rH5=qy$}z6BfTJR=s)e-8z!waK^F`lUUS}7 zNM5%n%5kolpQ)`FC(ZJ$H9eFY{9rG{RquzSP8%{#ie-gzf;{+YjShB_sLBT7&aJnf zna#amKL|p+1-~xukWW3`D7d;hl2Gk*VLwN_t_$+u2PMR7#z`?f=(X#wmz{RYr9KIe zz{U}1Iw|e=aBCCS##M36mYcS5%_W>>1AT3lr`yyos;@PF(O#o?@xp#f#V_-%D%QDf zTdQu1HPf$~-bVhq<*y>FQ=TcPZ=!hJ+e>-<%HNcl*VU1PYG zMQiJ~_lHGVkx6VdXI-MsReU^;W&xcGY##CfAJ@6m$Ma~10o`FfW+MR-AOR8}frbPo zRIfoIK9Nxq3jdoh-dm}Dv3^SZov(A1PDQ&WWK4rL)@UKJvJ9uua{kO7^qZe=i>@oL zs{X@Dp4E(z5-+M@h5t<$kEMRz73-&>kNP@S=>*-Pzu2ISMZFbeWD2e3&(!rI&If0U z#_Pmgc`ekxPF9LYfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@ z1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14c zNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-LfCNZ@1W14cNPq-L zfCNZ@1W14cNPq-LfCNZ@1W14cNPq-3fPmiq8yjGiCf7oMeXK)nDXU2WXOh6lGg)}! zvXd++_>DE0LINakHWC>4fvwkSyY;HvR*f(Iqqfw~fO49ZnW_*v1C?NrXE}kVU$9jG zaFlG7p6bSW?l`(RTNOq{^-(0q?B=X8YefPiKmsH{0wh2JBtQZrKmsH{0wh2JBtQZr zKmsH{0wh2JBtQZrKmsH{0wl1B3GDgRPAeCWyJr^Oo%!#{{7*NsS29S6)Y}@R7v-^W zl24b$;YaFsTgN!pyKQhnI8YUxy%~|4hPMzt7 znpG+wX?B(LN>XcD75&W|I(Ovs)-F1|#cj#bdXAmxYTH#Ruv*$G*|vDn;MitwfNrUR zrX{Vdp|s<_oxXbJ+-$pLHe5kxTRhyfTi_YhKmT~g#SbbqA(?TAFiMpb;^K_T2$p?3 zY?H`BGe)ZX!4=X~$QLqXK6In-q;MgrOQZdNd^#IuS1+upmrPmuI&)5Ls$-GsQPGH3 z_H9tys{YeXtfA)CzKHx`=N@+a zY^}u#QG^WA3hC9_xo*(0N=r~yp@csltIpMJ;lYn}+@iYU1cSroWNS=|bl!ldO-%z0 zo%gPETye}GFPyR3trOBdrpBG$RhvD(u};m=!Hz}19iD?EpJxg^5z>P`{O#euj`4vg z`Zq%FY}e>%=_R<#Ms5=#E%I)17eCl>YcNyI3lSWctr!_jAgSUmAgkSY*z>D}O~V=* z*@$tv)xFU)^VU>|FIhvq4f0xLvcCp~s(MNE<zC^b<^=Fe`gy|{^ z*0I`!qI9bBMpey9Eg3N_X{}JwDc9I zm%VkQJ3riUUA3Bx087S6jo-jvN#?G@4HD~!7vw4=#zo1_^1PaOdef_ zaS|m_bWFxcUleKYH_BH^6#As~!-?+`wY}f<$=Nh_m7_)so648Repf9Q{uJU3+{E

gm5B97`>UKeI#|>N_8!PmP^he`9Iez_J{r#$qK3VpC@<_)u z+@cvTetX9iZ@*8jN1xzO-TGNo>_YU;1RIJendO-R2^&-0-|%bJg=~stx;O^Y!*L$H}Jal(Vf* zl3QEtf^5Cw$;`(cLVuqmHs0^c43*qE$G*>dAE#rPUWmWg#S`V@YA(nd>Ag5Muq^uC z&-Eml%hjC3y27RBKC{(!MEV$1BjbIAh{Pe$M!aK@#uolFoL&#sAs&T#Ofz zw^%e*PrI+>Dw{5Ae9H|#&5Cxr-pCTGXP{y^VJ@r4!;BYaBJo4GqP22dnCiqX2%kT( zK8>iyu4p;a@uz9U#FcT2M^e31E2BypN0m5r{ifB)thYv-f*k3r3w6b&r)RyI;f@SO zSjpcmHG!>jc;p0PCmna&D0>Jc5;2^`$Ll&9_|{UKNFL|x>MTXn?1kPZUby3gCM~}41OU>F4rQ3Ge*dH7n!oVEEyDbMhIprQnPd?L|F8N zZi=gro!BC-6I^=?W1UGE1|wN-5)CW2icxO+r?aWD$P>qibcu^@>bN0VX_t3z#XCg}C2{=a#2CFH8B=A3E%pNoyB0lx5)c=g7*rDL8n^A=+G>ie z(yk6`$c3J`1juUKyu>Wn)%H?SQSwB6a%G)KmQ6((BLxOhd~qx~VW+UtJ)`)mwF`}{ z?anFA>#H}%RwWPlnMAp#z$00+1zL_*wN{ovL>bFO!sxjMPRPT>a^!%M3rC4L?iRUb z5V9@?A0dlmxJ=?BTYH=QXvg)J9T%=@#iw?*+*X5^FcUW~KF(v)*dCLygyXTsUlMSN zj<^ceG&^xX4k-Y~@dHRdDFs3h%jv?fQrlGO$0V#(@HSL91FN$_hF z5{wc_SdqD|w#!;Z2BePYbbpUl`{z}vV=b2{>8Mysb-Ea9Y;_u!5OaCDVl(jWcAH^W zW^m)hiStBI`XnOqWP|L&;}{nTalbnoC&9)!oOj{k&`Q`HaWn!3e_Dox1f#t;seX5P zfAq;{r(D_`Qqh#fRf*kMhKtIxQ&Blw>qw5R?)JW_he#NuTr1H6B+wse`u=g79rc#^?Ocs zQukT{bs%R(H75MwNf(hU27A8G>TmvrqEo@HtIgob!?TwYD`m?{Yf&x_%T>-eKKs&g zJoK7u;H9`~?U(fKaC^VDPVLaSok|EDU}cqRY2Reo4vj#=CjAM#ZgPV!ZnZTU z5H;L^1Grd#E8&zDkMqWbWK4jOhGHa3{+;S(3ZKMOU=i3ONYNd5$q=QelI`13oLA(}V8N;US~& z=e{kRo>peaj3jDOCE4F9deAVr9y%ERl~D=HL*)Z@Wx-t|>HY5=G^H?kySYQx*b(5$ z^lOzQJHymsgl=~4Q97o^Ns@E8AE}M&f?T6)%Vn+A_;?aenxqeVL}GP$f4m>&_hKMo zg3NU@D_h%pUMJN@r&OH_yDqBUk#mz}HJR#37q!?<;UfEP!6m;acF}p)h2y@-&9@r3vg1jLV@Z!3 zSN!qB;mFVdY8iSsk2)~&+WzMzFYf=Y8*rhrv@|#LT6JUEm;L}wT-~438`N?<>EBiU z@$!LJIK5Hz+EJ4}r~HDTH#$0sak4o2f)|Xx?!b?X-*Cf=U;CQN|MaGhz9s(VoBA() z%Xpgh_xC4Q+0r#Gd3mc%!J#BSo}|VcQX|IrytRE2^bQ|Be9e`U*Ie`5R~nT}PtX6u zVe_UWo%nw2`p!8$SQI^dZ1mWk>zv-GIsAH)j2<&ka+=S^&kdqqq))zk&kg3nAGzkp z;R~0Zyz=?upSUr({Q2Y3BMP0;YCAT+-j0@^xeINPZ;N}pQ$6ZDgd~ojY^&VwBK*7V z5B`1b<}qUOn2e-UIT76#{(kem`&`^_tF+Fd;LruFHgA)H@@vxJFUBW&Not@j>p}Xzk^x)-75B92D>AFB-a{p zM$o5ydf&fhdf|O3?}?4np!{jMA`$2Hl`6deb|Urel7TQ%Kks~{-cvdx(LMhfzeo~V zf1ipdZw*)a-<{U;gZdb+_Dj`k5Q^u0de5gaz1wG8etbuz zMKLnU=}A7PzuoI8{Xv(m%ri!mg`L}$y&_MM#a+PAYJhQ``QN z*dpef2rND)Gap{&aOQ^;>$aJw3%rYU$Bi&qPC?ehWh(C4&Ole=gG+q3#l|_U{B3=W zRBbXLJo#$NU&@HA_N!`lY3g(&ty^6AKd)m;Oe0%Sql6l{(<;jsy6A*7BpC$c0RnABl8{`zNDK&M6I-wqgsdVL3+&=zBj2XPHOFt4prC7A$k<5B?vJmr53s4i6IdrISz_QG4+dkNEisD`EsnlIFs)LB2}FNzpHA+=VcqA#E_yI?`^IgB1F1 zo`c^#?!1RPYl~3P_#W33vSas^gF>Qnxp5N|=-0X$^peG9T&=R|Lvv2qEXs+n{2vqg zaJvwWF?i(HRMlJK8I-17LN{&p+`fj^ggxBzwU}jq7PoWZz|8wrS;R2IXbJdvOr|h6 z>+|`cfkf}ps3gyWrL&mkcDNiVj$7ARvwdRt8fc|fW2^0A)DN3DreyiL$J=>Pr)|N$ z9ZBB6B(||ts&7sW_TnD9mZV7IW0Z3coo$D(v#Nk?OI6GdVohOTY;0zv~=+!-v z4nd{`&-Jht*|`e$Ax5F9MZZhj#Vvmyzp}x)6goub$9Su(!oO89?n=dKHnxbvmDQq~ z)DX1j%~+YTd#Vd@jFz&6@0`UJ$m8=%wg&^^9yhQ?PL3Qy2bqyc8DY`KRQdg?B$|u( z>`YaU#u)*EUE(hOpB*;@ENyCJpvVBh5RrWrULRKP$kSKuE0Y9b6(`#f2Tz+?_}X_= zHiM}d*RvMmKt3wP!={T+lMH=P85cWgf_F&BJUI)EnS~EuHDlx18KvGK>Rss0{r=7x zrID>Xr{oTn+>Vm1nh=bxUyx{Ju>uYWYVW+?hqu{2^v_Ophl+HfhNMTKCi%Rx@Q}&Q z=-HRxn6BcHbXLnyu=|a+$}X1ols_3JxmC`+<;iF?|wblQ-3 zLUP7xKPD7;Y7Rj!z$GMNeTWNh^pXq+U^6aVWxk}1f)k(`59u|_tH36q{*QZ zlh?`nClLFTvg&qx-7k|NPVVCG#o<3qQJz8WZgCg?`Wjmj8_ZIDY8+D(TqNjY2^rbQ z%VjP*VQCE`2@cn2Tf^J|GDLnS#ZjJvK>{WhM$^tT=G=aTaID%zgBH+?-G0+8DU z;>xeGN3KxEu9Qnm>>lW|ZgJ;zJWc`u4Ltbdm?a*&U0j4p&Dp)tkXFfzi$xeP&c%7J z;D`~sd%@WC(KG4mbuUJW+P8S#ByPtj76JIR3PWO>+*p?1=+KL$!&svpO z@8&=@o|Cw8jIHuLB;!Qft=77LkGY5v&BV^T?gVWYhb&!yeCp)obN0K`+wJ^}QZJH| zxMV?ku&hVS!uxPcnOC@)Pm>dnb(@P`({YRRoMerZb{2BqN1e=VbOJAt(#DeG*05 zfUb^vfgb;HbWD{nU8(V4*E|=z`+5h=u}Jj$pa9p?Co$2F@u;^-@C^PCGU5~&Cks2{ z%ln3g)DNqPLs4@6(C>a|cmgNhQ-7|moX|7suBa?WlAW)+Bi`Ag_MtnkfCc<_i|hP- zzr8w^_d2LUI#xY6^TF{~;f^m>GpOtOG;XipQc)-khfYS=M8Sx$n_@bvoApX1= zD(R_YL}`t9e>(ZTU)-PUQis0nO7(nQF5f%zBK2bRAJZ2^?;1|Ve`e;w=Oyo3f{FRt z-#z@^J||d)uuu+P^R59fuE>E<60J zk=ZM*Sa|!;j`=_S#792*3kQ!r_Tbl-KXK!qKJY8Q@FRcy)EjU4`kUYRxu+hw>CgWC zvFH8#&wczo$%(t}{?soxwbr8gcKnVRaf9h)!T1z+g2PTQ`#72~A0=MArl zN4M!C=k@-F7%xNV>$x#5U3Z=?A93RZ6V&x@{BV3=&%nU7*Y#qY^lsaCOvcByZIKqg zFIqT!V@ab=N>}Jov}Z^9;`ja9^ZO3={oujx{^93e|3iZh{@joJ|4$vbrT=BOeeUbe zy6LI+|Mv49`?-$~E!ey6UjD?#_k8i6ezIIDU2#=c^~sJqJM9y-JodA#ylZ1_pH1h7 z=k}@PrBXfp>1n*P11~zU=?R<&V~Y=b9UU1PTVBS)-(&Cnt6l%pKhZxi*gvPHdhoUm zyyIhO={e7Fm-_P^*MHMyjDDx%sq`*vP8 zm3$2PJJnQbAV<3M#a5TN9Y;EC$aTtII9dDt6FINmU$iF|4!91CZ-o9e=#v}O3CVY< zyf;PkuXSHM;u6t0^hoAkJ8#j2YG|Lb=;7_^O|QT86^Ys&zhQpn^?Pqjeg@}k_^}UM z7>E!_imeeNy+>-l*K8(@RTOb#*F<)S&?!#pSII-?9AU!RhOtdhYbV z^1$_nT%R1edimg!%L8KrPab^Y$)gWE&_#W+=}somt#FncFvukX$iHd`_KG z)+jZWjgzI}_QnZL2acz>LYY+quroG*K2g0GC%7(=aiXM8X4Tbdw0C+;P4|xW^p*zk zuuRvu^0qZJ#r27r-Htv1q^wWW>^`MVr8pGieNy+jq*1v?r|0LFkIR|YA@oU_$j^9u z$3QQ}$@19rfEw_9a!6f$>R_+JIO#pu^W@RN2fCfp=Np&f?WOO7p2FSEZgXiLW`>P*AJk$$ zzWq{V#P63_wZloVg&gZ0-MKT?FKQ(B{6UuQzHI&D{|b4Yv3Qjz9)sRI^0^KQY2D#R z*R6LuOlHtOW+ai=Nvzwh+=yI0x$BP+&$=$jrIk=F>efKd8lJ0fkBM%sZgLg5sHt^l zO`pW-f_zS>MX;W+)o}{`Vi))aVUW;;GgDKtw)AUFb=FCt$i0qPT}O5nigx_%IyTxC zZ21F8CN$p1o?jylS-i01q7ueOXU|gvl@)&VD5`68MUE{YNb_Iu>#(|}n9utAiiw>2 zI%pHnz#zeYgl8VzSMh~BNj8Qef8#x#c!?RDf{t4W;qpx=gSdRE<~fsx^AlxJ*z&IR zcLBE1R9n%-qjrdRK}NnR)#+gmH)=68@Nwm7GW1FVfB6`qI2<8qsEiMy2hRNjHXSoO*MjoQ1#A&ti&=>$gj8H^Pp0q}HNY%(34jiA)ZuS1mQ zCD|z4j<-g}QFJWTE|0<1O5(VYEyCV+k*?Sz?`_tM>Pfp=*HlM1K&xxk&=ttW7;~-gvMkE+MO~l;tLanU!AZvnJv$M*p6zel&oQmu@uE$wO}N< zJVg~`8@b?a>$qA$M zPBVywsPTwew5S;paEDmC{s|S06YKgm!55m@FX@D&?(qAs+~{@yt8+5n$c|lf(jnp^ zi(jJm(-VGQ*z8TqC*{`&(l{-@o`jc<~1MabNigRLplr>jA{ zwlvll0`uufq+h1W+wl-m*=j^$w?)9Yy{hl?Dm^A)IbrTLcd>h}VIx}=#)*^>XIFZK z@^F}ko5!9XSp>>u9M^wNZC8iCAJ3|~@qk6Dxiirs4n0xi1b&;RbwyyH-gL4tEi2i& zWtCHZS~XdoEsZFMgFd9 zHo7tH)}l;cR*v!5taS22A1Zm8GQH)g9=wC@^^t!4tFE}y=qtDD*vNIwWtBrZUJ7yY zP&&SC2z`Pfv+~?}rTr}?8TkChSJ=8DhDs{wsW<(X7SLBJ`abnD&pObfU-{nBCvUxD zmwnp2x~G2@IWH+M98>BcFt>n7FMRdlis+KfMIYSghV;l~1O@`uyCvJ) zaiUOSX#u|tqM}>=@)I|F`@uIHeeC=%ef77;{{79LxbttH^@(%z&cEOJzE^$rvPbj# za(AZ5R}a1YPk!+3xx1e=bjNwS3)Z?IdhW4}Zban!BpSkSK%cCbYleKE^!~v2eCCE* zc0GRdH!t|=SO357e0=%0?)=}s^6~9ge%p`Tx$vd<+a4VZ_1v@2_l1{THooodJMLbJ zOYeG5kav$i@B8?|EEiHWper?w8 zbp10uJqZ8t$7|ENBKCV5--@G0TPb6C`p9>mI(7Z^>J`hsd)M^?&qSXrojNr=jXo({ z*ZMyBj(M9I*VZxg$pc;5C+fD^_HIP1 zEEnWB-^I_)`+Ms(g&a~l=S6U>D$D)Q8f1P?% z)=3ufom6j_n}1V{p{|KU-+QK;GCe&Yza!xuL0MkzRdN)O-;cnWBFLAQ@e2h@&zSyb z<@YY84K6W}s^nJwxm|cX8Qk#oC&JIU<$=0o9SMDcv#aIhuP+~Qeew#dfs}RgPc1LI zKKZ~0f*Ca}ziA-4qv(&P=i=@Olso@@;dO$LkCUZSgE))&co-)bAz_>>-~Y8c^KmkL z)Zc}~4;NsZZ2y;as>WtAGjqBsv$TBw{q@S4p1#FNxbiS&fL3uceSfs z8#}NUA8F^zIdjh3JLk;IoqO-h9VT8m!K%9Fd&jios+v3QL~4P@w*f1RH};9WQ^6~F zzGtbsZ>i0+GpRM-d}+>G)gP9}w*fO6pQ#s&KYhabpJN#pG>#W}Z1P>ye=jn-myP^+KQSZJ4!quAsEq3yCl z{vrp5h_+&rdNNQWam{VTrf6cs4*E76agi!j6tml_ndoYiVv0$}_FF_xFarU27O)c# zKx)lGj!wbqK0+!d1P}w*kfR+Rto(4BMQEqckcoH)8H2)1dW4FN zrYojfAQ@^Zk17c*q=N|bpo>Kfp<)&+?NEXRO{n&eHld@#}=9Jj!63mmt=aSI%`z;O#4x4>}=9Jj!63mmt=aSI%`z;O$_%q+0F z<-T)CjZ=2q&q>0ObyocB5D$s%ekJbbtQ__)A-Sr2g$~lc72wJmYDx0YNNSJtWO9rs zcUh3ny;6e~BG2I~A@EwS-?(3qArkxZj45v66h?B-{loOiJh9)(N$gjGmmgJm>}NuP zVY;IOxtobgkXICn@%z;#1MJ;D%-^hg%;qCMl~>^6*)WH%h@iK4bcz{1ho6gNrz3HS zTA65ACjioTQb}cnAsK#fEzn&k&z$h!O_Do}z3kCrbH;9vt!gKG7Pg`03F(`OpW8Zyrj!l?s>RleYXpbk_-;rUOOxLgiSb9Va;9xx*}t zZ=|kMkwQ!Q79fMqJwHcLt+5P@Dz_o~Y0YuO!1AIN&4kMEj1d~4cN@eA6uHAChb;sX zvPdRIkp9Cq3S+DcS(glCu@Y2UscW~r7z|@LT_c^g1Ik)DX&gm-;pd^rQ&9{kjb9C5 z+~pbOPzDm87!>&K5I2khvB`;5<7-e5izS@!YwZ>bt)Z2uu>!ueU0^^RSQ4IN+b+yR zy9Ry@61^;ZI~SVU7~4cb$1hZlA*cVpwkVVd(`_XVuk84+zv2{5XA_zv7=4B%kX8@| zY!^l)juhhviv@f_TO(2n>~5QL)}BhAgK2WYJS@l9qeH_`6oYXbKHk|Y{Gbx}>NmE213-}}i zJIQfSv#Mo=7Z!G6C>J}t?DOpw$z#L8vewl2Ys3m zpEfG7TVeFs>=Yvi;HzDVK8a3$8hw|s>CvztrpeN1E(MKomjb1dC9&Qe9&)sbO4h~M zMRmM5kW1dxMkzGONW(TzhO01DXQCaGfZYwH+q!Ld#x?avyr>G|ws%4U;l&Fe;hY-K zE|In!vReKM@#ZeD9NHof^M=Q8w6OhDH92c0Ijx$|>9O=vtx5n}Hv_Wea+|JL#vqh% z5qpa{lKUk@DT(Ci2dLI@k63y=G2uyEM6^pX&O5k~5gWiP8;yTB@b%VZG$cYsN7tkz zdM6*lfeRspKQToq219BAzo4-pe8s@veMh6HN*LHJ3j7Qu%7B5@riA?h|b)*01Dmh>f2=g`f)Pv#^sK zo)WBZ$z`jDgce<0XM_TEnTPB+W4W|-=_)ofQCWqrJP@7y%zA`M82kZD???u{k-^qW z1b8)NIFdJ0B29FHeBzp*+e5G9pNTKny7>8biM|5p%x2}CI|i-I^h6*@eO=_mFQ}Nq z$@J~sMZsy33M;y}mrps`6h)pdEyj@S96~ZV1ZWIvgk=l*9Crd~4ECO!q9&u0o_>`l zHzYBfSS4oBcY%HGKX_sYS!7t8GqbVyhbI(Um67)^fe?ISqO$8fv7UU=`~1h@lTwmw z4*}CV|47j@McD&`lGpNJgP-4bOEN8QD7d{dQ{YeAW(1MFo3Bp}Z+_ha$qQEA?Jd1~ z^(W8Wx%1WUe8UG1^&~&ALin4LJ{n3Fj`WIwHGk5osE!L8+JTRW%Cb)!vAlQw<3*KM zC*;W|j>z{u{|L4yE3RXoEU`X;UOo?>xQT*HjF3l}Rso0-=QWm4Leicg594>r&8 zH<@d4kN5;03*ezo&plC`?#Dc{QSeftoO}0I4@KGu#42qn)QLCtPiS4fwtP~_hJ7N+ z(e5lrv-`)C%hXOHK6wZ}nUz1QWB{K;`!4WbVLn;0q+*Mv5xaj$eKPG+0^a!8RQhAe z6)Wfo6=*jjLfSq(%vAXPAmj!>(`^UjD?oQ37}pJajPSPNz!xwRX%qHEVHzw>r?giF z^fvs4d~Mn7{v{aZk}WF$Ly=G9b=q993O>0;n3cn>$Xq8Zz0J-b5<3FEFU+7z^1#rm z_{7T5Fw9&*nP2y4eg~yfK17563iHXDifwH94;e9&wq=Kd?uL z4I4!6jr$MwW89U?jfnX;?w7T|GIfk)57#l;CTDp+6WFY6pNy!*GKWvjCZCkylbp!C zZANG>+#YUk|wZ3`rO_G7@aSx1=T% zCpe+$z7Bb1%Xz=W2AGUtPO)rb5p7b<5b$Nu%7@sQi_p*s*EJ>{4fR8Ozna7Wbzr2b9^V|1VmEMs_=?uXaNM!%u#aPW*Q%c2yH7OlQ zto`?&-)ZBHks-uQj%<_pMKDPq5>?PO){l`Vs@6EU`kblCY#5{N6~1&pYB6>N zBVx|FfI}%3Xm(j;ie<>`WZe7iHqSn+kt&pL$46lWZy;;Jd}``FF*Saqs0@OrrlNDO zk8~&r9T~(7{1G!)ioK;91DVDCw0+)$kZ2uP7&X2}PN*J7gjMfPH4A$->VP^pA+h|18RO3OEyu!@N0Wld*kpqT?G|SkR1>}z&xSHKW z&LS-$V*;!Ht$9I$x>&n}DiHUSjfCc7O!gz-Y2OabuIKxPNXSvWLyeGH;9bUd{v_LV3-sxIEU~gNGJx7KAiRO8U?1=RuN!hfexEN zNY`ULv10Q=RO64rS|H;ND$E=5!X$sJ(hQ@y-N*z5)E^Smo)NP;I%xAd5=tmrOsdKN z)Kc3gNumIRCELgts=WnC&4iZJ8AaGY4+#+Sy(09%1CWSH;7T)OkOpdqxX?k0q>PL# zK?;4B08UC-(r86mC=DyLl#gpAF;Tm=?+P+7guRk1V4NUvtza5K0ltH(GS={PL^xM;AsUncoacFF*qnAZ$vGgD!`_+SJCQp@#BR?ugK10$=xl zvD0D@H=hvEC57p*1P*_##pO5$lxKK^Dz{@}eXZvbIVM^Q<_nAam2p`5QCgO#GoItn7#eUT9S4hr|>%5ya&Cg3VOFsamImxs~yj)7J6rLHs? z%%mr;(l}R)2!9CZNjw)oLomWkk?r-hltx!39!3ZS!VB+JDW%h)f3fu^no3tSK9OWv z!covnz+{}tHC8!^K#aOFF$`aI3yR@MfCj1o$}{khf}wH$Z(cJr$Q;KhIA2Gyb`^^# zO|$HAQv7KNn@dF9GCDn6^ZBD)0z<=8+~fsTuF2lX;K`PS1<3|aP?YQT__nL_vtEH* zMcLgY(=)p0$pNfFJqZFu$^x#yaYT_^5-;dJuZ{AUHe?!$L@aNnAaWb}B!9{@5?-EM zlfGhDJ{h*mR|gF=4KJQPOd5T{Q7LY1Ao9eCG-4*>5%m7+BIPig7TDDi#Hq%J3TYR; z`vBR_C0;TCF|sPI5Tu}`H-&1S>%)UGL>3rRie7w*Tgaq1Z)E9Q)_pK_v z|C27`&bEuw{8bho>gk#lj<^Bh>kks*04pDCRti%|Fcig;bb~*a;slWvU}+8HVq(h8 zKKc~cEuWt843?OpLXVIcA{=_eEUeKXT0A@YAA#AnjDncOpFg!A27dY$F_pkVJUkq;c{B9LP5 z^v3DoP2baX2o{#JmUsgb|xz|+xB_4>64+Mices>Dqu=>dF$5Z zJ}LV@@;7c&Sxno8Pv%LNeZo16jId9z^r76vK0)KkT@9bd(I@@qSFP3})}~LCqI%qg z3D_?*@JTLr@E|Q(sR6VCA%0XQpCl%?!tMkW35t!pKS%9^`B?eL7on>IpX9imROKs* zof>g&ZTrmI^ob~iKAErUyUOKkwz*I62pN5s%H|G2zx+hS#xBL?a}}SI*(YVRlc4X~ zEDlB2N48y_m#tvmt6QHMuTvCC_^*d721%B#>REaWParWRWgO|WHcsHl72Th#2>IbU zNAPRb;Dz~&CHz4Tj~ziv8UT!m!3oAi|0LzE8`zc|_yQ)l(7Lh_{9KXsu4Rk^0>=n? zpKVr{Ybxs(4c!NbZBxZ_hw(xj(fV;G(=ZHNBIGt+uh=7YjO?cMjhkpaBk{v^j=_4y z1&76yEpL^ZCV%nq@Ti6H4!!#%)}JcUI>$}dj1=LMp3Jt9Jg`XPcsO*=g8Vv{(ZBg< zo%`r07GRe#a^gjf)m$;kDrdI$(T#ScKdPoKjE#<#%d_RKvPjHk5<-^cFWfl?)$QB2 z_Tvbt167TA@<|NAU+lT?VU-ulssf)xuFsSMF3cHRpDET(hIAb-mmgxEl(CM!{JP(T z+9>&C`)D~eALfynkE>7CzA-H0i^bGV#Quft;c(l@Z29S@OXQQwc$i)my{F8x)pImV^dA30W4SbsSzhS-tuo`{W@wdA9uUTdx+TGzy<=MYk5|yXNES zlU3K%8n8+wHR719W7jeIRUGo`Fkk2~Pzv<0Z{q~?yZ=6*Z1rgy88 zFZEKG9dqF1%NVObFWlb|`!#x$--8yrspLf(H1=_1EZQH_^HE>Mfw%0cW@mT5;uI6? zmsnZP2!0VML=zA;gij%=!k0a?J`v9vC#+m`f5*H6TZl;x5g>nn#J-G^_!isV{T5H( zZ1s4*M-sq(jhj5k{j02FKQf}xFC1;5Zw#ZekSfVJ#e0sU%ILp@6AEZ^z zFWYqN&v@36om^cdKC(;}*Pp1izF5r4z>oT!eBNnJ2Au) znP1edle`rVeT5>L*2$4WQ^M08T}iw#BSB# zObZ}FDHgRo+Mr;*A@A8k2Zvn0EMYmLQ*nfYN*5*fwAp^xE4_92^0m?Vvr!IlfqiK5=Idv zaHvs<3GftY8PXi0RdXAVvnQv(Di{p~qwg!pqQYsl_C50G6iC0d*_qNxK^R5#sU+D> z!Gf3onp6WKAq|-!2;d=wz69 zm+`tDbi8|$27_H+x~xDI05J^-fUA_`h#DMn5E+6`P2gVUcYH8#a6u7Jz$l>q@Rn)c z$KaOlRM2N>3_r)v+iNnT&}1U1Ve*e5Qi8>Ksn+tOi}9^1Zo+yUTr#v!NDXWkv=3%X z7`li+J0+G2M=YBa-R^+nk-16COG>wBIKuZN^iUdU@DZ(OaWO3RBsxer1Cf}3|AFQO zF-S6G8yL(neD$U%(YCvys0Ay=aUY$%5UZp!Gf5s}^NBQa2y|H}5_lQwUGWJ+Tt{q^ zJ(vNma76gqsv{!@xt0Xo>d*zu@z8i(7D!;(sXsD@cwE4_zgbDxCP-vkI${Yq2Tz)) zr!fn4DlCZUBDyN&uR}Gb>F%ZVWMl%$0(;cdIY$a*58_L)TNq)my0~PoBJc>c6$@R2 z$SGQmq+Of`mQ8?DGFswhR#9p^VAWmim16>8nnkJZquSDSq9LSURay?><*Dx(6fh+! zH2!NrhvX2|e~)(2J{fn2U@JUg>7L>1KG%ZaK%Qb14^xL+_jc`F#QZTVa?D&M;u;?deMnYz2i?~~#i_wH-LD~`Tl7nc$Mbz1|Zk=9AEUMS+l1eOlBDu^*wB0yBD0SLK*2XR6{ia3LbCXO){}Eb(v=4pEV+5VRF~fpTWIxI}1liqh~G*-!@h zzC>K$M4l1dxHQJFElX_DDFft)ZbCwc0`9O08)26WQQU%irZ{_rpI-LJCpKs0_Hj3tb;UK8@_u(auQwIY4kY+WYd*{58wU~ ztc2*Bp~w0gv)M0Vvu2vN8WWIBzax=1R7B(C$(ClfbV|$+29zN-FiTK6Y!x;e&l`Bu zdyRMc$yaPxdM-920`j!|ASg(>AzDB*$HI%B*{C@++16IzO^zce66&VR=~J$(Il@ zH{C>-+KGi5@(u*x4nmO2Cjy^1tKKwlXwAk|8-MV#Lsy>nuJ>Iq{n>pD?#v-R4hU>OOqvg)hHx>p%Txm|y4Po>w(1L)9n3nEdYD`4SM; zm=Zs4Znz=v3GazXz6smOYj=L=(3jo(T37@g{?G*< zc+L60cg8&rJ-qg94`1;&Ys%-{bKS4s`?kIFXHSbaFP-fQeDa1R17G&tsl*Apc5b*} z>qj>J{cqiJ+d%TKx*q<(3t#@i&cBUO-?a?uXBH_FYX<;wf_ZwEBZzvB|tys70W zhrS4L3!m`*KDmp<*4+NbfB2}J6+g{ngm|{8Pv)~vK8Y14&Y zamVSdd&hOWp3&X6Ll7-CVI~i)HNPmZbMmIDQYAe5xK6fkB;VkXJOL*;CmDH z+K!cZGzbv6caQ!Wj_~dI|A3a5T9*>fdrv>z#&H%N;AP559Bg@FN8l4!k$p0c4?ncZ ze|U@7UoO8pw@@zh$yw}+`FZw9|DA6mpUBOjPsDR^^NIYGg|?{U9Hvh)Sb9h~_yeQ= zJ^N&JEL)drmHc+s*{JceRYn*at#2nIl!8wcP&>)Z{|DmSPRi70?h3U!AFplDXVjJI zFn#hXW%YivlQZBG^j)oeA~$1`a_q-gcT|v}Pw=r7KzV+YaQ~fm?!RkjXn0H5PA(Db zla}p~^5_gW@ei7vCtt8}v98BS4Gm1(YKbp`pyRF!^Oqn2JSfAuM8y<>q{e<6m=MhC z8AZ6Cqx*N2^@CI@YWVr`UwbI>nH_UvWZp zJ>#%27*kbgMKrB*R6z2*2pICpVw;aFS_1@TBp~^fyQzPSQjp@)&+Gf$nFIpdji9bRsJB-k5J?BD}h&3g{5mC5Pl3A~q*C zWW@j{pI@vH=ryQ+03gO878q!bE*j9R(uUB~6$|BwgM2D`F(Qul0pMDPVs|?HVg4Vo zlw&f}@Nk{U?7y+S^A78wt01pi>xA-+C2LX@$<%Q82;gX*yvJEkdiY~TM8`$N;oH$L zp~G?d&knl)`mi;s3JaS0asoEl{u$)}^D-ia^%bTJ+xP#jWV z!WdGhZ)pLF(jC0DuZN)D#3W)`-P5_8t|tS!75y?hZiAvq%bIj&&ezB z8rn-+A#{m|!SoQm8CcvVR1&@2tw}Tn2Ti3LN0GzQXkauT>57YSKH3;LD4&ef_~NzWR2l~CSGJ+qb8aR=F+7<98ZCcg0TcX`I4mzIKb}~Q<@?U zeku3`2XkS6`ksoN1ZiuB)|7W}_u^~gY6&tvu>1!N%VH{A19zAqs)~Y24$RAdxt%C# zHz7zB#0+DEC5`}v?IgtDE1^SONP<=+r%)6E!(PzcVz;3cdnus|9pg4!)3w58we}ilm6qu#ZQBZ1OcTb1dA%4fNCDx%ZUR2q zP*6pMA?>1|`ncb6#pk5M~?nlR!#!dEl>#*|CRTFeLfbSS# zI2Mm!#l_9ap#&8aVE_fAu$z)G*sMWIa*@UlaI*-%)P!-7!S#ghFEpiOK`CHbg$fjK z7y1Z^SV+(5$n*7HsoNm`8L4soqAaK0C6;O-Cx*t|DUlIff<8`hA=)qHI5#zpZc~d1 zP%(iMU(>80m@`c;JNyysW}|la5#efVP z(pOTjK9j;%-o)^j!1&n1N-gOPfJVv*6P_5s0o3W_cIOl^?oJGeS6iJpgexm^-0Dk% zA+N#n5xSyN<+PoHeG;P~i&kWTF>$H@lN%+j@gAU!{Xz)k?Xap8_!6n=8catWf+MyG zGOiR?T`?{O`y?8a;}7AX%b5cG)Bw6NgBCI(*JY*bGrpL_Nv*(;c=FOS(NMy}!~pv+ zNMoR}Z&H-T3|6ZR3)M5?kbmBlsFAjY*39D&R>NLb!@d$HA&nNV)I$;Z;=ke|>0r+p zI9~j=D>d#+*Jpe&_`o{&3RfcDL)$}cLUYR-#wd$M5s6{p7;w!t0V%Pp>Uz+f4kv%U zX$jyAq>bUH@uTiVQ>0CBids&O(8AvqfJQ|gNgP+#DM}>Ds zNo^<=g(#G8GaBNLfi|N0F1f|wIw1LkiA7FQahgLl7U0mMs0f%a9!4y7;5#%Xt%vYk z5Ha4epXXMCtoC8ZmKBl)YvdVIKt_nqpp)Dz9C|E=6Tnpp-6!M(uY2@qhg2L3|Ab=# zy_3xff>mm67wVv!@G@C!f}BZsS)ZGY)o@IpX^g>@2d1@*tQ3!Ahcz1xk9jkJl&~fS zg&xqSC8Pmh$1;4>L%4Ef(wL9^?K*?c9SFTaxp`dNXT9}qdZ;g%7%5>b7*;p>@Uilo z4eNz?yTTxQw?1_)H{rZCyDrQx1~{14wy-24c`=z)e#$pu#)X-bC)eXGD=zm2!iG$2 z1VU>JBM}8S&L{X5(06`#U-zLQ7hBHPfu?#LZF0Bat7u-zDdOe&X^Pgu7uGx7X%B;R zsWNAIz0({64?@eBx9{$#aPT&(@>l4Bz-%VpP^2tGI{_*nR?3)k$xcks+ zUpw#{VgBSqifb>aeGjcEfb;KObMEqFYWeiq4L3aa(?bv5DgM7RKk>^Koc_8$6#ww4 zXFqa!|J{dnZrt_3pFKAH$7_{3RfeX@jU@=3Dr zkJ;gD>d*^I51svi&F>8J4}G%P^T;Qa@!OfdbIa1@eW|W{e)9c${_~4}_rc#U&VJt6 za=`;X%0K^=4bN`;+19(SUb^vBAN;dlEIfVDuAMtKuD<<8Yp>h5YsZ>HJFnbv&9iUY z^}Ss?e`)7m{X%%0&d1K>$Epmu?QcB)tny_o=Zwz3zRdk6K1q8Z_x41hKX>)$*=N%_ zM!QC}A<3)@G$dqQ4(=hy$M>h-q4m$u&#u!1qYTMS~~hh>yx|gnxCIP=o~n3p#1de)t6nCNRq_4!jic$PL^;fKA>Wq8ah<{;0TU!j>cda z>lb-_<%+Sr($Km`!J`E2((!T6QomlZl6~hzR(z$|IpfBd$NUSiUB`%-MYNs~507bG zp_CzwF&SN-@kCL0SjdRm?hwoX#V9`*zA_dTBfFV@l`!cESFFEE%&a1Oy_k8&gzJHR zGCi?mi0D-pyW*7V^~~mr`-V<|9Ls}-oH!*sO6TKco0^s3)KjN_cVuf<*XZcI2hMzc zzWiMF>BJ+?H(29i*9=w0SF(~;+10BIV6E; z-@u|>f&Hu~{|FcJtMBx-&`7JY9y^d`-8IhDxon*JuEbptW7I@XJ@uPE*tqrJ!T$bF z{^Xn=pLN!ATc3X7FMr%%Jyo4g#BAzIPWkblCHmjo)F-)ey-%V`E_g3Tcmfxba_VWn z{P^hT{)E8T>hb>6fdkQ#q$|7g?3(?#%gXeOG$xSvLeqlea%W*$Cb7QNQW+WVXEN@{RC`DEI#AlD|Cbti;yT6HCs4W$K~cC$n3(I^xf9uki%A zWkKIXwq4jxW+S+NUAHr0se>8U)ze|YZaXfn50!PsTUe6yL z#oUf(byO_S`%5o2o9dwU#pYC_@2VOS1mEe@9<54MWA$pCN4xhQ;W;n37i^Z#f{T1J z!8$&Fu$U%6V#9L&qos@VN0TuvMhGeVNs@^PNHO@CBP>dI_kFaDF~jH6WA9gM&W-P2 zo0+~Dzb1#yAk2~@Z70X7d^0^Wn7jhd;7#TXc2*|e(@gMN157mbYPNj5l(c^&6B}^9 zco;=dEQ`=am}(ZZ7744iG|10X@~OtcECL+7T}IDkAxs7pBZr_gEB?1F;EN7@=uzEUB2Wc;84Kx-#LMJ3T(?@oe(Mx;~SKQ(As*z}(yt*#J zh-wmh*rxHvQ>ew@sjwOpCU^o0hPLg}^}^{E!H^8wa41aOpcxi6i@1bGx>xyv@*8mI z2T&Y}NgxA@8YZ)?dKh00v3OYXF{y|_*-#5n63P-d1U4?B1Az`%A~tZ+@4wihI88DL zF2hYyD{NACEv4-yGwuk;&@-HZ#$zQ&QUxqQnqvV!R%r13Z51cdJHR~XG`PR8+(FKv zDnS$K726JB1Zt@XN(q#JY=*>=d|A?zOl(aEfl?IIG&V38CJ~vm(O873{9zQs)>edJ zwIyB0W-tk)ZIn}eM%VLJ9Cc8t%;OhjIi@h6$aYQYgEUDXr zgTxGDAERPrr8p%fLGr#MDu`-e*^o!qT*Y-7A=x)7OB@CrVC?40J(4#9hQeRgCEMdi zYKj_w%}z}O&+{Fu`cmL}nh=4GS3BuDlS_3N!Gd~O&j{%d+q`Qj;yIjvP$Pn0?PGXO z41=J_2tOTYp|x;^P_z1>WE}9)d|Rcct?ERDKO3{5p}a!Ty7s|!o6-Xa#faoM0^B{~ zdg3Xih--nmF>Wa&q!3rYVMqh9BsTYC*74xD1&&+bxCM?|;J5{jTj00_j$7ck1&&+b zxCM?|;J5{jTj00_j$7ck1&&+bWoUt=_KnnGoLN#s*unlM7a>A8q%|G|M(Ht<^CRh2 z4`B^heRo+cuIz*Ixn9~I#Sxc;>7laS2L=10yj9~k?t;1Epo)obU z$~Uo33gutnhv^-R|M3XUT`kn9vgU$BStn$tlUA7Z$(4jKLeJ%^psG=dxe-!v+=dZ$ z=SEL#x=w46GF8ftc@ROo!m32XkpcONehI7YSVWuwymIE*!H7WyDd6%n$b=K4`NBdh z`Lr$ck%rL@SoH^+URYv41%8g%7`+e4Vyxb=Q+>ULMT= zHuwvxzOrfBA{%0g5hUnhP7TLY5l1;7UM!&BZB>luykE`2n$Q@24s|OolZXV97LZ|@ zKJ(>b(u2nQ6OAPL1zR+8jDiSgs`Z#N)MEv?4N!LU4Py;$CoL4w>!3qN8NrW_kFTi; zspwLJ3}OQ({nKF-1$Q46>1qrtt-0H0-XzRu>$4$Ye9C~dAP_VIyOjnd1wiK1A};`mI||N|`1}_+9pB%>XFrsy z(PR{LY_Wl^@3$(74g|EJh^8O_6-H_>)pWWT12hF>Y#t~DcC)k%DMjPYkX4;05o+%% z;LYKOZ$R4y!Es{(4TBtwx))0OC_#f3QYfu}V*)2U)NVm4^R>`lz=*IlDl0H5E(Q2m zlD$E3G$>C@;9df03Ji^31Hjq_x+DZ(8yCVn#XM5d8Z#cp-J&Uh^J@I;u@to!97D49 zI`HEH-XFJJ5>qP~bWLE|8XOr5cxWfMWRtuS;SK{r**;0qH=6?;lF+>1M+Yt=r8LFi zTFMvw)C`c&x4V7@DP4xx<6wvj!Jfm1T`8HwV*@9(d`_f;vU*s90~0R}OGpt>*>|g>2F_FpGL&kdgcQW+r-Vir z6QE6c+5^pE2zR4u8hm${mL&)Zd5IO<-5{aIpoO5i7j+U;@md3;5kH(3@75g-eOEyl zWiZ}ym5a_uD6%q{86T`yh#5@U9s*5q^6Z7a=%RE%yQPfNI1Ona;{r=twv)J=2=KXu32)DYBeqSj z%Z4mF4&mzGINVZj9fgt>u3vP;4HbROOpSEZ`$_yX{sc%uHc~~zv2Y(DZvs~mcg!jF zr5uT28$i1*eZP>DHGUG0SkV3^@pXF(<9Kf4k01qKyUz-2I~yA~Ve1hUMWWI=LJ9iU z)f_ZmLMn751!gA8HULKnBkslaLfHJrUv~ztt@io?)1zVFy)L~sA>i8;#zgr;;3zSH zJN)Q5P*P{ZNx$|Y&R^H+8YW$AiIJ|nld6?yM3LG1@N+adSP)4#0`MmR`6X;5HfkWs z9Bl3cPFx^y{b85H1R7*2jJ`tskPX^IZ5O65hV7#OBPNDf$^>3P-o6X};vac(rh$LJ zAbu7LA0gzT4OY&BbLi+`?N<-?^z$araOh#6#zou^hl~ZBcko?XL~(Ivx*Lci_F7Fu z9jr;G=Y-qqcdbayT`K?kC21HNU-NJwHUpms2e&x}8Rtz=Ny;DD(-E9$w2{nTnd>!t zBK-5}vh85fIkGu8d4r*9U18x3BKR3o^k$^EHAR-BKU=fePb9JcG&tUXdyVln zD>v8IhcA3SBjvc90^h*cl!xeHN9;@6+fx@wqUgL;>@nyl(QOq?cjY`Nt+S!`&kpze z^TrqfpL{%@e140{z6GQ~9uD!1$>%@2C%JEhck7Ay5=gNd^_y%f^BB{z9As-?>%I%- z`qq5(gSX#(=!aMC+WF44YxX_g-M#6iDbM>%!SmDkfz1Z)^RpTDt~oJojV zm%#<(6GQhe@Co%@q`3gDOmBWHxn=E+k6wA@^B=f;=dLwtlRw<@+AUjd#QsG4grB;7 z+U%PlpA?FpT~WMsdEgWAdw=(@cm2)3J@>u$Uo^3~Xzp0}jok%D>J-MBtB%>3R=;t( zsJ+e^Ij3AIjY4`?S0?wlIxxc{2rcXAGl>aT4 zJGCFXYnZvYC*G3#zz=8Zj@i&BnGAfA$h-w%IeGHXP@PT(lZl&-*~z!-lWX^*wm-ys z1;HmzY=7TuTRwRUyfOb=#V6a3Svh|G86UgxN}E18XXM{RsZ=g6FPDD^pJ11h%imXL zhKB8gdaW{~sh#j%PIXG1ORoKe!#($4ACiGFyHANAn(_$v*oOpfL;zO_|Mj?&SOGq; za6>sti^5oOposTn8{vxO~Aiys(9|O>)x?L5Ehy0{wTFa!u~10y2^bG{Ax}f zbbF9!c;6u8`*sjGj@1v38*1;+#T}>j4Q-<1&~Zb4=i{|)&ylDvYvSP0RHR(_HXsa>I}O7h`(3=+`;Wzv5nONpOi;wUxvf*N!j{@?A8B7c~^Gch=T{q z7)ueSy5GsjSy{Y)JM~l{<_}Uz2;`H@_Bic-;(RVF+u`Cw*H98W%PjCouAi#x_rBL| ze%Pc8mAqKYJWH4C^445#$*$3ZuSYwHR{ffGQk%8Yk6qAeS)ENepFh&`f39mge6s&V z`viU0D4tjq={(?-ty_1#@WNRK&k5RzV;`3x&9)P|52@>?;1k@dq>i*4FF(C2O}pom z9D^jLZPkO^puxuj+$3Wm6(m3}iZQr?)Iz9upqi8#@aS9UV%h5ny9dG)qMZmG@;en>nr_xd^*?o-99q&Aj3aAFv0WLf$dB3bO!93BU>XTsZcBPCV-JnaV z$karlHg43rVWxziAPrfSv^%6QwP)y|P##xiSn z9>&S>P-<~`x}3KIRKZPDkQlYKzJ_913N(I@91PAy;cZy~bd4~JbZ)TxlEXXqn!ZW1 zE@nyqP*a^Tsj0&1fF@oyX69i+9IH7<(3m&35bVN;V0pyC>`!$;GY=Pyv{pt1GKqBx^Dj6Bq2fp^g2DgNvKWRXY*-ccDm9*# z{J?Jfqx2#=6~Y?)0@vb6q6)-gkh&^N#w6vYfNQxnXcz@CsUd4fkS;t*O^I6UYuq14Dt4nQz+lR}zl475h1o`U#16cuIge>cmtiuvEtO`eCw4hNX6($Kg zQ%=@}ixiSIewc8NFeZ@R+p-{rC2WYOwICuDPQaq}QsJ?brIe@P2TTdZ>O@hoBBB;l z7>VM_L6Enn4U(jq)S^H!V^ZQatkr@yZUve5o;z>Ol04j>q3}KE5h0cp?PCo`b%M}UrE_EMM9u_NV{0aUs zs}jIrO2WQqNF`$O4B+4hlCJSS8d?@F|0Nuwxv8*jqQ_Bg)+HYsI+fT!@9^Oj#VinK z4gwma>M)gOs)EW)Ni4h)-*NOzm}J68J*Ku$KkgzKN$VD8L;?OWUcRb@87vX1%J2Bt zz*C1;1nxB&s5n9-i<{AC$a0*XbPX!7*EfeN3F^MKN=87kF+j5sIJ8$LO=s~36Jn|= zK{JrW&4#+gn8EViwhP2VtFZ5?(b57YN3!p@Vme4+3*+8G`Yx6mk|#98s+}7X#Ha#& z6rllV@M!g%_g2KzcqlP$u5#Rzsn8+6^Rat+yJdi32{eb%z;a{>yx^uqvy`t~*Ws7N zShcH?5F^R(hiEORrY%SdNh1V|B4o-`mE4oM1#a%+2Wxh>UnWBx&w|b?=!=Z)varNG z$S^My)o(6P}}Wv*w-A{e%7X!3|S5&}T~6<$uT z(vaMzh(oBMxox5i7dSge#8Vqyx0p7-j`c4krKf7?Ks*LWUeInKOcOzV=4A4A*09pN zIEcHU%~R;hgsYR{+RZ}$Ri0ZC1e=1_*e!c;$s2~U=`!Z@Z&kFNyx3c;)_@8>29ev_ zErTi<^j*8B>g7$qaEl&YfYFX12j(7gtrU-##F-}P7VNhJSrSS3UkK?W^Ppb~V6fXg z$B={xQ)IBkC6TTr*K_XnTdTYPwr z3F-LYu0L$IEaa0$?Idr&H+kpGX>a6GrQd9QVw^osJ)iWxR=DZtw&na^$=Q z{-AS6CzEMhbQbtz`QE+DvkyL*y=U(|_k8Qq-+D4U-?g`X^q#-@)9?LFNXH1%-B^22 zUE|Z1d|xWpFE{0A{Z(}0Z(F*Jghq3typ}6W%Ov_z$hn3WrgbnpG<%A*!g68 zVk3M~KJJslsPh}29xeaw56YOIeRSGMKPKHr>;LvAHa;!NqitUgqq;Bi_%UlIeNT^y zWtWSi=MzzD{>&47G4;vPw!c%dZ7Tf*JZSt{eI289iVEuq$0F++K@W^gr9Z}4RM#Uy zH(Yn<*5`w-*)+U0$GXKL)-8?)cvGlXPlx=@$31)6EyHz>6!A^G?mOz`gLQ_Ra1YNm z#p4uS?|7XySHSQ!>k*+#>mBLYL8d+*&<%a!Ycb(^LvqKpyWdXh7ehUwSN-N|Ds;&2 ze7t6P+hu4m?i$Ul#?UBHU8ip4#m&EW()nVvzqaFPaL~0sz4+n=>{lRb>4J4uO^wjP zC;jEs<=p5K3w-kFhu^uY+?G%F?{9kSS5(5%RNKXE;S;nIED}vr`=p?qxXZl_7!lL8 zeo;sqnwVHr;1!d&ru}^#TKJ@2tlnSle`0}8PC4h|_hH>>8$NmT(N~Pw7cFT2g^MP? z3=+G8bHL=g0PIj8qysz`rglE=*Dv=nIEv43l0(dPwXZ4zis?!`CXo~V&r4pA@NJi! z_|^XDC>B*p;4jRheeIXAWLL|6-k$v76`IVOXjJNj*(~JL>D8@D!7Wb(__Zecq{50r zWc98^OJNqIF62Z+tbwCuj>aQ`(Wn(MaAPB3sf8wKn?^FxKjPazl8Ff{=epLkFgi@B zyw<32!jy%WmK|2)Ym*nULr$}NZw)e_ca1aHz41oQoDPuZDR+7BZbh1@Jy1te*B{NZ z4-H(+)1mqw1!IX?W>lbQ+}57zLosC~8PWIAV*~xa*{mqlrEJ2{5DGhT!bCR#77Jx7 zg0xEpL1?+kMIvNWQmkB~P%|?)d{^X+WF?PAS{=wshr|EH&z*`5Yhb-7#qc$i#lKH z)aVT-_8TvUe&fikI4R8fRMQCMkH%=Dl91Bg#5x`IPXpDCWUV>jXrDIBWFZ?ysAl_` zLJM$}!XE=6O+Q2k+i;R1b*)4b58aweJ8CJh4y^-Y4-F*IPU6&5y8hV~b+OQsM%i>v z6UOX$MR;-GPYsmBGgx+|&|1g~`13S8qHPZp(T51PDu^&R2+7QBYK4dz6psR-bx<~R zo2V{Q6L89)B(^_EVN77vEyuVZe%)6A8&+uD>?FuH1dOd}iqKe)4I>|8xj4bVzc(vQ zu&mHlUsOQuiKKCqLOvW}7*z=T6B;v4__{5Ih;rlN+dU^dEa>Al520Pe7G+tMCTe$wVzgb}A zU-}Rikyu_us+RSaR^y!!t6boIHzoLwqf3PNYzO(o!;g$Cft0Fz= z&8xT4p1olB8V}lO(EQA0w@h7Kr23S5gr8Uw20zN?Q2{8DRpcDHo zCb=k`h|Ss+?6vVK6!hm0y2T;MD_FcV-) zb#~ab$Q+5F8_}=^Afpjru{tIwpi*jwVzr=aN$eMkZf1m)!z8-8ROSj>ab!vE;BPrw zjy;}^TvarZsVQ_}ERAD>Kq|%fTZq6`B~b5l)O)Z&2~cw823Uo!js{Fvb}|v>R~akU zAPeXKG=~OZ2Et-U7@?RIv>qE5#JoiKnH42zcs8-zCCh+7BnlwlWXdb4{2KJE!O(A-9-;-|=8$VySO zas7f2ee3aw_DM|TBj>`ONQqN35&a)Uff|EhHbNK;W}^ULim0^Qt1!#3VK}847>>FS zm=nT-6&1}N^^35u2M$27Avp>O&T$xa^*J`Bj3^a^dkxe)YFxO^&tR5{=iu<}a1tCd zgn;yliZk)dM37kwkh{CxLg;n{1GzD(>6scO*i`5mPDr?@@Gja1D!f-w($sTZh$O;k z{Gpd}lyLEhLf2UjE*z~fpo4>{n#2ZDzuvGY3S5JNDq--4I?0%#1}|Qz?}8~11uSL` zV?|g>;#nEADjYBgG#!WXz=emPfFEL#Hozu|cJd%74I?wO9`Qgy3$d;wlNiNMj6C>p zD0iblzK4Y30bSp1T@Do*9uudH6}Pt=aF9Xb0x$uG+Mv4xwp8YZEO+^e{Y({G1u}3u zxn4Y=MDffLydjXM>?_Womzrb}->5HP61e7Dcw@AeJY5?hv{(-=u#3Qz6vhM^E_JY` z;QA`WNdlu%M|9n(#Uu)??-Y4|M#zB~vVe-3!Vo6_Mg5IJ_oXJ}#EeFNRdpsC}W9~$D6 z!e@yzR>rl@*#KV*)4s zc6$ZkzCjNAE-oc7g0MT2E~X3H;vS}Npv3k!ZXPX13;C9aJ6PQvfUkXQ$iZ__sKQGz zXwYz697)o@pM-*4kVGB6>tP{c3gtgNb8aqV`YHo0yvwHkwgsc{La*dF3KaA=K! zkMR_$xnsmk_j>6$)50|nxYN^;`pMzY-d<69qGT>i7Yn!u8Q~GW&j?v8NTTBdCvR(2 z7Q@AL5(*dw?qOOx38P3eVsauQfGX{&N`pcIM8jqh5ktceMtUjK^>t_z>us+_S8oDb zQw&ECNR1$cAF*gNCl?sBOSn&^*H$O4tUx#JqlHJin1ys03mEn2LpNU}de#-t z<(oWi{<@!W#M~w!@wnZP=nbL#?HKyrmR^(UaaX#IH_Z ziCdgh_J(utq$Mq~iLC44-XtZS>cUOF$B&W2EIS=P)~W!eWDNFmFhl04>Cz4P?h@FD^KsgeIYYaDzl;pt5w0wq=4XU#=J}$}}C)E&=(@D{Xt}FeRk~_}OQ)_Nc8~?Py zk9oe7Lzjrt(2k^+7RBVm?rHPur)}1K-9`_K^rwdh`rILr9!e$)Lg`GHU+3dxE!Urr z4}^2mO+)*hntt%RpLkvAnK}66ru&T|{u0x~2B!R{Ka?BK|MGwRduk`9aMSN z@W2wsK+l*;JGtlX^UU3A*8bkpPkeaON8a$%x9`5?g4vZH8T{TY+53_kE?1}R6`!5n zv)tSBgYWp*+in4qb5auJ4@p418itq5JuSdFngE#5 z_iuUX!yhbf?_c`VcV3e{vHaSVpL*n!Oa7l9_b>fUdPDYdI%Yf|)$%?byE4#z3gtI` z^*wjI2SD_D?qDwSo7o|o9T~yyB=l{=a6g6+*QlKRbxQ9S{aeN8Xt}@t@&s;V#C&dJ zX8ZPQ)wS2=MtR?pe%}AYI@H{S7{JKz=a#vL58 ztsB~zve~*dyS3cEpVC8_5Z4^#?62o$;geDLq&$kr!R0dfq@4Q_q^?y$Sf3!oo-{u$ zlTWCj5kIvN2zkbB3l!YRwSvGWww>I;Eu@`xl6Wq=H8=W}w^+OJK^pqxy}vz+Z`t>6 z@84=YLOz+FFK_=+(Vm#y_auiVl!L!=PrwbFPk;I8&?gP^ZB?w7Z~B^xTAo`?JFz}# zr=298+qkhEpPc=5GHHJXK7qNRBSs&epGV)dpU&*sYx{ZM6YK}X+YnGY349`+j%nZJ z&9w4KxbF$=XM#JFuZ6UtiJ|m3y%}Ul9?uA|Z%Q)beQm6=4@$bIuwP23wvG96(>CE< zOE)CjvV`ewk?%Q>Kb|Oq9>>!eJOVvsT#NvVA&aYYm|y4P72j-ChH&2#+RtRrl`BGe z+f)%garZ6MH#7}MY!l`R!aH5nMM#eE06_rt%|$ zuDkC#H;;UK(%Xt=a1ghH*Np65Iqddib^xCaIbRfbf0cl~V~5zyw9PFJ;p+FdEJe_F z(X}126k6O$@hAGtqS)UbXq1!ZB@%rb1@%ZZ{eK1z8imLRvAuYc*@bO6a(5Q@?>9zZ z7#2OmWx4&oj0-(r6mZEqbIV6Z&j5Yl`$tDl9la3Oq`1H`+$Ohx&U26M zebr4Z&$ZqcA>Bf8?i;_kD|Kfs7kcFzKgn+0zJ2v-sMWNS{Q^T_ye|QpeUh8am901I zwLClw`GkD%?c5&)z5t5&D3t4b-1mc)We9yxk6S3t{p8|bN!L*NR(1({d+<2P1a< zVin6VfoX@q`o##g^4%)b3-bvvz5KxQd0(EYNx!m=k@*-*)ylak`6`m{K48}?y2}Fm zIjP_;$4xDJJs#)_@vQ*gUQdVlbv{1%!mtddc*4*vGOu5Z;2W>ORRMGjhSDjxp{7T+ ztVhv0n3@37U>)NGUQjZ&biL%1CPnivQxl~kUJ*ZP*C~p}s_PXqB=9d&bCY=2(xV$- ze8`Jy2Fb+$`hT}$3Ssz6Z5W<3C`C6lv4Z4ZA5L-VzG`0Se-0;)7P8j9ZoSk3M!f)f z-MB!{t6xM(bW7bMtHBc2p%4tW0?G#qjH-WHDw~2=2AFwg&HA|v^{JJr)wa6QrO2!SKN0_V}>JfgyDUN%X@9nr>_ z&G?uriK#OR6T}=a;{t0gUZf;seudI5!POIs^oUNul4m)rbV9>2({&psC=*#GJ#akckHjd}5Ju_+dXr_6uxi8-@5E&xPcZn77SpgJ2;UYmzis9*u{t`Ziw; zVN{f^i*ePr9Ab1nq~{ke11c&zLzbxc5*-aXch6voSHL$7^@+kRZnnNBv){6oBqFT>MbK@oyXh3{&@DxY^~qiF7^- zdkVU7rz^l1knPSw+d`GW1lZ;_Ddr}eF@YHpG=QS(3DhlEb~2x=uK&kb#SAW`_BE#DhmkN0rjMBbv>wKd zoP(tWO3;;VA+v*ql6Lp8%PUzvr-@)2ekU6no{V%WEx!R4kp<~unJZ0jBqq=)?hH$6)SNO ziiASY5DMUS!++?BG~{|@c1{c^w-;>CRq$Mew~?m|cqw;%lD-uog&BiOk~oSK;zF$b z@t;9#9BTM*gwUSnieFZsaUuf-PhJveGp3qh$H)FJd+!4$S5@APpL_T2cue zqV|r4I6w1TwMGQaP0&b{+*XJ%(Nv&`JfeRk(O=RD^*=RW6o z?)h`iJ?EZ|uhuF;v4uw2O(==XV?r@9&6s?z=-0Qr+ZI84m2lo+?5noW_6dp+$4Yp_ zXeAdj`mJuOpYj)7@ub6zIOe*r_rw4v^;nXzcd|%MS2J@v?h}EC3}S7=G{*6|cm&}~ z5Dp5gxVTsniLyx;K*~}~1n|&r0zU!?8l#^EiF74FmzotS4HF211AE_5*-UsU0et(t zDxlBdlj$FzldeRLF(QM&Mx`^1Zu?*7hh6QWegaR@mrpu_4Fl$-9F|&N$j2 zhG+n(L6V0eDMW-a;20oazN(DIMyeS_wMZ}wY9^wko1%b+mHlNr%Hk=;Qe{{ojM*`a z2oV(&IOf8#l1TR+l&Tt2p$`|NgeIgV0nC_C`xb5E=I#k5r-cDBlh2zE0$;`^us;{f zP>{LY;woJl-FZ0(Ha=rITvp7n@1l<$76ISHrYGR6Z?M%{+p7^ zC1szsn0&~dq)uq7{0ErCI3&^MPf7^ICXO*!5^Ui z@BaKLLx*8a*?H6Nj659ee_~(EfQ3qVKXv!BFQ4}BXD5IBqowC>P53yHNbD#Xe57IZ?c6*00l{RkL7X_Bc zHYi|;LP?-oymE@U&q;`-3kWI&|Faw;y-zDSw?h z?wEbYotykYfclf(@q$e}k6wdHYeliHx3D8ituFFS&<1I@rwA6#99c zGS5!fwktoQHu!if3h&9^u&bvhoo2_zdf331^Mf;3F|1Y@)B0?+@^q$<2l5(Zh5d^d zDHEWJ3lw;BBPE4W`bJpc!j3GhS=T05T@8Dbudy!4L3u}Zz2hB;U1QrkeU62)$9PXM zpXd`_xRQ^hZ1m6e@Ff#>KJ0X|weEh!wRjtBf!D$;Kh1ER#m={d;rxSDf>Q`Hgs)b3 zR>poM^pIW^U?IY&h0poYe#J_>>O*Vq)^v@bs=M*zHj0EMr30Gv+(G*vy?j=EC~~*s zhA|Yzv}6&s<25^D3G>>=v%h;Hbib3yRp(f2?WJu0s!@xr*$M21;}pjJ#@;0MMIs-F zK#(5LI4JJ2!uu1i-LJ&xV)KKWX7Zb2u_I_k^7*O3O;q}+u>(8cPU(IJZY5BERPC>V zZ!Grfj*gD0{As6kZtUrK)0@V|Fb)_Q*#$P0r>$_cT|yNZ1tz%qp9)2(ra#bTu(@z% z(+t~$P3z=mQ!`Dq2^*XmJOBJCcG~y8@W~TSc+-=#vukh{*+koc#uNGcmjgDoDrmi$ z=d=Q`hE34NvcXM*4D}>Netc9z*<@^L#{mTNent15F62d?8u^v+C^l4+jtgU*om5XO z>O<&NO{ooDw5sl=Q=CC`ievp6IvkuC%+G8Z%%h&fFfPT0LtRgrWfMFCQaw4+`BLY` z6Hc)H8)ip6A)C+*z}Sm5Fr50JG$p~qiO(AXc-SMUNK^r$W9g9w47;!vS?2VZjA#b^>?C;su!EZ|hIA!4 z>R4a9%dej$zR(nRyn_{QG>%29-N`tjXqTZiBpjHAhzjcj+SPZx-X#GRFd%~>czz^x zVThrs3d*b#TBnT+czHu1#*!DBQ04-XprMn-dDPrd8wOS~UQnR+w>>;fdL@fGmT5Nzi9m_=R8A9E00WVLq$_1*5elH3pZ3GS;)F+4`Twv}fyB#-W1GQ>0+zDmD3HY!E3^fAw zkmSYD0Ls*MRGJcRRya6_+vEvEOT?4q=ttM*@NlUq2nGSHe`>50)MD#D@C!r0g%au0 z0%agQQ-CT|45yJ2sSq)mq7ouZNi9$fK?@wQM$94v+HVr>M3iGpkEkkO97_y>9b)lL zyhB6BW+@Sfohk`qoScBb${&{(gcpNZ&x?DPF$srr>@cJN&#;^ui%Wo0hArrUBqDZ>SVJyk87n^eywX>*<5o~Xi32C$F$|N(_>AuL!FeILY95-cT)@F%B zQr=2gI7#?%!0G-#)srQUQrXIY?q7hq{eZC{5gNu1dqJT;J7?yi89Hm%=6IOk#OeWQ zS$Y9p@WYY>=oh%)Lir00E@rMI&fYb6IN@f$q1DYG(-NC;D`HVFG1dS;J>r7DudF;-N5&one?OZ_kkuT(7VP;3s=SsRkD*?IJ} z8U=z}PL6s$gn=dci3Cev6b$WRROJ|l`YjnBb=VMH#h~Z&)IleiVgn{;2G|MQXT;7P zy~D!dmc>xv0t3fIY8GYEjgi#sLyx1>%VVd=llC~pSm^C_1)xw(z#|0yssQplezXgR zEJiXG6IkY|b3;Wk0Yh#I)%QCiWJYM70OMfw6pGpfF!a7jD;@x}dF&Rvq zP%TEH_=oJFAmX}c=s^~({POd@vD3mYk1oqEaq;p_=qk>wel)4cpts3`< z5xmvHKa4q$!*;^Nis&Y~XbC7~S#Q8dw1*#ItUDCA98Md*&`K2ZNY{nOJSBlgeZx|9Zta#n&`4tQW}*@ zKjF`C#~5cIa;dIDmuHMy2Aw$o83@qDSjGTYI^dV4iWjpktyq2QtoT_S(dm|?-_!V6 zxP#4Up#6;cW*19%7YG;~2z)@zLJm@RRQ+>3ai+qe1Ex!j>TQ>=%x}7C5%tU|E|xYz3*aI!KpXT9stchO1Ue zvp3Q0SUh23Sqj?@`wyV9Fl$*N5;e9kOQ#pijzjejL|Y3rXdvDN(`C;RCOZ!;7$~)+ zaE0&_TKcP6(n2K@h_f*6;>3e3jvwp6Lfy`F@Fz!DXF|ry?rCDG0#ebSv{KuEW?Fp9 zXwSFLVZBdxuRH(LlVR@D*_xEGBPwBjf&PMwK>w5jW>e61(zpxf&sq#5X*tnOtN%e_ z2^OpB05 z*qVe*7+W#1ciB!-&XUI?U+FpJ>C~~$MtMi_0^``J?1tX*wkuPXhg2a$nS?%7qij-a zW$xYd@a_xW@{{*l8-KOzlnd6My#13GpFVK^A>&ueZrivuIs}`bK|{sZVoq*2E15c1 zSp@ZDLo~V}ev5P5ZMR;3_L9i84=$g?5m9Ouv+U|V4y+oPTX=WBTRwWmtTn)8>x6gg zm^-f`$DaJ=XBpd*x0gs`Y%{y-%JhY~Y?jUiOdQf&n~Upa72)!-{7tcA@LH@_?kr{* z5Z{TPpSvKQO|XWya!v73*d(7v$3%M~W5OKEvn#G#a|B_s2_p}{+Z(4tjFsEG--Jz4 z`Fy9lYs=&EKR)sHxyx`w>nPuBn@C(bkIjiThfSug9G#y{jDtG{^U5Y;0bAeQORu=+ zfW@*&UXo3g*p>sEj9u9~Kbx>;|JNC`H@Fj+3seD%gw1{>poz6E^l)I;Rs~aA4^~t+GHNWD}FlRkVOFWz%umSLp38B#ihHo6vcU zMR3zIoX2=PQ7KIM6gdh$n+{lXu1?>u3O2!9v$`$@&PY<0j_4{MAhYL5HoC-4thnaM zbiiz4{EW(34R8wf-Lx-f(_@<+8ywuR+tl0&E zJa$`d{r&-rpMSBOvKZ-}VV$St^H}Ro$H^AiCY|49GlM&zv#G(m^Z3rx{jkfz;8=NK=g%WQk27RQ zIcS@_^wLjpUO5}H_Y`u?zlC;gDITI-H@5uCjQtc{2}omsw8@e}*(*GBFgewe$2M(x zOxtAev60{G+=$WF*vtV~<$kIs3%AJ?jHR;U(@9)*#=Z1R=V{-IVk8#B_d5#pMA<{x zM30T>3oJA?$m6K&v9TT+2?wm6bWc{8q7c+JnVH%2*khY?+eJ3ncIDU(?EKwqxs!WEb26lSwLLTzj&O5!M=sG$7yK1N(ejRp|z!539&Mn+*I!CNiW_hZon zT|cccE6lrr>T~FNW32+Dxf*w241Aeld4P|@2<&?rcg(D1;|Q8r6$!^0Wm3&)d4xHz zWL$Arf{>ZD1Sd~+LJ(r#^TL)Ghak~gtZBknl{&2%u#ZtPmU+bG=SUL}c+HxlC94-vd{#8tpaKY$Qz6)hM>SfFF#4M3_>VRy zezo>m)J!XD#F!OyZE5N*LMUipWdn1NidiU^!!7+OViiXyTJ_sn#}Na^vpV61K~~f) z?xievJc6I`vVWda`qJ`Bbg~3exr8h4d>z4yEFf@YM>k0U3HaRoBn28gl%c*zY2HM| zZ~`lqivXI$^4aPV6xn>|i>P_Ms$vUJ>F0qZED++L86d%r^Af!Y509rFCT>huAz=v! zlXjcH1|tHXcb?$;&Y0Dri{Kjg6{?$H)3^&fz~rV>#@3u3+5fmRU0Q}h={+JXL=`$9 z;APN(e$DFX%wtqot(c^R)$V-`c06yW>1DD+!5Zo^2C_@(YJp2QSRU@eFoWV@9*nie z70wv_*taNXRTI{!NR>wO53znX5vYNIzE3t-6jG?b54#>Z4V(-&sw)_gnObPga_~v~ z%3+q7%cHql3sP><6c&nip^eg&%H_2zHbFb!m8m6&AYkzZt_Tm0izF_L=)geTd0km( zIN;MDTU?qey9I#a8^~~t1S&*sWN5zRyGOA$8K9;wV zSqM&~pg{NE)hUUjP8AwbN=R^K=4>VhP*sw+V|kQxM@#Zbz*8rp(eRXmUQMa%lJt^U zl7lP3CXm3i*D_Q98*>BdidX{1EV%|h22e|j;6_*{WHOC$ck7G5TNz2K0s{lbE-Nhx zFAbFYp)7!aQmB^}ZdWZ5L^a5vMo9M~x``1)e(gg<0*VZfw6oNR30jC1&>x|}@Oma*SC!yK_6X#sg1_%O6 zxvn|jCv#~i`aDVn=8V%6F$^YwIbvU%oiNt`)6fAsAlPTDj5`R{1~gO-g0X)jk1!%k z;4e6^>oHfnr<`!1M#))-3=MYoJM87{ColjpHg~ zEEAVPJrr(L=A>Rq_f&<{jO=59j($bL&~!qLGl3AAIy81t8_Lbx-v~vk33$%vVbY4K z?St#NUdKZGvSyNbMCbuDHZ?LU!UYap6!^HeZFHF{2iR-z$!(0roaMGajyEyJC8p)c zKHp+I13!Tk$q)h+h6xg^{&elq2*#OZ_l`Kc_qDb&>@tel3Fa50OwHJIN}yT^JoDg` zKYUU}2-F3WaV$KeON}tZDCh!~@Yyhw?FbV!3LU=#A-z!sJV5~avvo@$smzWv*Ch3{ zM_~_;f!kAohrtLCiq@#3?{Dn9?i%TkX>m1kMxCt6C+k>fm(V7$eq2D9f)7*X@T1?S zs)|p3ShUX(ChDhPX=_PgKST8Fn$k{W#M8(II8foOCm7uAmStx~-5^DN6 zw2YtQjI#)Cej8)6VKdD}4O`@JRm?7SWvS-SCFx5Ns+mFph2i#74299E%1&)xg!~V$ z(c`8n1?h@AG_JyER8HV0EqOBz9m6*@q$HyEE71jL>U>AmFi>k`;cE~|wJQl@?^ka4 z&FmpFWzo5@_bH8FsolxO;2IntgzdRbUcq*wes7xQ!3C;L<^X zp4#^pJtyN!bEn_P*s9}Lm({_$-BM?iEtD3DHsKU0smX5?D1Vq;Zop@6K8A^#WE8uJ zjnO}dryS>l#(8n;di7jtV{Dj{82wHf?BKbW(}ACQFAH4@pfm1t^DVep0s~8N4nTD{ zhT}ZNPI`&7W{b&J4hVjC2E*Z7#)%yo;ADYPO-Kp4)QTpaxxjMpB_hU>qr+AwAKGHC z{43VOIol{QQzn=8smB~|v$bap<4iknrKFpkz9Nk^oC!`hK$fjFS%axJCg1)W4}SCI&pdzcqxXF6i9h>HPuaY^4~@-&Q)P8aG0=un@mxvp~7 zb>eZdiM;C9zgqSiKhJMD`;nKUpLp;;-}>_3|LUcecmBu8yZicfU-0=Kz0KIS&tRWE zlxCBvo*3g%X<#heW3Rq>DuN30(G?q)t-E0DDYNqTE#buX)e`-fo$)9??$q?@H=cQM z-fYVv`mI~zUHk4j_uvl>#gCah7Wmu^lapIulcC=D z-8p=I#JGLK#%271Sb%I|9ImB7IvNpic`2klH73QTO=o_K!dOE*Q!CB<=u@4HZQe|0 z%pEzBXOBMmBKrou%Js|p2Hzslg-h&pte4-B7Y7B!>$R$8tRAnw;!dz?$?MsKJKUTa zv#rM-J98s=7tJP=HMY=A;cO_n7wA$A*~HHO5PUFdU?6%+t)h%=-MR^F)63L8OpTd_ zw#mAt+2qIosd4k>byIs(J(;gfu(Do@o*&C|9weJMTWZ?GZM$r&SD6~)j&8f?e8uLp zU8Ob|II;`1;ziVx1l5zbxXN~wUR^@ZCe(IexE7$c%h^!9#ELoqSGR50oi@yz4S2hl z!1;+DrnrQcp3Z5c^BBEw0~kF#vxeCr%gxur@zU_n`71}=a~Orfc)TaT{>OXJ?F?h+ zMawm6w!wMzeFb{89BbOa#F zpK(BS!=>LXpiaO8kM4yV#A7&AHnD3EnGrMB3X!Mz9E}B_C^=6#(JM#;i|5yd6 zE5Uvsiorgu9_6XR=2w#264VhNMj0I3-?eBq!QsowCi%fU*<{xTt0v{S^cqUWiF-d$0Op*4B6zsqSTWqY>&)7gHutltudQ8a3F`TuDCWiXXc!# z>T@P}T0HDkkD%3)zMq%szp5WbQBMquWfN=`RW`}btVDhw!8j=^*cyKiT+ zOLh{c96Q8Ge4ISnX{i?h?Mnn~e_er2!TAB7AG*js~Q$ka{8*{mlV$GR%>_ zGP>FMRp#G5Ve{&`vTz+s$n_d72E`+hw*X2v-pjYzJvq9QSM2lB@gNgQwsPle*ljMbmDn zWV2cQM(Oy#{3PZ@_F9U-jf+*j1(3=|6z!v6(O1UJ{j3eoZN%&ms_;S5Htm)>4?|XmhS~GX!o3>_UB_YA0Y6 zL#H!IuuKN>CLdAgS8yw;1dj4VTtaaK!!d4cemSJBLITfq7IH_cMc1&HNGU{t z5b9{)#P`>UJnAUN5e`Q#QmreA+ic|;G&3+%@E*R8T35vkmR?cxH_692ni>34QEaNl(rnYYOm*IZ3=*29o}P_Q)QdfuxOhA+@L9akk#RvA67ZcZ z)ss+f5_Ttb72Ex@y3q@XR22n|K$XDv&gk1y;v4RSpkeW-0H?uvJi5tMm_<**atOT5 zFxP>>V0#rEyRxJG6d(7}-J#Q4e;UPb4Cj{oU&Pi1T-VEAF%`nra+5x1VKDdH6ND3p zG^{t&&dhHyC)C^@zg88+yaiZ7L$^M_6=7J1F;_B5bjChw^DMDUjB?2&{)vd$mCq`3 zdg;sub^4B(2l!ctHvd*}RdFn#v+(k_Mm5ufQ22WjVgw%Zk05RU!AJc>c@ zMQFC&)mrtG+#}~O!2u3tIgV&fHtmwjinq;E5<}T!o{0+VqTs9L zK|_Qq5Rl99D+l#N3X&j30!yO+xhsA#&%(^90#PGFv`GML>;}ezJX~Fmh*|(yjYzSw zz~Xu46vSin9X@V8&+%w`+yaUQ3Q9ax)Lu;K-RVV&TSGK~m(a^1O6ftYC+646OIR9` zxI5{Oz{4s~;&A2HZlwhCb1Q+$EB9W9Q@Nq4U-rU3rO6t=)IJ=aR)ac(S5BgOF0jeP=*OF+> zZHP3hQ;$mced6sa?r*OlvBUNYjFU{SAriz#lf3|;m4P@3Z()@-yZ}kR1Q!CB017RI z;nD#4h5FYSdvR_WAR#>(VORsR%uI0M)+AmU>vMni8*3Fn79xb}bJc}UnxbW~1$WyQ z)xfyQ!~Cz-Jr>0&BXZIozJXRWiN{&4{E{l-T?UNG%hd&F9U3yzrY5Z3CM%5ZNUU@> zvZ}D(o!-nmN+5H1t1e0tNH+ijF!JZ{(||?`9y?37vsZ8YKXcQiGx0RhW}9_ zDv-*>3GXGxHrKYxDmEz?Uw{WqdH11H98&Foj7Gt-c0*RKtSfXO@L*u!&D`&?))|Lz< zh6>?~(tS;VtaT9e#5=gBn9?AHQ=3IVo7~72!#WLPLJ$S6>!E;2q^e*uQKTz2i@Vpy z6~>JuqB%G$G?^U~Pl4LmA<}OUJ6uy@I+sL&!p3)5=3V8yQa2pv8{otLG{Q0hj{@k- z^STrdDKe>f4v;DyOIj63Xg*HoKHGA?BG`6@B`}1blQv|UZkd2U?>{zL5T^_GeYqwj z1?6RwgTcf!TmcV(#OT$u2k=D!ul6XiiYoZ(d&tm$4&|~mLtTv1-61g5MwM1RkmF4L z5UVjHFIG~`?QeG}jb>^BbU-?pAO;hM!MSC(D9j}O2)J_DIx!Mu(>%#2wufOHCTXYy zn@D1Sqy8ni=;tDI>$JUfLw`RB+jA;q}hJh1mT{;%uWF_^ML_a<_9=hLL#IZ zOdam2X1nY`OG+_u!OY#9bYg+bxX+H#& zW}!0rgI0+{A_)ND*`Tjehy=H0R;S347YrYZSaycaq+_?(_I<~^*6Ql+K0d(>hFTmH zh}2xu<3yu$%XYvf6I9wy{od5O)}8V}s#lgOJ-QJCHkr7B$xPQ0dBx$!qbEO>d%fHM zn|!?6{?qK_L#x=5dvHt&nL?&v5(2`8OjoHVdMxZ7|6>v_46!6`N8?Li(Jw}$8{_uJ zj{E0*lSg{(bIpBUcx39BKl)+UNB{8NL@s?#fNawFVWrWbWP%F~ZW*`Mc5m1|&=<(B=$n+`tQ%_0YsP0}y|DH$fAdSl4h zZ5P!?swtjL7?_biwO#QDY;sqGtuT#`ANRaHd37&_#QVPR=FcB<(lcEj{pjx}__?ns ztHD)@<0I0l4>T(5j|8<{O%nG)blp=BSdH3xfzXKr5@i*S>zG6 z3xr+yRBmwQv_DVf$|8Loh<~wB@ptT?ul~Mva2CI7lLH6tzWeUW$tLubY=E*!Grz}N zZW9pjbMg~TWm!ornKci&p!k@Uph~P zLPJ@4T2)^*QV$_Rcyz^-=P=GqDV&pn__f3v5V*WnIiOhEjTMyYMJ)cJ} zGwAjzG}h8EE#zj;-xx0R;reUt6`MdIu$b=Ci+W_!d9q1t9_L)mjJUE?+C-7_c|6Hu zoV9J6I*5jBa{qw?V`JJT*nl4xIHt2!QS`ZoD%KtUW=u8}`(WO+4<|WrQE{0eSRTIo7kWFwwyI4=iCPAtv&OIf?Zpf=Te(0whW544t zx?m&n@6oprW_LveX^`F3P^JwqnL=IhfXC|QZ+LQebl+n;`sjSiu$Jb5rDO^tu^xn) z-4F0_sHbC8V+vz&7xqEUH~(7vX|)fMjeGIPpMdsP1`L+md=v!|b<@hau?vqBvy#%( zWq{x{ZjZU3B8j@G)KiLneyqz^KbOj+I@d~SfWjt=e9C9V5k8Z5{^H7&-7(N*-K5*9)ej|zePT`hZ1TFyMCwu zwF%&MC223KLe~IqVDu-86OXAJ9t3@UtF2ov0Rt@x7DzXqo z3ttuJb7=~6-+MZm*PoQAUsl&ksU>G~h}onv3gU|yNQx>3DHIrR7XF+~trgV{sa#c0 z7-*82Nfl*l24aHtJpFlCksETP%f*qqP=@y?6v6SEf1Z@GZDD!MHFpaW*(xL}`U<3Z z>5dnYxgG&5@TW{IiCE_oIN`np$fx%is{0kGrTZt~HKjlkgSJa@$?(1fW?BTml^Dj}97vCc zjX;gNRy>b_%?~WF(@z0ZPhW5*)fh@cFo%vo5THlKs59QZ>|xC`A9p2>RE*;&FHTp5 z6CkkrkG3#aR6GI`^)mBp>>k2~&rWshU&N5enICQLCF$1)^zkL(zU%rYB792gUg&!Cf-Nw=#Sy@9ea=do(_YXw&qSzyp_TrBg-=eNrnv2(5 zdAKyr&;I3?%vbtxsZwCMqq<3TeZdGQ0kUCkplu|!9XG_K9qiH-tcUiyH4n^n$wFqB z2@RSxblFb$i$WP2^lxmbt zq?Z%f1pfv(0fLS%&ATvCA_;zkv5yLYE%eI{ufAd53q#5!WE0xYh?{jMo(Z>p{iSbybMvnse(oFjmv*1| z!h^f_>|1u#mXpuL^0?+e_USb;d0w&YLL)h$>&Z=Iogh_}itiB2tv{}95-HS^EZb=@ zw)N5LFaGA{8^>RMbk7aDH(q}FRb-PD$wSj~=hzs>z70=jD(Z>bb}5@QmWeO8Vr!cv zCf2edE36S!p0TkVJ66v$D{smtms7dH{6UBAH#Mt-FhwUb#ef(C36Y(ifF z>ui?1?VC^cAIw)a+GmJ;i{CEnH^lT7?Jq<=1EZ^$#a%qaXrH5^&-W6w`1Q+@LM$fO z6s!!=n2Snur7l{dszAgL^n-e+x4YN z1eM3T0oOJqQLi>{arckvZ!f(6{tNSY?90jYv;2WBXk!T5wuaDp(Lii5_v(24y}M;8 zFm~wMH}9fU*yR2TFT7uU!()i`=MS*1{atJbJG+L)c5KC7)UmDe&cERVZ*e)XN9@%O z6*jr>er=Nsn_%p~ezw0WgROL#u%0aVKI#6`c_*!~2~48eF0@z^>;T)3{4)3wN=CI^ z{FP|Cf>uvf?V7hu79)XlGxczz*O)JVqxrU!ue;{{_*YUaZ;5~YaSLqRQ&q9@mai!S7nyd+Vn zzl0nVZ{O2REy;r4IElH$@EE+>Rl>jEi!=F_~D=IGho!=-Wl_ZvTMb{UF#63xuo?PrjuqtEXs zUZ+HE*LQ_jU&WZ;#oRcc!$OBfC{5NaUQK&XLG1EB^&4TKs9 zH4thb)Ig|#Py?X`LJfo(2sIFDphX%u>w8VTuo2;Azs?cgCsN?zvz%@1m&P|aB=e#gQmcoQkq5mh<%(Ee+3KHh<8A1gE;F#?AGZwiR&3R{56tda* z6?1MApUFCL(9)tp;B~mD+6yyp4-Lo_ceaNh4NIZ=s)o6J$=JKT#bV3GuV2PW0s4`R zIDP?w_y?O&7V6OUOYDF6Ce#;zOcGQ5q<3# z%~>y8(1BE⩔x^I0nP>7g(x$#$B?g9<8Z4)D1(@XQi_OA3DU50>gqnivTA;u=KfR z6-IiRi8q)dRUp(2Z#@_qA;DPEC78e!;NV+^qoC=Em-N!PT-1gI1bRpbO$1&&uNvf1 z<|0V!Xu7yOfnP%%r!1o6u9~C3^yT3K2<4MZ0)GrY&m5Ilu_-R{ zNvaC!!}pp`+IQlpAP%CJ4&ER@_wy|;#a#EebR`tR^|%cl(v>7F@w#ljMJs;V4AFTZ z6V7r4KRn#Mhj}TH2^G>>Ot~?#9FyK>g9OQ@EOi}24WU-d4SOr3v$6@$hn=L8R3^7W0ElJ-_b!3esW$Aqr zIPu;lidwE2_oK`<7id_j3{{1D3!IE~+cw%Q>z%M2H42Xca2ZJGS29cP2S0EI;Sx-FR0GOL*lfDkT+wWo zF=4cNe!H5m3#2Xmn*}DUmW-P?-b|_()m#!%%_@SV%25KQgLVdu6ApEP%S&QhuTa=9hHZ?bOv4#x4u)!O z9=cU4O=PZ&qG>a&;ioxl$C*9BB_GDXYnnaDu(YC-*WZ5QaMR?UG&$YsbOS?outi)o z|2P`O=Em%{3u?vK76U1saXQgMkQ^mPK~b;_41_QqFmr4e2Y4AUG)(iylG-wQiL$ng z+1G)k$!3ZFnSJIO({|8ykxiDc=&|uAjfHK#Gs@r2bCuVTf8z z+O7^OvgFyPFIk!FxIY=47|8N`w(F0k#goR{?#BrOfq{vpmxR7`3&2-w)i+sp!M*Gg zRjxwc?k@cF!RY1_n|o3QKmu1=Z7pRHcD}P4dbnd-hCE z%RN5Y{HaHsO^$_pteewr%eV6HW|a& zH05nqux!HCRH|yBVT1K%DJ{qOCvG0}3`juOQoh*^=om7q_&BAn#fRapqu0^$Z#m4y zqYUpa$FuYHDWxaZM8QWXuk90AWs~hpDw_~S!xFE&&ZSJoM=iGIQnug27g3lYT**t} zYnW6var2E=;%aGL?X;<>m}>9ms|V^GD2fscw_G>R4$$?e9ll*(6w~O^WrTz96V4iXr&*gk4@=6Z4N%qbRgs<`B{vI3}Be zQl~{Tg}z3`{>H+-MsL4kU2Ir^+0Te?557}tq5T7E;t)a&ERF`2PA^Wrl&hZG)oW77rEn1!u3M{J<1PnhDEA1;H_$z&pjw6eAMMGt+m(jsBC`=)Z=e(|(1ppVF zh@ut_sX3Zg!TBgl|9(#0G=)Kp#_H!Z7Yi>Wm++|&ciYE8OdveV7vr1Hs)E27a#e)a z?21%hV_*^ZqlJwEoK&p{Q?(*YSqM}zYU)PtV_4E9K(^ol2MAUlT&%+2#XOU$xv6!9 zVn-r87U*4rDP2W-3KuNJc--N_NFh_shE@n>_j5i3e#dL(ywv{2&dZA=zt*lvx!2d2 zVkr~CYs6r);?liBCT6EfK?dcNOs{pBoeRbJ6IM5EzN>!udHrZoZB3Rc`gW@rSx?TD zv+v@&&t4>vwW^@bgvsZqDcDn@!NaZ*q{7g<8^(%cX~PDzGMTJlCp4ybuWq?H`5KwG zE~@yt1;ZuW8@udc6?&Y-QbBNAFV)FYhRW213zX&T@4)hh7E69k8KaIUpj)~QNG}du zy9=I2GF@GyjXGlIupUp^+~!P15r$nd;OB0dfFQH!=LA79XiJonk-%uXRG4Vhz|ifE zfenySf&oh>VHr54)D}`= zERUVgL84+gaajvTrlJQJi}eyy5*0htP#tlzO<gODR( zTNOaPBTFKT?!@9iEHcmhDNVb=iNDiq$-H`^O<}0-6xF>3Itbdo>jFH&^DC^ap!d~r zMCmZTTp*NDlywwiV4P*YUYw%vLbl}N7XNgCP~pLSj(gm|UPgEGHsU=ylwsk64iZzYSX>4ExHl{H+ zV>bh5!H_X}4%6b{2r&l)dWM=^5J$CLw6Bqx8^$&u>?98ryZ(v`+NzttgGj>c?VyPh zZdx4-BWX^(48jS8bvQSHcvwp^wgyAjb*3E-Rd9=7Ejxtr7J!(G!K zmp7;HKb)OT1K;s;d;iVgYj!zWmtXU~x8jvS*#xbOR5meTljs)IldWESC5~DaY!YFe zm#BKu(RoP*^(4|^j8pxH7@e0e74AHoWj#5xS%=fYls6l%JDf#5x!E}Oa5Rp#3l%Da zIW^$!4N^NB>oRZNtfFh}5%Lz%&xPw=BaGBK_IAvv4Tp7<656CfIVV(vn-?t9lR2{7 z^ZKx!l&Q!$wk+7pK!Y|pm=A4IuJ#kpEDs-j2>T9c@@g2b0Z*sgMp*owIdZKSCsT47 z1S=?F{w+10!#>7xtgq+sxyk&DmThac^iVJ<)x^F=WfSJ^Ypi`8siH2W{f&6+DB0iW z?Q@(9uhRP)P!V-@C8b@>H`4Yse5W({U$N$_(k3Lawh8TH%;%qa zs@Y{|ZGOwmW?z4>P)~HuvD*{*9qdg@=DJSpda_N~ioVWLUQejLG~s_*dM8) z40j%w_DfX;2(BYHN_! zZ)~f6)iQ~NH_>QWCA~w57m{JDtX8w6l$1kyW)ip2Fc(bVbKDACqyqtPWB<{@La6bp z;5jiYEyLkerWAxHUBPV9qhQSnysim(k?Mb6uhL6P%0Wwm3P8(Jl7&ze4|i!aCr=fF zbNADE!i@+J%C(>@vT#j_4n(4U3;-EvtYIz0)bNP1%7o2yXaIxOw-|p{qwtGQChcks zn}*2_3fiA&K*zH{ovec8V!EZuVW|=USO4&+gXoA76fpl^3rkXHyXX;+KHxDo2#;mI zH$q@@)-5lIU-0U)S}19TYJkj5P3AJxfJulVc~yCGE|uzpN<@YrUWs~wr0@j?oU>b2 z7N}C00SMp1JBX>q1g|CxC#7SPN=CJGR?bbtv51wj5Xvak68e?4d~XXRm+G1m%GG|f zThsk39EJtkWsoU^&{nAz`x2Hhi0Vk%(#XjhFo<2l+Om{(;_>wOv+*rJzyk@h3+{ zy4lsI9%r3?n5WolDs{JyqwT^Vjp)6}lo&9XUTc#DfeW^eq3ts2PbydD+1_FE7p;&j1Ewfnitc3tp)E9Ke8>DWiZ7Iu`wCg*N2vl~!PjvLQL zc`BK5_H7x7CdZN|SEloE_@7%P`_4%_bskT}fB5oqzuuktuieM(zVYSp-Dl2fOUWh} zB-@uVd&7!kDz#JFr1R2jbi+t8)v+%=5@j7H2gxR_GD+dON1mdSPx4>QF}*Ih5aD|C zSvPg|-;L4I)H?B%8Mb|R=?kqEQQ5>A9L!;bd^K6-vPqt7k`I(kzE@2TuOux$lRv`j z!NKls>?G;NM)?YGZBlbDcYfDXhLQi==PHu zJE-jnl1+MFs?@-Huv zqlK~4Q;a{Cs3p$;EVC=W2WR}IQZek#N~PG5J$YG+-N$s}`Bn)(_>C;f$85IiMNfjU zr}pzHdOEKP*Ijqy$S!P_(>BTHuf3LRQkB)`MB|68D!}GPQAb{HyCY!EMq<}tuV_t^ zu?S{7@%2UoX;q{ zvb74QxgJkFz_}6uVS;hx!dc5W+>E=A(acVamN#${qCD)S^DkE4MrjlAU8A&#G_4b( z@1w1|_EBD$yXiSqq#)U|o$84Yu9jcrD0ZuF6@UkN1?t#{ARTko(Yn2J`Unfw2VEOje7REcTh8iL| zF^H?VL{yp*FpGXk<{B=B-S(@TzZmULU(e;OmYb6RC2FsfM^+Nb!zNXnx*3%7`yk}B zY`&|g96FYibg1fi7YZRQu{sTe!;_2;@B3`eF=BDy!HMjgoGK$S@vos9fp* zECMiTSG-hSI0jNgy+AN<-|Ci@Lvr=Bf#yj)V^~@k5NiQ-CiD-G%4L!gi6I>bgxk^I z>SAy-QQUkxvy%g;4~7!Q5VY5~47|<;M288JiL%&01D2 z682;Y>ZV3aX16%mQkg_H%RNI7eUeSA!`IY`HN`Y1O8Nco@BVSC%YYM?SDBWhI(6*G zGRzz#vieK+lUPm?CUap((s^@Z9bR}slCMyiDByEg^;az~z#AW0vnd&|;%krZW)@C0 zOL2TV3Vn(TaXgP;F)>1tD43r|2a;5N3NuSeG+d=MNs)c*^c-ll@W*tE_plX1EV`1@ zi)eWZUvaBltQJ^?mvtcHxt^Spa$-t!sB<_KNhZt*y9YHaFtF;qtuD&D&;0f751n~I z_v$m>yvmLn>DxcJ@wQ{Oo_vZYSA23Zjy-d*i6oNo7xK<$hfeun;k?I*`!W;Jo+Zb4 z{Qk$QPHJ@--m>{WetqVdPi-Na+!isiw?Dt}wyyJvZP%8`NqkqOXp`^3CaF{87Ef+% zlSqK-N$;n;vb73#d~Vl^Gc&l&1)Uujdp#Rtw6hWZ>Tu!vVuNKdig$2h8O_&$zKdEe z{uHeOX6#xqHbt`J#|)#sP5OSjOy23j~J}K*NeZD#UG(`UfBQG_`}whAv>UC7>LkRV|;t|W_lhe>`z1h z^aR<1;@LGKeFKoPj|xv@DO}(un!jN+Z?*i#?tuhZ#s>53I#-r$WipNR>_Puh+#ip2 zt)norLYxD?F5~xoVCm0WU4&ydOWp3|qZkDf&?u}39b2D+O^WV%IL(I>BG?y=)|X2C$00KRenuklxrW3KlBP-8bhMuMWSjqLy9JF5>2tASH&GLoljY;HG-c=V0|&w6Usv1m>h) z0`=6Wy;a=$u~icIjbuLGVu_`9eNG-&MPc%5@a&{R(xs{%g(IM&IWq%fsT03bC}k@> zCU-mZ1qtEE1tn|OM7@u-iDXbK+OCX+`yKbZy8T_JS`Coi$jhrIbF_DDQpm={Saw2V ze2dS;RX@VfcF|uQ9ovXi02}I^jxdb2jT_-})KPqY*P4<@@3N_C^}&nuaDlt9kRq+3 zgvSsB+>>jUQdqL_d)*xadkt8-6ro9SIDgWlj9$@f$a+#=5#}Li+@6}ho!!2c?{z3@ zM-;vDQn5g**GR)x%)Y&Sv9Gn4e1fb&3a)JxLrJWSFwBGsRqhLRi9SVt(>8LuRJCAIaq`zesNDag?Z(vIJQq!UXEpM0)ez%=97lG>4${TPH9y7tuO_EC)Sy0#J4 z9e3euWlYo8u?eaPjk~0_LPT$-Za?OwQUxY zlFM79l)3vRU?o|N)2B3?K++yyWik*%8dfxFSw>Iowg^=s!dOJ6CEtIG{75?YM-$9h za#MShq8U;c|J00JnvsW+a~Ix6C|#(37w=F+GO#pH>mcKhQgk@V;U#kgg$KzCL8O)j|< zF5<jzu|eZLGu0mJ?z5M~Su z5o#dRK&XLG1EB^&4TKs9H4thb)Ig|#Py?X`LJfo(2sIFDAk;vpflvdX20{&l8VEHI zY9Q1=sDV%ep$0+?gc=An&`J%&KG({t&-2=}Vn`Izlz5B80QmZT!(WBq{t|a#(w?-i zWGzWWo9|>xt{h(URjvW&0)Ht0Uz7p_dnsz{c7NHVR9aaY2>qc3LJhpCG_bmj_Rfh{ zmF8;~Hr#(wTQ^}$r~yv{Jv%*L>#=B9gtq&LWy6w(jQ-R>*q`{*ZlTnn20{&l8VEHI zY9Q1=sDV%ep$0+?gc=An5NaUQK&XLG1EB^&4TKs9H4thb)Ig|#Py?X`LJfo(2sIFD zAk;vpflvdX20{&l8VEHIY9Q1=sDV%ep$0+?gc=An5NaUQK&XLG1EB^&4TKs9H4thb z)Ig|#Py?X`LJfo(2sIFDAk;vpflvdX20{&l8VEHIY9Q1=5H!%M3SrhRinPC~zt~%w zrCnkSMxWtsA(*VAc~`I0`pRrE?_+*!mxPM+qxZ?^bnNJJDduo!>7k{?P|$oOHkx2} zm4t#;P#=}YD%K3xq$K2{GK8Xr8VEHIY9Q1=duiare{TzU>I~Q0LcUOlSGfk39%%~& zwD@tbEp!kH5o#dRK&XLG1EB_*s)5*lH#NH!Wftsn=vt)I@Uo!>LJfo(2sPky4TOEX z&kY!gA8H`fK&XLG1EB^&4TKs9H4thb)Ig|#Py?X`LJfo(2sIFDAk;vpflvdX20{&l z8VEHIY9Q1=sDV%ep$0+?gc=An5NaUQKyWoMuy{q&n-on(nA~!_c-IYc4mHqp4J=|k z(VGc320{&l8VEHIY9Q1=sDV%ep$0+?gc=An5NaUQK&XLG1EB^& z4TKs9H4thb)Ig|#Py?X`LJfo(2sIFDAk;vpflvdX20{&l8VEHIY9Q1=sDV%ep$0+? zgc=An5NaUQK&XLG1EB^&4TKs9H4thb)Ig|#Py-EWAl4pd%Qh%&O}0RtP20DlW;xqC zLbSJdp>)C0KMUNt41!!cifVM$7X3c;3COKKx8u_SREq6bl@x!3v;Gh>lrq#n zsDV%ep$0+?gc=An5NaUQK&XLG1EB^&4TKs9H4thb)WEA=15R74_{h0-@NlDMnJ<5% z`G$O<20{&l8VEHIY9Q1=sDVY$z|KX;^Oej}vfwS8IPyv=uxZ!wjv#7UhHaJ6m2D-> zyo4!xwBqwh+Sbf{?`>=Gst8wRi7N5_C&e!FT^T&1aONMy06Z z*m*_2KYS5$+3#BsmathI0?VX7q@ItIv9ssH-4486@4woLI%_O7>owL65;a|hpEo_n zMb5Bq&+dEIZ(YCM-Wi|dV-o?aC(e>ZR$v`D!-|(5GFQ;!7sm%#b9)8D6hK=R_gnjW(Vm;#4HWzmx z;{EMH616f-YTzCDgY2Y}NQT%qMnx-SS)6P4y<>6mUA$bUbMF{@{a>AQ(i3lpW@6vC zbzqBP~hGM`Pzo<1}hiDe!WD$eHWDkeBsSLewpnHK^H8f z|K2lZAOGXg1sB&B37unnA!dn?)1zlUUJ?wV*LUxJSyWdOI}LLf%&{e5hi2~s08Ngkjmu~kc_i_b|0k0ra9Lzs&~mSCVWzcM#Q|b5vF$Gkr0HFF!5<};kVg< z!QtDFUr?ZL#&;z#(4RP>AhxO~!fVb7WIuaW`$>4oQ8y%uvPlV#X9rW5foi(?R{F*! zj_S$#jf9do1B*}6gNhKl6Udc@E@JKR|5&xcX6ZSL>K_K*jJqs{8!U%r zD~Zh~1|Av3$Qqc$=Bft(;{{ek2ti#vY6{$ym>Uid^!=lM3WFWky_f@DbM`vxoK0->+sRWm45P9{H%NnH zemFQV;+LYBmSuCnnGt1MqUPI#u_2YR*Nj@9WGuS#ya@M8IU102R|7n4!D5bWv6EZZ zvcBC{?7r$a?CBK^A~gTv_iNT?`GRJ55~swuiq1UDtF}8 z(R_ex!hACaIg$O=zkhA*=TCbd`#Kx_m%krR!6t0#b=ST7-7Gcw_*j72F5Gm!16z>D zoY5QvXDsC;8B5^NF);9q|4KshD~xT=rePDCU51w_Nh?kt#0dz*-tD)7+}C^XyeRwK z^9IKfyNspX-7Lmp|KE-eeBE#5s4Z{oziY>}XUz1$>4VX!93z`Bws~_tHWtgWbJ|nb zg-O-3uw<=E_0af337+_F`tlV;}B9G4DCCPQAEFt*V`*T0Z&LM2h71;KgLPpdeL7(rw6-CSJ zXhDQiG=r{?#jwwPv3vbefPxJoSl6|eTN2A9ScZK}jfjgIAN*3BI&${Ct4?H_Mmd(C zt)&xKCk(@|QS7G+6!iIKZ7S5B#ZR)&NQs4Z`kWxP#^Ov0w#p35SeUWC2Yqyl36j-B zBSsJK2IEYqXC7EcNQw#wIKG_M%s{6K?bOEzs3YP`2&o-0t1iur6ioW&+0s>23h?O z9J{tmwk|I3NiDD+LPP?3dCEm}UeGl*tFy%M0Td zrQTq&L~kdHj`L*H92pt+OF8D2vv1$rJng{|G1!2Erb>`F>&%YGhEwCol(pS?dy0!* zGeG06*s}J}_}o%#ToT#1!ZgjDo6bCR;h7hozi0QRjW>?1`Mn!IaKjZ>ZN2Ju=gz?| z9DOJFMbeGOL^t*_Gjhei`p;i{=Ed*(>c%UtKl8d(zw`W_-ESV={i7TFQjWRhbgrG7 zr(HPyQ$3;FapiVwzdq@t=(cxsi$6Br{`uU6nG;T6z8TZctxe~hbMv$d$7)WJ&_uAZ zN%S4vws`GtUuWm0PB>vKPjSJ3*ggI!N9G{O%9X%V`EA?Yv02>uxqq9={e0b6UZ2;f zqWteX?Vlp7Qsmzfy`rQyEfly-}0CCR3^u!f@BjPp0AT~@JVh?`xsBB`)MfK zn*|yse=s2CyYsZ5ch%Q#XL>&)-T{wdG7^uIfdNbz`2!NH^9zs^d*WlUO!oJa`}cRg zFgTby((}|HTC%Ai_3<>d>I;x;7xph6$;So<2eUkD9zIMq`9l7grv~#=`9T;aC=mM( zzm(*OKXvN~i^a}KT$#IIYiDN+y-H698^iO-m|x1#fSkUWC;C7CE0NIkgynfAF`3J~ z@Iovf+xARH9ySS7J-M*~yR{jM>f)Jwv!I1{0R-pI{8y;6T#-3p?|ep=76jyBV2_o|$q6PP#xNVgDzDbb)9fqvUEb^*7d^iW%Sgs1I4%T?vxC?Qnxg`{dp8tGn@ ztMA}M@m&uBJIj)6os&tbP#~N>-<84~jWWxyZF~7>#CgxSZTB*37(2CmSCETgO~qY+Sbe@*`)nIoJd$AGg+)a8fJDcD&3brO*8N}9s?lHkKz9LI{%XL1A7$E!~> zw59HA3T17v)-8#gy22h^f6=CsPabCuzEw}7v7mteo=@zpA6mWsg7xcnZ+dz6hjxGX zEmto){$eY!;@qHE1WTg-&2ME{edg{6*<|bcUb+f4`P~o2SMNSA(&NAJV@<`!-c~cJ zT_XmMpSUD@D8Z%@ogY|xitQZR;k!PuzG`D%sUQFUw|75ql3ev+;H!IjcY8;po!0JZ zcLD8gGf~j87DQ&T<8uJDbc-Yta#>@oOq>L*33iBVW8(;f`6J4*KE7omJ3^8DQNZD| z(ZxP)eK9^9JJ`Xn27Hz=Ib$a##N3%bPR%EyZSXJt^6&m`@uJ*TL?7PP+A~=B z_S=s{=O0*kcW9H)A0>`{?Ss+BW)Q{%t33W)6D)ipMc;n=Psi00=c{M0ti0!uci#F9 zPd`3yZ4#C5`}n-2L%+uCno2!<-#AZ0qgmdq*&W&>{2#^h^x-6I&vI#g%QpYp`L*^zZNbsU+t6LYsW(g+CKrx$;D9 z>EKay-1BEZ5L%X7Qd* z+vLB!{K@bCzaE{hHfelgxmqMdyStTyymnqsZ?mto=aa-z5B0tOv25|bef2xVx331C zkIS|ledCSymhOGmuMdQ`!|CLlyy#ueu|B_S7`E05*zps>pJ$NY7eUQnut>j0z zms@43)2$^AuhGc^9VbenP_iXIN{heKN=KaC!4fNWNuS-OoF6!8Ap-&Y?G zimyjnt(6|LnjxuD3Gaw2(V?*a#9?+$hUJ$RZ$ma7hE|uvX{?n>_8GqVaQNmos+>;` zWZ7qx;%&=TB3jp&Qls)=F|F$(~E!nq^31uKU>IV=izE#ckYAx(mG} zJ$8jBG=>M%gr{rmiVlbLR(GB<&+VW6_okcFJn`&$+zjL^Q8lhM(1|`a?<37vkt#n0`E5i)^l5k1WHs zj1c2zN61sCEH7z15Vb1R5Yzr6;SAq6buu~^MdzLWcOs?q3 zlzh|a^scUp2b)nn`Se(8UK1{~g#YGdSpJO?Zc4Qpo{k--fw#ijuX=pCHAhX7Jnp+> zLwKuIOMbsAe1;DVlKu-j$?EeoOSUb&!#)1q-ph--^yLqoU%Bl>k2rltts1U%HKKp|^!TyH^Iw^MWSMnr7G&X=6Aj0^|$?{m)-e=W5?cnXy5+UpT6k5Uq5#L{a+i8M-fVClcqr?Ae4oJdrWH1&gAOzI)}qGiO#x_(xg(;qu=Ve!Az z7NRTZGwI5>=__;ACgr={b?I|AL|?e) zo{xXxN8bNCr=$P;&!aCz(T6_t6E_s~Z)gi~ggsZoKc* zr@mVKPhW~Y{NbM{UBAr!>dXJEe_F9q>T!s#63*_~I6dDNJK~X}D^dTG4cnBoM)G{d z^T{~;o0DN*at~qAhxGG$dh=tCNaG&MO1|itLd3tYjVO}dCk6r&6*&Ici55SN!jl{8 zlkex}W@!9Q*)}C!eXEtlT~BU;oU`FrcsE)2VfA8G`7!HKk#^^ zdi6@wOs1>hX72Em#;~wCPv?`8-6IhWR$++4fA!PV)>4>GziVhk&03l=7ca}LGHpiO z5$q%JJEC_-m%@@(XqV*FKQF`aGX36YICZp=U-qc(kM<|el#NzuH$~B|R_%^jvpFv< z61L;svTRFhF`WIw=flS0(wWvuD{3v=@vNwMx^c&?;a%4^mSrnOiF5g(QF0X_PuNKs z&FsdZG@NI~CoW#B)qeb$jb^j*;2fP!qQ)ad@E$FOO8Bt2(yWB;zTpG>iP}w}mE!PL zI5bqF693$2Wt1UTdEN_$76^TSqU`@bo9r3&Fc&_wv})0VWxyUW#^vyJb~%Rp=oH4u zWGlSZYmG{+R!`m%hnAU}p*-i4@LbWdpn9bF?Jqs@s(SRC zSIyUs2?FKSd9t#D|Ym!Ukr`F!tU z_1?QqeEaU#@7wqKyH339&fDH{SsS|mJ^=EY^%mU|Z$ zlQ#K|&?Y~8>&chh`JxxS`Q@*;>un_n!Ql|M!oSWjlt)xm?2I@CUw_Y}e<$ zuyp#V^DFl)FGu13GuycvX*knVb2R>+sa7|Z%AQJpbL@ThEZz6-qtLhX((>8mD|gRP zn~Vi%+J#(9D!jCK^L=lL-t(TbSC-G7I(zq*rya!P>RW!-{d!)3?tJ9p>PI?n8WU--m$YdSp_FUS9Fc{gMC9ZBrp z9sOu{ADmoenU|sQ!Ln@0rSET^{KUokFTUXqPc7H>eDyiIo{V<=%tyZO7k5SBCnV;n zmsW|Mnfb)$e&~%)M*pt)YmY}~pZ}M?6772O(ylAf*FuXtxqSA9kA18xe_O-jEYEMF zUpoJ~x4tp{v-re?D`&s*)Tg5_fBDLL-W7dcbo26)SFYS}CH)CfU{k1joaYWX9-^@GvE!rAvc_0W~pP0PE!bm@k5Ka5kBjS^=$1nPT#sT_gs zpeWU?a;Ty4d7Onz&U z@5;l!hm&zKwK|{9dD$p%{AV{VE60+!8K;3Z!)x+yeum@Ob-Yq;P(6+Mn&g23b2Ti? z{I>`5cTekBo9pH`%qB;`blq^*S1W6t4SCAB;F^yXDDKwQVws~`R#JdQ`rY={EM~J- z-U7|)T0fwAGdh>tcsD1*)sy_al~#(Bz2;usbNSNtxEUssf5V65;1x$vxY@ok;u^!t zEJlu>E=Cw@Q8dF;@~`iZ?Ed1-uS zSvMryRG)_aywK;Nd29AjrL5bsF7EGIH(#RJ^ygMWpVP)Sw;EgC+lsiouPtIwBgWJW zEm4W$>q1Y*YaSeNoib$mt7QnXSB&9PNobI8edYOayi|YU8++v`=d$B}R?fIPqOKYR>#x>ZSwlyTbBs^i3*B!sp)o`Ac6t_l3`uBwS&ZQlN2TDZ}mz zI(#%){VJt%X^E#BuPAHqXQEab`hSj>&%Px}AIn_UO<5QB@sF-sP@37#L?2IM{jbrf zD^Dg*$)1~`@tU%3%Ab7o1D{G_|G|sPXTSKV<O;`mFz@0O4fMpUth+Duj#^9bu%Bf8^fG6O69j^-Xg03tif*n*fn35R-z*P=JOp%XOeL7 zD(p6!`Fefx2fL#D8TN_e>RbCHOnY%F>?hS$_otH0w9K^QonU=O3(|Kkp5Qi?t?1)F zSDc8etq@By{M+O?KUrm-hW$%3+nPA7IeAT|(w8lDS!jhK=4n_uRE(`j9-Wb#;kRZXU*_=2$Ft!>!9->K(T+KA9>@}Sn^fF?$K}8fQZJ`LiWgBNC)#M=7%%*qp zYbE*1oXrrY)n>2V5hQ!c=)>BF&CypWcFx&9$F!b2C2RFOQVBn2lYS_vZsNqUxfU#T zbEMH7o%ywulr-Glm6?Cfn4Cf?9a~=6o7@}J>R2*(G90>+ zZgg`r9Q}jYZ%lGkCH*gi(oEiVZSo9}w#Xbc%f9cKeVb(ck}jNFIbW~U-WJstt6TY$ zQh@CkR|u;|@^KZng>tIt123!5qmPE?!M`mO5T5e4qlcxxUVzPiFxpjHh^~D!Ij=No z)uc@x82Q~)vQLG~Bj+!`_6`YQ`FDn7n0#`zwwS!j3dgSSD`^L#g{3gNnfJo;)Euey z(n}|gKDdU(-3NcNx~H~q;e)?Yz2>^3jXnGJ9ok)eVB}+JEp#)Tv;E}f2a8Q1wYocN zlbe6#!c~ip{^P?xxo>}UGi?%fs`+Y@tN*_#s1K~-)K{|P)8F%t-Wo-Fmc!f}-TOOm z)B7YIop~SAQy*!ylHg9CJr(Ya50Af$uI%(SnfYhNQyTUOP9|7%9Q^@#$6KgJLa{OK4A+hS4KW#CJf?#tTb z>}K0!af|g9b+!Ek2&}VBqUh{hr$+t^p9MchKkJchP-9O48YK-OJ9dRO+4QmN*Z*Zv zwqZf5vLozi|hDgHnImm$!{M-U7mb?6x>udJpH89XiBEo?o0T4_6Yy z(C*Ke?<@JZccg<;d#_XMrTY#}Fuv^j!me)(2fWQ~u13;|TBF63wc%WSofS5`8XbDs zXxl%%T-o3K=zsm$ySC}YH~E?>lYF*poW`HM4&Rh~e`=;#v)6%Z<+rL-=B!zc|M|ep zo=swFlfV9yH_mLL9eb^fzdQCKw_ISgm91J$&T(=3Hm^C`4YG|K@Otzk0}`j1RBwhK z({5Dq`-GDpVcDs}fnu~tdh`h`(sh^WXl)WFyVP6_`wkaobK=58GV4J8+N=XutAF)O z-CSF+QzsTaS%@uPd*`$^QHZc+6U5PX&ZgcCwbq;2Sv`4eZb%)lVC0Ye1Ij2?Qe$6X z;t40~X1H9^Oy30WN%CYOgv^!%G&06CW zCA2BW(fBJ|1OJ6ZYL(n4q(>N%GnZ{|0=~QkaM*6v)1BolwDB zC^mhLTvXntu5DqHd#itIvjgm zQ8xV1@Eo~hxMnfEhi(UdRykIf`&N=RN%oJ>Cdq!XgU|8DzOg|2$-$a7DN1vQg8%^n z1WGS(tT^{Up2_+(ep__#eCb)Yw*lX^z17FMc6vcL+zxriSW7KkVf(TVY6Xb<^yyR2 zO2XKGQ{`V5Ae>o-FuUL3?z7eVZ+hO>`y}m<#n~~u7#n*!4dai#w$s}rnq>czO*Qqk zQFiS5qp$7sW7odI{NBuJf5zsf8gec(?>kYf&8ime{5E}`h0D{cGhAWZ(y-O_wp3XW zR_cCQ(hMW2MTP0AKSKpo7gJzg_$Bh93_JMi-mWG%_VljV8P4puvqoR*eb@I*8hb)| zIjdi(t&p&*cjCbHdaqLIrAPm`AmQ&c_yO#V#|9)$Dyh|3aMw&{!j7H3`m+VubSL<= zhB#1=Yp_kX)33EjqbPr$h4~(5jb>&OM_)ICs#~3PW;4ysMLT?YUtzATgswpLmGrOi z>OU#SA7xySI0_I(alSuEF?>o149ALcj!&ATQJ611(?5_|y)^#9tZLp+Z>u$D&sp5C zg(EK5_e~>aoOrfyUsw3QIq`amUqR!AMTxPN^$9A-^X!YFB93AR6zF|d97omqPVUE; z|3w_TDxaG5xEYRJ;nxRe9Yz7_FU~UrninoK57isaC($&&XB_+|c>RS72Y1&Cb4_$` zuu=&SAV7dX;RW{fxqoN+f#2fW-&OQu*G*r)ca1)o#m?VekwPi~FL|0Ppvx5_lry0h1Ga^TCT`34qJ z{KRUs_g9M_Ct_o416tCg6i8d*oKsh72xXG|Ln}3tV%T8cb;P}eqDDtnc^6^@S#;z*YQdg6+ z{*3LVU735%Y$k8d0t&Y9y6dMKQ2w>%!YI`?2WQI58l0pRr$ zCp28XowpF%vh5%m;aSwv9QyRH>)q2eUD{`j5Oh~cJk70`Y+c9y!(_{!TIs!8b!yd* zv!cdh<1DSato)dgk9&8rUQ6v>*&G1^1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7 z2oNAZfB*pk1PBlyK!5-N0t5&UAh06^YB!E)vpYH!c1)&)ub#K009DXCot-HV$^(d2V{c?5FkK+009C7 z2oNAZfB*pk1PBlyK!5-N0tB`u(3r^$p%=FnthETtNTBk>7%R?iGVLm|y)c^^?{k3K zrFT_Y>X~cKO*{N*w1vZEvuBjOm-ftRA%X1(T=RFfv-XJVJ{vJn_vV65l(o;S$17iLrIpJ6sU)^-US^A1YenA;KpTN7xswzginR=#dN-bPVY zB|v}xfpQBtpOm}(L{ESK0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs z0Rqz#*#Eu}>+0w@*fH6$@=~LJ5b=N z|8)!--5Ns~iXcFM0D)2qIG>cd`2jNTAISNAhpO z(7%^tM@n8z23x z0z@1aAcg{ku&HzWkWPbH@}!@?m0IjcNIkY@E-ntzCze#snrTaLo%QT)~Fo!&4O>Ubisrn9ui_ ze4HmG^Xr%8X~qO5EYNk1U)O0cpY0xJeGBttql7mo@5Z!zNjA>sdet*1tyg}_2oNAZ zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5;&f(UeU z{Og!ZgFF1bJjVXdKll?QwTGoy+@|+0NB|Ze+i5I`fu!x)HifZFgAMZUNTs z5?C7J^BMKg>7q45fWUSIIu0rwlWD2XSo_U_{?9<{UZ;P)VPSTc)6Sig*e|V}D_YAl zO5V=(OcNkLfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNC9A+YWy+kEz_ z2iD(*yZ-qmdCrcq)=dt|u`w-Ql8@IF)-gLQN1mRKJ60|AWaZ5T48PeKQ+QrV=X~dM zXSO+-ULNE9!qa3)o@~>3?_G~4-Apr_vDS6X*T!1hcna%!&PllOzjJT%a`QijqBt~hUds~j+!qo*Or*i}k^009C72oNAZfB*pk1PBlyK!5-N0t5&U zAV7cs0RjXF5FkK+009EC66omA*D=`*0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7 z2oNZlz`9O=`E2(%>sOdBOSbU9hdbwbZ}XrWgVK7J)?S*dyVRcDFqM~`k2hqP(*?^f zF5!kXOBnMeLO%Z6o5)72#)P=>52p_O@V0C0d|qQH%(EG{ExL0GSl0W>6>uar+n2*O^fdUB-AV8pi z0++`gQ){)vd_49F6i9#o0RjXF5FkK+009C72oNAZfB*pk1PBlyP(Xo>8)iEuI|A+h ze39<_8}luFs9j8V-uCi*s$Y6iYQMC6-DI5S$;X{(qfc*d?a}LzlR$^SLdWzLC%1pI z=@u)V)72JVvT?&49X6U+QUZaF8)iEuI|A?je39<_8}scx-!3N4n~&Qm*;N1K8_Qk4 zZZe;*pO1Ux8NO_LYY#794gv%S5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs z0RjXF5FkK+009C72oNAZU?hQc9d+{A?s3+yFkja0LD;{B{U-+JYM0f&jP8{Di6%>F z|HVP;=V|%4yPO?7mlGC;pxGTt?=sx$~7phf2mnYvhJYu z^R#?CtUT!i2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk z1PBlyK!CuM1UmY!_3qo(|M`dA`G@E0&L2hl{y}>i*QezvNvZwP@;u2n&y$Zk(?*}( z-rA$rBPRg@1PBnAu0Zd;ef^(**qwiPzV7_p=lJz$`IaZ8_Djq2B;!0!KJH8#eR_Lq zk6w?Q1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U zn7+W(w@$y#wGLe~sJaYQ9=&Y_QMP7K=T@p**Nrcq?H*_S3iD;{9)$fXZ0FsWCrR7; z%8knhFUd>H#`#>Yb@H@)+$&F^m(3{fU9Tv#O0VFW>le<`vl-WKoB4tW{7gaO7(I-& zXENri%-gdWm;Z9UWu+L$vy3wD)z>}F`W5EO+C2#SN7~N2F;9}VbaCVI!AtTIvvEGx zYn?nTANR^*8G$kgJmbf=5oK!|>spln0RjZ(N}%?O+t{4eHrCzRs?)D=YjIkO009C7 z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7CMMAT`G?(I>W1g*&fgBW z-|}l)Nw3KM<+e*`_nz!mR%hP+)7x9Sf4N&vDO%sVYxiz_TdYZdz|IjUT7Sr0I=1!s zmWGAv=kt8VUuRDKx3;QqcUuLrQ;dT+>DJa>Hk2{h!F}c09 zH&KzS1PBlyKw!24NoT)$|L2Qz_XQlDuRDKx)A}#(UuLp)=Q%zvBOkX*-^|qZ*4|7_ z@)96GfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N z0;3D$z53RVyGzJZyO(y(4azYnt+R||I?J1{(VnXecz9fQ?)4>_pOnDy-=0*-(<^tL zp3OKtH8pKUVEKv7sj+@KtT(mKmXrn9{H8tu73 z=lJg2>r0%U`FuNzvPHW#JQuqtkxea*R@4f0CI1RCT>H%h2}BqK2ozet`J`~o<9t%M zCJ_(;0t5&UAV7cs0RjXF5FkK+009C72oNAZU&P>s zm6?Z_kMrW6et$kS>Uez#qpm04juuG1U?2HQ_D1w@AFTZL_I$iP+h&)qU%%h{;kWin znZM=3_V9k`{gzKkXwTxLN>(m`4FVeuE&1W>d{@@$LmWNb-kkI8|^*PG^1~9_-mSG?GvgiPRq^i+nP`n zlPvbYeUmJG>SeduM}(=@J-!N`Grpn&RZujn=26c<)(u|Kt>;R6&3M0RjXF5FkK+009C72oNAZ zfB*pk1PBlyK!5-N0t5&UAV7e?I)U_lutNQm_q8ur7vkK^zP+qlQh$2!ZaJH(Wh?Yp zh(nF%S8vd34X8a!%X4(k4OngDq`dFZ!3zVsV~$*2nKR}V1=)sH^?M2uN#8K4eN(oU zu)cFgBTAO6U)rziQS&A1XL<8Ay65_ppDeF`Y*6Zar)B#`EgE;LZ&R(Y@XOmQVdAUz zc}w*0x{BA&H`mhRwW$FUoyV_PpJE&TWwO$LSxa^uQO|ddn5oiU1Mvb9iF`&#UtbzUe4HZ?4I9aS1VeKs>6SeppoRMH};Q>bo&MU@b-%+ zW(l<;&G6Q%G4zCeB&sAEkbaOU#+DrTY%$`PKore5YBWcpZl0Jx^;<7;_oueLt~Cj4 zP9V;*uZ{+-J3^L0tB*bH+WGqZt`492op;73cGrd;mJWtXFbBIY=XaDci^+xma~8Eu zqt0rxxfq=}IZ{>Ckxn}!6*Y!TjaQAKkU|!5;of^MoVe?`?;aN1^A|5%JXCKK=p)L3 zx&1zVF>8}ij$IFjHVKEYq6~-PqC_(8IBr^qo_F)jMY0}w3-1{@XUQ_&9PK}O-Q|)6 zorc?(+uuh2(lWsG{1n7bP`2}{$P&$$$CKp30Zx<2)rFXUn_ivSou_hv&a) z=ylUUZlK=9dJ(VxX$9c-;^XDZb zHBGlIgf&sbn7( zn@M@$<6}Bbrpqxbyt^E64v(_ZzU4Pw%biXY?CX)W;QCE89`Bb@zU5($2tz%tt%Rf0 z#VC599+sq+Ski>PFWGv1lc%1r`yErSazYh$>?h6DDjJn=UO6A-_uZA|d~*MUh-Ogi z+I|u}yIF~=&FbRf#W>kl8d2IxtM9=!L{_x@3dgNxGA`k8xr8wf3^}a?50~C+t;W)=jp)Z(+bC*At1kS(j4Ga7waw(a+W)sD>YJJbP)-K@6-}3*4pgxvd@@mCVbaqz(LmU#)fdbv*KP1!Z z2MZL;SVE~RWZ#;+{|CPmuiP+}BBxx)!mFlS;nb>o|M!O*iT-@Cgx9+o*G>&-!WFId zUwr$z@lUPJNA(M>lH9^_xRk#V)2n&2{)^TBX>FW*n-%}qZ@2R{+ml6}s$cyBMGkMe zv9(sK%g4iN&-3NuVfjZ*Pwpp}_aV6+*=uO^S~&Y!5JAt5LKBQ5uP-0> ztLm!X>6cQX<#E4Q`|Tn9@)u%xW7p3YB983^(dt}1Ikjj1lGkK9xnDS&P8SsZ<=_*A z4{^i*!_wH5vk?GZ*vo3vKPVY2TKucqYVz8Tl$8+ZQQ|HH7FOO{?q zS|EycN44mVq+LRb#MLN{N^}@o__bsU=3}S?_-eXWByEzk#_C+SZeOY)?-X0Apoay! zx>IDMILlq0hB^FG!?v$9>CM{3G}dN%H6@Ok;lFeUt+Cojakik~uM6K<@Bp_IUM-wW z!iANNb!%~n_LI+d1YYvVM7>^3cZoQ;99(-KoZ3TMJeZtjR`--LY~sQP%Mj%#F@}C~ z>3_9mIu$*XjMJeS8Y>P{WoeeiZ)I_p|24eFdf-Q+N?ZvI5T-*TB)=vR-g||qv`N~d zFjeHC@#-Q+x0%>hcHh~ITIa&=-Xueqj2huU7KiC-Gm1W*?j+^dQ)-_LLC?idxheVF z9-Xf4kLtB>neWHLR)zMdJsh3?NSJIz)#Ml!m7rPn?3;@Q2^(=S4m(HnmTL4^f!9sY)18T9NrWM{I%oM>Eya(X@p}J|9!mcD~lKYZMFXK+YT;Xcr>(03HFo2KRYYK zao78_R~&oU$sc+DUthfcO;&z`LQFg~?w*Q{dMX1#m2xqe|*Put|nd-j~Ya$k6^^q!~gzWY=; zdpe{)!&?~EZ3S}R)8BFT@|8VLC2evljPJht%9U*uIJ=eSXFo~WWO>h1VehyS+QhMI zc7IcAHQy37j?`<>ZOJ$+tlje9k(Vu=u74X6}^Zr-&k^oG9@or=z;S(CHL zmFUWq*6HZKM3>HA{&HE`WX~@T+0@b`f78vU!g=Jr`|iH`=9@d)B)ayd=u)&2+GMFD z`^n*dSsL^qf$myf{XDX^pDd;O$*JUQvK&QEd^P;A^`^n|Y z$+7G5$HG;}C&Lx5FNg0}N-^wtycA(>BFNoSK11Fy_WBNf?S1PBl)yujM~pX4z#*}V~kkGW@njXCP4wYq_|^t;4r(lCuuHqC** z)w8L}xUkl!M{zT`e<-v>nRk@~pD!bSub4w?tR1~VdgpYn>;+!7@J|XH+~z_Hteh1*Z_{#fA(a9pn7JEC1E(S5WXVGo!Lw>~DR$q6NDCNHHM4t#6r zLLL@yJ#=aej{|%lJ*AZKv~nO^#h#O4v00BUG|Sis>l)xd_C4vkrDdEA50VYfH7ntx z|2AMB_!}D*m32Wg^p0Ce_LH*jDvcY<+5{WoPMab(0EsALLCxl{+(7b z4)=K_7gkC-9QgH;2Hqp=N+Vp~%331-oYEs#@fR(;wD>WKu)G4zEcBIRl%7|z`Ki2) zv%bS`n@Y%2sH7S-!<(*Wt|YJNC;2JVIhiUNk4&cA>6aSb3a8gn(jO+Ohxc90>Blgp z8b3Rxa%Nu4O0?2kss4qPm6foc?2T?IZ<{>(6EnvgQvjhcR#uwNOxmPct5>GHpH#-Q z6-hCNKQzX|6g38cYP9!P$54zS#vt%uC?olmp3o-0G=|~|QN%m{L--!+?%#VVioWl* zaL4utF@>K7*!@ERBFUOx1sJeeJ^GYl+!Z>^FFY2uB<{O4T^&}M(PKw`?48jcMvpx5a3lNg52J@0 zPn>+XQET=uqi^Bs5~|63oGzT3Hc7X}3xP=p)aU1XG6^1K5=aGFdw+#Q(FFGWyP`$3 zA)a`{lKEcH*z?N5Z(ytN5ejg)K>8_gc($VESSbE}vQ@g$w# 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + { + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/project-spec/hw-description/ps7_init.h b/project-spec/hw-description/ps7_init.h new file mode 100644 index 0000000..94d5e48 --- /dev/null +++ b/project-spec/hw-description/ps7_init.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 766666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 127777779 +#define WDT_FREQ 127777786 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/project-spec/hw-description/ps7_init.html b/project-spec/hw-description/ps7_init.html new file mode 100644 index 0000000..92ccadf --- /dev/null +++ b/project-spec/hw-description/ps7_init.html @@ -0,0 +1,139986 @@ + + + + +Zynq PS configuration detail + + + +

+
+ +
  • +
    Zynq PS Register Summary Viewer +
    +
    • +     +
    +
    +
    + +
    Zynq PS7 Summary Report +
    +     +
    User Configurations +
    +
    + +
    MIO Configurations +
    +     +
    + +
    CLK Configurations +
    +     +
    + +
    DDR Configurations +
    +     +
    + +
    SMC Configurations +
    +     +
    +
    +
    Select Version: + +
    +
    +
    Zynq Register View +
    +
    + +
    MIO Registers +
    +     + +
    PLL Registers +
    +     + +
    Clock Registers +
    +     + +
    DDR Registers +
    +     + +
    Peripherals Registers +
    +     +
    +
    This design is targeted for xc7z020 board (part number: xc7z020clg400-2) + +
    +

    Zynq Design Summary

    + + + + + + + + + + + + + + + + + + + + + +
    +Device + +xc7z020 +
    +SpeedGrade + +-2 +
    +Part + +xc7z020clg400-2 +
    +Description + +Zynq PS Configuration Report with register details +
    +Vendor + +Xilinx +
    +

    MIO Table View

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +MIO Pin + +Peripheral + +Signal + +IO Type + +Speed + +Pullup + +Direction +
    +MIO 0 + +GPIO + +gpio[0] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 1 + +Quad SPI Flash + +qspi0_ss_b + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 2 + +Quad SPI Flash + +qspi0_io[0] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 3 + +Quad SPI Flash + +qspi0_io[1] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 4 + +Quad SPI Flash + +qspi0_io[2] + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 5 + +Quad SPI Flash + +qspi0_io[3]/HOLD_B + +LVCMOS 3.3V + +slow + +disabled + +inout +
    +MIO 6 + +Quad SPI Flash + +qspi0_sclk + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 7 + +GPIO + +gpio[7] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 8 + +GPIO + +gpio[8] + +LVCMOS 3.3V + +slow + +disabled + +out +
    +MIO 9 + +USB Reset + +reset + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 10 + +SD 0 + +cd + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 11 + +GPIO + +gpio[11] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 12 + +GPIO + +gpio[12] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 13 + +GPIO + +gpio[13] + +LVCMOS 3.3V + +slow + +enabled + +inout +
    +MIO 14 + +UART 0 + +rx + +LVCMOS 3.3V + +slow + +enabled + +in +
    +MIO 15 + +UART 0 + +tx + +LVCMOS 3.3V + +slow + +enabled + +out +
    +MIO 16 + +Enet 0 + +tx_clk + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 17 + +Enet 0 + +txd[0] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 18 + +Enet 0 + +txd[1] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 19 + +Enet 0 + +txd[2] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 20 + +Enet 0 + +txd[3] + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 21 + +Enet 0 + +tx_ctl + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 22 + +Enet 0 + +rx_clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 23 + +Enet 0 + +rxd[0] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 24 + +Enet 0 + +rxd[1] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 25 + +Enet 0 + +rxd[2] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 26 + +Enet 0 + +rxd[3] + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 27 + +Enet 0 + +rx_ctl + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 28 + +USB 0 + +data[4] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 29 + +USB 0 + +dir + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 30 + +USB 0 + +stp + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 31 + +USB 0 + +nxt + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 32 + +USB 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 33 + +USB 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 34 + +USB 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 35 + +USB 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 36 + +USB 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +in +
    +MIO 37 + +USB 0 + +data[5] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 38 + +USB 0 + +data[6] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 39 + +USB 0 + +data[7] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 40 + +SD 0 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 41 + +SD 0 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 42 + +SD 0 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 43 + +SD 0 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 44 + +SD 0 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 45 + +SD 0 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 46 + +SD 1 + +data[0] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 47 + +SD 1 + +cmd + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 48 + +SD 1 + +clk + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 49 + +SD 1 + +data[1] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 50 + +SD 1 + +data[2] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 51 + +SD 1 + +data[3] + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +MIO 52 + +Enet 0 + +mdc + +LVCMOS 1.8V + +slow + +enabled + +out +
    +MIO 53 + +Enet 0 + +mdio + +LVCMOS 1.8V + +slow + +enabled + +inout +
    +

    DDR Memory information

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Parameter name + +Value + +Description +
    +Enable DDR + +1 + +Enable DDR Controller of Zynq PS +
    +Memory Part + +MT41J256M16 RE-125 + + +
    +DRAM bus width + +32 Bit + +Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
    +ECC + +Disabled + +ECC is supported only for data width of 16-bit +
    +BURST Length (lppdr only) + +8 + +Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
    +Internal Vref + +0 + + +
    +Operating Frequency (MHz) + +533.333333 + +Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
    +HIGH temperature + +Normal (0-85) + +Select the operating temparature +
    +DRAM IC bus width + +16 Bits + +Provide the width of the DRAM chip +
    +DRAM Device Capacity + +4096 MBits + + +
    +Speed Bin + +DDR3_1066F + +Provide the Speed Bin +
    +BANK Address Count + +3 + +Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
    +ROW Address Count + +15 + +Provide the Row address for ACTIVE commands +
    +COLUMN Address Count + +10 + +Provide the Row address for READ/WRITE commands +
    +CAS Latency + +7 + +Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
    +CAS Write Latency + +6 + +Select the CAS Write Latency +
    +RAS to CAS Delay + +7 + +Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
    +RECHARGE Time + +7 + +Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
    +tRC (ns ) + +48.91 + +Provide the Row cycle time tRC (ns) +
    +tRASmin ( ns ) + +35.0 + +tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
    +tFAW + +40.0 + +It restricts the number of activates that can be done within a certain window of time +
    +ADDITIVE Latency + +0 + +Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
    +Write levelling + +1 + + +
    +Read gate + +1 + + +
    +Read gate + +1 + + +
    +DQS to Clock delay [0] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [1] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [2] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +DQS to Clock delay [3] (ns) + +0.0 + +The daly difference of each DQS path delay subtracted from the clock path delay +
    +Board delay [0] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [1] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [2] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +Board delay [3] (ns) + +0.25 + +The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
    +

    PS Clocks information

    +

    PS Reference Clock : 33.333333

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Peripheral + +PLL source + +Frequency (MHz) +
    +CPU 6x Freq (MHz) + +ARM PLL + +766.666687 +
    +QSPI Flash Freq (MHz) + +IO PLL + +200.000000 +
    +ENET0 Freq (MHz) + +IO PLL + +125.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +SDIO Freq (MHz) + +IO PLL + +100.000000 +
    +UART Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA0 Freq (MHz) + +IO PLL + +100.000000 +
    +FPGA1 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA2 Freq (MHz) + +IO PLL + +10.000000 +
    +FPGA3 Freq (MHz) + +IO PLL + +10.000000 +
    +

    ps7_pll_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +3 + +300 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa3c0 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +2e + +2e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +2e000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock and Rx Signals Select +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a01 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +1 + +100000 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +0 + +0 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1dc0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_3_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +270872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reserved_reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +Reserved. Do not modify. +
    +reserved_reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Reserved. Do not modify. +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3f03f + + + +3c008 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQ pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +Drive and Slew controls for DQS pins of the DDR Interface +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +Drive and Slew controls for Clock pins of the DDR Interface +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDR IOB DCI Config +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
    +DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
    +reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
    +reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
    +reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
    +reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
    +reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +reserved_REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1 +
    +reserved_VRP_TRI + +2:2 + +4 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_TRI + +3:3 + +8 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRP_OUT + +4:4 + +10 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT1 + +15:14 + +c000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +DCI Calibration. Use the values in the Calibration Table. +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update Mode. Use the values in the Calibration Table. +
    +reserved_INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_CLK + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLN + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_HLP + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_TST_RST + +25:25 + +2000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Reserved. Do not modify. +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7feffff + + + +823 + +DDR IOB DCI Config +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0, Output 10: NAND Flash Chip Select, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3f01 + + + +1601 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +16e1 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 15 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +16e0 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1280 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1280 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1280 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1280 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1280 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1280 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +a + +a0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +a0037 + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +39 + +39 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +3a + +3a0000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +3a0039 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0000034 + +32 + +RW + +0x000000 + +Baud Rate Divider Register +
    + +Baud_rate_gen_reg0 + + +0XE0000018 + +32 + +RW + +0x000000 + +Baud Rate Generator Register. +
    + +Control_reg0 + + +0XE0000000 + +32 + +RW + +0x000000 + +UART Control Register +
    + +mode_reg0 + + +0XE0000004 + +32 + +RW + +0x000000 + +UART Mode Register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    + +DIRM_0 + + +0XE000A204 + +32 + +RW + +0x000000 + +Direction mode (GPIO Bank0, MIO) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    + +OEN_0 + + +0XE000A208 + +32 + +RW + +0x000000 + +Output enable (GPIO Bank0, MIO) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    ps7_peripherals_init_data_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0000034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0000034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0000018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
    +Baud_rate_gen_reg0@0XE0000018 + +31:0 + +ffff + + + +7c + +Baud Rate Generator Register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0000000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
    +Control_reg0@0XE0000000 + +31:0 + +1ff + + + +17 + +UART Control Register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
    +mode_reg0@0XE0000004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    Register ( slcr )DIRM_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DIRM_0 + +0XE000A204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DIRECTION_0 + +31:0 + +ffffffff + +200 + +200 + +Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information. +
    +DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +200 + +Direction mode (GPIO Bank0, MIO) +
    +

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    Register ( slcr )OEN_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +OEN_0 + +0XE000A208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +OP_ENABLE_0 + +31:0 + +ffffffff + +200 + +200 + +Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank +
    +OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +200 + +Output enable (GPIO Bank0, MIO) +
    +

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_3_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
    +USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
    +USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +reserved_FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +Reserved. Do not modify. +
    +reserved_FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +Reserved. Do not modify. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state) +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    AFI2 SECURE REGISTER

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_3_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_3_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CPU Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +3 + +300 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa3c0 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +2e + +2e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +2e000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status: 0: not locked, 1: locked +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +GigE 0 Rx Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +GigE 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Quad SPI Ref Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Ref Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Ref Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP Clock Control +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +PL Clock 0 Output control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +CPU Clock Ratio Mode select +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Second divisor for Ethernet controller 0 source clock. +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +GigE 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Ref Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +UART 0 Reference clock control. 0: disable, 1: enable +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Divisor for UART Controller source clock. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a01 + +UART Ref Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +200500 + +PL Clock 0 Output control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA controller AMBA Clock control 0: disable, 1: enable +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB controller 0 AMBA Clock control 0: disable, 1: enable +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB controller 1 AMBA Clock control 0: disable, 1: enable +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO controller 0 AMBA Clock 0: disable, 1: enable +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO controller 1 AMBA Clock control 0: disable, 1: enable +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock control 0: disable, 1: enable +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock control 0: disable, 1: enable +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock control 0: disable, 1: enable +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock control 0: disable, 1: enable +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock control 0: disable, 1: enable +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock control 0: disable, 1: enable +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +1 + +100000 + +UART 0 AMBA Clock control 0: disable, 1: enable +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +0 + +0 + +UART 1 AMBA Clock control 0: disable, 1: enable +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock control 0: disable, 1: enable +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +Quad SPI AMBA Clock control 0: disable, 1: enable +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock control 0: disable, 1: enable +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1dc0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two Rank Configuration +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM Initialization Parameters +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM Burst 8 read/write +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Row/Column address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Select DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT control +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller 4 +
    + +ctrl_reg5 + + +0XF8006078 + +32 + +RW + +0x000000 + +Controller register 5 +
    + +ctrl_reg6 + + +0XF800607C + +32 + +RW + +0x000000 + +Controller register 6 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown (LPDDR2) +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config0 + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config1 + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 1. +
    + +PHY_Config2 + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 2. +
    + +PHY_Config3 + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 3. +
    + +phy_init_ratio0 + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio1 + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 1. +
    + +phy_init_ratio2 + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 2. +
    + +phy_init_ratio3 + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 3. +
    + +phy_rd_dqs_cfg0 + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg1 + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 1. +
    + +phy_rd_dqs_cfg2 + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 2. +
    + +phy_rd_dqs_cfg3 + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 3. +
    + +phy_wr_dqs_cfg0 + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg1 + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 1. +
    + +phy_wr_dqs_cfg2 + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 2. +
    + +phy_wr_dqs_cfg3 + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 3. +
    + +phy_we_cfg0 + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 0. +
    + +phy_we_cfg1 + + +0XF800616C + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 1. +
    + +phy_we_cfg2 + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 2. +
    + +phy_we_cfg3 + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY FIFO write enable configuration for data slice 3. +
    + +wr_data_slv0 + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 0. +
    + +wr_data_slv1 + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 1. +
    + +wr_data_slv2 + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 2. +
    + +wr_data_slv3 + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio config for data slice 3. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control 2 +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control 3 +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask +
    + +axi_priority_wr_port0 + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port1 + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 1. +
    + +axi_priority_wr_port2 + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 2. +
    + +axi_priority_wr_port3 + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 3. +
    + +axi_priority_rd_port0 + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port1 + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 1. +
    + +axi_priority_rd_port2 + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 2. +
    + +axi_priority_rd_port3 + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 3. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control +
    +

    +

    ps7_ddr_init_data_2_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two Rank Configuration +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM Burst 8 read/write +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
    +

    +

    Register ( slcr )ctrl_reg5

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg5 + +0XF8006078 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
    +reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
    +reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
    +reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
    +ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
    +

    +

    Register ( slcr )ctrl_reg6

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg6 + +0XF800607C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
    +reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
    +ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config0 + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config1 + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
    +

    +

    Register ( slcr )PHY_Config2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config2 + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
    +

    +

    Register ( slcr )PHY_Config3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config3 + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_init_ratio0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio0 + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio1 + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 1. +
    +

    +

    Register ( slcr )phy_init_ratio2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio2 + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 2. +
    +

    +

    Register ( slcr )phy_init_ratio3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio3 + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 3. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg0 + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg1 + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg2 + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg3 + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg0 + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg1 + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 1. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg2 + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 2. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg3 + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 3. +
    +

    +

    Register ( slcr )phy_we_cfg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg0 + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg1 + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 1. +
    +

    +

    Register ( slcr )phy_we_cfg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg2 + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 2. +
    +

    +

    Register ( slcr )phy_we_cfg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg3 + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY FIFO write enable configuration for data slice 3. +
    +

    +

    Register ( slcr )wr_data_slv0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv0 + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv1 + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 1. +
    +

    +

    Register ( slcr )wr_data_slv2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv2 + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 2. +
    +

    +

    Register ( slcr )wr_data_slv3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv3 + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio config for data slice 3. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
    +

    +

    Register ( slcr )axi_priority_wr_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port0 + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port1 + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
    +

    +

    Register ( slcr )axi_priority_wr_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port2 + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
    +

    +

    Register ( slcr )axi_priority_wr_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port3 + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
    +

    +

    Register ( slcr )axi_priority_rd_port0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port0 + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port1 + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
    +

    +

    Register ( slcr )axi_priority_rd_port2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port2 + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
    +

    +

    Register ( slcr )axi_priority_rd_port3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port3 + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 0 +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDR IOB Config for Address 1 +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDR IOB Config for Clock Output +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDR IOB Slew for Address +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDR IOB Slew for Data +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDR IOB Slew for Diff +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDR IOB Slew for Clock +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDR IOB Buffer Control +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Pin 0 Control +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Pin 1 Control +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Pin 2 Control +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Pin 3 Control +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Pin 4 Control +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Pin 5 Control +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Pin 6 Control +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Pin 7 Control +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Pin 8 Control +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Pin 9 Control +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Pin 10 Control +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Pin 11 Control +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Pin 12 Control +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Pin 13 Control +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Pin 14 Control +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Pin 15 Control +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Pin 16 Control +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Pin 17 Control +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Pin 18 Control +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Pin 19 Control +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Pin 20 Control +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Pin 21 Control +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Pin 22 Control +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Pin 23 Control +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Pin 24 Control +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Pin 25 Control +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Pin 26 Control +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Pin 27 Control +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Pin 28 Control +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Pin 29 Control +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Pin 30 Control +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Pin 31 Control +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Pin 32 Control +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Pin 33 Control +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Pin 34 Control +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Pin 35 Control +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Pin 36 Control +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Pin 37 Control +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Pin 38 Control +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Pin 39 Control +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Pin 40 Control +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Pin 41 Control +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Pin 42 Control +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Pin 43 Control +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Pin 44 Control +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Pin 45 Control +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Pin 46 Control +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Pin 47 Control +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Pin 48 Control +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Pin 49 Control +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Pin 50 Control +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Pin 51 Control +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Pin 52 Control +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Pin 53 Control +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
    +REFIO_TEST + +11:10 + +c00 + +0 + +0 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +260 + +DDR IOB Buffer Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. 0: disable 1: enable +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 chip select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Chip Select 0 10: NAND Flash Chip Select 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 0 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Pin 0 Control +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Pin 1 Control +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Pin 2 Control +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Pin 3 Control +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Pin 4 Control +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Pin 5 Control +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Pin 6 Control +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Pin 7 Control +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Pin 8 Control +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Pin 9 Control +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3f01 + + + +1601 + +MIO Pin 10 Control +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Pin 11 Control +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Pin 12 Control +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Pin 13 Control +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +16e1 + +MIO Pin 14 Control +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 0 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 15 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +16e0 + +MIO Pin 15 Control +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Pin 16 Control +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Pin 17 Control +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Pin 18 Control +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Pin 19 Control +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Pin 20 Control +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Pin 21 Control +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Pin 22 Control +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Pin 23 Control +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Pin 24 Control +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Pin 25 Control +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Pin 26 Control +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Pin 27 Control +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Pin 28 Control +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Pin 29 Control +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Pin 30 Control +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Pin 31 Control +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Pin 32 Control +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Pin 33 Control +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Pin 34 Control +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Pin 35 Control +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Pin 36 Control +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Pin 37 Control +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Pin 38 Control +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Pin 39 Control +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Pin 40 Control +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Pin 41 Control +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Pin 42 Control +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Pin 43 Control +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Pin 44 Control +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Pin 45 Control +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1280 + +MIO Pin 46 Control +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1280 + +MIO Pin 47 Control +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1280 + +MIO Pin 48 Control +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1280 + +MIO Pin 49 Control +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1280 + +MIO Pin 50 Control +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1280 + +MIO Pin 51 Control +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Pin 52 Control +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
    +Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Pin 53 Control +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +a + +a0000 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +a0037 + +SDIO 0 WP CD select +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +39 + +39 + +SDIO 1 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +3a + +3a0000 + +SDIO 1 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +3a0039 + +SDIO 1 WP CD select +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDR IOB Config for Data 15:0 +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDR IOB Config for Data 31:16 +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 1:0 +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDR IOB Config for DQS 3:2 +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0000034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0000018 + +32 + +RW + +0x000000 + +Baud rate divider register. +
    + +Control_reg0 + + +0XE0000000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0000004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    + +DIRM_0 + + +0XE000A204 + +32 + +RW + +0x000000 + +Direction mode (GPIO Bank0, MIO) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    + +OEN_0 + + +0XE000A208 + +32 + +RW + +0x000000 + +Output enable (GPIO Bank0, MIO) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    ps7_peripherals_init_data_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0000034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0000034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0000018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
    +Baud_rate_gen_reg0@0XE0000018 + +31:0 + +ffff + + + +7c + +Baud rate divider register. +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0000000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0000000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
    +mode_reg0@0XE0000004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    Register ( slcr )DIRM_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DIRM_0 + +0XE000A204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DIRECTION_0 + +31:0 + +ffffffff + +200 + +200 + +Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information. +
    +DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +200 + +Direction mode (GPIO Bank0, MIO) +
    +

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    Register ( slcr )OEN_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +OEN_0 + +0XE000A208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +OP_ENABLE_0 + +31:0 + +ffffffff + +200 + +200 + +Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank +
    +OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +200 + +Output enable (GPIO Bank0, MIO) +
    +

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_2_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_2_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_2_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + +

    ps7_pll_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +ARM_PLL_CFG + + +0XF8000110 + +32 + +RW + +0x000000 + +ARM PLL Configuration +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_PLL_CTRL + + +0XF8000100 + +32 + +RW + +0x000000 + +ARM PLL Control +
    + +ARM_CLK_CTRL + + +0XF8000120 + +32 + +RW + +0x000000 + +CORTEX A9 Clock Control +
    + +DDR_PLL_CFG + + +0XF8000114 + +32 + +RW + +0x000000 + +DDR PLL Configuration +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_PLL_CTRL + + +0XF8000104 + +32 + +RW + +0x000000 + +DDR PLL Control +
    + +DDR_CLK_CTRL + + +0XF8000124 + +32 + +RW + +0x000000 + +DDR Clock Control +
    + +IO_PLL_CFG + + +0XF8000118 + +32 + +RW + +0x000000 + +IO PLL Configuration +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +IO_PLL_CTRL + + +0XF8000108 + +32 + +RW + +0x000000 + +IO PLL Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_pll_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    PLL SLCR REGISTERS

    +

    ARM PLL INIT

    +

    Register ( slcr )ARM_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CFG + +0XF8000110 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +3 + +300 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa3c0 + +ARM PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +2e + +2e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +2e000 + +ARM PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )ARM_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_PLL_CTRL + +0XF8000100 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
    +ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
    +

    +

    Register ( slcr )ARM_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ARM_CLK_CTRL + +0XF8000120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
    +DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
    +

    +

    DDR PLL INIT

    +

    Register ( slcr )DDR_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CFG + +0XF8000114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )DDR_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_PLL_CTRL + +0XF8000104 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
    +

    +

    Register ( slcr )DDR_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDR_CLK_CTRL + +0XF8000124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
    +DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
    +DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
    +

    +

    IO PLL INIT

    +

    Register ( slcr )IO_PLL_CFG

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CFG + +0XF8000118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
    +PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
    +LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
    +IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
    +

    +

    UPDATE FB_DIV

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
    +

    +

    BY PASS PLL

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
    +

    +

    CHECK PLL STATUS

    +

    Register ( slcr )PLL_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PLL_STATUS + +0XF800010C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
    +PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
    +

    +

    REMOVE PLL BY PASS

    +

    Register ( slcr )IO_PLL_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +IO_PLL_CTRL + +0XF8000108 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
    +IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DCI_CLK_CTRL + + +0XF8000128 + +32 + +RW + +0x000000 + +DCI clock control +
    + +GEM0_RCLK_CTRL + + +0XF8000138 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 RX Clock Control +
    + +GEM0_CLK_CTRL + + +0XF8000140 + +32 + +RW + +0x000000 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    + +LQSPI_CLK_CTRL + + +0XF800014C + +32 + +RW + +0x000000 + +Linear Quad-SPI Reference Clock Control +
    + +SDIO_CLK_CTRL + + +0XF8000150 + +32 + +RW + +0x000000 + +SDIO Reference Clock Control +
    + +UART_CLK_CTRL + + +0XF8000154 + +32 + +RW + +0x000000 + +UART Reference Clock Control +
    + +PCAP_CLK_CTRL + + +0XF8000168 + +32 + +RW + +0x000000 + +PCAP 2X Clock Contol +
    + +FPGA0_CLK_CTRL + + +0XF8000170 + +32 + +RW + +0x000000 + +FPGA 0 Output Clock Control +
    + +CLK_621_TRUE + + +0XF80001C4 + +32 + +RW + +0x000000 + +6:2:1 ratio clock, if set +
    + +APER_CLK_CTRL + + +0XF800012C + +32 + +RW + +0x000000 + +AMBA Peripheral Clock Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_clock_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    CLOCK CONTROL SLCR REGISTERS

    +

    Register ( slcr )DCI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DCI_CLK_CTRL + +0XF8000128 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +DIVISOR0 + +13:8 + +3f00 + +f + +f00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +DIVISOR1 + +25:20 + +3f00000 + +7 + +700000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +700f01 + +DCI clock control +
    +

    +

    Register ( slcr )GEM0_RCLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_RCLK_CTRL + +0XF8000138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
    +GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
    +

    +

    Register ( slcr )GEM0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +GEM0_CLK_CTRL + +0XF8000140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +100801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
    +

    +

    Register ( slcr )LQSPI_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LQSPI_CLK_CTRL + +0XF800014C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
    +

    +

    Register ( slcr )SDIO_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SDIO_CLK_CTRL + +0XF8000150 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +1 + +2 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +a03 + +SDIO Reference Clock Control +
    +

    +

    Register ( slcr )UART_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +UART_CLK_CTRL + +0XF8000154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT0 + +0:0 + +1 + +1 + +1 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CLKACT1 + +1:1 + +2 + +0 + +0 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR + +13:8 + +3f00 + +a + +a00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +a01 + +UART Reference Clock Control +
    +

    +

    TRACE CLOCK

    +

    Register ( slcr )PCAP_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PCAP_CLK_CTRL + +0XF8000168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
    +DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
    +PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
    +

    +

    Register ( slcr )FPGA0_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA0_CLK_CTRL + +0XF8000170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
    +DIVISOR0 + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
    +DIVISOR1 + +25:20 + +3f00000 + +2 + +200000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
    +FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +200500 + +FPGA 0 Output Clock Control +
    +

    +

    Register ( slcr )CLK_621_TRUE

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CLK_621_TRUE + +0XF80001C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
    +CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
    +

    +

    Register ( slcr )APER_CLK_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +APER_CLK_CTRL + +0XF800012C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DMA_CPU_2XCLKACT + +0:0 + +1 + +1 + +1 + +DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB0_CPU_1XCLKACT + +2:2 + +4 + +1 + +4 + +USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +USB1_CPU_1XCLKACT + +3:3 + +8 + +1 + +8 + +USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM0_CPU_1XCLKACT + +6:6 + +40 + +1 + +40 + +Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GEM1_CPU_1XCLKACT + +7:7 + +80 + +0 + +0 + +Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI0_CPU_1XCLKACT + +10:10 + +400 + +1 + +400 + +SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SDI1_CPU_1XCLKACT + +11:11 + +800 + +1 + +800 + +SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI0_CPU_1XCLKACT + +14:14 + +4000 + +0 + +0 + +SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SPI1_CPU_1XCLKACT + +15:15 + +8000 + +0 + +0 + +SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN0_CPU_1XCLKACT + +16:16 + +10000 + +0 + +0 + +CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +CAN1_CPU_1XCLKACT + +17:17 + +20000 + +0 + +0 + +CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C0_CPU_1XCLKACT + +18:18 + +40000 + +1 + +40000 + +I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +I2C1_CPU_1XCLKACT + +19:19 + +80000 + +1 + +80000 + +I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART0_CPU_1XCLKACT + +20:20 + +100000 + +1 + +100000 + +UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +UART1_CPU_1XCLKACT + +21:21 + +200000 + +0 + +0 + +UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +GPIO_CPU_1XCLKACT + +22:22 + +400000 + +1 + +400000 + +GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +LQSPI_CPU_1XCLKACT + +23:23 + +800000 + +1 + +800000 + +LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +SMC_CPU_1XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
    +APER_CLK_CTRL@0XF800012C + +31:0 + +1ffcccd + + + +1dc0c4d + +AMBA Peripheral Clock Control +
    +

    +

    THIS SHOULD BE BLANK

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    + +Two_rank_cfg + + +0XF8006004 + +32 + +RW + +0x000000 + +Two rank configuration register +
    + +HPR_reg + + +0XF8006008 + +32 + +RW + +0x000000 + +HPR Queue control register +
    + +LPR_reg + + +0XF800600C + +32 + +RW + +0x000000 + +LPR Queue control register +
    + +WR_reg + + +0XF8006010 + +32 + +RW + +0x000000 + +WR Queue control register +
    + +DRAM_param_reg0 + + +0XF8006014 + +32 + +RW + +0x000000 + +DRAM Parameters register 0 +
    + +DRAM_param_reg1 + + +0XF8006018 + +32 + +RW + +0x000000 + +DRAM Parameters register 1 +
    + +DRAM_param_reg2 + + +0XF800601C + +32 + +RW + +0x000000 + +DRAM Parameters register 2 +
    + +DRAM_param_reg3 + + +0XF8006020 + +32 + +RW + +0x000000 + +DRAM Parameters register 3 +
    + +DRAM_param_reg4 + + +0XF8006024 + +32 + +RW + +0x000000 + +DRAM Parameters register 4 +
    + +DRAM_init_param + + +0XF8006028 + +32 + +RW + +0x000000 + +DRAM initialization parameters register +
    + +DRAM_EMR_reg + + +0XF800602C + +32 + +RW + +0x000000 + +DRAM EMR2, EMR3 access register +
    + +DRAM_EMR_MR_reg + + +0XF8006030 + +32 + +RW + +0x000000 + +DRAM EMR, MR access register +
    + +DRAM_burst8_rdwr + + +0XF8006034 + +32 + +RW + +0x000000 + +DRAM burst 8 read/write register +
    + +DRAM_disable_DQ + + +0XF8006038 + +32 + +RW + +0x000000 + +DRAM Disable DQ register +
    + +DRAM_addr_map_bank + + +0XF800603C + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM bank address bits +
    + +DRAM_addr_map_col + + +0XF8006040 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM column address bits +
    + +DRAM_addr_map_row + + +0XF8006044 + +32 + +RW + +0x000000 + +Selects the address bits used as DRAM row address bits +
    + +DRAM_ODT_reg + + +0XF8006048 + +32 + +RW + +0x000000 + +DRAM ODT register +
    + +phy_cmd_timeout_rddata_cpt + + +0XF8006050 + +32 + +RW + +0x000000 + +PHY command time out and read data capture FIFO register +
    + +DLL_calib + + +0XF8006058 + +32 + +RW + +0x000000 + +DLL calibration register +
    + +ODT_delay_hold + + +0XF800605C + +32 + +RW + +0x000000 + +ODT delay and ODT hold register +
    + +ctrl_reg1 + + +0XF8006060 + +32 + +RW + +0x000000 + +Controller register 1 +
    + +ctrl_reg2 + + +0XF8006064 + +32 + +RW + +0x000000 + +Controller register 2 +
    + +ctrl_reg3 + + +0XF8006068 + +32 + +RW + +0x000000 + +Controller register 3 +
    + +ctrl_reg4 + + +0XF800606C + +32 + +RW + +0x000000 + +Controller register 4 +
    + +CHE_REFRESH_TIMER01 + + +0XF80060A0 + +32 + +RW + +0x000000 + +CHE_REFRESH_TIMER01 +
    + +CHE_T_ZQ + + +0XF80060A4 + +32 + +RW + +0x000000 + +ZQ parameters register +
    + +CHE_T_ZQ_Short_Interval_Reg + + +0XF80060A8 + +32 + +RW + +0x000000 + +Misc parameters register +
    + +deep_pwrdwn_reg + + +0XF80060AC + +32 + +RW + +0x000000 + +Deep powerdown register +
    + +reg_2c + + +0XF80060B0 + +32 + +RW + +0x000000 + +Training control register +
    + +reg_2d + + +0XF80060B4 + +32 + +RW + +0x000000 + +Misc Debug register +
    + +dfi_timing + + +0XF80060B8 + +32 + +RW + +0x000000 + +DFI timing register +
    + +CHE_ECC_CONTROL_REG_OFFSET + + +0XF80060C4 + +32 + +RW + +0x000000 + +ECC error clear register +
    + +CHE_CORR_ECC_LOG_REG_OFFSET + + +0XF80060C8 + +32 + +RW + +0x000000 + +ECC error correction register +
    + +CHE_UNCORR_ECC_LOG_REG_OFFSET + + +0XF80060DC + +32 + +RW + +0x000000 + +ECC unrecoverable error status register +
    + +CHE_ECC_STATS_REG_OFFSET + + +0XF80060F0 + +32 + +RW + +0x000000 + +ECC error count register +
    + +ECC_scrub + + +0XF80060F4 + +32 + +RW + +0x000000 + +ECC mode/scrub register +
    + +phy_rcvr_enable + + +0XF8006114 + +32 + +RW + +0x000000 + +Phy receiver enable register +
    + +PHY_Config + + +0XF8006118 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF800611C + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006120 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +PHY_Config + + +0XF8006124 + +32 + +RW + +0x000000 + +PHY configuration register for data slice 0. +
    + +phy_init_ratio + + +0XF800612C + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006130 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006134 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_init_ratio + + +0XF8006138 + +32 + +RW + +0x000000 + +PHY init ratio register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006140 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006144 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF8006148 + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_rd_dqs_cfg + + +0XF800614C + +32 + +RW + +0x000000 + +PHY read DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006154 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006158 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF800615C + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_wr_dqs_cfg + + +0XF8006160 + +32 + +RW + +0x000000 + +PHY write DQS configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006168 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF800616C + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006170 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +phy_we_cfg + + +0XF8006174 + +32 + +RW + +0x000000 + +PHY fifo write enable configuration register for data slice 0. +
    + +wr_data_slv + + +0XF800617C + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006180 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006184 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +wr_data_slv + + +0XF8006188 + +32 + +RW + +0x000000 + +PHY write data slave ratio configuration register for data slice 0. +
    + +reg_64 + + +0XF8006190 + +32 + +RW + +0x000000 + +Training control register (2) +
    + +reg_65 + + +0XF8006194 + +32 + +RW + +0x000000 + +Training control register (3) +
    + +page_mask + + +0XF8006204 + +32 + +RW + +0x000000 + +Page mask register +
    + +axi_priority_wr_port + + +0XF8006208 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF800620C + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006210 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_wr_port + + +0XF8006214 + +32 + +RW + +0x000000 + +AXI Priority control for write port 0. +
    + +axi_priority_rd_port + + +0XF8006218 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF800621C + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006220 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +axi_priority_rd_port + + +0XF8006224 + +32 + +RW + +0x000000 + +AXI Priority control for read port 0. +
    + +lpddr_ctrl0 + + +0XF80062A8 + +32 + +RW + +0x000000 + +LPDDR2 Control 0 Register +
    + +lpddr_ctrl1 + + +0XF80062AC + +32 + +RW + +0x000000 + +LPDDR2 Control 1 Register +
    + +lpddr_ctrl2 + + +0XF80062B0 + +32 + +RW + +0x000000 + +LPDDR2 Control 2 Register +
    + +lpddr_ctrl3 + + +0XF80062B4 + +32 + +RW + +0x000000 + +LPDDR2 Control 3 Register +
    + +ddrc_ctrl + + +0XF8006000 + +32 + +RW + +0x000000 + +DDRC Control Register +
    +

    +

    ps7_ddr_init_data_1_0

    + + + + + + + + + +

    DDR INITIALIZATION

    +

    LOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
    +

    +

    Register ( slcr )Two_rank_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Two_rank_cfg + +0XF8006004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +82 + +82 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
    +reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
    +reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
    +reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
    +reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
    +reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
    +reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
    +Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81082 + +Two rank configuration register +
    +

    +

    Register ( slcr )HPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +HPR_reg + +0XF8006008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
    +HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
    +

    +

    Register ( slcr )LPR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LPR_reg + +0XF800600C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
    +reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
    +reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
    +LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control register +
    +

    +

    Register ( slcr )WR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +WR_reg + +0XF8006010 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
    +reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
    +reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
    +WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control register +
    +

    +

    Register ( slcr )DRAM_param_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg0 + +0XF8006014 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +a1 + +2840 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
    +DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4285b + +DRAM Parameters register 0 +
    +

    +

    Register ( slcr )DRAM_param_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg1 + +0XF8006018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wr2pre + +4:0 + +1f + +13 + +13 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
    +reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
    +reg_ddrc_t_faw + +15:10 + +fc00 + +16 + +5800 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
    +reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
    +reg_ddrc_t_ras_min + +26:22 + +7c00000 + +13 + +4c00000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
    +reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
    +DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +44e458d3 + +DRAM Parameters register 1 +
    +

    +

    Register ( slcr )DRAM_param_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg2 + +0XF800601C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
    +reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
    +reg_ddrc_wr2rd + +14:10 + +7c00 + +f + +3c00 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
    +reg_ddrc_t_xp + +19:15 + +f8000 + +5 + +28000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
    +reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
    +reg_ddrc_rd2pre + +27:23 + +f800000 + +5 + +2800000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
    +reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
    +DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +7282bce5 + +DRAM Parameters register 2 +
    +

    +

    Register ( slcr )DRAM_param_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg3 + +0XF8006020 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
    +reg_ddrc_t_rrd + +7:5 + +e0 + +6 + +c0 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
    +reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
    +reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
    +reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
    +reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
    +reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
    +reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
    +reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
    +reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
    +reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
    +reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
    +DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +272872d0 + +DRAM Parameters register 3 +
    +

    +

    Register ( slcr )DRAM_param_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_param_reg4 + +0XF8006024 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
    +reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
    +reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
    +reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
    +reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
    +reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
    +ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
    +reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
    +reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
    +DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
    +

    +

    Register ( slcr )DRAM_init_param

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_init_param + +0XF8006028 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
    +reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
    +reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
    +DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
    +

    +

    Register ( slcr )DRAM_EMR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_reg + +0XF800602C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
    +reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
    +DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
    +

    +

    Register ( slcr )DRAM_EMR_MR_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_EMR_MR_reg + +0XF8006030 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr + +15:0 + +ffff + +b30 + +b30 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
    +reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
    +DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40b30 + +DRAM EMR, MR access register +
    +

    +

    Register ( slcr )DRAM_burst8_rdwr

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_burst8_rdwr + +0XF8006034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
    +reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +16d + +16d0 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
    +reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
    +reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
    +DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +116d4 + +DRAM burst 8 read/write register +
    +

    +

    Register ( slcr )DRAM_disable_DQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_disable_DQ + +0XF8006038 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
    +reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
    +reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
    +reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
    +DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
    +

    +

    Register ( slcr )DRAM_addr_map_bank

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_bank + +0XF800603C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
    +reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
    +DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_col

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_col + +0XF8006040 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
    +DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
    +

    +

    Register ( slcr )DRAM_addr_map_row

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_addr_map_row + +0XF8006044 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
    +reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
    +reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
    +reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
    +reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
    +reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
    +DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
    +

    +

    Register ( slcr )DRAM_ODT_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DRAM_ODT_reg + +0XF8006048 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
    +reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
    +reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
    +reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
    +reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
    +reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
    +reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
    +reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
    +reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
    +reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
    +DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
    +

    +

    Register ( slcr )phy_cmd_timeout_rddata_cpt

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_cmd_timeout_rddata_cpt + +0XF8006050 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
    +reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
    +reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
    +reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
    +reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
    +reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
    +reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
    +reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
    +phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
    +

    +

    Register ( slcr )DLL_calib

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DLL_calib + +0XF8006058 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
    +reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
    +reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
    +DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration register +
    +

    +

    Register ( slcr )ODT_delay_hold

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ODT_delay_hold + +0XF800605C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
    +reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
    +reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
    +reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
    +ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
    +

    +

    Register ( slcr )ctrl_reg1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg1 + +0XF8006060 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
    +reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
    +reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
    +reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
    +reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
    +reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
    +reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
    +ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
    +

    +

    Register ( slcr )ctrl_reg2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg2 + +0XF8006064 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
    +reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
    +ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
    +

    +

    Register ( slcr )ctrl_reg3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg3 + +0XF8006068 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
    +reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
    +reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
    +ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
    +

    +

    Register ( slcr )ctrl_reg4

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ctrl_reg4 + +0XF800606C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
    +dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
    +ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller register 4 +
    +

    +

    Register ( slcr )CHE_REFRESH_TIMER01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_REFRESH_TIMER01 + +0XF80060A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
    +refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
    +CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
    +

    +

    Register ( slcr )CHE_T_ZQ

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ + +0XF80060A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
    +reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
    +reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
    +CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
    +

    +

    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_T_ZQ_Short_Interval_Reg + +0XF80060A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
    +dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
    +CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
    +

    +

    Register ( slcr )deep_pwrdwn_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +deep_pwrdwn_reg + +0XF80060AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
    +deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
    +deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
    +

    +

    Register ( slcr )reg_2c

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2c + +0XF80060B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
    +ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
    +ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
    +reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
    +reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
    +reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
    +

    +

    Register ( slcr )reg_2d

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_2d + +0XF80060B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
    +reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
    +reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
    +reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
    +

    +

    Register ( slcr )dfi_timing

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +dfi_timing + +0XF80060B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
    +reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
    +reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
    +dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
    +

    +

    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_CONTROL_REG_OFFSET + +0XF80060C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
    +Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
    +CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
    +

    +

    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_CORR_ECC_LOG_REG_OFFSET + +0XF80060C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
    +ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
    +CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
    +

    +

    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET + +0XF80060DC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
    +CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
    +

    +

    Register ( slcr )CHE_ECC_STATS_REG_OFFSET

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CHE_ECC_STATS_REG_OFFSET + +0XF80060F0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
    +STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
    +CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
    +

    +

    Register ( slcr )ECC_scrub

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ECC_scrub + +0XF80060F4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
    +reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
    +ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
    +

    +

    Register ( slcr )phy_rcvr_enable

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rcvr_enable + +0XF8006114 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
    +reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
    +phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006118 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF800611C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006120 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )PHY_Config

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +PHY_Config + +0XF8006124 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
    +reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
    +reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
    +reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
    +reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
    +reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
    +reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
    +reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
    +PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF800612C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006130 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006134 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_init_ratio

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_init_ratio + +0XF8006138 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +0 + +0 + +The user programmable init ratio used by Write Leveling FSM +
    +reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +a4 + +29000 + +The user programmable init ratio used Gate Leveling FSM +
    +phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +29000 + +PHY init ratio register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006140 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006144 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF8006148 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_rd_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_rd_dqs_cfg + +0XF800614C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
    +reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
    +reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
    +phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006154 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006158 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF800615C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_wr_dqs_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_wr_dqs_cfg + +0XF8006160 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +80 + +80 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
    +reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
    +phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +80 + +PHY write DQS configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006168 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF800616C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006170 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )phy_we_cfg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +phy_we_cfg + +0XF8006174 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +f9 + +f9 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
    +reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
    +reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
    +phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +f9 + +PHY fifo write enable configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF800617C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF800617C + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006180 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006184 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )wr_data_slv

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +wr_data_slv + +0XF8006188 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +c0 + +c0 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
    +reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
    +wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +c0 + +PHY write data slave ratio configuration register for data slice 0. +
    +

    +

    Register ( slcr )reg_64

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_64 + +0XF8006190 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
    +reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
    +reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
    +reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
    +reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
    +reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
    +reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
    +reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
    +reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
    +reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
    +reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
    +reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
    +reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
    +reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
    +reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
    +reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
    +reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
    +

    +

    Register ( slcr )reg_65

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +reg_65 + +0XF8006194 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
    +reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
    +reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
    +reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
    +reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
    +reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
    +reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
    +reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
    +

    +

    Register ( slcr )page_mask

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +page_mask + +0XF8006204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
    +page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF800620C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006210 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_wr_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_wr_port + +0XF8006214 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
    +reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
    +reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
    +axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006218 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF800621C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006220 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )axi_priority_rd_port

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +axi_priority_rd_port + +0XF8006224 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
    +reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
    +reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
    +reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
    +reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
    +axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
    +

    +

    Register ( slcr )lpddr_ctrl0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl0 + +0XF80062A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
    +reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
    +reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
    +lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
    +

    +

    Register ( slcr )lpddr_ctrl1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl1 + +0XF80062AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
    +lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
    +

    +

    Register ( slcr )lpddr_ctrl2

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl2 + +0XF80062B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
    +reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
    +reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
    +lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
    +

    +

    Register ( slcr )lpddr_ctrl3

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +lpddr_ctrl3 + +0XF80062B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
    +reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
    +lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
    +

    +

    POLL ON DCI STATUS

    +

    Register ( slcr )DDRIOB_DCI_STATUS

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_STATUS + +0XF8000B74 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
    +DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
    +

    +

    UNLOCK DDR

    +

    Register ( slcr )ddrc_ctrl

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +ddrc_ctrl + +0XF8006000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
    +reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
    +reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
    +reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
    +reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
    +reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
    +reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
    +reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
    +ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
    +

    +

    CHECK DDR STATUS

    +

    Register ( slcr )mode_sts_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_sts_reg + +0XF8006054 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
    +mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
    +

    + +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_ADDR0 + + +0XF8000B40 + +32 + +RW + +0x000000 + +DDRIOB Address 0 Configuartion Register +
    + +DDRIOB_ADDR1 + + +0XF8000B44 + +32 + +RW + +0x000000 + +DDRIOB Address 1 Configuration Register +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +DDRIOB_CLOCK + + +0XF8000B58 + +32 + +RW + +0x000000 + +DDRIOB Differential Clock Configuration Register +
    + +DDRIOB_DRIVE_SLEW_ADDR + + +0XF8000B5C + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Address Register +
    + +DDRIOB_DRIVE_SLEW_DATA + + +0XF8000B60 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Data Register +
    + +DDRIOB_DRIVE_SLEW_DIFF + + +0XF8000B64 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Differential Strobe Register +
    + +DDRIOB_DRIVE_SLEW_CLOCK + + +0XF8000B68 + +32 + +RW + +0x000000 + +DDRIOB Drive Slew Clcok Register +
    + +DDRIOB_DDR_CTRL + + +0XF8000B6C + +32 + +RW + +0x000000 + +DDRIOB DDR Control Register +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +DDRIOB_DCI_CTRL + + +0XF8000B70 + +32 + +RW + +0x000000 + +DDRIOB DCI configuration +
    + +MIO_PIN_00 + + +0XF8000700 + +32 + +RW + +0x000000 + +MIO Control for Pin 0 +
    + +MIO_PIN_01 + + +0XF8000704 + +32 + +RW + +0x000000 + +MIO Control for Pin 1 +
    + +MIO_PIN_02 + + +0XF8000708 + +32 + +RW + +0x000000 + +MIO Control for Pin 2 +
    + +MIO_PIN_03 + + +0XF800070C + +32 + +RW + +0x000000 + +MIO Control for Pin 3 +
    + +MIO_PIN_04 + + +0XF8000710 + +32 + +RW + +0x000000 + +MIO Control for Pin 4 +
    + +MIO_PIN_05 + + +0XF8000714 + +32 + +RW + +0x000000 + +MIO Control for Pin 5 +
    + +MIO_PIN_06 + + +0XF8000718 + +32 + +RW + +0x000000 + +MIO Control for Pin 6 +
    + +MIO_PIN_07 + + +0XF800071C + +32 + +RW + +0x000000 + +MIO Control for Pin 7 +
    + +MIO_PIN_08 + + +0XF8000720 + +32 + +RW + +0x000000 + +MIO Control for Pin 8 +
    + +MIO_PIN_09 + + +0XF8000724 + +32 + +RW + +0x000000 + +MIO Control for Pin 9 +
    + +MIO_PIN_10 + + +0XF8000728 + +32 + +RW + +0x000000 + +MIO Control for Pin 10 +
    + +MIO_PIN_11 + + +0XF800072C + +32 + +RW + +0x000000 + +MIO Control for Pin 11 +
    + +MIO_PIN_12 + + +0XF8000730 + +32 + +RW + +0x000000 + +MIO Control for Pin 12 +
    + +MIO_PIN_13 + + +0XF8000734 + +32 + +RW + +0x000000 + +MIO Control for Pin 13 +
    + +MIO_PIN_14 + + +0XF8000738 + +32 + +RW + +0x000000 + +MIO Control for Pin 14 +
    + +MIO_PIN_15 + + +0XF800073C + +32 + +RW + +0x000000 + +MIO Control for Pin 15 +
    + +MIO_PIN_16 + + +0XF8000740 + +32 + +RW + +0x000000 + +MIO Control for Pin 16 +
    + +MIO_PIN_17 + + +0XF8000744 + +32 + +RW + +0x000000 + +MIO Control for Pin 17 +
    + +MIO_PIN_18 + + +0XF8000748 + +32 + +RW + +0x000000 + +MIO Control for Pin 18 +
    + +MIO_PIN_19 + + +0XF800074C + +32 + +RW + +0x000000 + +MIO Control for Pin 19 +
    + +MIO_PIN_20 + + +0XF8000750 + +32 + +RW + +0x000000 + +MIO Control for Pin 20 +
    + +MIO_PIN_21 + + +0XF8000754 + +32 + +RW + +0x000000 + +MIO Control for Pin 21 +
    + +MIO_PIN_22 + + +0XF8000758 + +32 + +RW + +0x000000 + +MIO Control for Pin 22 +
    + +MIO_PIN_23 + + +0XF800075C + +32 + +RW + +0x000000 + +MIO Control for Pin 23 +
    + +MIO_PIN_24 + + +0XF8000760 + +32 + +RW + +0x000000 + +MIO Control for Pin 24 +
    + +MIO_PIN_25 + + +0XF8000764 + +32 + +RW + +0x000000 + +MIO Control for Pin 25 +
    + +MIO_PIN_26 + + +0XF8000768 + +32 + +RW + +0x000000 + +MIO Control for Pin 26 +
    + +MIO_PIN_27 + + +0XF800076C + +32 + +RW + +0x000000 + +MIO Control for Pin 27 +
    + +MIO_PIN_28 + + +0XF8000770 + +32 + +RW + +0x000000 + +MIO Control for Pin 28 +
    + +MIO_PIN_29 + + +0XF8000774 + +32 + +RW + +0x000000 + +MIO Control for Pin 29 +
    + +MIO_PIN_30 + + +0XF8000778 + +32 + +RW + +0x000000 + +MIO Control for Pin 30 +
    + +MIO_PIN_31 + + +0XF800077C + +32 + +RW + +0x000000 + +MIO Control for Pin 31 +
    + +MIO_PIN_32 + + +0XF8000780 + +32 + +RW + +0x000000 + +MIO Control for Pin 32 +
    + +MIO_PIN_33 + + +0XF8000784 + +32 + +RW + +0x000000 + +MIO Control for Pin 33 +
    + +MIO_PIN_34 + + +0XF8000788 + +32 + +RW + +0x000000 + +MIO Control for Pin 34 +
    + +MIO_PIN_35 + + +0XF800078C + +32 + +RW + +0x000000 + +MIO Control for Pin 35 +
    + +MIO_PIN_36 + + +0XF8000790 + +32 + +RW + +0x000000 + +MIO Control for Pin 36 +
    + +MIO_PIN_37 + + +0XF8000794 + +32 + +RW + +0x000000 + +MIO Control for Pin 37 +
    + +MIO_PIN_38 + + +0XF8000798 + +32 + +RW + +0x000000 + +MIO Control for Pin 38 +
    + +MIO_PIN_39 + + +0XF800079C + +32 + +RW + +0x000000 + +MIO Control for Pin 39 +
    + +MIO_PIN_40 + + +0XF80007A0 + +32 + +RW + +0x000000 + +MIO Control for Pin 40 +
    + +MIO_PIN_41 + + +0XF80007A4 + +32 + +RW + +0x000000 + +MIO Control for Pin 41 +
    + +MIO_PIN_42 + + +0XF80007A8 + +32 + +RW + +0x000000 + +MIO Control for Pin 42 +
    + +MIO_PIN_43 + + +0XF80007AC + +32 + +RW + +0x000000 + +MIO Control for Pin 43 +
    + +MIO_PIN_44 + + +0XF80007B0 + +32 + +RW + +0x000000 + +MIO Control for Pin 44 +
    + +MIO_PIN_45 + + +0XF80007B4 + +32 + +RW + +0x000000 + +MIO Control for Pin 45 +
    + +MIO_PIN_46 + + +0XF80007B8 + +32 + +RW + +0x000000 + +MIO Control for Pin 46 +
    + +MIO_PIN_47 + + +0XF80007BC + +32 + +RW + +0x000000 + +MIO Control for Pin 47 +
    + +MIO_PIN_48 + + +0XF80007C0 + +32 + +RW + +0x000000 + +MIO Control for Pin 48 +
    + +MIO_PIN_49 + + +0XF80007C4 + +32 + +RW + +0x000000 + +MIO Control for Pin 49 +
    + +MIO_PIN_50 + + +0XF80007C8 + +32 + +RW + +0x000000 + +MIO Control for Pin 50 +
    + +MIO_PIN_51 + + +0XF80007CC + +32 + +RW + +0x000000 + +MIO Control for Pin 51 +
    + +MIO_PIN_52 + + +0XF80007D0 + +32 + +RW + +0x000000 + +MIO Control for Pin 52 +
    + +MIO_PIN_53 + + +0XF80007D4 + +32 + +RW + +0x000000 + +MIO Control for Pin 53 +
    + +SD0_WP_CD_SEL + + +0XF8000830 + +32 + +RW + +0x000000 + +SDIO 0 WP CD select register +
    + +SD1_WP_CD_SEL + + +0XF8000834 + +32 + +RW + +0x000000 + +SDIO 1 WP CD select register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_mio_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    OCM REMAPPING

    +

    DDRIOB SETTINGS

    +

    Register ( slcr )DDRIOB_ADDR0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR0 + +0XF8000B40 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
    +

    +

    Register ( slcr )DDRIOB_ADDR1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_ADDR1 + +0XF8000B44 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_CLOCK + +0XF8000B58 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
    +INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
    +DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
    +TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
    +DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
    +PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
    +DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_ADDR + +0XF8000B5C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DATA + +0XF8000B60 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_DIFF + +0XF8000B64 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
    +

    +

    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DRIVE_SLEW_CLOCK + +0XF8000B68 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
    +DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
    +SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
    +SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
    +GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
    +RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
    +DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
    +

    +

    Register ( slcr )DDRIOB_DDR_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DDR_CTRL + +0XF8000B6C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +VREF_INT_EN + +0:0 + +1 + +0 + +0 + +Enables VREF internal generator +
    +VREF_SEL + +4:1 + +1e + +0 + +0 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
    +VREF_EXT_EN + +6:5 + +60 + +3 + +60 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
    +VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
    +REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
    +REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
    +DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +260 + +DDRIOB DDR Control Register +
    +

    +

    ASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
    +

    +

    DEASSERT RESET

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
    +

    +

    Register ( slcr )DDRIOB_DCI_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DCI_CTRL + +0XF8000B70 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
    +ENABLE + +1:1 + +2 + +1 + +2 + +1 if any iob's use a terminate type, or if dci test block used +
    +VRP_TRI + +2:2 + +4 + +0 + +0 + +VRP tristate value +
    +VRN_TRI + +3:3 + +8 + +0 + +0 + +VRN tristate value +
    +VRP_OUT + +4:4 + +10 + +0 + +0 + +VRP output value +
    +VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
    +NREF_OPT1 + +7:6 + +c0 + +0 + +0 + +Reserved +
    +NREF_OPT2 + +10:8 + +700 + +0 + +0 + +Reserved +
    +NREF_OPT4 + +13:11 + +3800 + +1 + +800 + +Reserved +
    +PREF_OPT1 + +16:14 + +1c000 + +0 + +0 + +Reserved +
    +PREF_OPT2 + +19:17 + +e0000 + +0 + +0 + +Reserved +
    +UPDATE_CONTROL + +20:20 + +100000 + +0 + +0 + +DCI Update +
    +INIT_COMPLETE + +21:21 + +200000 + +0 + +0 + +test Internal to IO bank +
    +TST_CLK + +22:22 + +400000 + +0 + +0 + +Emulate DCI clock +
    +TST_HLN + +23:23 + +800000 + +0 + +0 + +Emulate comparator output (VRN) +
    +TST_HLP + +24:24 + +1000000 + +0 + +0 + +Emulate comparator output (VRP) +
    +TST_RST + +25:25 + +2000000 + +0 + +0 + +Emulate Reset +
    +INT_DCI_EN + +26:26 + +4000000 + +0 + +0 + +Need explanation here +
    +DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +7ffffff + + + +823 + +DDRIOB DCI configuration +
    +

    +

    MIO PROGRAMMING

    +

    Register ( slcr )MIO_PIN_00

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_00 + +0XF8000700 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out_upper- (QSPI Upper select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_cs0, Output, smc_sram_cs_n[0]- (SRAM CS0) 2= nand_cs, Output, smc_nand_cs_n- (NAND chip select) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_00@0XF8000700 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 0 +
    +

    +

    Register ( slcr )MIO_PIN_01

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_01 + +0XF8000704 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1602 + +MIO Control for Pin 1 +
    +

    +

    Register ( slcr )MIO_PIN_02

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_02 + +0XF8000708 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 2 +
    +

    +

    Register ( slcr )MIO_PIN_03

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_03 + +0XF800070C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +602 + +MIO Control for Pin 3 +
    +

    +

    Register ( slcr )MIO_PIN_04

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_04 + +0XF8000710 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 4 +
    +

    +

    Register ( slcr )MIO_PIN_05

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_05 + +0XF8000714 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 5 +
    +

    +

    Register ( slcr )MIO_PIN_06

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_06 + +0XF8000718 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +602 + +MIO Control for Pin 6 +
    +

    +

    Register ( slcr )MIO_PIN_07

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_07 + +0XF800071C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +600 + +MIO Control for Pin 7 +
    +

    +

    Register ( slcr )MIO_PIN_08

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_08 + +0XF8000720 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +600 + +MIO Control for Pin 8 +
    +

    +

    Register ( slcr )MIO_PIN_09

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_09 + +0XF8000724 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 9 +
    +

    +

    Register ( slcr )MIO_PIN_10

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_10 + +0XF8000728 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_10@0XF8000728 + +31:0 + +3f01 + + + +1601 + +MIO Control for Pin 10 +
    +

    +

    Register ( slcr )MIO_PIN_11

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_11 + +0XF800072C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 11 +
    +

    +

    Register ( slcr )MIO_PIN_12

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_12 + +0XF8000730 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 12 +
    +

    +

    Register ( slcr )MIO_PIN_13

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_13 + +0XF8000734 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1600 + +MIO Control for Pin 13 +
    +

    +

    Register ( slcr )MIO_PIN_14

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_14 + +0XF8000738 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +16e1 + +MIO Control for Pin 14 +
    +

    +

    Register ( slcr )MIO_PIN_15

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_15 + +0XF800073C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[0]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +3 + +600 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_15@0XF800073C + +31:0 + +3fff + + + +16e0 + +MIO Control for Pin 15 +
    +

    +

    Register ( slcr )MIO_PIN_16

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_16 + +0XF8000740 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 16 +
    +

    +

    Register ( slcr )MIO_PIN_17

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_17 + +0XF8000744 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 17 +
    +

    +

    Register ( slcr )MIO_PIN_18

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_18 + +0XF8000748 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 18 +
    +

    +

    Register ( slcr )MIO_PIN_19

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_19 + +0XF800074C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 19 +
    +

    +

    Register ( slcr )MIO_PIN_20

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_20 + +0XF8000750 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 20 +
    +

    +

    Register ( slcr )MIO_PIN_21

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_21 + +0XF8000754 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 21 +
    +

    +

    Register ( slcr )MIO_PIN_22

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_22 + +0XF8000758 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 22 +
    +

    +

    Register ( slcr )MIO_PIN_23

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_23 + +0XF800075C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 23 +
    +

    +

    Register ( slcr )MIO_PIN_24

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_24 + +0XF8000760 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 24 +
    +

    +

    Register ( slcr )MIO_PIN_25

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_25 + +0XF8000764 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 25 +
    +

    +

    Register ( slcr )MIO_PIN_26

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_26 + +0XF8000768 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 26 +
    +

    +

    Register ( slcr )MIO_PIN_27

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_27 + +0XF800076C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +1203 + +MIO Control for Pin 27 +
    +

    +

    Register ( slcr )MIO_PIN_28

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_28 + +0XF8000770 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 28 +
    +

    +

    Register ( slcr )MIO_PIN_29

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_29 + +0XF8000774 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 29 +
    +

    +

    Register ( slcr )MIO_PIN_30

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_30 + +0XF8000778 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 30 +
    +

    +

    Register ( slcr )MIO_PIN_31

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_31 + +0XF800077C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 31 +
    +

    +

    Register ( slcr )MIO_PIN_32

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_32 + +0XF8000780 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 32 +
    +

    +

    Register ( slcr )MIO_PIN_33

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_33 + +0XF8000784 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 33 +
    +

    +

    Register ( slcr )MIO_PIN_34

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_34 + +0XF8000788 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 34 +
    +

    +

    Register ( slcr )MIO_PIN_35

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_35 + +0XF800078C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 35 +
    +

    +

    Register ( slcr )MIO_PIN_36

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_36 + +0XF8000790 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +1205 + +MIO Control for Pin 36 +
    +

    +

    Register ( slcr )MIO_PIN_37

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_37 + +0XF8000794 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 37 +
    +

    +

    Register ( slcr )MIO_PIN_38

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_38 + +0XF8000798 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 38 +
    +

    +

    Register ( slcr )MIO_PIN_39

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_39 + +0XF800079C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
    +L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +1204 + +MIO Control for Pin 39 +
    +

    +

    Register ( slcr )MIO_PIN_40

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_40 + +0XF80007A0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 40 +
    +

    +

    Register ( slcr )MIO_PIN_41

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_41 + +0XF80007A4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 41 +
    +

    +

    Register ( slcr )MIO_PIN_42

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_42 + +0XF80007A8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 42 +
    +

    +

    Register ( slcr )MIO_PIN_43

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_43 + +0XF80007AC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 43 +
    +

    +

    Register ( slcr )MIO_PIN_44

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_44 + +0XF80007B0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 44 +
    +

    +

    Register ( slcr )MIO_PIN_45

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_45 + +0XF80007B4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 45 +
    +

    +

    Register ( slcr )MIO_PIN_46

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_46 + +0XF80007B8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 46 +
    +

    +

    Register ( slcr )MIO_PIN_47

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_47 + +0XF80007BC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 47 +
    +

    +

    Register ( slcr )MIO_PIN_48

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_48 + +0XF80007C0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 48 +
    +

    +

    Register ( slcr )MIO_PIN_49

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_49 + +0XF80007C4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 49 +
    +

    +

    Register ( slcr )MIO_PIN_50

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_50 + +0XF80007C8 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 50 +
    +

    +

    Register ( slcr )MIO_PIN_51

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_51 + +0XF80007CC + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 51 +
    +

    +

    Register ( slcr )MIO_PIN_52

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_52 + +0XF80007D0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 52 +
    +

    +

    Register ( slcr )MIO_PIN_53

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MIO_PIN_53 + +0XF80007D4 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
    +L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
    +L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
    +L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
    +L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
    +Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
    +IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
    +PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
    +DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
    +MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +1280 + +MIO Control for Pin 53 +
    +

    +

    Register ( slcr )SD0_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD0_WP_CD_SEL + +0XF8000830 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO0_WP_SEL + +5:0 + +3f + +37 + +37 + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO0_CD_SEL + +21:16 + +3f0000 + +a + +a0000 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +a0037 + +SDIO 0 WP CD select register +
    +

    +

    Register ( slcr )SD1_WP_CD_SEL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SD1_WP_CD_SEL + +0XF8000834 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +SDIO1_WP_SEL + +5:0 + +3f + +39 + +39 + +SDIO1 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SDIO1_CD_SEL + +21:16 + +3f0000 + +3a + +3a0000 + +SDIO1 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
    +SD1_WP_CD_SEL@0XF8000834 + +31:0 + +3f003f + + + +3a0039 + +SDIO 1 WP CD select register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +DDRIOB_DATA0 + + +0XF8000B48 + +32 + +RW + +0x000000 + +DDRIOB Data 0 Configuration Register +
    + +DDRIOB_DATA1 + + +0XF8000B4C + +32 + +RW + +0x000000 + +DDRIOB Data 1 Configuration Register +
    + +DDRIOB_DIFF0 + + +0XF8000B50 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 0 Configuration Register +
    + +DDRIOB_DIFF1 + + +0XF8000B54 + +32 + +RW + +0x000000 + +DDRIOB Differential DQS 1 Configuration Register +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    + +Baud_rate_divider_reg0 + + +0XE0000034 + +32 + +RW + +0x000000 + +baud rate divider register +
    + +Baud_rate_gen_reg0 + + +0XE0000018 + +32 + +RW + +0x000000 + +Baud rate divider register +
    + +Control_reg0 + + +0XE0000000 + +32 + +RW + +0x000000 + +UART Control register +
    + +mode_reg0 + + +0XE0000004 + +32 + +RW + +0x000000 + +UART Mode register +
    + +Config_reg + + +0XE000D000 + +32 + +RW + +0x000000 + +SPI configuration register +
    + +CTRL + + +0XF8007000 + +32 + +RW + +0x000000 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    + +DIRM_0 + + +0XE000A204 + +32 + +RW + +0x000000 + +Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    + +OEN_0 + + +0XE000A208 + +32 + +RW + +0x000000 + +Output enable register: Configures the output enables of bank 0 +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    + +MASK_DATA_0_LSW + + +0XE000A000 + +32 + +RW + +0x000000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    +

    +

    ps7_peripherals_init_data_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    DDR TERM/IBUF_DISABLE_MODE SETTINGS

    +

    Register ( slcr )DDRIOB_DATA0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA0 + +0XF8000B48 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDRIOB Data 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DATA1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DATA1 + +0XF8000B4C + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDRIOB Data 1 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF0 + +0XF8000B50 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 0 Configuration Register +
    +

    +

    Register ( slcr )DDRIOB_DIFF1

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DDRIOB_DIFF1 + +0XF8000B54 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
    +TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
    +DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDRIOB Differential DQS 1 Configuration Register +
    +

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    +

    SRAM/NOR SET OPMODE

    +

    UART REGISTERS

    +

    Register ( slcr )Baud_rate_divider_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_divider_reg0 + +0XE0000034 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
    +Baud_rate_divider_reg0@0XE0000034 + +31:0 + +ff + + + +6 + +baud rate divider register +
    +

    +

    Register ( slcr )Baud_rate_gen_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Baud_rate_gen_reg0 + +0XE0000018 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +CD + +15:0 + +ffff + +7c + +7c + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
    +Baud_rate_gen_reg0@0XE0000018 + +31:0 + +ffff + + + +7c + +Baud rate divider register +
    +

    +

    Register ( slcr )Control_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Control_reg0 + +0XE0000000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
    +STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
    +RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
    +TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
    +TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
    +RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
    +RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
    +TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
    +RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
    +Control_reg0@0XE0000000 + +31:0 + +1ff + + + +17 + +UART Control register +
    +

    +

    Register ( slcr )mode_reg0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +mode_reg0 + +0XE0000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
    +UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
    +CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
    +NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
    +PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
    +CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
    +CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
    +mode_reg0@0XE0000004 + +31:0 + +fff + + + +20 + +UART Mode register +
    +

    +

    QSPI REGISTERS

    +

    Register ( slcr )Config_reg

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +Config_reg + +0XE000D000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
    +Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
    +

    +

    PL POWER ON RESET REGISTERS

    +

    Register ( slcr )CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +CTRL + +0XF8007000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
    +CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
    +

    +

    SMC TIMING CALCULATION REGISTER UPDATE

    +

    NAND SET CYCLE

    +

    OPMODE

    +

    DIRECT COMMAND

    +

    SRAM/NOR CS0 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS0 BASE ADDRESS

    +

    SRAM/NOR CS1 SET CYCLE

    +

    DIRECT COMMAND

    +

    NOR CS1 BASE ADDRESS

    +

    USB RESET

    +

    USB0 RESET

    +

    DIR MODE BANK 0

    +

    Register ( slcr )DIRM_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +DIRM_0 + +0XE000A204 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +DIRECTION_0 + +31:0 + +ffffffff + +200 + +200 + +Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank +
    +DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +200 + +Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
    +

    +

    DIR MODE BANK 1

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    OUTPUT ENABLE BANK 0

    +

    Register ( slcr )OEN_0

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +OEN_0 + +0XE000A208 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +OP_ENABLE_0 + +31:0 + +ffffffff + +200 + +200 + +Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank +
    +OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +200 + +Output enable register: Configures the output enables of bank 0 +
    +

    +

    OUTPUT ENABLE BANK 1

    +

    MASK_DATA_0_LSW LOW BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
    +DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    +

    +

    MASK_DATA_0_MSW LOW BANK [31:16]

    +

    MASK_DATA_1_LSW LOW BANK [47:32]

    +

    MASK_DATA_1_MSW LOW BANK [53:48]

    +

    ADD 1 MS DELAY

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    Register ( slcr )MASK_DATA_0_LSW

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +MASK_DATA_0_LSW + +0XE000A000 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +MASK_0_LSW + +31:16 + +ffff0000 + +fdff + +fdff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
    +DATA_0_LSW + +15:0 + +ffff + +200 + +200 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
    +MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +fdff0200 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
    +

    +

    MASK_DATA_0_MSW HIGH BANK [31:16]

    +

    MASK_DATA_1_LSW HIGH BANK [47:32]

    +

    MASK_DATA_1_MSW HIGH BANK [53:48]

    +

    ENET RESET

    +

    I2C RESET

    +

    NOR CHIP SELECT

    +

    DIR MODE BANK 0

    +

    MASK_DATA_0_LSW HIGH BANK [15:0]

    +

    OUTPUT ENABLE BANK 0

    + +

    +

    ps7_post_config_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +SLCR_UNLOCK + + +0XF8000008 + +32 + +WO + +0x000000 + +SLCR Write Protection Unlock +
    + +LVL_SHFTR_EN + + +0XF8000900 + +32 + +RW + +0x000000 + +Level Shifters Enable +
    + +FPGA_RST_CTRL + + +0XF8000240 + +32 + +RW + +0x000000 + +FPGA Software Reset Control +
    + +SLCR_LOCK + + +0XF8000004 + +32 + +WO + +0x000000 + +SLCR Write Protection Lock +
    +

    +

    ps7_post_config_1_0

    + + + + + + + + + +

    SLCR SETTINGS

    +

    Register ( slcr )SLCR_UNLOCK

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_UNLOCK + +0XF8000008 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
    +SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
    +

    +

    ENABLING LEVEL SHIFTER

    +

    Register ( slcr )LVL_SHFTR_EN

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LVL_SHFTR_EN + +0XF8000900 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
    +USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
    +LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
    +

    +

    FPGA RESETS TO 0

    +

    Register ( slcr )FPGA_RST_CTRL

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +FPGA_RST_CTRL + +0XF8000240 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
    +FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
    +FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
    +FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
    +FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
    +reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
    +FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
    +reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
    +FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
    +FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
    +FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
    +FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
    +FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
    +reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
    +FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
    +FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
    +FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
    +FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
    +FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
    +

    +

    AFI REGISTERS

    +

    AFI0 REGISTERS

    +

    AFI1 REGISTERS

    +

    AFI2 REGISTERS

    +

    AFI3 REGISTERS

    +

    LOCK IT BACK

    +

    Register ( slcr )SLCR_LOCK

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +SLCR_LOCK + +0XF8000004 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
    +SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
    +

    + +

    +

    ps7_debug_1_0

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + +LAR + + +0XF8898FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8899FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    + +LAR + + +0XF8809FB0 + +32 + +WO + +0x000000 + +Lock Access Register +
    +

    +

    ps7_debug_1_0

    + + + + + + + + + +

    CROSS TRIGGER CONFIGURATIONS

    +

    UNLOCKING CTI REGISTERS

    +

    Register ( slcr )LAR

    +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8898FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8899FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    Register ( slcr )LAR

    + + + + + + + + + + + + + + + + + +
    +Register Name + +Address + +Width + +Type + +Reset Value + +Description +
    +LAR + +0XF8809FB0 + +32 + +rw + +0x00000000 + +-- +
    +

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    +Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
    +KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
    +LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
    +

    +

    ENABLING CTI MODULES AND CHANNELS

    +

    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

    + +

    + + + + diff --git a/project-spec/hw-description/ps7_init.tcl b/project-spec/hw-description/ps7_init.tcl new file mode 100644 index 0000000..ad6599b --- /dev/null +++ b/project-spec/hw-description/ps7_init.tcl @@ -0,0 +1,835 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000100 0x0007F000 0x0002E000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A01 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01DC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003F01 0x00001601 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x000016E1 + mask_write 0XF800073C 0x00003FFF 0x000016E0 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001280 + mask_write 0XF80007BC 0x00003FFF 0x00001280 + mask_write 0XF80007C0 0x00003FFF 0x00001280 + mask_write 0XF80007C4 0x00003FFF 0x00001280 + mask_write 0XF80007C8 0x00003FFF 0x00001280 + mask_write 0XF80007CC 0x00003FFF 0x00001280 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x000A0037 + mask_write 0XF8000834 0x003F003F 0x003A0039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 + mask_write 0XE000A208 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000100 0x0007F000 0x0002E000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A01 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01DC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003F01 0x00001601 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x000016E1 + mask_write 0XF800073C 0x00003FFF 0x000016E0 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001280 + mask_write 0XF80007BC 0x00003FFF 0x00001280 + mask_write 0XF80007C0 0x00003FFF 0x00001280 + mask_write 0XF80007C4 0x00003FFF 0x00001280 + mask_write 0XF80007C8 0x00003FFF 0x00001280 + mask_write 0XF80007CC 0x00003FFF 0x00001280 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x000A0037 + mask_write 0XF8000834 0x003F003F 0x003A0039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 + mask_write 0XE000A208 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA3C0 + mask_write 0XF8000100 0x0007F000 0x0002E000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00100801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A01 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01DC0C4D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000260 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003FFF 0x00001600 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x00000600 + mask_write 0XF8000724 0x00003FFF 0x00001600 + mask_write 0XF8000728 0x00003F01 0x00001601 + mask_write 0XF800072C 0x00003FFF 0x00001600 + mask_write 0XF8000730 0x00003FFF 0x00001600 + mask_write 0XF8000734 0x00003FFF 0x00001600 + mask_write 0XF8000738 0x00003FFF 0x000016E1 + mask_write 0XF800073C 0x00003FFF 0x000016E0 + mask_write 0XF8000740 0x00003FFF 0x00001202 + mask_write 0XF8000744 0x00003FFF 0x00001202 + mask_write 0XF8000748 0x00003FFF 0x00001202 + mask_write 0XF800074C 0x00003FFF 0x00001202 + mask_write 0XF8000750 0x00003FFF 0x00001202 + mask_write 0XF8000754 0x00003FFF 0x00001202 + mask_write 0XF8000758 0x00003FFF 0x00001203 + mask_write 0XF800075C 0x00003FFF 0x00001203 + mask_write 0XF8000760 0x00003FFF 0x00001203 + mask_write 0XF8000764 0x00003FFF 0x00001203 + mask_write 0XF8000768 0x00003FFF 0x00001203 + mask_write 0XF800076C 0x00003FFF 0x00001203 + mask_write 0XF8000770 0x00003FFF 0x00001204 + mask_write 0XF8000774 0x00003FFF 0x00001205 + mask_write 0XF8000778 0x00003FFF 0x00001204 + mask_write 0XF800077C 0x00003FFF 0x00001205 + mask_write 0XF8000780 0x00003FFF 0x00001204 + mask_write 0XF8000784 0x00003FFF 0x00001204 + mask_write 0XF8000788 0x00003FFF 0x00001204 + mask_write 0XF800078C 0x00003FFF 0x00001204 + mask_write 0XF8000790 0x00003FFF 0x00001205 + mask_write 0XF8000794 0x00003FFF 0x00001204 + mask_write 0XF8000798 0x00003FFF 0x00001204 + mask_write 0XF800079C 0x00003FFF 0x00001204 + mask_write 0XF80007A0 0x00003FFF 0x00001280 + mask_write 0XF80007A4 0x00003FFF 0x00001280 + mask_write 0XF80007A8 0x00003FFF 0x00001280 + mask_write 0XF80007AC 0x00003FFF 0x00001280 + mask_write 0XF80007B0 0x00003FFF 0x00001280 + mask_write 0XF80007B4 0x00003FFF 0x00001280 + mask_write 0XF80007B8 0x00003FFF 0x00001280 + mask_write 0XF80007BC 0x00003FFF 0x00001280 + mask_write 0XF80007C0 0x00003FFF 0x00001280 + mask_write 0XF80007C4 0x00003FFF 0x00001280 + mask_write 0XF80007C8 0x00003FFF 0x00001280 + mask_write 0XF80007CC 0x00003FFF 0x00001280 + mask_write 0XF80007D0 0x00003FFF 0x00001280 + mask_write 0XF80007D4 0x00003FFF 0x00001280 + mask_write 0XF8000830 0x003F003F 0x000A0037 + mask_write 0XF8000834 0x003F003F 0x003A0039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 + mask_write 0XE000A208 0xFFFFFFFF 0x00000200 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFDFF0200 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 767000000 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/project-spec/hw-description/ps7_init_gpl.c b/project-spec/hw-description/ps7_init_gpl.c new file mode 100644 index 0000000..c2c173f --- /dev/null +++ b/project-spec/hw-description/ps7_init_gpl.c @@ -0,0 +1,12356 @@ +/****************************************************************************** +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000110[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x3 + // .. .. ==> 0XF8000110[11:8] = 0x00000003U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000300U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA3C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x2e + // .. .. .. ==> 0XF8000100[18:12] = 0x0000002EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0002E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0002E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000154[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A01U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000170[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01DC0C4DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82 + // .. .. ==> 0XF8006004[11:0] = 0x00000082U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000082U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa1 + // .. .. ==> 0XF8006014[13:6] = 0x000000A1U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002840U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004285BU), + // .. .. reg_ddrc_wr2pre = 0x13 + // .. .. ==> 0XF8006018[4:0] = 0x00000013U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000013U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D3U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xf + // .. .. ==> 0XF800601C[14:10] = 0x0000000FU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003C00U + // .. .. reg_ddrc_t_xp = 0x5 + // .. .. ==> 0XF800601C[19:15] = 0x00000005U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00028000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x5 + // .. .. ==> 0XF800601C[27:23] = 0x00000005U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02800000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0xb30 + // .. .. ==> 0XF8006030[15:0] = 0x00000B30U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000B30U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000738[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000738[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF800073C[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000016E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000740[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000744[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000748[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800074C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000750[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000754[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000758[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800075C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000760[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000764[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000768[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800076C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001203U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007BC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007C8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007CC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 10 + // .. ==> 0XF8000830[21:16] = 0x0000000AU + // .. ==> MASK : 0x003F0000U VAL : 0x000A0000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000A0037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 58 + // .. ==> 0XF8000834[21:16] = 0x0000003AU + // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x003A0039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x200 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x200 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000200U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfdff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FDFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFDFF0000U + // .. .. .. .. DATA_0_LSW = 0x200 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000200U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000200U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFDFF0200U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + { + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/project-spec/hw-description/ps7_init_gpl.h b/project-spec/hw-description/ps7_init_gpl.h new file mode 100644 index 0000000..46ffdd2 --- /dev/null +++ b/project-spec/hw-description/ps7_init_gpl.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2010-2020 +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 766666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 127777779 +#define WDT_FREQ 127777786 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 100000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/project-spec/hw-description/system.xsa b/project-spec/hw-description/system.xsa new file mode 100644 index 0000000000000000000000000000000000000000..0ce502679697c122fc3ab788bb94fa7e2fd02063 GIT binary patch literal 557743 zcmeEtWm6nYxHc}qAy}{=fdtou5G1&V5InfMySux~BEeHLPb zPSt#xnyKmT>b@_#=cgPZ(t9{KI5fDTQU$ff5RwT)bwoJJ7C|^v*j;5iF;+th=i@dE zZ(}K+y(i%kkXP)Yp)=i$c|VSH49RzQ3fxqW;JIl`LsNYUn)7gVd`WD22TI%}k~m(2 ztwV_Qhm9&DPS<}?XhQTxiumWJJeovniX;T7Ly7P}MQKMTVG?Q4+udChPVFr^jDDXZ zJ=ML5qSR@wDWBgn4}L{Lsy871m0vH4f};nXo&V-ZuMlyyv1-qran4#VZ0v*`uR}qV zEvGiTt;QGGb}bvKS8PC^E%+fh-8Tr?>O*bEeQcVJkk`Y`SQEMLJ4wBJx!Sa`_8Vf~ z-N*$^cP8yWG`l(9ydIo#c~R#&|Lu%^41Ddd0-LtOs( ztv>i{J|cmuitsw8;|4^Wb1&aMwQp;@?^ zzUlP&En4d2;M{j9ySB(WNUQS+^HEm)Guk;@+#v_zD~xHiDWI($GwSwS;A&a{0Ya!_ zsH2ghBb<+h>R+%A-U)U&C)5DipIU+|x<@V4FGyT?qy%b4zEPSclO0$+TYKGRCxFK> z#FvzsjOMzku3J2R*X{spkMUO1-(aljhZBEz!zD3j|}0EUG{al zNCdqX6M571+rOgHO8{>&8N|{hH)|%p$l6ropt{_oCfqLFjr#O^mRK+zq8iM)XcFjE zs8s~n60VmK^v6jRaNHynb2z?c@thefbFUQdaorR!SztPwOVwu$O?k@;>F(KR2`t@H z6LVeca$Ti)dg?Ac{LTNNZz90%!`a;5vE|Z?VoBXf&BDW>pK7jF_nY0<7Z}!9QF%_}{4W6EFfV_a*73oG66+DhpyEPF zP%t}ax-U@nxH>`lmT!lQ?T&^hnQ*^yG;|_q!q<`Jf>f>N86X>tDS5$rvA#+#I2nE; zw7&!Q;c51Uo_!rQ$T)>l2=W{3JMl`Zn``JoY1TQ?9m>oEIeD7+DwuTI#yx*E7kf{muc8&a4&|01XH8fyn=_%G%u(u3OVqgE zwFY|n9s7*!iODGNpY$*DAoiFvmW$_2ojQ4y(Q6xwuR%P-LdUXz#TNxw5_`8$r_< z#*$!bA&}=<1bc0!<%}7$yl0;ELZIr@Q;I7O$Bgvikuyb1pS#1j%E?cF8ZE{b@i3O> z{dsmsJR?ntK43DpB@*gv$!$$#m#4Eb*}G;>n7dJaQd(x4TGL4zp_VkW7^p58v9`(B zp8wc2MZNmWtg0$}bmQ17Pa5?d?C){AgHfMX*3xfN zXN>JNPKU(@IBh!;&)^Q-rlX;o4)<*Y*S{YWBxvhXQnvKKZ#!xKJv>0=La0Yt*-b+J zH&$%unK@Y>Ti-!G>=|LN3L6pE~%>`(;-Lr&a&(aA)@zOtx@w1iT?Gd#d~pYDO~L0-N@?Fw^MXt|p0@ zKYBd7hm@S$E^}S8>6X0U%Ziiz-t&1R=dTVXRHT%^tbWU*axU;GwU|*-IovaZ&Q+Uh zJWrU`(EaP{WroE&#c)aQ$6wP%iA%IwyK(56``vdt+wkm%@5BZq ziG9mX!fo&SyyeN33ByHkY5lfkd;KFAnwW~-^QiuHlU9eznrlRU_q^cpl)vUm=x1;* zFW1>PfDqbqGTB%=M3}aHDR4K$P3mdA{LDd(A-J>fb-`+rFO;uSd&veVR*R?K;pY#a zM)dY8<*r||M4K|_Z;Yl|%WK9d^XrUxx;05*=ggHgoi&H)B*UiJ2$#HrF|U)li@ zjiPzSjSH#*l83~ri6kE+C5)`EosB?vdV8?_8!6r^r#+*>0imn@LR3zV5dsMxW>}p} zwsj<2Loei})Zs2X@O|i;)9%u$VpxvfpF$0>U|OhABuq1OB1x7)jUjMuGL=Xp?2zeusqu&~8z$WesT5?Ps?nnpHWx;Kap27L~) z*SrZK+f7}?kv+2~)Kl6KUqCuywbpQ6sgJ%<`&VcN2!LvL>B(M!4f%j2*IEc`?dJ>r zlS=9w`+L1YO0LL$9_|#ttcw%PKK2FU?B=6nyC9aZe)=n1y-`y6Vc-Nl!C`~N4Xz8r zgIa%smAQ^#X-9b3>Dz^{G+=^jfh} zRIY@IB!c;|-7JD4v zOnZ`S4V_=MRnCSesH7ox3)@=hHhQp4{&nY_jq}aFs3uWAT=2U6#-4VFMi2c9@9Dd} z0Z3kxnX^6k0o-1ER?eO+JV{8-%D>KtG{NK!1V;Ns=Zj0(zig~J`EK3Lb)PyA#u?E2 zou{bjFwcj{F6*4sf6`ZMj66#R0kB2-5xQ~h)e7L2;UqeDeR8nZf3JpcayHgmdo5qR zmoG0CNW6_vtv27h`+|Td8~oyLbn2sD;+rGLUFaHnrSA4#HUJ!7R+q8>=~49#0aolJ zs}{bpVuZPT=~mVV_<|^7Q+3)di3k4qd1nYV=|s;jvmR{6*uUjT2(u~GQ(v}nb-Jt& zvMgpg@N}fK8HA2Gggk37zqD9c&L}~Psfvne z#WIt_omC5=Svt1$crCc&6dOvv{9}uAH_YUAjc4OUDOhM(f8kWtk*}*K2voYVwP?pO zA8T2(E*!2Z7iTpbSlWbe7g0G8>Y*3)7M%PZXePSbg4cTcR5u4NY-*zr+Y;Ge56-?l z31<38kJQO(!?+~4dN>_w>f73%E;eTXFRt__7JAQ$#$-)+_Vf8;I}FP{b-U2g{UMFE z5hqy%nN(99Ra&j#SN@2*^jf)sP!_!%FpBy2GBReO)G4svydHjP5!clG5>0#urJSDm zcGnyU-RGC%`7pnM<$pG@mY3ss@suWB*NlG`~qcJd#b`n^|Zk zBf$NXp4!2GGLQ6qVLL&3sc_~Oz~aFmX>tZeZ+FyM6mU(FxG-058CXn`N?xul(!Bz3 z00C64$a-HI7LQo{E&jF`=2;_13BCBl4GyfqFmqVUdXG8NBl?i?BFMji$AHHMGuU#l=<2brP_Bjc>DO?*zcBgRQ zRvJ~_&)D&R^=X;K{-_7LDe~>O9-wp*zB6Hm=zTU)k!a~~iF4WTxjyf}&1877$xQR> z*GmUn6B7c(!GT)sKEK=FK;xb5qc`Kh2r57X#_MbD$7g-&GfCpty;imNHhw)nUxx-unN=G@bM66g601pOW=ulMUd8cVUN^zcB%xv}&d!&b~xRD(ITQyM>&x=lZ1P z@=Wt7H0$e;YtybhDgLk(Lh&M)d{wu;Z7?pYU^87~x4h)X7`*_VSnCg@ntcyxdX5LV zV;uQBO$*9o@Y=qnkNZ?~zRsw6%H8?NjOjn}$`4kr7F7#MPLT5x>r~m*8W(e4kJGL5?{0(xM~(vO*g+s5YM3YwApeAf_rC>r?>O$e zlR_gQYj+({gXKdZ|Bt01kMO(xIin5A9x@Fv?YDhc2&?S+-j&Kh<%A^sxjv#F(s(K+PB^fpFOgsN%vO*LPAWm z;~JwBGk%s}De}J-lxQ2QSLHepj^T~_z7$X-&V4AHWjdtGh@(2UbnhC1v7JD^?fpns z%@8Gr8P{2&G7)^3Xk6`X%K@GS@-wXu(XNvg8l+?t(rG;2GRox(f5Gwjtq|e$9&t2?fAU`meRLn-S|!{#wK*s zXLdc+%bp{0BGW>fu(37W6rM!N3mkDp79lInmwqQ4jhV-aTKiFF^4QK= z1jB`fQpawZai_pzla3AL9%e?ycG9)@Y~fAD*TDYyLi_EF*%XVS1_`uK(~-RsOf~Ha zjBU|68p->^!%pCBa)humVI2BL%w}6!1m@54TG*-iV+t&2yuS9)9Z(oV%v9YPn$F3K z85PL+(e)47zLyLP>8WZ>QNxdVn}(IQ!G$N4A4}sX{Z+xmA_*6HaT0iX6>d&HIF7Sm zrFy})FXv98zNB?5nIOA^EHw$kFw2LZk5UW7%HwXLDjAa=oThV1K>CW|mck582Znjpn*YR+^uAmQy zUBGH#^)d>F64@L;T|dwtjc5)$M&TDyR= z!taU-v!qEASaGYcYskU2mv^;G`g}+^;IIYu&-ydwqPk+lxv|MESFeW%6Iz z=EF+_%zF_APKOZX`o68*o}e zDD|+`s*vOTBBuy!8-qkDxN09WzB>M(hu2uP+%Zn);|10cseYvfUWb&!S??PiiQdd0 ztbAizrE(!>vz}Bv&r@G&xZvw>C^%zyQtS&7jA+?HQq;*FVHlnZ12L$jEfRIgu^;sO z8#R)r{9LkkmuTC8K7NqDzXX1@i>U3O=Fl76jzd54J6g7B4#qgn$pDrd4@>UZyq{wW zX3E0(nq*;zFXW|c>+ezftW{fCl+ZUZ^=7e;Tae3>lcS!8ICNiUupg-KYSmDr*bVm8 zP3IkIbHVJ0@4HRKdOgR=A5F`R_ZJTTnnSQm`1rt3Y2X+>%lzH6N~SB6+23L5MMwBs zHi{x$&dpfWCni{Z?HG0evKl-igB@M1uhGf+Zs5UO^?5biX!^#~i4TXhPJn`$;MlE@ zw*V%L7K~{N8h|*YDFNa zgt23Byy4A5M1$e^l&<|FRj`n<84KV_f!75*Dl4cJvi=0#E1p3!J@;5j z30`!#Pj&8o0IW6ju_b5wtuwYyMys5Hh)f7A(~B?-+q9DzzovJ1+aQ}P@Hd>HE33nh z_qcyZKqXbPb2Gov!>c;3^ikdvohz7$F1Q$#_oFN3NTdJvSqN8r$@I&!gn3MdC1CSH zPB>!gbe4rSw5n}!Q=`n~xw-M9Y_0>LUIK@Zw#fOwW?&Y0M!!y*NLjU%<-5;IW$%bg znd)IVYDKJ!J)8>4Z&|N_X9?Vh5~i^txOzF_SRK`tz!2*(<-qbo8aMCd@R*MB_49Nl zh5)r2gYUhSFwWehPil*ByWmKWbM^WHxAeA7^#Shflp2jRSR~AlhCs2|GmRs98^lRM zMWMffJm!Y1_w_Pwu`=Au=QKsJ^?pasYiOXsyW(b>N^oy;Pv}*w=w!&?{7KI>i3vFG zI5~bI6F*h0*>A`Nyn%P z6$U#_VH?I$5cAEkZYJ~F<#XFvR*T75LR^ESip^}_Bk~rQU0+triK^0i@-fX%=><$X zX4m#}!T7=$gybZ&h~(N7SlN3qf3L*M5H;raI?+_%WMo838x%FSO-^*YU$@v)07@?3EiTN}cZ@*`#^$p@bZDDv_-V&(DU|I0M5uH=YEyT;#Li<8 zi`%q-Fom^VCi=i(Iz_1Wi)l`|(B_T6eSv@da`sP2NY}1fSJLVv+}}dYUS$IRwQ98* zXvO7`qLO}U=ooG$pVKs$l=Kq!W<5H!QwY30%xwq(gtl~l&v^U;VEme=%87=0!APjC?#MQ$7;oD)p!F6q zt7CkQ58E*g+A#pBxgzn#?muOiihAh{$X{Q@b=L4CwMt{ye4wgmfgk_ZMIw*~=S}jw z6K_TQ7kC_&2wt%2DI?1V{ym7=Sn=#g?&?}QXHmaQSpxT&bp~h%8LR!&BKn=mV7i!# zwdA9CDt+CIjaVf{-|8)EeXk?87U8@9=K5)D_e;ND4Su>_&9-B|a~E5*`-}!>c^2~1_Ky*)owJg&Eu;S% zwxOw!v1p1CW_QY6$?Coz7}%>FHMEk59_Xqmekra`Yhh1P}AIx*=O>K#^AwG z!X%R|a35UsI(w{DGA5S8zYq9-G8TiKvir(EI7LNr46kF22W0ouD*mK3Oca}}C)NyB zhK5?q6OoYF(s3SgV!c zj)Hn_5>|3B4lnZSfk*v<5F%XO=}dZujiyLJkUn;6`pL4gt%eg%Z6c0VBY{QPt!u0~ z5GoE;u_>&%#pca#`!Ywd?qbDMvaom3MKkYO0dgN^)Lpxz-C^P|V_PS;M}1GMZ9X!- zN+>6~sA0=i@soaagR#Avy4*lb5`&AHJ>UihHK_&Pafe3!@KdU#nl$P8slrwqjMGaC zaL)^+r|`tK*ol9f71Gm0ur_3$Lq@sDqu6-Y_p7B3rdxZDg`;;&TwFEN;-ptNFAqjo zA4V^NyluH39AI0vNA+e6X$vd1en$RZ+!`K_Y6t$TngY6`4c||QG3W2GUw!Ns>M)Xy zj}xW|ml#t!#>x`jW5Au?Q4|JY=zzfUdP1gBrz3{d$O0TtdhW;n#>8qN949+$L3Sy_ zdyhVZ5o53YQ#mp;av~Oz8_ws+kf7tPjqUvS*$MXX5X(k5uC8Zm%~c=1^|Xp*FFOLu ztx9D`q78ZyTWDI^l5yyO%F0aVtA^n~K|*CV%LR1Vh76bInIaM#g$* zItQ=;Up*X+fThh=ofz{tV?rWNsa6W3`l3y_Dk2aZ!&;(_$*Y51YJitD^W5SrYtPlh z4*Y2v=f73^2bd$rR2^@pMoPNcI^L>@yjO{8VV!^N-JJC*>73~E(-1yvyv?&I0+69N zNjw&d{emy-;q2|8)PQ^jY)PPc*q1tMKC0$|%k6KQpPSZ8brr;@NNfKnO9iv#Je;4m z2h@%xDjRIGT9h=4XPT`l5BJ`tlB#?u?UaD>ucfd>R)*qGLGFl99}>(2#Oi15KiEDH zYY4|t01IC#ZYGJvEzECiJ)NId*VLOnloOxg6=!|Dxw@hHv!-CRkPpaMh8dW@2>(z) zwC=#;%`%OTk)MgjgbY^VAV;?X|FnIWlP{uRKzjWw{$=VRvVp}yGn0MPNISCTe)3>g zmA`N=X4dAhmnCPN6ukMhWcCX464+B)Q2eytgQY02vWlAjaNZQnVZ<3(R5ii;&G89L zbe%vN;-^n+52ZkY>BD=zBXq2REBY<^sK2=+ zg8cjE{7XHt)netZG@;xlH$P7DIvx}otcFpe)Lob1^KZHty~Q~J>V`=@5ViN+)Y-Tt ztglL2CNdt4#2A4Th5#n(`;*~?hKP|w#@&NXGvW2(&^Ky(YnkE zbRrMN($9K_k*BwBuGvdFzT^2Z1Q+Ix`_ekS-ahWnQ_RBybo8Tchl(AQY@-SX^gBYEJ%V&?5VzqP@68sV11cn2eZ%uEU;cpEXGI zLSL%0G!q+pS<=^u)Gty^hQ&0|CtERH9>#^9S3;DfW=6b!`B|uUBSAQo%zH?KnD~3R zLcPXp8hBOOZ7~px2vDd~ajdr-61Cl*#YS4}(i+;J^WtrP6;5>{-rR0imol=A!XV~O zQ4IGU|E*m^h&h4k59d|Jso+JTfcgQ6w7)8hKUdXwA*EVCB;}d4*1!0w-M#ee_P}5< zE?p9R>#e2?hLRE;bW)&}^QU~Xcm)WhlM^`6tlH(e6hv*D?-HIF#zY zMWIad8(p^gm;=m-JI&#}P@c{Ho?W}o1!zT1fA)fnfn<+Cve7J}_21`{)0?3YVjaK- z%EpCYoZfycCH0rx@lcMojG)YB39buO*ovg)6s3?=0(dif*9{zOtBt7EHy+xqzyOU< zGuGQj0LM%9tOm%)>*{=>tvvgy&*BU!lzjn-UGH1W(Q;K*@~%{a##d6B*?GE*T=O%n z{y#=vzfe%D815Lmm%ejBoA-(a0->L2rfs}U8eBS*SExjAd)3qroZTY}qJkI+DArmu zbZcQ^$Z(GZkn|9p;RUy{R<*%4?-89V%u!1>kyfN7s-B%Y=MVQt(vbaY`z|>ozo62quq~0@MLaHczF<;#4ZRDOLuPDkNZ44I?Qnyx_CrUDY`^E8wQBln60$ji ze@#Wh`5LYa1^qS7DU1Jsyrn=jxww4XefRWkQJ6xyN+0zM=(n4y-Nr7Vc!Gt58obl3 zW$HX_ARcwSDHy^V=@7l)8t3TJ>%g`gntJWnX5t_(GJY)3Xpzxjo#~4elrPwk zeX|t^wn(8WYMD9av?k)iz}ZJ&FuK)2Fw3K z5Qacm9A$#LT5%JfGmLF^4K^sXw2_mAf3cQon3k7S875KVtJO&z=5}2RGQ~ATHms{s za=MG-Kz|GkFsAE}P2E@!DE|69U*lkiHx^`(a_zI%S40E1b~| z%JjBwFoPq*A@#@nRQ%3?p5jB)kt1HHYZ#XE$dk3N)dWL-m>FBAvj`eld9>p-8dsz{ zsU?3&(TMfTl*u4JiRwfkzqFQK2;_9q_M%tpYK3jf9&^Q>zrPDxgP+}Pf(Bs-(e-a3 zi@;~VP2^YrdZ~2(jVLpt1XgyO{tR#Wt+Bg3D6^BBF;2s z!K-btbhjTYO2$W{>&UYAAvHox+W-h z>Or!mbl$TFDM~Y2%@EFR*Y02bJoEQ(i}&v4i|#(aF7`MVpI~|s;&WFcl;Sg04z9Ez zyXCm%%dnYdp|0iR^#{lL@>nI3FfKN;qzN<*7K8-5l!32?>0PlY#Cg1{ zF0;JW9D5jYTMvTPyaPp4)!-m)ZyiEazdBxS?~rC)ncM{b&_H-QxG%PygxX&AeddzO zhm_A3;iI=!A7FMZ(@aaOYKj8B7Ltn&_Q!DmdalzNR^{7qiS6$PD5{&kKrCQEx5MvK zsfxXqem0o#Ofz8cHUZJ?Wf^*_7OVRR`BOeP@X?x6hVeJ8`}+clH4sTClwR+}a?fF&u|!KMPUwF9CAZrLjth9a@?_MoZ8Q0S4A|qa zCKb1N%59vad;X6WY}gqy7OkL?eZ9UF$MCqn&$PObYKv_Xc#~DWReE}ee$XD}s%r=k zRysP|rOi<}ol1_flAC`a?zrd~pAR5Wte&&@z>T5FX`=oPDt6>mPv&rUPnW9goe zUF-W}x>Cli`;V&QSkl#v^`(!Cw`Obb<$|>T^vCYE%sb}9!Ez8LQ|-^tOQ@NFs~RzZ zwd`z0Fh#e_(r}hGuY&NG%ErMePOn{ux&czYt17(NfwQJ2n`7gnl*-rf$B-trUd2%0I2Z9_=J_b>~(2wZO(>9w5I3sviIEcGCD|NcW*6JY!3#_0z2>j zwV#=~3&jI~Gz`BRw@fjMtF!T8ywg)VQe>Vuahny`kV7sP0p$t6iUL%> zXHchm72l1S~0RFY1^rP_M^ z8hHJ(>a!7UR5e%;{DkTj-M@%7W8?~5W(}MVe;1WZ+qx0zP4K8Gls_kX{q2PhD=t6M zL%GM4Aq?~>Pg9ktomO#_iTNb2kzOs3Fz{G^qyI(u!23X8M{<#1qx^2taO)9PfY zJknz~#$6Zt8~kEkY#DF*UFA1z`(Nl$or7MeF>2u%i?05440|IOx`H4V5Ui^DC1g;( z5jP$Jm#N6G$2k2@UBzOrskE8tH4tg;E<_kgrm9iosd3D8+udO16yqCCs^<&??^4@(~1}y5@ubHCmRqe z(BHUFgx9r6H-X?OEr_3)Q6}B)_-+a*q>~la^OfMA*3ho5LLO?`h|1a_k2)z6Yfi>2 z!K|G$QcxX%Aa4Ry!VGqA0o_M2q6g@TiK>eebUH{rpT6+h(p8N(p-lv`A{FD9Mv3{m z(ThX_vp*d7z#%ie&R#gGpQrfu2(^Vrj(8Cvjd)3_6n(10-OMf=bc3{iEp}AIi!;RN$j1pF6dDoR6{l zL&NyUtRR3v`&Sy+TM0WaUAET2it|MSCp|Sy_>}FJzbU@hguV09nMh`2D&MLfW=E)~ z$=6Czmn-ds@zD>;mTK|cf0yZObJ1ZkUQe@3r+V_QN>zR5+Iq{`+u@w8=UtK_QabeV zR*P2kM`I)6Y5P`OocdwI7a%j@XrvvvaO~BGBewf);b+&Kv9l)<2n#-BhJb+E66bGg zL;e|a%(&ZNpOEem?aY0SrAk@!x=_@wg>B*0i|QmhkC&8=U(lg;-Pg4M7sFZz|%)hA4-HE7;3a~1!`;eG6r^L3az5T@f{ zpy7-85qRZ#&V5S8{cUN1{)17{)F+=QApoRNqdz%TLCx37StY|QySmTE0M01+sb{tA zthH!`zM#Nt)EHpF5?jyOe!oSpJ9Y3I=V$=OJW0*U=Ig`c+}-IXU>4a{obKJ} zZL^j0bvY=O{J=WN7>7E=mbI+qcf}9D*YnW)Bk)Ew`usz9lSi}$gW$=BQlCVwHmWV8 zW>aCw^r|bW6fLXu)_#v##jQOR0UE>G--Wnk-$Kg@62J`t{aP|wi3GVxRaCyd@io!WWqn+#yTBi(EE^ZSUZ{n=^dJWx?{pBaf74gIHbpnH(Df0FU3qAaaS?%?6K_(V*r+4TUpuH7Gz+%^%u(SYXpWc zWg)IS4;j5pz#7}iMQQBehVn?H%8sYFKKxi{jW*Qo7Q!9)l<=M*pyRMgzo%0-Dj{7~ zqmPc|_{%oL7IP0H@FXal3LpPgOpMz=;>(o%=N!#>Dh_=)ekG^4b^oo(fa)GWlO)yUR^XiMFOJ@RewavZ47HbMo(4YgkVep!= z{^-%sWjaR~XK7@FQG65hYMGD1s%};J(GKPp1E3^E#V+GK`1_ftyv&3g??lvSKM56I zX|oHy`+_E>;u78KBw8cQaT*1E z{V~MJ1x^X$ikM(DomtI2uN&&GSh909^q?X_G6iUvesd=Kcx^u8sNFL}QLCNKMCAs* zTsgIcCMZZ6QeqcSa1yf8n_zIrT+Tj^@n1jMOsnUawDKUkrF8AuX0SC_vTNmB#Cl=I z&V4_=*O}J;NI@Stgn>0EGS>NokkV4W`{!MuOKVP|dc6r4jvf}j*-f|*OXUioxo59W zm~icw=;1LD;=8%4W-JbLV7?$XboOu?a(y!yd(EEv&B#<^VWpG=pvBM9k^by+ZR5NV zUf3HB!YDn~8{8WtVHs^7#I(_n&?%1k4o0ssDo^s4ffRPW#60R#y$e&Qfi^nocTJOLfx- zDJpB4S?gCO+YoyWaF%tlOP@>ZH5Upe=8LBc0z<0@2(cc%@3h?@v`b|)55Ua(*YfAc z<~m{ZIgi+dxSc`=E0?)XXE=;0gL)wD8&CI^=0_7l46Pq3o@kJ>vK1XHrZdFiAsLCZ z8o0n3Yvuxl(@L;C;FtIck4G*D6VEj3K!ZQmtjD3m$n!3v%GlHfEAg@(%qb3|J)?p* zWe?|`pMlGE)|^_~S%0y6dur7meveMl8{vEal2dm2D%f~W5r(4K1kGyj3p*14*AouG zx|}!;UkvT_Dec!JvO3InIW~o&88g4!CCxnSI}Lb4ms_QdW`)eBeByx*u{H?(HcMTwd2`KkW;UfjzS+| ze~)Q5hD)51Z2JCOh56ky;3$VR+`qYthvg3iPM$SH>*Q8uIW9R|6U0@q9eUG8ul`C0ZuxH^1ps9*|BO+cjCZAkV{jMEGCl5HlG1e%Z~eZCh@7d8u+R8+E6FkU^<%3$@{-teEn}xAonPL&hX!cW?5Ub zDmb#EM;HP`n9yyGV%x-<*ofG+3RIZz+F zX*sEKG>kJv@ncbHh{210_hkIv1I9=4%$GW6zjsG@@1kXQFhKN1J<^BT*cZf544^<- zXCXI(BdY`R`4>StLS7+dKo2L1s=$DX3w~qud2u%6s^l6|{emK;1s+4rG}$7!r_sT^ z;W6PhZ|3;OwT@vf6;mU6!n^l0@VC8BN=eNj<0_4a-DX2Gg<1+rVA8~w6%D;|H?8d| z1l8qQhi#1ASK}GTg*%Zn3g>SgEm8Y|N`&7kZB%n2l*RSG*S@%DhmFaxSCWp(OcQwh zs7B$gI*GT(G%{*2i$P07d9A9C%vl1d1mO6?o3YVb&1SmxPU|2qAR17?dPXuf>`^JV z_)96(1u6_I$g=8YBA#;LA6| zT6*MpG$U#EhuA9|@zvwUWmy%lU7~RKl7txkgiKS*G0{}Km-spExfX)=&Q_qnuRctQ zX8h?PA6t|{;u2Icx$qeY>*LRHARMhLDvQh2*j~XOe?}&g%Q2lkw{(Ax;qjI8#RplH zC8H~T>MG^1M1-QhT{9fACZIft>*Zge7(V)m-Ql?>jA8+{(0YcHSv4*68bJ~swHPRg zf}#<3jH-zIb2i95dRi)HF#s4UY=@O`#Q@(>J$~~(axz$x51rr$Shpwt1D486$Iw>( zT!`>Wj2VUdR!?qH;qBS9MO~!{UcCQsJHGZaVqZ^wxW>yGAf6P{jgQw^V+%9643*+G!K=UFj8Q=H58yT=&~ z{Q^5yHOC-5-;=^Zp^H7ZzQKmA{|7VVH`(spmY0J(@4~h>iPeY|P~dT&d{zgzXk6QT zbfH;?I-|1}nC)i1M}7E0B$xMZOmF&%d?qFoo9jq)lm6g#gVwje%8hE>`yVcixK}@Rs7T2)DcxrpujXf;k?2}=UyZlN89BaYdc-#RZDAU@kyW702ZAs$ zcAz;CPOFz!UbERa$!5NI9ZX+6IF*0o+Scnn3^Fg7U)54=Z7x-u zR(0EE;ZG4ULl)`El*8g2BR1}nYatPakhUzo)RS))uIi*jlx!;(-(sh2Mo)Rv(r4~Y zog%?w$LKr4uwRSNk=MB-&HN+*nm!@lc^B*^Mva0mxUKJWoHvuMPQ0PpWlr$tJz`hd z_YkWK4|Sca^ZZp8E@_|bx`>d{R|xu&sh1ZpcFnZAxCa2rTupmP#+15rFu zJNGewO2Kl*#$E^UXG=7Rk1Ar7P;#a zTuv4Siou^9;Y&Hx?lHYzu){RMx1`g~GXz$TWm0a4Gmo_QRj8vlD5^ed%otJKcUCR3pBJ%^-2)90+gXW?-^M3^+ z%i9NU&psfCe+<}=(2FqLbWd9~BwtF_f5$5+qvWDWaJ^XQseN0{iMHDmT;4VzpPQPY zDI(g&(ICrle4h!UE!DxS`t-1RX-J=UoG37n1#)t@+7_R`6yu!ezRE0{9Mr#X|y-K zoIAg$%QJy+yA{()K!AALLI>r3VAUi)G^|}hnfOjqRX?kb7TQn$VOR-8&fOwvJ4bQ7 zvRRW@gg}h(wE3U*3;k*$%C(Pz<@;LayoHwPkKGtLCM4qotKafvzjN6za@Pc)W+)F& ze$do>XYy-;P|U{s7NIT};5EfuFG8^UE3GIU+T_)_-lba zB^>T=)zXVE6r~(+yMJRd>4l|QCecVqO+=Z!+HBx21?!OS_$`hxv`LDOL z1Z9iPYOF}v_Mb0Jm&pd+COb?;yJFvjnt#2tL}a)xkEUSEKdHs4Z)X#JD`73II)RFX ztU&SHRRqD9zt?LQ@8@6wRjpcJ+T?!j7iEiTyHuvnhZKcW^^_8R$2MzUC-0j);fG$? zn~Ti$INl2!?Vp1E`rfjO%~o2a)^KGCfr3imb1Z7164eJ;q-XZGgRp|WZT>@T?7%$f zmScg;X*(Q*yEpI~ST|~G{G3oLy@V5L4;GUGt}n0Hl9E*^grY8oCBTwx^>0t?y0G6L z{q>kcwKp+Y7sC{3ZXR`t{eUMe>7#bjiWE*yyhP9M9S`MT$B-9eIgJAox>sQ3K-F)o zyZK)PKEhsF=9O4}XuaVL>iCBPoFq zhFj!Nrl4rtLgmtaF3o!wM)KM)VmoGhJn!x1@bYG9*hyoePZk1mwpLTfen5@_?(1My z*&z{s=>zW!qRtH*nW2q7wR>WXAkygnq=hGm8Dpck=6((0TO-?k!dg5Oht!5bx8;0iTq;%r5a1SP8bDKqrO}pJR zaT|tyexLD_Ga_n%%M+hl5EZNdr5Em@bQaIKRvcuK@*DMS9qCPMqd6uh#-W`BGN1$6 z;FM4y`}Ws-<)ne4-&RM7jjPcgG@NNiq~BBb2H(hll~}2r)58)aRHGFIZ~U2ON5-#p z9CN6bF$zm|`8{R`3eohV#hvD!_COh_>u}g4U!)}q4vj~^3_rTAYhULM)MHl8av0D5 zES7KbXsP9{Q2%JV>;`Hy-(dr$EypgOxpNIJBPe#JKCNr_*$RWR7LW0eTg*Oh7cA!bBg+L3V^0DevHG?9bt& z*FzHcY*!ekTh_45B<2v98v&E=oGN+$?oXXo*~;qZ4333l<=n} z>M3}htmD8Pw8QnXuGAFJ~i%vCK=}q zT=&xbJoa?`bdfvSR(c9bS+Uk*LlGj?p(m%($^9&R1MftlcFuB2>f$-bL^-OIE$;p4 znxXP>pn8KWSrR2wd-RFJkYT#YepNkLTEfe4g88-H9P;sX?C$*RHUzXMW?OnD|k$oyb$y0DcChr?Y zFOOpSeiS~6AML(9>MLNvLBqz{9ai+AMwaQcOxF0Ivr6$E3;%s-Ifx1mv+cW6kyQK_ zxGG#yoGR=w*zHnlp`x)6+hMY*k|s>R1GI)qTJ}|Mw@kgU7WUL#55uptSc7e3zR8@n#w5^gLEFafK4C_asb28|6;B0zY zUu&Yq4q;o*U%vD%B|SIkSP4Oe~}Y;#Gy_TL5PK#uYzp-zZK z_a-$#qNLsCD*Tb(%VDwwu&heI;7Sb1SD+ur$TrWyKgqadmp^m%bTT(5ZlOO9ibGdT^4;5s~ft|m!Y&XaPliYx}UZbxleZs`6q(M{ay`dvR5J3e-$^Js^-D@lw#4&ui4HRgAHTNt@xb54P;*Dwe(s7y@27P-6D5_1 zJ}&t_IYHKpIu?jhGoLWMZC(mWQLe)OGORq&2N@5m74 z=NS{B6_>J+P_fdTnZ7^&ZDvo(h|mCTlWh)XacA$j14d^oTQNBsmg0gw7ZI!#>Q;f^ zNdEaZr5i4~MMKqB@!ly8OkA9;XtuI~K)+S$s?N4q46h(5e%b@L?qOyDM50VauewE} zCdX$ctK&qOUuIkHmtATnQO;QFlWEA*gO46QGe?s?2UC9g+HbHf_HNm&6cH;DOF#Ys zT1A2X#~lXm>XUL+g*G3B%m-CLUl)nHm%pT66bvWWe$W)6*xt_NmLbvL|D06_^g$_w zVA6{bTY-+QA>$wT{IS1q*euO{UJnQ=pvSvy?HLXcRP8t&52mO5t236Usa{$8@P4-} zeb-LoJyJjut)@FPZ`Y`iO`Ynv5Ij758Mc?Xd1kgdt9%2VMt((krC9TRc516}kShe5 z_PwmE)ouquqg>O>s=OXE6e_Sk{aecuF`PXemYJ5c`&*93%d|}dVlCAl2j=VSD?!8K6DRi-(6*|P}PtHSeX zfkSN6wYV6Wa5Rt0p&x^5O0&0JNz=4i4K9``ZDrLweYBpfcBtFG+{xd{f$wI7!qL$v z-f`E7c`bjWrM&gUcaUOVwrZ45Ju`-n1^IF}<8SXAO6TW`ut5jJ^9{-qAU~0OW2npK zzWO;!jU00LhA-s(ru$HbfN03ef#_ExBMAI$x^*Lz`1suH3wc@jIyGwi^=|u>Uovyx zB_JUJ0^1CEcSuY(1Qe`Z6{A{WA3Q@V7`N0exPc9`0aV0PMs( zA4_%FKA39vobtBH<;pA&=!fOAzWb8FT{e?w7n4>F($wCWP&lG>uJ{ROn9PSIo4u-Q zz90F@9rAvF0s+C)Nw0B^nT?v4r}Fx_I*2q{#)c=nR9SV!e={H1klS%i#nG|WGx14s z^*k-$ieZ&G&biKihPLFv9H6i(YR?#*NC#?|%W(e9UsF;__Is?$FuP6kwQi%K ze8x$?#qsFBhjulXPl$KXQ`4YItlRr zonWV(DhK!+bV!(vDt2p>Kr-Bt}+nssl?=J2U_57xavK5e=*x` zT!rQm=I!GN9^QoEIOUq}Q=T`ddx`ei7nOwceOW40!1 zd3?-;14M%r5qhepahy2ThPsMal+8BHj6Mnp7%e1ePRZ)f?Ai|;a!BbYqhdB%@!0$a zkY3qO51?JBxbQet0 zfJIu_uC3*R40S@|st{a*)>!_9Pw)B3?)cl#!#QT>LpM-TIK#xz(**-n@c59ERI&6U z$?knK0m+g6j5AHj8ND?@H%%a&m{Ln9hnG|_A|Qt?9-Mw>{eEr2Y zC{0e1a#s0SU2!RlR6!=#Fur|)LwbpmBh4QTNa^`>kSvb5J_gx%*{aSY4D+u^w`At+=3*I|*SB6iO!js3saIXf3Oiy~*`Cma6F!!e#4G?nWF% z0B*0n&Ya?jyhQ3pxN?&Uk(7pS2V-A8H`+u6{5I1tmxFhTN<6p3m_5hMYKO6uYU!-c z?x~5SaKbP;0->XhZ{WssDT9u)a7=({{nC!CL8DZP_rV%e?$rU9!^zNA1B|0kjYyDm zIi(tUAAok)=Z%fLQq+4gAQ9nG$={d7L8pYPg8DvF8C2&|4K z3u?9jEamQfHT?j~!XCgdZ_>OI#b+E^i@RpUL!y>!j8@feFrpDTJ784FkCt7B zLr;CrH1ITda@6^n$9kpD?hfn#-g*1!-MtrfnOXdcbLIdHE&Ez6^YxR|daEKg zp@eFz0QRcknVj@9d09r_l(0p-d|Js;Vj}HqyIEm-^f9H0(H`RkD7#X(ad7=2IMvhW z=R^H6?L@#qEmLS(S!+Q!QujF!YvVSbCw%uyU?TsLQH({CB^#`NGEI7wSsrEqn}+Ir zBy-8nvJo@|ZT;Q)?FcBCbg?@68^HL9vDL)tNon)@hlvOV&5ZO+=k4DPOVCQkh~=Ij zgZ+W8?}pqqXC{1rV(A%t9QO&yrw_!~w1BgIXzDkgzBTiL<^V-SKn26=23odFg<<>v zk?RC;dIr1ss&moY6on(49N;Ds0;uOO-TT!1TgGDom}1NnV7m1zGG3NldyR6>;@KH; zjq!IShKk*2$V&um{u=j^a|W1>wEt7q?h~3uOWqk?aqu4G0dI4WT#Y7u<;PB6^6KDO z$I`f*^d3Y1_sf<}#UM&k8>4KQJz6l9w(TB!(KU8rgeBHia-12ObnQ6lurA9jG@^{D z<48wup%%2K|8@V$=(<6h@igtiExll~u;%C;y8FarwcY`F1++X?Mm9@(9coVv%OGP2goABnble?q&!`@zQ9p3z$<@u~_bxI%8SkbVIP^Y$+!7ym*IX8t( zF|WivT4c+e`jaVIXVUoj3@=_rCzRSGX?D*1HC3A6G>vljCGA%6K5OWorUvS&B7Z9S ze>J{N=C&nR=NU{iY<5_Is_hZ$j_d4u^CMm*VwB8PZ1D+V zT!};%%bRLDZslMT0{Gg|o)$Id5RtKDZDMLYLBUw(#F6oTGW^9EIFQdUR>y8DX2iwt zvE$#CRGvlnfygFsu`cz2YuFs{){(wKeaXpgbI_Q+MnE|m$=>il_3fb3>CT_NOO(wj z352ZjkuY<~Kt`}HRp+pZSD*CNu6&fkry(Z8RVzcX_+yC((1eG78gCVervB9&SPGvcjfbZS_c(b#jkNb;601=TLIc4$|lYfTkc-G6|c z5Jh)7TWG-8NeG?CG`#x!Z&JZ_L4jkIIY>T`mhJeb53Q>zZDI{@LC!Io#G~B@6u=0` zEeMZ3bZS|<5bo=a&!#?u1F8`I=I6E*@|aj(%c54yWBDIV_Exbqxg@C%k>wAF^lAMS zdL?QoQfTVFX@qrY*dHNmCO;S{V0DBv^q5tD$**P)Lrt^khprnwzmCx5Z{O4Y0#D&( zayKL(T{1YE6shz=xR@#5;!bxw+!o+j98OP8dEOgb>$fNxt=HK$Q zIf;@`@3v5}J%lkMu^IL!ydc0I!NM^*oy_}{;#OY%fB*txf4(`C&XglHI)W{MGpWQ8 zJ}}f2q1LiDrp_l}zQq`hwuOd_#J7bx>>@&n3qa`wx_79S`QnM#7)X~TMyI}OScQHd z-?@h98p&8FA82g61x2cu=A$)w1Ru~$FwU&lMZcE%qYr+!B#;l#wx8T3Yu>l2>J37_U){BB|$sF`*H6bQXAt zTEe3JjSXEt2`)NcC`1`MS#lw#N1zeVgpVE?Tc}{ZZ558C(Rct&1ucSN45Vk&-O16g z^25jswGOo&)1%={VmRWY3%>=bq|eb49WJS5@Z5&fxf&-pQX#Cvd&ou}BOJQYJps~4 zvGG%3aOc!YOi0(I1$;$<%a0Pril4bVp&rgRyV7XIFHUjr1zh=a5h^FRhZ?eSDK4ba zk?;JR2}piO1~pJ!LitrKviT=ctb_X9dx3c*GCVH+7FX)L;(IF*rvwx$w+T zo9ky-wn}7UF7$5(&AphIuH%P|fhU;FGxBECy78bM%u)F_qxPwX(mBXG8={H>UY3Gz zb=8n6|2|>(<*JDY3%i+Nh@QOpO3ON!q+}r~!W5eu8}FyZfZCBkA*fI=G#i@OS?VLC zkpqM@yx?0qh~+T2Qos4!oxyR%ZFeAhIp;GioB2n4a&dt_b12m`lkr2B(}4d)(&y8F z>91<3*&q=A+h}QD=g27YgoBgGA=+ttLJj6G#s})*a0=rkhRXmq2XR~a>ML1?XTs}@ z#ApMj@s9Wmar-lRrxI?;{fKL;Bk`=$USbfiv+PyvnkWTFziNHrOxpSFX~Id(`8Hc% z!Rhf7vDlbgCv2;%|>N#wucnefvbha@4k<`n^P|Go#JNe7*mEJ!Ml?akl5JW zEMmr=DlgurrPTMW6L;)3QnRh)FJn<}Y4@J10sBC%Ll`^bUydCQbo*^&xWhZ70IgG7 z8yg!xprLmPl38lPRkn}bGGgTcNSY7`tv(S&?)RfbYdjym_PK}9`?UCRGa6rQc)YM1 zp^s;1#qgzf6}Q{QYOWpvQ|) z|6$@~u*Bn_IZDh1lH>MFTsRh{Dn8-AyPwsxpB5T2&%VY+beXNpQTg~t!Q_2wHsIM? zsNs_YR6jtwR=CNCLKM2712ETwlS_wBbymZUhaupVUMmvB0YQ^Nyh?m?Gi4h2ui%qo#ba44{=(`D zW~U*X=r3I*b++ql=qb%sIwD&8Da2#1|9Yp@z28y|akP1qJ0vC&ARExKbVw-$mY$dD zw#cu8=uM_K-Y$fMW?f`lB_H376Kf!qILHxqW;j{gz%hU=Pwgg*_f>R;`c>#jmdMK< z!cT4RUFEG1XkObod`hlh^O%HsiVU46U3x0lW^1msv{x#Ijuzh(qhk1W&mh)GQK#1t zY_Wen6uKMxXdW_ZNV(|FS$D4s4#&0~pSG4|aicW(yoln6X=#qSryG+JWap;@2c9)r z!b+SQ)JA48sOZe-xKGE^bHUNQ-~o+#sjH=N@KUyNuW6ppNYDR_(kc!oAl|Ag$B(+v z47z%RbD_5%TL~4WlcuROH>4%FV%166zIbqQZ54d0J!JVM^y8zVm-f%%C`B-Vqc7Ez)6}MIQZ0TK|@c)u4z%6SLT+wEVp> zS85Zfz~o0Nfg*Kg=S~Z}OfR>f1!l&%VQsbdFmi$!U^4Tj_<3+}xMpH!=TH%8_)kE? z9m&}l)%30;f0V2gnw<`H^8RmO+Y8eC;j;jLjz|%!Yxn4NA+C&LM1{t8=8aY_0(1w| zC~=-{!dhjDt-v%?=SiKurO!Hwz#K6tpuY0domH6t{*dpTI(|BO=@#in`23SaL4Wc6 z)x3@qE~7Q@RAed*otbVA+qDkRXx92dm6wv8nu*Pt1PwJCQ_CdBdwR`d)WL)WKR zg+gibP!&`V*uQl088ciyd?3$GC@_qJWaU-YH0alzs?<%Cq-gncY#@TI_z|=jLcSFI zxbVGBc%wZ-7JO3R60P_6N#R;)-|=JF?|U7WCTa?x_{IKcVLJ-esFZe^R{TZGXIw&8Ucp3T+%e~3Z==$;6w2;

    !;9lQg#FkgJ_wB+)s-K8NftoFvtaWO>fS*(1BRUofFo}8`LyFaP$b_%#z~WMqE5C58Cp(MT1?Z)f?b>_OEcd2@J(v(#{(aAl88}%n^kvd4NHmTS_I<66x{P*NsF+%REQPLH+tes=imCA zVad|e_>$dbd|zSh!^6XX?+2o;kmDXSWuzlgkRb-x*=t`8FB0SlaQ4iTQ}`HtAnkRa zAUEZhuqc^Y4Y+a}N|WeAZ8_D>Sh7m|SiQGQxtA-nw}UGJIliZ6;kT?5dF>dpHnp*f z`(Zf-%H!j(Cj96=+n09XAHnulfote7Q`AdU_}z^mg63CF)DHRJfaDVr#%QCZu2B$~DbO@1d3bS!dd(G8F&nriO^Y7t;R_}%G zSxM*sO)gx8r;8rP5E*J)20Fx6>Har00CU-R#X>2;_Rsj~rHe>2t77r{v^ATVi#x}> z4pgyU3Ofq{JkJktB|fU6zbGu>Qg4^-gL8rNF_APD+2Tu((CKrmjEM%`tv?clC`UaM znK8ZYHrWp|Q`a${Uw}%)f-@73GCk%kA%Q@mzH67?Ai!IWAA+{$Fl<--M@@CJwW0yx z;<)CWEhlDjOjT9Py}fTj+7rPH44ub1Q;vVV^Qv=yuLH~;W5}a;)F>*VX=rKh*Ry$e zcwelT>oXIF`XUhAfqHFJm}^hN`yF(+BVFf2b$CV6MMY%vW4>jcR`exe`1Tv%h?f(va?b zeieY)@Hnb#%-N1iK**)8h~AUza+5@DQyxP=J_E*t>F8DlFzgjZVx6<)u<3<#_2{&p z$RE57G*WJM2|MGAcxtrr6!sV=K`u(DS?-;faa*|FXK{cG{Au4_yybSgu>#I!U4BEv zI^&EI`n|R-CYoBn-m#TWDDf_pUCxRleeTSd(lXy*_%D}JClQWw__{H<>J(>4Et6H+ zy+~&9Nd)OSO-sm4Y*2?!PF~}YHs>t9_uQZ!dznR>zmqr@?N1K6&^S?~aE|Fz0fauu%nCJwzFgHLR$2m8H!jV9Xet9uJdtV(?TN#+X`dxvTSKtNnB~L zh~ldE7Su>X3E>J#gmiLDe~AcIq~lj)rZFnWXxIe*891KRR8Wvur9L2Ja23{wjv&ek z(~fPT3#n8KJ{lB*dOlCO_TZiMX|R{YaPLl?v~%x7v{KRcUUGZMFr31`xQJOK$uDKF zU|BBWgYg6r`j0B$Q%=REIJ_iS$B9gD7d`3w&&@!a-(zqnwYz$o%b}$#^`3R#c2z!c zlb#Ouqtjt!IaKjcf-$S;LPYo+sqbeQI>Kv z@tZM!o36}UoR-%N@tSRP#7WaSI0wM_uP!n)4I2Puk^Gg%wsZPPNL!Mbwx%`j4x&FW<4ezxNW4T2)2}^Rl``=zKkxj~j2`nrmB^lVw zu=7lzIvL>r(?B35i&oY`rz`@1rGS{zfVhN30j_MLo)F$ypuD>(RB;ULNb6XJ>PcT_ zRk*wF23No1r~mrO4IcRaR#Zbb7rf=4ndIl z`20O+B|$7xi#5z)E|A21PbuSlO^NWV){Yy$G1V!?S8kPJG#FP*#t#E)yJDhx4G??J z>`&m1nJn?+6Bq@2suhL zO+sQQucT6_yV8|g^5~x~rS)akgX`{bea2!U>8%}pk0*^vg-nSFw{>7g(E5cwO1VKk zvosxbG2lC7-_OuMeD<4pva4tTuN!*X2W*=8$3Bx3)5VYQA%mMy5hC9xR*~4YL3cG zm64Z=o6Ue(SYVgw#Ej8deHK$wi&=lI9;3`&M6Vy2Lna8#XMj2^BJLK$M$XO=4ljm8 zo`VTPkM3F&d%s8v_E{|KsnmaRR=~DDxo*kL9Z8@}Extpns)avdTFr?g^o$%9KDccK zK7#bV95pV)Xw^Yv-b8UK{1z%%#x>0ypeyN zY-AjC_QmJ0usNjovGtXhKh>#w#@cp*_qiM4HRoNk-^jnL+k4&-bBm)bk&{*rkyA`# zvgoCKR*H#C7Rstw-B?B3EZ%JUp)9P0!^cQRsY|tzm;Aa@tVfuvsPjE`p;N*!vi;Qy z;yOzn)=0Fl+?;*dHG;5fGMp` z^768m6+4Edm-(P|^}qonC!jBJ=&pe?;-~TS5zerQ{53NtGw+%@g%q9U4q|t83lWZc zq6Z16v5fLp5YV--T3S)S*x~l*F8oC&oVSGX7-+Q9%)D97t3*+86jlm1HbQ2tN>M_| zy$Qy{oG^Uua9zI9HJ))qN6xM@f5q?rLy+%um@Ft6J9-L&0oWU>?|q=<@?_ z%?GgPgoi8A;JsyW$wq<}7~y65rfogR^i!SX*(ajPA! z`O2SGQg8QtmWd)$#h%4G>y}DBwaL1?F6lV*v}u9l+j~otS2CiK)>9>e-T0X75YzpR zmfI;3$4VF+t->Q5o`@bcSLiD#mX(A3{=}!3jy}mABQ*5TeMUyU?upo8R|`iBYA)`7 z>ws!o8=}4_tY+>Uzy!eb+$BdI7oH1I_3i`^br8n#Jc~pBbLRYX?*N3A6yh$bF^kg$ zvVY!q1}3w<%_tufGR_sb3N8dDm43zSaoSexm{BX<;}Sk_lVT9P+ixiaYsZn)$Pm|J zQL7Mu3?#vXD!tt1z=k=EQ@EGG&$W+Dz-XlwQ*tCS>!InkUrdyH^nDSf)V|!-QK+?= zW_@@bG!3fFLhx#z5??IS>RCyK+dok}*aMhbhFeiRQBre5K9yK`s*o(Zz{cthim4$E zuL?9a`xG`P;Zys08qPf_>5t#Dc_BVF zeMWiBdoR-8=O0HOzI+^Q01$fh&c=w5dgQ2DvER?~am2ScKl1P^v*@uqsn>wD8fI#w zeEvc$QP)p4r;t!zV5~2<6$ur4Da(e5(5@qE_}*$CDzx?uuqh^*g1H7%tOQ+;b@_+; zqX8w^)Ns-t@plkgs9M|E9QCvAEyqi(W`a&&yrR~xPl2&;y*INWWn`Mh+o?UFi)woA zbFaD3NA3oe5CntX9yC`=y4+qOjq9y4RhsyMWdf%>=hec?cvk`)GZpMU!*yN^>N*_> zH*;Q}C&(;x50Qc+dtrjQ~930SCf%8a$Ykzcgm0k)uo&&#$hhZ={?b`gL!h2zS#oA>^^YgS-Ula^lN` zJ?iD#$RPI?2r}t}ai7;HUACTD6|_6?=QToN6>ba1#u(;rEXL|_5LFwcd8aIsb%gp< zfD{`?yJ@AA>klm)E>S(2G2~NRi4t9>_+vh0dWkq#BC)PbPW(lBP>g!y^zAt9^MR{k zU5@ucMA2te%NPZN&^&4Sbmk>yOMji8=$5Ry2Wrk>8s_DkQ zSdLDzBfM$8fhpdQsRq3tW79*~=LgdQ+%EdS{b(?$B1Cv|cqezCZB4C{tb~AsH`#vZ z2CxO@?ueS!Fv#A1$niuXm9wq1eRi<-`CNTUkpA_&_M+=~e03Q8+#mN|MfdIHKAY1p zyW#{fq(ch@VeYz^%~;U7iQ_$NebuUUY6h>=sT}8fSmQgLgaMtC*72;q4oi-jeM$;R zc}<>VC|)>>2kGQXpSANJR<>-OJw{OQ%3XT3O<%|VIdPBn>LNNw9tZ&rK!sbpOAagx zu$)l$peJ?yFkCcib19VY3dfzXl^kdd=U&RXrvB2z@%*n|O-lyI8QEm_(%62pp9lC;^)xR2NkJKgIg7auFQeLKo z)w&G~V_SeKM}!4hKI<_zf3vLgN+I>4i9e;}mry*n12t$Y9{JsI7ZuzCTbdY-jm%$v z@Q+{^k?+7g{ovy7RI_dHc!XJ1sXVM!FOri$Lv+ehG=6`Czm9;@zi(!QaY4&iIU6X{ zhl+Q<*yM>Q@Zb*pExgAOo$+D~Bhg~QHxKYfplc#=3o&VUrTQ&MQ`;IrpOVX(w3@g( zU*6t64b0JkE0IAV5)bdrNe^a@+Sl#=Sc>HKQ%Kd*Q8(=8d@-=ucqk^aO5HIUM1F(z zo9m0^-UUcTwx@i`I` zP5gR@E%%5Gnv!!%Q8J`kC=u-S$nu#H8fli-hBpM>Ev1dj(Xq@^s3DC3jxGBgmond? zKin&MiANKrKwAB0NOUpO3W`j^odym)T*TqWTNTV;)Ch+Nj#u1RISk>90d;M-mCf{> zYescM2epRlQ1^BogDETAoy$F~0FirQDe51|2f*6SJ&(R$RPSn2!{`f0my?d%^NyLC;h0wH&F zj=rg>d+%8mSc`x^q|U>u$wKSvbP~5mVDNc4IyF#=wyNYKfE*~#gX;0I053oA(5m&F zTI19v=^k^$=sU_hF5_;!Mzn)pTcUJ#rY}whXi%_Rh_`=`X2(pOiK?)`!(Kk~G*nqY zvdZOLo`Sw`6WH9%n*4aCKc3(3$lD^r1yk2nLJUFlxk)6OqX_Tj0E7nI76Q=5*co? zQxWP$M+N<8%x64W6W1iYW!seGd1c($SP{IbThsW*`}NT_sLqz@1TY=A2>@^kA0@hu zvsKbM1H)=zg@oZqES$G2q8dKV*p#t1N#bc}P84 zBwbU3pK%CvCN$L5#><%;Q31S-%36QI*uqsmSPb-+`6OqiVxLK)>I*Y29$@`~5) z^K;_;tIyk+T<3mF$93{+akeL9&h~jx?{Rj5C)LU-YG7*-Eqy3;q&&OhIUL8<{Pp-8 z^~|q0^-ortv*UHd=8***u3IX;cRci{T;IBUo|k&I2mrS!FFhf;&c;_qdwXy`X0KpR zJ;+}6%O(JF{&smz|2l37@P>rEu9Q;tj8R%tmw0n&Xm#RC>%FRGv|VLA-n3c1rJVn* zVRm;+DL_4M{iH)N<@1lJ$?`lnQ-b{HD*{EFRwwtVRM)rhkncU`LL?sL0HjgFy?j#D z&GD4QMM=rfbdudgRAEs|nt)4mp)>(x$ocVC39TMy(d-)$&ih!MDMTa2Wf zTDR;fzJcI@+W?TTf51bgQ=09cxa@m$xf19qUfw#{(bg^|tpXtY>CS zXi0C@8GT0Ga%636*A1^3XyYrrqt^5|AdPRAeWq%v4U~OS4DDnf20A(hgi9SCm&+}w zjLvw|Qhbo^&w;c=_BP`5hN+dFCB_7aM%lEUwhGGG;Dja*W}MYn>2$9Qd?J9Oi-(8R z$tcc@tM!R7A1%tvjEk4!95cCU+8mnJ^!6QRRF9dhtKIO<6Z*cr0tF~bn(zeytGKub zQ<|64QC0g5ydcfH#CILHq$ZPi{12&zVCyEtW}QkG-yA}TN2JS!4Ob)`=Q^2<69MEy zxpu_he2J4POm5-et&A?$)dD1SaFV|18%e`*bu zod#S%J9@viP$gjPRM6$wC4lF(6nfd6rs5Bz1shu@`Eljy+wKd?j=vq)xFANqg%ja$ zXez!vCV2m*X{jzy+)l*%6#|0K?NLsRnRhzlHpm_nRwFO8mncu0jl6;-*GbMajnr%> zL;;`4hySVSQ=)&_!aC}2kLq3}Z=3NtDNgk{78AueEvWItO{&QmhtqNwakv$@S7Zp@ zoCjQz8t1$0EbPiI=aT~@W#us#Qzt6w4jwgbN;tKs!^>iwjY}QO6D?3}|Lz&6ah6(L zwP?{y>7G1?<~;N3nYpr|FDYXPg@2`Pc>vBas~jFD-NBOIy%TP4eGvgL+r{bKtf|#_ zFivXV_G>9?Iq{g54M~@*Q+59gr>sucz0}q$dgiBXqpO?rna5JpBqesD0$c#e&G_Ib zMNO0N7{^>H_Tw3p1}lUq!fvs7@MPW4zm!2SPPUbgxd40Ov>iyC*_OnWwZXaklz!1UoR%?$e<<2ovtD1legh4CSv}SvT(P?X z?n~Z%@QzZX;l{gv(gHsk)M?$uLycCdbW-Abg+$PAEe;1F@3B5(ec0TWJ~87MG@F8X zs4Z^2fk64PX*`P7wijikX=EeT_QzW*WMMdyb#kyCMZ#jGzvHHjPf7W@MNbRBr`k$JGHjD8js@)cDUx_j)ea@6mhHcTfY>zCMMi{kkY`l6!?q{HoU z$&^7?IQ6SgBZOXyV$l_`2Tr8ryVQi*D40A+kw&F033p{cRIZNd^|sV@&!t^zsN{btlZr{i(}pW zbyg80=ybFtZSAi%pK1)SJ#ekTZe-)54E6DC#A=T|uekPWh#zyUx#Sa{JNEJ*@Sz%R zjnef=CSD$dQuckk)?T@svZq%02tv6iaZnXnhZC47X3Ovrue<<$5(;lWmH!JPvC>NBt_E5)r9sy}w&?!aB+3I#+5 z<5tZT0rbv9WQpE>KV*ZcK(yYF?&{q2b&L~d8I5aL$e8^-t9g;sYQT1MwI_e_%p~wO zS4Yq1IP4C#J%w{y42jF!u~Yf|Yi%+_^vUlml6OZ8>HD~2A|ROOt5qwZO-K#$>T5pG zX!6O+dA|Ppa{l7I_lYxLN6h1A70Zy{G+hhCO3brQqNB6OLW~6$=P}5z-c{b^cWPtO zM5{xJrF7`2d;&>+}jkHrqM9l)H`OLV1cs8$9-{2-lh{g?I?FCvE&1AfYj5jdGc80T>HTN^_u2gg^H5)+lIPtC=ocJr*+) z4OneGQAqu|I)`_g;X)(?eSIiZ{0p4%w8RuB_B=Ml{uGLH&#(@)UIqmczd-OZOL>PF zE1x+dxw*J;Gx9sn#c}{8bCV5CYssbpI-Purck3^j<1e62<1MkLa=nq}b!#QsR=x_$ z^V@>POGteNM8{{OH^#}I`5p9)=>LCQzH7pJ>uVB9fcMQ+?p%8waJvVcSEMg-72@@1 z`fC1|hrWoQtOQkk@#FV!8dk5T1o+zqWK@7jmR&dxCg%_$9PC{<7>}Yf7c89@Xeg-b_4kzd9Ytn{N_hXNbtYp$fzZ{>LU|8_*!0s~kt zp*dPFw$cV6bpj*rS{-iWUOu1Hrvn#boS0Lr4fQV0v+rk!Q@yi^4vhv8nko?~7%Y6Y z#Plo4&o4;*ZEoSPMTU`Yq)zpoP<_4S5J93Rc2EekGiNz;84d;W6)?i3N zJ541sqB()sn8dDFFpROn?$62$ zH}85P7#Jj|lv<$1-n8_FH1GbA3IM}MHjL~f@aQ)#FZUm7fY}gTIE^pMtAxY?k6ftl zVkBurI-|0sAj>W3x}VUu%Y{pX}7^EE^V5$M(>pDG6^0&k^& z1;`%S!QS~IkiH+Q5_mnC(r9m0M2D=|{o!*!FJB$ADWLr#Qs+dBQ;irxOLB1A@W3<7 zjb4n*XE=w*b9)?^yVju*U_nd*bpHp)C$0ZE<3@jVt4p-m#A1o}Oy|5%IOC?N=M5M8@9eHj*1pI;s@xVC;XE6)GpgP*YPL~$&KKD1p{~u%P%KbFcVvt^8W{vZDrj1rnsYt;9IxPK;EYD`$Cr z!}JzvDZSfKdl7$Q?Tl}!vk=l8ShWCRXKZ~tmecv`TkELK27ZOKj!0~3k93-?s+vJ?Xo`5pQf!vFHT!`w+X z%D`wvEzt0NAJDrY{dF)>wSb!?W0pO#IJsv_DFfrmJho~2EMEM`iew!La}&01Gi52- z7_aKgow|1i4K)1wMr6|7$T|<#SN2{<=~nCaixzFFm+#CyB8je;|Kkwwzh>Hkp#27m z>_;U4lfv7|t5r(vXMtE9evkKyNf0e(*ZJi|qdU)+!5s9Fd5Gd&*)^g?=D;F1`&%iI zIqL(@O7^g8al;W|U}^HRc>e1TA*STl(aN_^wc70yw|g-Us3qVfT^n|#zMG8i|1tZ& zzuLq$a^gIRQxFUL8R^RvmL4V++dZ8mwMYo%v-qy;QyE{vg1sPm@Rq<+kAG6 zBdR6+Xh#QXh%FaBgJx?cY!?=R-Fz*Nr$8f^;5vH77Vys{+WHeqtD!}kZa%I@HUKk> zkS5mRdW&t|B8Q1#fdczB>yb@a`lXlX|305@K(318Usd~gmkrS6isy6aHVbeE<~J~> zJ=he@0hg`r@p$%w{F5I+%OfRJfD<ZJBCS5XN}j))Z7Md8WIZy;5amuE zX7AYj_&<*YDF+R(E!M(x6g8v5-q(ugyVre0N6UGX(x%AcaNvI%W{ii-lde8xN=D5I{I%%MeYWz z_L|6+yanxRMd{B{|EDZO6>Y~paaXb6^R+;^P)ZxH;`7f zteX4gl^Up^Cg@fE8E)(|wSRugTo*41aA0IDhs!**D$A5xSYbWG`eYVDyHWu-4}toI z9^F{!XmF*c`2S;B(2w}oo|n+ap$JOF^RHF?QGsPSgagL|a{{#9YKf@D0aa4(Dh<{D zSd=?={9WbQ6#KN_g)R_-%yVe(^#9mMm@2@%+@6EYARp<7ZshO^4X1Z5*uj%zAU^*V#H(Og89Kk}f zf_b(m6}s$tIt?uvjR))8?mkcvZ+=C8ih#l?zQ<)$?l<)J;CQ<%1oL6@g9;!IX%8W6 zYghgMTf39_Z^LShmkB3U);w`JiB}l7c!pmK-VxnKwTlcI$Vu~mJja@yS4SY&^YDkn zTlRkrhB?VNLc-LP|Kn7mJll;|AnyEFbj<&K?f+Rph~6M#J-*vPqk0kXddF)bntsj? z)bp>!@33hz3=B~9ec6gO%0rkz|5@}R;`}*aJpOO(!=yphG88u3aD)%)vzGv8_Rmo+ z00H_C^BQ)*E#3HHE8d9}*!@ya(Z$_maBBT(ZC^ub!ktXI^cE*@{*D|KbMD9k@}56{ zFWwU^EC|A<9S`9%>47OBKbrrXWK{AZL;4Pvrf}X{G0~6j1hW6O{_pEd&%V_j@2N?( zIpD*Gzn7~BXXGt_-gwmUDcAhP;y+bq`)Bv;Sa589er?Vy@>`Sh=jY@Qgp8xMseyOe z*Zrpz?iYn3ZLLQsgLB;;;h1+tNVd`Tr7%m|j%Ff!ZXgIbxf~v4=->mf1d^s_7C5griL})PHbJpEmSV@k3rc48iRz@tIGEY zWEXd|DlS(~?}4|elChusMMQlC9d&Gk`5lb>iz7_j@W2h*S9*06uD4%7x3FZpH`GcS zet&2gGXN8v?e`quWrCjx1C*V({=JLT)40~_u_FL&c%1*`-`PzT`uj#ixgUI~CpZh= z(zsaU6g(%GutqnkxcRqT6?R^=_>xBo;eUV3N|T)Fh5T7g!v*htI&)^xN^#M4={SQ? z`Qf^|(^+)Gf+Vj6^VSQZN<_X2Czvl=)w;&o1d}wz! ze6Q8Sj}?Hz^RcP(hZ~98rH#mII5-xU22u#~vUy<7MHJq%9JI(>$Z0TqSU(q0&x2zep8 z=$<`e#Ntg-g)e@DFD(Z|=Srz-a?jB-Liszj4yWjOG2X=2?d|Q|) zzhCKXmuh;^qSd{X_us8l=?;>1{zLz2JFSVg6AY!N2_q=3F_QQ`s~m9c^mh3bY-ybW znkpW>(OoX5n=OLUc;E#1F>6R0U7N$HgB+9#$F=CmB{_#~4}L{4C7>661fp2Bgdezj09{ULm zN9)%DFm9G*1kama_MBGSBFWA>R-AISZ)t_uc=jl1_o|v@C3r{LMplKrrgf&h5p^H!qWY zO+Eg>RsL2KlxqqsE#1=CNjChv5qqxvi>Z0mNJe<`9igMB2kuLI{@XawD4P6Sw6Y1M zXy$h}Rf-Csw_q$B`^)guuQNmQy@(!5I^z;RQ;%S!&Bei@Q5NA|sMdhRelX_>;Xo_m ztx{i$IQ%NxDS*?Cf@3aVC>}lYtv8w zruVmz>~!KTj=R$dGne$vImg&%z#OO_x-NjUXKm|@l?4D{O8{N8nc(~3OL2M`tmQ!#I0H9MuC#Mr#+p-d;Kgg~&?lwBM zfW3$Zyu&qQ40S$vZc7!`S~wrhlst(W$hm|b>x~!TMrOWi!s=n?kB~XWQ@a9(_7hQ0 zxkyW}tiY8&K%)M52;aL3~ioEsT^55R$JN}$HFCXV3p(!AjEdi%>eU=mEo<@p$Nns@hi$gmJ`=uG3UBpa8X z=5*#k>(~#v0yCR3Y>nwQQX=6~>9De_A`-gDRvH>6`i?;0kD@&#uC_ebcSV@(^+bx} z`cm#K6Qb3*tnIcq2gI%xEJ_dIxg@6&yzQk50K@F5fd8_4)og@%5Ux%$yyPhN6{9(z^0P}to+2@g(3Y8 zAdWpqsLGVITV^>6odCLaS4~y>lKu5ND(nwFOxebk!)LAT?M;8qJHIE~=jXT!zl`VJ zkps^TR8tfeY4?=2*o3a*E-hlh!hIMjh`+oXT>AXb(msq;4tv0vRt;C`YL$Vyl|yY) z31@B|v=ZNl1FhS0Uk@Dt6tgb^<@FG~5-0j%IMM#09E4Jq`kagk+~-iF6iF?BC@#yn zm9q^0fZ_@>iI9Teh)YNOt|8?OiSo(iKp_&Tb`~gv+Ufj}oytZs@sgYvv2LeY#U*vA2a4(Q_QqcG)aT%}jl)iA0UDM< z+N+$7WCeJ2OHP@J4Vlo2vMV7vxrI9;6r{Q~x%|2(9hv82=+Z4$LM>mxjqx z|2h887kUBdjliNF#WIYtF5Y>WWFHi}jnA|=W-GVS#;z~QR%Nl#%pI2-S+QxQ>1qkF zX+=)Y%GB3By>$+Nhl6&&-GiCt)M=ohY|f9di>lvhWZhZlTdf#awhArZcg3Qj=ZYTq z0_k=4>qr_@$;{d~+-JO* zSg+o}t4WWSZHP~Ps8I)dw3p}X#_cB&&Z4y}k5v|T||i(`*zuc{-?kPd`(i#jK+F@w);wx7DvL2kaw4<6waoi;g1rw6lk zrFJuxYp;Svc?~Bu?&U-daf=cjI+deSYVizwRc1P=;-Arff9ZNBPHSdGjz_;0?UQ!p zmMP@X1!%4uYo~M*zeLtcx4c;jCnf>@CNMGLGIvFTc&&lLrVhBITPEB6a#z%zjbiZLyw@RDTu8d7r*aBO)4`TWt9RvE70J`{>r}@! z2PRSEXa(Pj*nf(s9BJk2DP>%VL?309TI%3{8XIle4=Zm6-F4C=1IboJ5A9n2Kmw2X zG@= zcB%|1_7wjBg96%YKOBX-auue6abZ7XktBNLL-kHv?8y>#)gmDg!{r#w1ae)<#vOXbrcAPF zC)6CD>J{ph6H==ySQXuHUE^$zj+oC{O{e>m2l*u-!rHRVK~tXZ9*>`TA*3TNLvVO{ zP|{Dh>;2b-t$N0m-}S<^+%Bt+BC(;^0R?J_T;F6xs|Hw8%6VpPwPr=YY0jK;96ZIs zAHuEjHjT44ExFJ6kpKL?W#KrUYRVgr6X+#+69q2&F@uf&*hXR()s@=X;X!^#JFK2M zUfyRJx|wauX_@(?vRNMcjbXB!ETr>8UjUb!|LQ?E(`(eX>W;Uxiv8b5Egr3vbwTuM zJ_-mfdA74$ZIt9LdQlYiliyissXmJ(z< zL!YOvFN$x|V(OG{gMQ$tu3uQj1-71LX-IKvBiLf-a-RC`N>N-)zI@&~<*thlglBm( z%U+U^F~7pLYW8QsfG!L^VA>N5E7F!}Dst89HnZqgqN39XQO9c&2O2g<-tTy;)AZ7h zptKG}YnCW2HX4T7k=N@c%m*ClaX)<}8PiB%ZL?Ktcy0PS{ta<2RX1Eko}k^*lWLC4 z)*&OdFxi^yI+Zp^Wxzi1v9MJ?f}*e!iQ8s@ExEHWu>$`fRWK>y9>C{&upn;V`K?h_ zeau|wcoPEa_vBrxAeagomTo#NNW|%UB@B*JA8^nSFfuukEwrgj?jDyrT}o&c=l@qf z5+E^6zpmqM)j3m(Qgr{K)*R878WubAMcq<8Ryv~?N&etl3FH(7`}1%S+Wb6^qNCId zSeR+(6tyn`kY_bgrB+8%Y@$#-V`-wrtmq@}X8u-c2=U}xG6+mLR3~dF0<&P$6NzA}8LEZDWe(s%lYX50U({6pFNH(Y#tOFUs7G z1BmHRYge_m-)UTSQdBwwqNpvYp&NF!R8Tz#?w64o3t$Q{Q7KLUDVH$sT(cG=go_jz zw@6QZ$cr8i!GjtK(=gK39%%rRG1J(I?cU53HgTC`r|>(^BzkGNRw*DKoSP}%>06T- z7s~pz2KN+!$w-A%^v2jFkK>8R#b|%=iz9@9Fv7$TN!bOSKMI^W`YkY)w+zAEW1sOr zLJa)PKd2;(BXhVR12gdjUO44N(p-^lA5>R}3S%D#OVAez!a)!1z zfPdNxrKt4RMtb9{m42k(G{S{gNk;WwsAUB`f5sCGm3|U$0k?NlNCxGMQvhornLXcQ zB|dNDxKnmb8>n|HizC;Y`Sh=M6z7UOe!G+Bf-k+$V9AhG5feP2SO62Qv1&v3J-Kb~ zI$7z9z>9X4WxnBzf2faEBMx>ZPOha&;!S%ar=joUa$C%0#*&C_9?SATiFsqpN^WD- zW>;rXY7_4D< zm^`eDG~;mGA#2j=M>3h?GetIJsYDBlb?fYQc0c8yo+t>ClqfcBmEd`#sG z47(rSg;ERNRSMA51do-zgW{sBig?gLC0RS>64+BY^1z)X+Sz;#Qp;I6CK|m$RyUhG z=&o3TQy#HV-Jw~sR+*i&P`;WjuVs*{^3WTR_#UBjQc#uR3~A8E10NJq%eY48-&TYy zgV4*znZ{y_(;;)q&xBX|8Ydd>-5xgajA!of*9TtH#lg<;wuP^`uA{7ON4Q3b&+N4}6gNBPs|qH(|dx{yTVd<2ES-m$oR^d`ctUPbKi4m~cd2 zA%|uw%?fh`a89ke-9B~Yjx25*pRNdvj0NpjhY0Tc^ZXWSxvpU)*HF7NMH{Va(Qd`P zOt6kQbc0uI8+0h0v7(fDMO z$jM0To5U-shCVR(f=k)#NL7?#rus|*{ecg*&e(nnDLWJTo_^`xNbS3ngPVe$f#6kf5V zir<3?EN8El%vM^j9uI$4gFdz**91kq|w_N^Rbt zgiv(S^yX;1X<1Ue&x^*s_^paPWx~)MW9nZ!(MG2k6Gz$r`{MXbGq86LT6^pCbhxs= zk2gScU^yG`u6{s9s`D^lJXtc$?yjn=Tl>(l!K2hss`wOYau)QhY*u@(hj9>x5j=|2 zt|u^_TX=vaR0@_n22d8$ksr$AkXW^Z(EDz8wqq7;U_jz$82-5HUQvB3)R|;YbTe0+ z!YSoF8z}yX<<>fRJVJ+)FI&%6_riBv!j?anm$kR0YuBKgt}e=6UyRjHgx*5xK=u0k znDKeYunosNV4E_0 zofRe4qwP?wl_zT2^)sB8K*NKf^TQsuq;vb#k$nwO?(?)C;F8-}ZfMZ(ZtvJ~#-z)iI#+Oe!|Vv`uF3znKp<9p^b-Z6G(l zu!J6tDUwwi-Gn!K&DJ2hOz-X79M7BjgC{7@yex)F2BLWA@8=-sEpJH>9o_pCt^lZ* z5ed#}XJ?V6kZ!CpV{BxoMck8PC7ZzGP8luPgj43}j{O~&U1*)BrvfZ!HKfN9&DB*K zI4bdj=|+$0ns{~)eOakTp&auP?3SEipvy|1>)@;oOh;WY(#<=o&=#J1ZXkqS?27Sr z3*KBT-S!Q}Swfv(LBLb^jCxamF0fL8(V@mcnVA8#O+oIQQr;|+F7mKTVdng#Tj302BasD>NGdrw|^m+$_Iq-E$9? z48GD}vAzVq_!b?owL$cb0~X~hjg!+x3Tcx%6r|-Wp*_G~hFZ$)>t4%~BV!g2d#jE4 zVueyqhxg$h6*XKFlc|xrdngcl9HoYQ`P=wkDFFOP^J?z+=#%&eqoY`3v+%&*v)fk! z(``48QuWxv=jb+!4?Po(;|>GUv`4hL^U-c&v~Mu_{(V`6TFXghrh)F$3U7o&#D6+l zwPHL%lmesrADsiax1A1Y<+Ax5x8esTzX`zL3=OT zZL#iLy75<+4e>5MTvwYzN5Ey~h2!K5dHN^u??dEbq`3zhrbSQP4sUA-Ja49}xxT&A=RefoXID}ox8-YP2El^sr}G@t$+YmMwAT~zBj}SO*%kNC zL5zGyAk9_Ht|vs1Mx-BdcM1C@)kKAzgw~IXDK6$NvP1T;=AyaHTDz%dfejo*0WYKM8URv zDcn$)*K;~+F1yt?_>*$r=|E&kXi8a{@#~><3n;V9AEkIP$^@iLpw z2zm>yRE;X|`C*eYP=@X1wgoR>7R|>*D8ihhOStkR=QMiKiMf(PsYh%$H|06qF;0%! zxSOY`E5IysY!_agYE^x8U*~2zzS<#|=kjPdG_;|{$qjgs0MNKLQ0_Z-xhagi{ZHT6 zjm~6fc0P#mF2bT+SCEynP)%83W2DYfU5PrRirTz6CnmP*^`?3BqJhtIQ|x+W@(H@Ag9WkepYq$M*e5olK6o0x0tsLYt`z-q{}66^ON-@iVk5 z@v^mjcHk-TS?$jCa(UW|lXdL8W#k6mSdZxkCQFf%4Yr+{UF+99kvBh8I(L}%oIb|4 za-|x3Ldpqqn#iw(`1v$nP7bxb9Zb_iIhysyQ(1+3{yjEu6eh2@X9zUSPP;}JUzd2D zetH`&p^PPYwG$t8ye8>-P^CUKiTA4~^#&VQoI(r$zzgF=)T? z)Q08OcUnalx=BqWQ+RVVRweRS7$uswSq{^;dB*uG};PzSfs{_!F z7c(JYZlP>%TfbMyMU-acag>}a978nsX<1S^Qo|63G~7k7N?)0)V7WjuW!LL|;X9Y% zMX1a8s-R0X<+H7@thH!vm&})SUamDEhd0G$J%T+122FRU!yrB|H>slX53S~rtGvZV zG)(HoBy47>TrFa&1$FW3Ks6u0c;BUAOz~=Dgzerw(Y1f>4WWLiUjA=+II6kCdOy4>&IVF0sVvQe z85;xN34Sw)Dd!`OVvj+{rwDYNbQJUfV=t94CobW#kIHWv zsa>NXGqQJIo~@++D7Eub6HXGd!Yh`!lO)dpZ@Auh1a)hd!Tj6-W5udQCmfw~>bUKL z1>F2{S%OkwM_D}rR_Nbo_qa3oSk0&0Go0dxu$pg@2s386BJ0U~;#7aW0aEVVWLnwg z%78wlNk1C|pHR~94cjuWOCVv%4m<-k(lp2U!3Dvc?&GMd zg6*EErHFrL+dINdxo+fz91Iv(X5VYQ)(v-R+o`&p5^c+ZlUFQgY==wur);^7!Nnu5 zNVimvDgjD(tHXDhK0|X_^eD^cD_`G++Ax(b`liOV_c*%T@f0LhRq5tRKrj@)^VQC5 znr+SzIilSMu?=M?8$~bG-D~IOJSI9DG4p4F&oI#^7-@;8<}#zAR#3O`;iI=PJ<23k zK3@OgOqs!8mu|>oyEo!gG$*uTv{e#t-obQMWhSnNWE*@aF;4qHrhSR0IJm6S4REbZav}O z7iyE;%=b#6h!7Ox2(K`!VwbwQJJEIsdmdnAwGgcTAcR((IEN!O7;y7_BL~#VdRkT3 zn&eydmj=zAs$zzPPx8)jYRJI&ASmk9pJ0N{#Wz4~?&DgeMBo&Abx{tT0oDM_!JgTq6_jct{VIQkI5 z!GU#F`P1yDfn4jWMjEmVpTeSI)gnkHD?fr!I=)M;ckaKl)rPychL-er20gk+*UwAs zhVGe?d#kQm58Xz?$6|0IOwN#quiO@e)Rt zT8rQz?d6#fHD4zB+rN(4bH;qxTkU!l&AViLGhjv76-@J$#q^Ox-j%>gU?3|o4drxpM(#_FmN}{~YSVH}FhOT<>wP z(zl}>j|nS&YhQA;r3PU~e#qXZ)NYMY#TSCn zl6;2L!6A+Pgqg+~0}F_3Zs$RACu6@YjLXf&)06ioIG301UcCV;xgck%EP+?bWmUD^ zbp5p~h1xJxo{iK#N4frFRFG0bCbY+@rTqt}x@W-(of0xc(uE^;CCUdb$o-qBZ^fY) z%h=ac!G;79l3zXb)^zx!A>1g_;>{mOmsO(9*+rGJ1t6Ynbh|!PtX#w-!)tn&V$29W zq6uj4QLmStFgtG;#rZLNE63-m!);jLMIhxq1~HP)sK|_BZ}7 zkc*#LHWy3jiuE??xsqedKHu>`) zLXTc%fc(o$2I6@^vr_T{C!banuaUA-WB!SQcXL*+E@UZo+5us-IO)v^Bxz$Y`tn=8 z(o^oj+Ab*us2a>(0y-N$`NQlo;)o*{vtC zcn`*bZC=)AbN4mT9@V$IszWQEh)^hyqabd6M)KwLk5(DP_3lakK$C?Z&W60IF(x*k zv92!Q=>+k_j|j$lGk8fC{M9jc3#`ZcyMXGCSP&SppVr^#o3Vi3(s!tT^P#k*-6WWk z8_UvDC-)tpW9<;4+0^Q#qdBD@tT_|gPlwh^Uk4*T&y!TG)Bmu-u1gzUIs1MAIl zyKcDoYsT=Q(iv%M)g-_+WuXGc(1jpZtWDOG!?WFq|VRS1j7oL`ejpb zYEp(4`MZN)&3M>yM2^?xqO_#@$Db51?8S>QrMOuGc~W_+t6NkoRwn)_A>LtxaI-9a z{a}n&*`R6uhwX7f_Qo!#{X!Chl4>dADK1utVyF}xyL74vcuxx5$bG)7ovz$7SM zn34BX!sdN4^r&#wp`3Jk%bQL)>i$JR2KMzZDnHyDx}vJ-aM&T~)s`1@On33c6X#?xI<-p`PU2&eC8x}#T4U52au(V<9TDjZtc#h8{(xyM zkX?wyN4rcNgigVnlk<+p??elRTGlX4mWIMsSext(?qSl*pbDqyk&sLfSu#mUSjhin zHAlj9bX`KK_$+_^X)94*Db7H3oPao;CPSm2tihCt1Oe+)u1Wz})gC!r*!3>O);i9G z`!1QtPn@rKyJ(1dRua1fFGVH|U+x;ot5}2fVZ`c0ukCnnTB&@PF=QOrM4Iv=FB(tj z-UoDi$;_n@$DkA#hwJM^tg3J)c;rPMMJ?xVge$Jku|tE$`+M^lg)egW11M`K%@3B- ze%MR;B@Z{bHB%CcTta^dQyfD2gGN4|7FFz*)xBNn@`3jfhwQvV7=SBTjN$34kKA{y zPDQVm-v$?w=`sjC`TAO z@cHuWo1|QR7GoExNbGYiEa-~ddhCp-k*NhHs>4K7k}C#B`Cui6Be8pq@S#rP_Dl3)7#MEngMXk)U(=$c4aEI?;3>0kYN->Bptj8dd(BEK^PRUL;$z z@P+2fZ=r}x3z7z%^2Meud6WyE+O9jwPIP6QX>Y~5VGpUyisSS`4#)}S%+Tc8|CUC% zGrZSw4K47nEU12AhZn?!30r$ zWA@pp;TBhe<3kXAU_?P2#dDTD|2*MI^}mdQdhMn=EtZEw?mk21}XF@ zV5fdFYf)1ugN22nI-7Tjt2JZZ)_@1y1OyVZagM4lL!H&#U$TJjGs|!ac;e!+&Fex+ z5%6kZ2)@3EPA zS2`iPxIwKm)j!fTp3d;dU|!hZ`FD!y`^#73q=k-wB{k|;)!nLywv=xq}^1^ z`*y(V$2LpUzSK{A!Rnpmq)+JV$IJiLOZ)qSR~72&o}!}l2pX9{v^T4?cJ5(uH1yX$a)jh-=rh-oskHy- zJmk<&oc*_n#*w)LtMwbpeeSEC?74B{#s*v^8NZG@Z@iSPOdM;SI}UIUHB8qy@q53?_uS_6 zED7@Kx2Dp~pFNMRjf;2%xK|rRx^-0doR2M@BVTpAF2=_JE;IhLyba#vKHa9hK1AoP zdCkV>-uDapLi3d+Cxwj{?UgLxO2ce^NxpysT*&J^pDX_@=0t}%m1iC5F@6vT>z>?6 zwZwQGTDwB1X+P=gsrCkubhvunrEX)jmA)x0$O`#Fp|fvRv$rj;Pc1b*`@J5E{@WmB z!H3AI+?V@dzzcNuTG^lHbvdx=#nn}DgHu_V*k!9XT*=$(dI9{iJwea-b)NojABJZu*Fv4dt=;_dES-ceasr4}n{#1k-MS1nHFVahs zKv})t-}T&@^nTph8YLk2`C;|Qi&VAawtX%3=uCNtdx3QIwkS}y?!`RNW$dP*!%Jmv zW!`56BvosMcU(wPQ+~b@FnZIWVJv71elD`FepqG~y1#LDeg!hG-@QG@lfLbcuHP*q zko+Tk+FRaE#UgJ$t5n)e(hTx@gcEM-?5de~u>f*bRJ?X9B6Zyv@1xuCnWZg83i1m3 zh0+NbOw_CkuDXRpIo;zP?~a-az4TJ|Tvb7gUk09X`R=#k0e*YK0O;l0Ly)rn{ci4B z?UVV)Fa4VCmjLIsi}G-#*3H6}gM|?8QAi|-kk@G#LOieU-sahR(|GkUv`U#Ld+DcT zy!BAAR;QA`FUECMkdj#Y9`wjfKgwD_z~dUB4~47erg2U6wVSgtiRrK~didAwUzo}S zaI>TD2!Slj#4%vKD)f|4-e^kOgwfKOIX`)l`camRkB@61g(+y{XL8|sV!WcG!nXI$ z(&1qZwZ$-Q%ju3%7R7231PXwxsi3+yOr>JLFVK z8X~_ygS(${UJ*iy--bat#l)ya)ITQ}V9I787Eu7`Ngb)E|IU!xBG-1pTQVf{AnEjG@ZC63_j-mJdqA7dv3tFR>G_;4vw(Et#r)k3 ziFfMb;a{A@mDrMgrEChtcQ@aaTL?d?N;mlMb{QwjXISv1x2MY{w`Zc&Wdz}`6V zAthzVi#Vvi=E7 zqPSezhWi~n2TGM)HP#fC{hXiFA8)hnT4SK|ULXa0=i_DJ%qF@=MDIyw@$#A!PATz2 zr+6xPEEIPWHuYQXuKm3^Er73II9%^uOe&I@IvcsVT8n+l+g8}xZNQdtt*C6hx_x&~ zDGZRzb{9SuyEPmMi~r^H*4@nzz|`%sqnubRxx5Vi#F%|?*w=lWpQ_}ZC{QcRqz>(C zF3Aa2O5D{vve4aV!X>SC-*m4>6`}sr9bH^pl4xG0J%qUYHukbx<{ae2eIrQKZJ*%* zmC9kORoX78*C>9nG~Qga z04LVt$?`inq)p>OBlA6d>T*(lczd2{mWk<8<&avBzvHHC~FS?3F8Tkve4IsTGd`13+K=c0gW|~99TrP=V)Ygz`w#l^0RiTJEcv_`sbdwhzpqZOQy{ipSU`je zllEJaOe|y)A0FJ9eQhrxC0~?klD-a(9a)GDp}{gQrAJo5L;z942$lIQ-=g?bqiv;N zvnd#}J8QgR2zoj$Pi?bmlan6qY2*2++Y@N#M|crJDu%t;5|#Q=`<7PJTOHNYmE&)+ zJKUKKkw+4JzFG{aM>H*c;N@HMI@4=*Scp8i^2NG$gjgKSA5)y-N#tT@7eXYg8HE@h zl&D+n_bkaq4<(|!4tFu?10}PG*1*_aKaN-NbgA`cvjU>0WT9#VUd0<=2EO`vZ!Sv+?$#92(3q;*6Jdu7?Yq!5q9&Mc+G37_;N?RV=5OOo6csR9B5MriBF&J`JX z`@LQe+!JrH?mBgB<26&3G}rweF*3TXDNWK8mI=__ zbWglATrIgd7ot3;f#FFRg-|eGeQmS@ygpy)QorPxl-ZL$Mna|}k)!REx0>%L!Sac4 z2TW@S@4}9TTGZw$gG)ouAh$&(s6(m}@81R;U#y&86vEE;m?0_8tsyGQl*~ z!Q;u?FKzxvZo=crG6qlAjh)bZPtyhxQfuFx;EjUwZT?cYj6F;AO@h-0s2^HCAXJ4V zF3Lc!TGyI_7jz%@OqH~^$Gqb6$Gv9P=9TCUK*2X7bGYO3O7yJuWw`o7iTtWheHdpE zO<>%KN<@InYu0d{kJFBy!cWphXlCeHe>G!F5B>uLKMnhz5ubg}rr3#oV^&Z=IIiNO zG+v3J(C)p$E|l{5Q+QU)OSCQDROy-6ykFXC%@Voa8(2sh!^}4m<1LWgg{h|Yz81}2 zXif7Y93Aw!b`j$O1qTl*&~kCttz_)g&dnD43lEH_jM`i1+_B;OPe4xRw5uZMIbuQo zn^f}9x!q6c2uZ}>_Wa8?P(O}gLQ0G8*Y^>USWf3u6K->AIpT3<#^kA?`G82~`(~wo z^oQ4rx8lJN1&nHrEpB0qIVkhq{1)@QAHv@zrA|egL63^Ve37Rfc+wUjhraeM@1pgO z2}-N6KP)p@Va_`~5`g%v#!Z31cgsSMb&GvJUNtfj{u{a}nuDOsoCNuYm$colt2w&gQ z`Y>SwKt2ofFe}dl*ruteYQ&d&c~^LT+EPpB6pJ6%zAy!i`-XUuDCnP9(r}2{8)Vd3 znamby!>$28{8*>GKX-g4Rx|jlzq6hC9sLP48vCt87QZoG+}Jwm#&y%;q}uVuUY2FK zQ2Qs+WxwQ1eUw7!2&n$&w2GTeS1y;LM+;F4+#1lP)8`+V#LUnL1MCrJJHDe>8+$%h z78&l0SBn5P#;cEMG1&Iu%i=#8`FmQN8%dd|uX0rBf|YaTLM$dMu}05)%#xDb{hNZr z?)nRk_{+`9IuQxWGDE=?|2Fj!{IyMy7v7p+;jCOpwRlxN;d~MwvV@iJ4I0kv?;>0F zK}7mWu)PZWhHOQ%utd(Xa%zF)&X1J9@HmXf!2}6YpNdW(+CjtK$TI&pjq@Y=XBB-G z%#H*}BeRe>6Sz&an=33Qa8HYH$OI;N&C97ULchNs&zzPL;}aK)sMi2|<+w9!`2f{G zf(up7bxerjkxXeq%je_tWLl9H>ImaqaV(x7X(wxY#wrHPo7Ga>r+fzX0@|d=kM+fg zGU%euF3Ndhh1S8cm0q)0btCGQKk1PPf*lobp2nywRg($~OgQcfc^#g1Fn4xR%M=n- zaaE}Zb@ux&`;hpnu70v-DK_`%>=5`iQ+>8hpCJL3>zB!oaUPqANL7<9`25LAl~cgN z$89{jdlrmD1%C?s;6@`4{`GgDI5$}oc@0-59OD>2`W%ME%MFb{48={MKMsp~^luM5 z@|w*O&C18YPdKqivknf6Q^aiNWhNs`beamh=@_)y{@kjf4nw`A@YGhH!?qvepN^bM zZN52FWlG9f{7C%h#zn?l?nr@PpCK}dre;xqISc$~#&TIbMAX)F_bZ5G>LVHaxk6-U zAJ(EFt&Iw5TcdF~7kOV?-#%T0kk;%?2Yyn`RB~OK+zk;V zYWo)0r^Xv9{^r36kzVZKC~7da)mIp9CZOW%ea1=NNgcXatE9&W*Q@>~UfsdNB8O0m znCWC!JoQKvEKGqmkFJT_Ed zh(LM%9ZXpR`(v)!`AQ&_QGlpjqCaRkU-oPASY%x=CVZBLzp6DEW09L=ybd`*mEM+G z5KN##SxSE3$J6OrvE=$L|M=UoTB=^;vx_W&pd48FJu;V|!5FCvoZ~zkrip&LI||9J zPZH)S9XeAn;?kEH;=k$i@*a996OiNwxf3ojf7+8wN0FCh6id?(h0!AIe+YHdNdffZ zGBq-E;CIi7Gjt@H8MFnBXSQoY-`@3N$FM6n42G##PwS-(SSaW{#C=X0Wv226V^`qf zL1I<3sc_MvTV>=3{7ojARZ>ZoMjXhzm+Y~y4fBp-w;3)mq)}qiIg5#;oRx>_ss>fE z@n-4$k2CYlFm7ZDE-0li{&UYpUzyP6c(S=Y!cD;-RYbaLF1yFJH{TO0?dyEF>{uOW zu_d_6anH?rVCyv}Tln6(!)wQS0;3hZOvP=P?BFOOm_Sc1f59!L*XdB{U2doVeuyh` zmzsurJ*Y-f33IvjeoqyEVp_-k>hlB55^;>i;yaP5;!=(6RJV~9qFxUyjhNb@Y6Z@x zzyh*kg()cMJdP%srUxFk7(OK+;%6TLqj^mTW`(+uYp+$Ttm9AO1U&ipO&Fw*#`>>0 z*g`-ut{_Ll)GAHpslG>FhhqnHg{;%h%~h7vVuXcMJ)5wnaK{#~LK)v?>Gfjo%3<9& z1QO?qvqca>JU*-AWN|a_BoD@-qTFi*Nx@Rnv&bWEsk5%5!HxNn52ebSybV+p3lI#p zh+_qj2C_Jzz}R!DTRF}DuweZl64q2c6_&MGTZO41=^tbEWJl^Q&pH>Ab!&_q_SN4vcX1n2`}qKfoLkR1RifW zP(FJ$A^q5|s|<|jRrwHzOEPvrIPkvxzoSe*9Tf6I6@; z%7Ho4ZXvjJ9ZI)0q8VT)*`bPK?~Qof==q5|s+r^YuQ?e3cvBlQOiF_ig8vVtYK%8W z;n!nq4t_pR5bL9HVH+GVZ`A8pYEhki`2PZJK$5@buNRG5Ljw(@t^T=kFpOEZ3M-Z? zsWM$|vrK>DpfISYRO3#gu%Xvla4D6=nrpA(s1c>ZTrsdC+_{Up8j#$C+dzuH2DoYh z4+>}m8+q;wjxIzrVlFCa|26Va+WAVzkyl5cUz5r!dHtAt8%j?%9P~f(aSReKC(lQALM5xexgv`&j372T67bss*kc zJ*7ll=W{!a6@KPmt`xJTuGQG!75VY20t+=tHWPAPJXJT6-rI{+=M~!BAbiq~Z7hKQ z>uyjuO0|1gVA15!ggu0pKmg;8TFuPBU|BRH6y-vm=kol`u(-J~@U$|(N(G~wRA9lD zSrAp(;hN()HjJi_)7*?wbT`nVu(nLsU{G-C4DbaaRxwd$bV&9gBYw@fG>48hXrH4Y zX_0a;-AuLb1WizCAvxbLCOge%OVf0vd=D9%3S{mSIl3oi-Q?`NKrWuGpC#GSx zj}g4oz?N7syOK0%lKTbw(vxDg_n-`tD6K^dO5NdTumdT>o!m?pm+gpnY1uP=98Zr7 z+$FdL@N^-n2kQe?77u>h8;T9g9pXGczUWK9$svGo2YON;#qJ>O8a9I?aQNYF@=F*C zEr(@x7mXNaEpo#Q&vfGvnqXy2vQ>&@D(8=R_Eo&BdjqCL*rCGM;ii6?35>x|r3166 zT4hTJZ|1ooJCrCMWw*zI?Fv%UU_@{=NCOhT8SnJ@8OK_jQA#100gN(EprOQGdDIM~ zq($izoV4r=`!U=W5yNq~z)`qxnW~2A1a&xXBn<=0!e2AqLP!(-xlnl(E3s3^M)m{= ziy?}}bb!>IVejN9+%$U&YZq<}qx>AVG7J~EoK8)@4PdKy6A&_=6fmRcTfz$dvT(%r zu~(nmJ~;{snq2)l(5~}L$V&>s2R@2;L$Bu~*@UC=^&P#*JdQ6H1!k0IGlprz>^4D* zA3T&HogXa)5zjkwIF)pe9_9g5+Kx+%fL$@0CFLVJ8KU@xCD2-96U>#tP5QLkeT7B8mW^fXN&7j~GQZN_y)71t1dkRX%b@U#B;%yio|r9h9A6ee zv&@}reczp7la!-#Q6R#D4Isq6W0Kbtu^t^2`kE`4F-2Iv^BK!(1>I2d|HuHzbphCZ zQz<^|o*^fDd{k8oOuGyy+p-)Y@Ti7r5zZ2~_$t6pks}=MhI#)#__gB-rz)C z=+T5{N|c~$drIAC6a~LJJ`u)qehQ&*!R%6D3uh0HtIEuTy)-l`IciwVh}d8-c}=@4 znhC<10zFBsIizd8JizAhI?ojcvT}`ShB>G0G+wWg%q1nPM-u))m7+S&uNw9&ClzkT ztURB|?AljmNE?d2`7VBPPz_f%YhzGNlvDwqJ+!W5JHW?qaTOOM8CgU~GGFY3wLeJj z#0^7;UPrxku1mA~sn23)CXgeiOKCRdBP6p&m>W-{kkenjQ&Olb$Yr_LxPx)C!Lw^> z!2&K0-|<*>tyX1Uvd7IU842gSH`RdG(q3Xx4(amFgE@+1d-j|Yo^J}(Y}tFbv{*-I zM$@=AnSSTddD@~87R%@OT6%aEVNJ+gGSEoEIz=v)w@zOh&XV{tU|mqN%J9TGs3@w@ zlAnnLj`(~wW^hS0m%~Uog(&|Ys1V+}NgJ$WvlH1J(@K$|g^cnr!D8OqtVqDWk^D zTcQ|NTf2%*9nUv3Z3*AS@#rcDeqRE(jMua71x#bZa#qD_`tRda8hI-rr4*4GBb z7amtk&A~R+l|p5M?c}NG|0`(cwoo3i%QZ{MMxby?Y>ny^lmZ`{NQf zd^U&_K6Lgp`-Fw)bQ4s@%h2oUfMu!!do3oDE2mcVluzgh8urEw)R@>1jCgbJQH-hr z73{`X7A~-d;&P$JAV5J^wJhPH67$npUkD$m?#i+xxCkB%L4}-=L^6n!DRX7jybZtzP6uj2V5Fy+Y@M zb9q3V-ML9&7?}ktwNMwnM*Sm`T{~6{b6aET*LkCd3MbR#K)O=e^VJRo{O8%Z%EJlP z*aTTi*5=)dZUKL@#=Y)T=p*?!)TZp-+Qe$}?5cRnh%N0|HT(3ys0rz|Rl_CD*&stP zty)EDBF-5ci^v0EiRVrCM!HBpJUM_53d(;HQUS|}@D(3U(q=>a=pE7V-P-x5kUicA zM$V%PbT}x!y^_zrn|i8$NdaD0ZRxRd&WJ9e%HtN@OyT{Cg57|Rz&9Z;zY=uOk;fjK zpE&9h|9E-$<(2yJ>rY&r&zr5qIKJfv6L&tRfAqs6A3SxP&&$(>=s(=2u_kMZ)U%#@r<(gZ6El;&s z7)~eLm$&zI^~}|7pWUBpg#Y!p{M`5QG*`*vVHNqdsgs_6RnUlv!>jW7-CK(0@j|5L zcw`^=z>TXuy5)qwI`6?R-M;_Aw_fm_?Vn!t@vX)3mJRpaIZL^=9-SB0vt#%^nM-u~rZ>c?*iY(?6@#E78zwf4%^zARM zUmfKiW`6q%KiGWdN1y)6MfoqCdgO&~pFV$gJ^!33#y36B{p4}I=DNSVe6xM{wA1gI zdGAMOe{ub(ckR7qt9ts%)6SlK?zw!=x%Dsn;`KLP`Yu%t^S2K~w7S-N`SbsK^Gyez zeB-|+mu|Y^d+4}pzI^reYpyx%njgHG3cF{$pKXKt@^oJzh<6_O@!NLl zf&aR9WsH8(XzGNTI?3HTyeiKRRMf>fDXb}$A3vG8bR5N97qU*auHXHg2OqrspUyjF z>+f9pxnn-QH7e&WKbgJUnq1#CgSY?9)G-(Q)-7MiKYvDJ)1!ZL&2#I1_$%i>dsVQK zbrNiOp}Y2}bJWzi(^Ko#e(dy~E1#RcegE@&Kd^mhBo~Nhe81x7>0GdG-R^a)lNASl z=l;I)?>_9t=T`1m!~IKi(sS#s>lZGvl_&OY-I33&5o20l%#v+{Tp_do`&7sa_|Qt$@H{4zw3pBN<1^L{ryA5;sDM-6grDzV~W1T+53_!R$P(Ra45jS^Z9LK8_QTY-kkUbR4PcOb{e%|S1`8{PZPXe1u>)T)|*|>mkIGOIt>LfaA zSn7T+J^S~tl~iVj(n&Iwuui7>4yBW1YTj*FNT8Gb(211mJ9lg?_C}<5`xcScqMJgh zlkHw7)bL>w;nnJ7(M(O9o#3b+)k#Cz#Q*yGSton5Iyvdj zgihaBU#gQ!F9oJ-4QT%B8%t81u>I{{Om&i+n?NT`ynTzF&s3HklCxdA&`-8W|5&OM zQ0bLonLWcP9S-lgr!QGYi=4~8t8a9)Av$qrO`S-|JY>;p&SE-A;{YrG<;N0Fclh~) zJs0*wzZ{^wWv7$neAm&J9a1N>QP$YAcW%>3y^i>ciJVm3rjspSoS$FUB9L^+J_)Cj zM10rsI++rkOqHM$n7s2{2hLsW@Li8R>*zWerI6}myk4m1Yth6-wZd)rQuN3K&4uv_ z8orqBJvm;X)=$vA1;jZ-`udA$^yD~fg%dPd;BYvNm;8Q4elWU?LlclY^Ke}DA!6U- zz-<_zv`Y^WM@%o-3+Q0n?NP+uLB>;SE|L9@*w5&uzAac)8F%{*C#XC)DM@ahB9Dmv zTtt$W-kVaqao=Xf^LyI{uMXn;Cf$YD0?uDVNNHTld5n*QvE~*O@jmIzZ$Nmyesj;{ z@rBJUpIg&~YNdRP^64H-eYh(RhNM2(*BEW`GGiz}W)$O0!)RDxk6sul75lw;*uQvu z7-FxUoGFNXiX6(mM%jOuhUuAu9PegbTunP=zappOS)J+CuSPu|GWDxNJVcC2I`fHr zkh0g%#p~^R0aLiz?FroUp+|SVd+@68)(_PyOs9aoihjRjx}PzADW;uRm(T4>&x&-< zW*5=Uv<<-B6ubS2*dr-zcKaN0W@P=e!K>EadQn|o3;7?V!Rt=h7nwQ3(z={ES(g!0 zTnBxZ@9=qU&YpRv$R2wz!85mcl-scTqBI?QMSF+SJ*3$0SVq{-bB?L*e%Fs&Uz#e< zjD8Tart$}Anx^~SUjE>L&-1^pOks=ywlqEc4ho_QLZGbo((&i!V)09djxCW?F7}7&q|z9u9%qHCmGIc24nh z?ksxdv2x;0YE6>zl^grU*jsE9?#ktL+-UaL7%lz3u@l@rM%vDQj^CF7euOjJe0(mz z(ZI$=9FKM==j`Ua5$vvWzV=jFbpGipG&guIPPHknK1TUkLc{t`XUxiMNJi_UOppzu46B^q- z&GU&-Xkm=bE%(XT$@AijP98{-ecY=apwU-U3FV8%j-6VXOm!j~wx-4o!51yjN!r?N z8Fuf?x@SMFY;ko?pl&MR{F7^GQv!7sZEhlAla^0sb z-O|xdMx~!@o3g}{0`4bc&$@o{%qz5q`^ng-Zl){?`KQx(+tjvgQy(eONy*q1PAA=OnQqOQ9vBB{Nk zHTRQVer_3SoeP@k!uMBmA#EDNSH;Xetq3%caT`VP4x=@0;}Wl53z>jd4I z&;+Ng*Pt`q7PD=!{|xA0NttL*drAwMsIQ?J0Qcix7Utx72y!tRzkHeYR7b^K|4)GF zOdxr_?M$MjE$NIO0t_w7K9VGP?yzOPrTU)(%Xpl2PTG_X>`a?prg?bBgk|RLUnl6! z1h-UFz-AIjQ0pCLUtLz2) zAr6ad=*&;o1_oh;5Z{V7V<6wb8@Lx*)8M$t&m z2+6*ecAHDF(wpX2NSl496^KIlhlS#A)RMoXA&&0|7 zAv@lvbYB()(Rgg|lc_;$M-!tBe9@Fu{}O$908)_c7rJ=|7|PgB2B}Fro8(}y^?fes zEv-*2Fypv3CSD74Tc{~6 z8V-g@%ZldpVl^5JXR%r3WSU9HvhMV=NGwTYDmT!f5#rO2a9L%(E)CUqCx!F ziO(583?zIAMD%bfKPMb5HlVTaRZDV_Z)Z4V15%LEV)1^f*rEH0lVBR>Fq)AoN1`*ZxD|Kq zcweVVd~G6@V{(}HNy#^^c%U=ehk-1GxMJ((GDYsk(i(SWB2Nj>Pq;lgYQR$rN!udJ z7{EvS+*ua5w_LiY^IFpci>sfmAao1ImalavZAWw7jO-y?o5P1Qk=Tt~(wtT*z_{Bo zx(-BEYCh_C0v%xF+L_nyCrJS^%+mb-5SYxBj(Dz_-U8FSYc-@*W#>yN%+3YRP}6T@ zX|y1Y(bZ)wxom6m5bzi;En6N8wQ9%x67ZSOzZQ??EV&aRxIN9G(%Qu%Io&q3F=ryp zdqyp~2&`76sU#y4i4(Vk4(KY2WUQ5BN5x^a!1?raaWiK}MJ>r$RADf8PKJ{upfmT5 zWo+6_)19fJuA(EcA?3(olSf*+U+m|f4zI)O@H)H>ufyx`I=l|A!|U)mybiC!|4ooL0l9NXBs|=oXL5LcoLp!mR6g`^ z+9B`H0+er0Z;yvx_Tle0o;L@kqkrrPhV+HwRx1^$4pz4*K9{;;!N*j#b~|&r$K`sWkB>h*tc)J4Ym~ zTkUPu0cO{|vy=b~H!{K*a;-tWTT5lWdB;sSKLz<|+jqGTXTxZw zqw0=+C;rknw~^x(Y0H6b-S}IZrlg?TV(Bv8)^c8(-Wc31$gR72kaStj*#-;#&m%vb zrhAykMudcQRpt8S7pchD5K&0O|43n|*W-{y$_<=ygT$H_4<>WXrgVbT09eQ*3YgA> z*8qWBn{{M<`pHCF*&TJZVVi8kK?k*EAT*sR%Yeyn;Olc2xh`Unf zZB~UY;2N2G=f;K4MO!k44kK}V)N!2myUq_id}X+<)Y@GGlbhMQ%X_K@;I z%_i%#L2~W+5)v%sC3hAV+vGA#*LzuVlrsG5^u{^{eB5e|Ym7;1q}{}=25M7GjDb-U zEqi2Hx*5>fh{w&QMY2#k3eid6G5u;(Su-5^)kRK7MsBev6!E|>4roFo%g2yZMqrSJ zl>(uVk-}IRA^psK!&e+b1>d~oh;b#GBt0!pN8`rgHYUStrd0`|#jOeCQ;~0Y+PRwr zmm6R@fG<0WYJetbLMgOyDBlfmX^t@g<7*3ItPTpt`5twEXJ4toU?%!Cz6@uMhM!7F&6f$Ol=q6b-R^}E#kb3u-FN-dKHa#NgoWIf zZXJmsEPM!NNW`HK6+o+8J!~T`bqK|})v;Iz5l33-nv-ND;t{1zs1_$3RG5#5iK$5x zH|}YJ3Yzvsjc|1<4(Q~eyLJp}$%#VIlZB#@9z;2;@hO6Hj*sMV;E{ZXPl|`uE8A-098>$G zG9+!A5fp*WU4{pXXrPbgN<#U=7@vMl76iRiTrA`v#JY4)GUC^DiU`YVw#=6^8rtJZ zqN0-qz>+zHghEdipKVS1!!S@EL+@nY+n5hXn zej!gZNV%G|%OvN!>kUT7;yi&K2$*q=l{&3&@B%4~P$oAau7)b3Ar}dFw8>vY&rSL&djc9bNmiUMsVKa6HtMMi0K!d3e$96!0f~8Ways_$po^$#` ze?re1u#z0i4zpaDh8wn`29_styfytw^Kyqr8j4uP8e#=cGhwYRt1mE4WrfFye3pT_eXUQ8zzCD(W2K zKX&p?n&82&ts03^IqI67I=?xA}-W{5WG4 z=uB70m)3m8VrXv7XhC2%&IM+!{lh*75$N;f9? zev)RpF{BAP^qXIRx(2p4KI)^S}z1;vG*gnV}Z9a`++>V*|5b4T~#$)Y!oA^Lot@{ zU0XFNWJrz|p%LIpeAqM~0Io|18oDz`mj^!n3j(Fs`%dU?8`|FTnQSUiz&?Rx{B@1- zpc`hOXeVnIi|kPw<{dC_&gYnsZ5pvUIociJfG4rVnCe3;6M95jzAnVIm>Xueg`=38 zapw<5Xp`e0#D$xP&w`?*VQ4N1AH~hnAeFyEg?ZL`KHMDgLxzQ3svt@$cYEK>Z5!ax z+0B*6QIW^T8=YBq;Q$tYMi8eDlgtkpdKRb>B25pXE5%{h|4Wqx&0bt&m=A2XG$y|Q zab3sOS$bM}j+T82n#8FJ=zdX`(3Oi+?L3#p#UnD3j{U|Kt;}E;neKEUF`CBzOv#}l z#Ztdz!N@nG!D-sW-YPVRln}P!GYK@QS(oh(`H9d8TpEvY;4*VrSV29URH3li&v$MK zx4cS1jQ?zFG-nv9<)n1l*a3*01tC95#2B!Yf2+{*4)6Z?d86cKCJy4bcfC?kbeN`` z;yxx5<6^rL7d-q;MvoA!azYHlDtC^YoGFt-KT$gFRdGCVQWOU~+*};yX&|qAoCN&P z1~e9AWOy=>e!~J_f#GE(Lh#m-X7U4{@H~g)x3i2#3HmHa76ldd6o&C8nIfKr_`~Xb$O^y#hsmWl~}9VL_e$^y;WvqtD^9hA7lhF88V^9&MIP zZ452aa$|goFC%f2wipG_!b>Qf&iRbI;YY|V+8H7HL5)H@rHm?u>O2(*v z7LA!yq(eXN=-wHyaIt#|zWi=QcM)EOaMhEF$Ar9w02C^@bMBgb}Gt(fTMT#5{A=^|@g6OdLf+$WYi!5-6EbK)sl1YBpTV1Gv(_HH})zA=fwq zd}@kZ?lgkqsG#m-A@#UC%v5>EME9EEs2-xaIQ)gQDEb-hjGqGeWY`L7XwipH&TPJo zTVsa9g;w;0++oCMgA5hix+u?)d<*cf8l(;(eRiej0at?aCkE01~6{?%h;>L%peU%UCj{>~$%7Dcsjupz4jB$x!O9*NBMZ0Pb*SC@)=hCv^8-EB; zJd0o@D%WQ_)hBZkR->b400E!W;KuF_IZ;gaz;vBDXVx(kS zDPt&}3td8%RqLZjhYQ|RP^Q0`%Cush&Dy}S*n^wmx)sYOT7&P@!RLV+B~S6`MslgX zHlnR`&47*9`{s6-<-QTDJ}1D*z`+DsW(m|Y5b+2!sW7R-yRZ~em878Ae7bN%nm`+Y zPSk9ixg9~=Q1SSI=(Yu}pGOvMrbTXrIkz}2>KHl3=J+i!<`7(_Hmvd^6T!qpoX1FO z;t^q+3*j@k=sBK)Z?5G2uc+LW+EJd(cY-H9JYp$Gv_cb9k9XGc7<}!`aJ+ZpT}pYBIQOb9^71$_!*(d z!ZxStUkHAl#?>3+I!|iE{RFvCN$05w|6M2Nb-8pk;qWE@meT>Ips*5Yh_n?`4bhn- za3sVd{*lVE|1(h$=X{1HxQOSXEaDu^u-_`j6@3E^Fya4^8+J>qyI9V_sj?N$g*=S& zQv!u2Gg&ud64}ydeB*b!3Ws5uC{KI+qc2Xpxp1r;am-a)aAV)NfOi?J{IpaC`~fG` ze4VNxZtF5^G&bX{sqKBlHuliaqunL&GSpS#0@tkXrS;USRE|b&JZYS#5*U#g3K8{& zhlL{}P}_83pO8t_ndS?uBOuWi}@3{b1R;D z4)#*qJ35eKcYRzWGjyRNv-s=j#y!JsMzpiRUHkB=qHYWWZi==tz2{1`&NXtDvl&S=i@JK z+O~D$XS%D^T9tNG9@$|ZS@`0gf9k%KsHns=nv3OU@$Ud;+%q0pZwJ4 ze&enqrw`uzE5G>GKi+x54WFu1dG27jH>+Img>~0#_`o$I+t+RUgI_yl`?H^3b?Qe~ z<+q%0++n#jt5m>GU@Qx!)b-E_U;4KXeC+&xFXZ#PGdf|6yqrpe1T+*=a>nOJ4^bG^ z^7;FYi01l}>fY0T6n*!{mxpr`7hQGHJAcWdpHy;{zkT|S)82jhL&tsgGsE!-TjzE} z3Quo4FU{R}>DHAKTg$W6EjfZtNOW?Qs?KeV$^#WA%izVMZhYxIr?36%>q6QYbSe7z z(+^(w>lc3Hk1Nb#7wxQken&WQ(-$A#x%+y1@6FNN%}yuazA#I2da~2WcUIl-=eOQj zW8YP8;IQ2<{nLYgG<@dgSG{n@-9I|=ZBIV-k=yMxTZTS0#m^_XH?7LEPSoLj@A>F6 z8-HW;N;M}s2|oACM^9gK_6a8(|CK+;A&6nL3P>}uiHPH>#Bx31B`mPT=35y{J`bcZ2$OsuHF8tQx}|g^h>>0owO=a z`7iY3*5nlo&+8%y(VG7H$R(xN}pQki>1@?7%4mM2F#MgA6F+n%YK59_MLrnLdn5boSXNp4i>J zeYzyr?|8?X8H>I2#;LXGq9X_M^Vfa)?H7C+ay<0+ZC?gbolM^Yojl*2)yZ_%>~FJ9 zI!e4cD2q(K>#IHTSu}|<0 zuuc-1@1}U&Qk@)g>Dw>BSv>!Lbdn^~_e@Pa+ts0yXTSB-VzbTvF&L#6VRe+z$yoB> zPY!1K$+GZDI?3m0zOSj1K_}n(*3{IxbZD6#ox;9-`Fz5;&`C1CxIfiNl6akzlHnJg$G7hDtc~OyZ%d|x@{)$G5}8iTXE&bS=z!&g+xTeI<)m$&rKJtB=T|r92lA{G)F;^X6TDw3a z%_khC>_VB#UL>ays!iiGDCI7acONP&dAxCVZVK8~4&ouc9q?_Fbby-^mqYNz6BUIJ z<mc_t$9r0-55_9<&oCzXlbA+@hj_td- zu)55h(NXf}kzm0F>c<%(N4oU}_JTIN7-xV`=`x4UAZL!q86!oed$q9_fIdQryK*dR zcNPixGeNF4J1;oCS8Yn`0bhfxOAbE<{EuSNFVp^n#)^c0e9nLNBblh1ic#X#$ zE53~CqeVI6#mma$qpe6!%lors6l6g(thlc}Cf-H-rg((bKRWZ5w{1gLzcQJpzI#wU zp#ujrJ-_dPgu15iJ`g@v98{@9s&zuviNo_hZjHY{_;1Oy#P4^$DRJka95{gaQA21i z2gAcWf-JI!AH#eBbhf=9XHyMhKJ`4R;DKr%(>Q!7v*)vWjz~~eCF0xJ< zK!r}Gm}jq(KAe)JO23$rKXI5kbdu6(=>+GY9C(q((pP|~ed5l!+#*joxXCbqVVZv+ z`DwB?;fZ1LQyw4IemmJ;#`yKv{{7v-OUYw?oN;w~oj?Z3{{06JCilxZ4j!CL&n^LT zOY&Iq(oelkn*0Mw$pft2uE!4CP16BA!+boD>cow~GS6h41Y^GxCqc4x>icav>Fb+n zqX(yAVO-HqaIWw4H112K^Q6WMa6d66nHNC! z9Q6AaziB`5I-#E%3%Gr^+)|gbolR!J4%-8C%eArbkg2WETg`d ztnP9%aHkV)L(;Ajsyq91I=NDMiRi>3BpGA;)jU6QG}-8$lM;d+Tt69o?5Q+As}uB-KGvDn ziPV+?`pK2spp&tw;p7=kdBE#rJ9N!3b}Fv$UC_zY)V4OAa6idLNxFUp`o^Y?LXbBk zFTwm?z;yqi>^lsCLb~5D-P4zbe(zrHhaKtEEZ-J3_xh#yx8#4pAbi57{}y#XgiCWD zCCW#L|Gp1D-BI7CcvkeV!jb1(r`lj7&xIVhfw_shjrY!{f%k4biZQ7xG>${2t3XBfls$mDhumT z2~pkGbJktOO^jc?`!2nS=t#}7hI>tdW{q_>NDZ!ZSZXOz zK!gqkv$?@6IE=7)p)4av3F%QxRV^#TO5)4PMmO(LYL4DQHj;v}nTW{03DP+{q?7F| zO%KR2{=PHp1e4wfy$pLD58}pO*_kwJZuW5Z^JWTg2AZ&r*@2T6Aog_p>Pw?2lxO&t z6JN)Wo$)FHOB(ONENOCQNy*1w6LeOpKB0MS1MLFSOu&YdW;|S`%#wtc0kh=h6~S~S zbO^@9mI})>@0u+)h5yw|JS0Gv?Xm)NrgX-agDj58+%F5ZJ=(IY7G&s|_WJ#+hF1&i zCaK$E9$bH1<`uA(=UTa;_HLU2V022zRcdk3O;2TLE_Zf{0qAVAD`v7OopmlL;=!Pz za4wV5SyI}dJG!xLWxE7_)otlZnn!*G(UQJMZmF%7q1Sji3#cZdq9NPd&KRYro=wKZ z3V}G~%?6UzRsnE4C)y_s`w)?x>4Xn>}p#!oY+EdY`|i9 z$gk9)tiACoLQ9e-h2`gk04sz!Wwq33%$Y(3{Bs?_I1pxV!Il7D>7+4^fV7b<0iT=Z zEG(|5Aiddi+iVklj&d9#ESZrlZl6P!alG09>o_YE>>#(5@MjeexCV&7hbOo0`_%|Q z&3a22=L#PN(ZfJE;<={{1D7jY^o(1=vb`I~)e|5w7lCUxag&Qh7~stozW!{SsG`9j z@Gil%I|ZS`|GD}JNf>v@##8IYB1a&}%g~Ol!@`mkl7`M~%*7N}LsgcH&D!tmie`8M zZ$$t2ftCY}a_5NYXd{(a5)B!qV>nW(^RUHAiH%l}BMP|%E_1k}@#gU~Gjip83li?1 zaBZA@2?3fYfhTNz;e4JcL>6vv?LW^2s=`S_v>QLNn`#uW5V__eR&NAUWkJsnD=rSA zJ50QXX%0+~ov{5@1QwS|>`wy>vA$Na8dpq~Sn8_ZiB{ItK^r-vEvCNRf@764IbWm+ zsf4xspVY?07FJ_#4vbPZo-}A~g>y&;0Y8N57>%EZg@?#$BgN5hQxJxtDkL0Ou{bP| zmF*!G$X0N%b<=HRa#o76gccf<7HMmqnsXrtihftN8pYYpPi{XJ6Sb{0iHpwrtI8Cp zyOFawLM7~xw7jYS`?tVmwtYls!=_p(hVpmK>PK%ho0%gf*v>23Z!uNrAq^L%Gjt9kKA1H>oq1}e0U&6S#LgR3u%xDGq(WXq00VW}^QZD3rDQL}1C!52y@tFUXw z%i4jzu{V%fIY7heW@!nwNJZ7q$_^QMZ~|Ubjp}JR2Sy&XjN&WXj-@&qO|N3kx$$9F zxK}&d@er}!@le%P6JrSOCpm~s(ZL;ka| zwzeuMq9~EPY~ccqt#kL|&L1ikn>(_Dp{6TMHM_B|36VGvC+j?_&XMffv|^qP)dtu< zgmDm7-(0TeDPrZNg`DAKxPZZV1sp3CfN?Rw2{<|>C^mHc)A_D+M~jdOW0XMV7Lq|M zgdYf(SPzj`D{ffcl1U#c=X@+QU5^{eo5^@E@z~4vWU$wJ^wBxbf6nm*+W0;LWx=9`u6~T4QYEDs?Su7(50~}FR z1c1HrTO(2xt`<|fhAr}4)zs^I4EYXaYnG~2w*QJEvDnB>McD)l=wQ{nqls(YdedS$ z;>qw=cWF?)rT$3-%5YErgltSSdx-m>~q01!;?(GrZ<`#jaC|3j4hvNC_9=4$UzP6 zt0Y_ihRde6(x~W8nlXjYQK{#Li$&Q{sU}3R18!0@!hWl&?ww^c_l~_-8dx zsD(#4E52ZaXwA(uudg4j>xMF`*yUDxiZrqSt|NYCtuSu9z>==k)!(Vvsx9u3dSZ-H z;DH8ogE@wP!vG>`O4$I9iKw|8>`q~7kPpwaw42Kf6PD1UC9EQ?mG=_V;k#U1MOefN z47krd-Ktu(`UZBj`4St<3@6XHF_c*5=oI|l@N9G#^5CjVh2W;RU**Od7A~){S8z2) z3h@GS9lL!c4EW6(BSZvkVs{SG1Gf{U#4W=_6^2n6B|Imr=W8sTYJf(e9rmp0Xs=lU z(E{$O3)r%Qw#Gco=6M2p?a&mMD33DrlMRY#Aogn`Y*B7*HlT7G*ULeJZDb~};l*HO zwcBboLx0D!8{rK^`R2)jc?8=UgFO~=06cqDLV8?p;u%q34V96|vs)XwZHzQr7eQNb z#617*sgCTd(P7q)Cu+<14Q$=u#{=ePPC23}{90feyB^WC$cX4?SmMAop$+M}D)z@> zJYi`}Aeo%**q(5OXGBC{9dztAM}s1d39=_csgVeykTDBYdD7sXY|)?Td&;7^%8&(t zIqEX^iKGqT`GmD|7KOz)RNZK$0gk9811gS%VUb=x0=3!(Or4)RjFBfIhG=4j=!}p) zjT4pR?5n|l;~v8-VK2_8Vd{lm48-t;*v!-uu?vVwTy*@pUWzC14N14N2u+m*>L%4# z`Tt|@ZQ$dou6xma_M90XjbzV}7|X&Kv!y5?J1!B(Nw|)St+l_->~(fHnU{mor`f7b*@6&fNa^2%qMZ2^ zR6`)fsmYJ|idf!1p$D`W8pzSy!g`s8o`82X4t!&XhomFA2dZjJ4w@ioYLdMJl+TwQ zPQ`;PQbHcpSs$R%!o8lglQs=amQBbhOqQ~AQNOS(sifbhr*QH(g}+Zpx>r7*&VdC1I3f{++ERALf&MLC1@rY=54Qt|s? zl;;QB*WN*SscPEXW1gjHfY)BY>y$YG#3j>yRp^1!0x_tx+^CiCidtYp8+2%-(tN)X zc>?g1w`>{skw!Ra^^AXj$vwiSHL?)Dbw09s;u6#|NQ4K2K2$4DVk+}u0>J8K!Dl>U z=sL_`-mU?p9fXV%Y%53g#JR0tUoT$2f6e5b1 zyTi@nmQ^H%Z@i1-QO^%N>M*oPmaNkAASw`J^TRav_Pgci7#@J3q4#CMxKbAV1;ji~ zDA6Ug)bXxe@VYU;`wg$7i{vvwF>5ZvmllQsQZ*i6X+;AAM*+qt6NVL0l^)?Vfy!{7 z(6MQs6$UcmL6!HN=ZQ1^6xQ0>2#8Z-%|=6_q45KU{Hj+8jA)_RK`m5+z6$RfYVbk2 zu0}4#CKRTJ6kxCk*7sr!PE)}UDU0$U<-k+IhXUFaKCQ6(Xb?6bb5LS?XelItFnD?1 z(n!|>SO?HjPs#ylg%ILx5?eQO^CXt=36N@5X!q&e2XO=eEslHgTueYyP^pN6G0^A` z50xS2MT{>9%q6@NtYtB{ygh>k{M%XM&^#X0cB$D_E)&FT3)grr9h$mGFd!vEB6V*f z6pIL2#ZVIS#t1WSDA$|_s-~{J*}m;tik{zLB(PB2om13zUU9MyOlgEPFXc@qkVyCsLOvl zkmu`-!=kL7Tyu}WramAN#)8@e`Wp>H4W)*p7P_9zhr?IVXc71o9(o;2W1m7A+E-Sq zzZvq81=vveqFy2WmzW!5FfLB@i@`3@)7d|fzwsiXqBrB$#d0yJKJCNSIYEcq%1?~~ zs%vnr5fF1H^BQkkyh%|EF~*$yW)Oj)w>T>#@xHH1%k9D&RJMme^$al;9Tm*YleDN! zyO!IHdT4h4K^HCKHwJQJX{h8;`rvUvxN2sGwTCE@X6$ZJE!RjNf-u)ztKaEwIhi(? zp}gwxzANX>sjnd2_p=xiCUe+IqP}Dh9;7vW*g@Q;@mmwU9T#eBm(~$)Xc9yYrc2Bg zp;j;`7wj*0L4rnH0B;op|#60y^& zCP~3yX!dB5BxR~r@451#hVcH6(-rrXO_ffc#?s|=?{8pJS{xFcm(zHq{Gj1Y;}aq4 zHi&_u=o-8z^AG0Epa|9`5V~>D21H-J*9-lt21IxvEx2iGC&xwiWCwMLe33@Uj$WC~ ziTrQfu;%kyR{Y??%)P@h$jx-zGMleTQ{Hho$%OU<*JWpCzjtBBlUu(0$rZbLW!U?s z`*$C_>5ree@!A_#e{A#6g-<zm+SGjooc_{6Vc&FV^a-w(k3r zL+`uh+ME92#|N(X(DSc;{4>w}%i2@7eE!s1cJIFT3zw|@Lq+lzWiu1g{nj;iy}j5m zmwjJe4wnMcebY5tZhXVH8uve1o;~>eA^nt$3zVyx8mgoQKi!WUI z=qJ1USrZ1042Ex#$&VWq+6Y~@ah}!O5xBZ3L{DIzerSY#U&!66#m%ZO3ne6-AW%D0j zvHF^e*I)P-H(#HB=(wRLZ=0FP(Vo$h|E*G~zTz3h-S_Q1XHLHT%hr~!*-tih^{xpE;mU=ebNHN~-d*_TpWgU} zRXgv0n#Qj0_m4lx`KdeK_-4Or{nW|pKeIen9W=GOX?ywCYgfGcd)IvJ&wkigc;w3i z{hOY?zVFmq4Pntyq3{ge5%chcDWIf-vQkxYI> zGRc^k>R12i6JP!2)z5$VL!Gnbve@+fXXoxLt}J}F`yV!bB){{b4W|~iUGm+b-zxm^ zD;GR>*(X*GUHis&zI@Gz@BP@e&pdzQUHKo}-Rv3pV30Gz`w!{;GI?bnQ!wyQ|BduT4WBM)$QuL}K5|FEj2|{QH2c zR2td6d+Lrm78Zm!@r&a3rlP{WsRassV;_!3?=DaZ#qA!6?zm&$zB>pO3WRWEYTq}$ zv9M6MLwtjZFC^!7ZF{55^lvHx)va*#)l(v$9~c-NIqNLpzwwPz-Hs>u?uRok77E9O z4~p(+YD-(O1g0($T_ZSC?07p;7?~2$l-M>hFmUOmR}VKLoa6O3#uk0{Y_F?>Biz3P zo=?dnTJXGfewG%s0T4w~BWT^hmpQmQf=t}W zBU7*{%~)DWOC_y<8n*ENHp@+Hkm{(y%-HdmlCc< zp$jsJ%`|>~neYkj6qHJ>VGEE6uv(c!B$FsDlO3p4+|sULz_%Uw|*LRT|FEvuuP(8 z6!Rm-F5o)S*aaIH7f)0!F?KBpdq*LYhWq{(bySkc-qAl~+@qtdcDEK{`$P+Bf8p_$ zUtU5c+h_#c_slaib~%~!y+xp(?1N0~*cI8aOOQ-NQzkriwaKJ??24j;k+mZL96V@$ zmlz&CxG<703>0AL>JJP|bsxgvdTgSi%;u318oOS1B$-TIv~PYSyLjxH5ty>vF;?vx zr}VE=IJQ^3J)rPd)#ot9-%ir7tV%o6X>E0 zLY(mbY^wF#zT)1lb2e4`F7$@|@ps!DyzgAj8w~p6$d|vjD@hm5hB9e0(c}qgV+OJF z{&}kVcv{z=FI0bsk9wV_PCI_GD}0x2yEsR1o0R{)6762%4KKkMKD{P5jv*91HJ|F+ z1iMAhLv#rBddlAep1|(X{bb2De|T|hZR)Ih4(tZkd@Ofs=kSxI_@d$@!oUI@7 z51a!!DOz6c>i@8qb~!B&-1!rT@?m29k8z zBZCLrHb2PSYHcj#In?GJ(CF+KQ76AgKsd{7$pvemzuYEK{7`L%@(0OxZ$gdz4_-l8 zxKhmj6&0j5hmRu+ddXRX^01!_hfz<5sMSP46zu)>fPE3HltgOm+O}+Xbnjj}dqmHL zFuQ4B^s4QLt@Z4EQy>#vGbo5Zbr zuKsPyMl!>r(dbKT9Tq*e0GZHWUbqSM?cV+DtI@~bwe`(YC~3>>W|=SshNetLi6?q~ zH_Ie}!^&g;hKuZLrtx6nz&16CVwq$LkO>B9fA5E1ez63eKg>djcEi3aiiSr=M_Dq3 z6KH8w7&)9w=4qk*-qh*|h}&fn(JZ;}%FBnM??eyONG4A_F%|uN_F&7ZB{~sCeWxV! zU(7POcI&p${ZGiKD|(n@GR4aWn`dibv^l?~`iU5Eepf%dS(=w@*@MpsTDT|$UgWnL z>L*f(A=giA-O(v9a@wgjNpk zFT6kI$p~!VMqv9Y_T}?kUHe}y6fzfQu78e(hh`}P+fR}p^(6`i`H8OXjFg);b!WvC zt)VC4JSmyb>aZ!3_I@&z#kyl;l@ zQ@kk~Mf>I#oJ^>nh=z&lviaL&q9Bt%z*2evQgHnw(=|Mwb9IGO<3I$ied&61!Og;V8Y zSR$$&bbG{6K(|L60Z_eekNmd-q?KM0{lcKyBT}IFxtM{g{xx|i&H#d%xfbXD_W{)& zam)Y;75mc9BY`?xKRF5<+qm<~fD_%`@z|jGLcN}fjiH_D_VB+i*xG)X;+Vj+g%v*s$f4a30yaXp zQ|wFh*)_k$N0n?&h0Ul>m!KAj!s z5muvGK2Yoc@zB3S&)SFR_HYw8Y@FYB;W*PVyC^BRE2h-KLrNSlHl^=hL^BV*j^+Gt zYFs~Tc@Xkrs^Sbj`XV30(>BV81V1|nr`%>OaX`D67Ql^xZQv+Kh(|-XH0ZO(ff7g> zxKrRu0hV$XtwcZ0zu_F4ANKPBm_8m1C?TfLiIdMFiG*mBGI5A;H4V*T7;Jid_!WHi zEQ!6}AXI&p9z$s=@NHU5a8T23$m;s@kP-tC`ayqC=UakQ5aJ9ePMBKS{J_IaI)hNN zkU!MtZVY0;+s~L|o{En!TDAd@hT=`_&Eou7vw1i~o#JH*3|eEki8Gj?vBeOF1A_Kc zC({g!CS4TuD+ReJ7h})QA>Q>WpOb8I`f%OhK&1n^ebCX(7OQ5gu(f%HT$AJ|G1pkC z9u8_VXr>lq|u9?xMPGt-ojsVEzj5j@;8OFa<($dhDC27*)iMS1hn%*!j zCrKl_IS|*)hrih?oxA#W&;|pL#1Ny1SyaCT>X&7 z36Tb_Eqozc6FAN`Aq~?>7;gO64&Z=>MhMoEK5I_ku$55Qa?2)SXv_

    sq)XR?al_pbp`<6lyyf zXo25ROCc%N^L7T{(c;)5Agfs z6~S-^MbjKV#B+R&{j}cXGFPqmiRkl6sy~ljq%4;#AQuG>3(C2&IVvJIbETaL z3>uFi{8w?hqQ8KK3)zQt5a9_xW57IK0<25zh|r2}s;}xZ_xe=K&F``jDZAQo`wn)h-2%u=#3?g!Ly#V~X*# zXca4)b6INyzQY5ncNo_%&d)&?bJ9D?-_&4N;V8lbTQa02YVBOf|Jg{5#|Yz+ z1)DnqYE6~|M_L^8kS<*zb+cc9E`G#u1#Y6zT8X9tV(yV?BUW3=*HFynP zgV*3Scnw~I*WfjH4PJxS;5B#+UW5N7Kx%g4dq|FJbK`qVWD-9HwpdA+Uq--+jg&t{}-_<#3sYP2T@+<#`m7Y;n+RRxxeFFDY;EK zmG6g3H1~tH@Qx&`*}X+t_bFRWxcgPy?@(R*ZjFG?!feaIj`j(T!0#N}cVnxO!4B&Cky&xS7WtzQdGvMePe?(~SS6z;xTMC0dJl z)M(-`eqXEMdptIzUA#aRBk)2!jxu;?8?sL+PPh{8zIhG;xG{ugazheja~tQ{XP5KM zbBUH}Io>|oW8?5rE>hz#gIt_14J_Ct*sWua$A%rLQK$t?I=&rrTc|yJG_b!}@o#9h z8kHp37>Z4gD($raN2MbY5tFg8BU0Ys)vJ#;$o-wjmC-|U7Eho26oK&Sjh z;0wv|IL9y@dzNmT8@gLTH*+`jLZ!nV*QG5Z@vE}E1H^%8eps<4CIdb|8YclUrWoIF zSwon5zi&jX>@p}r;G8kV92Seu>*~aJxPG=vwMB47 zu4xDt#~31lR#-AfzHY4rNYL%W2%_miE@@fc&uxe`DgqZY9M_-8%oe&m<&+}2Y)_nSj)|a(XRfukiED?99B?ceVrL?Lr z-Ts6@9)YGCIH(WhX~MAwoV{fJty))u0!l&C1!^$Nw+Y1YL~KYM4Cx5cQ{XWk58ny~ zSl)=_B#IX*_MzcklbON_g_tQrha6*NyK+KqLC;PwJ}3P2&rwREf$H zKa9vxsg-~4%k#(kJbVC@Rjx51&e1zreA3q*f7`q9Ex%% z9RKz75Y=x$RNQ|;94GU{q(=YF2LZm-%F?TZd?dQAb4ExRpQ91B)0<{6jw4Q1g`*Ik zl9K|Tz7}YMK@W+~c{#3xGW4beRDx?WIH3m20Y0G1t1lz0unq2o>CmLW_|6B#%6|~k z9_=LFKbkse&V&TR>n|Kt^ zHt!Pp&lRq?OiF!_=P?S7WiDZwvoos!2=+|NM*^mVICz~!69rN7hzZs zroPybfaM8;z50RU$a6A!C9xbW%q1L=H7V5NCv!GMdlP%?9oS8PLyw~SNr#I@HIc(- z$x#YtC+9IlXs$zs#(qb{_Iw>YhJbOLx1b>>U+ZQ}3Q%jULD<3|^Qb~hKISs%YL`gn zsF;ro5C_wn^d71soS+rD<~R=;CObieKTkz%<)&2~Y>;wP@PsnwjOZ3sn)?}d73oT- zN~Ok!qf}fxZd)t^ncRoQcR-lHU}W)Kb$o+>fse-A z^IQRS3(6&>PM@uo4;x~KG2&jt88ewdtQI&SR^zi!Vs!yswB=g3X6|MQejczkJ*Gi@2VN6tmlc|y zY3N4O1kIJ<21P^e_QJn|{M1)`b+(`F&6r-y0O%(rgE2W& zlxcpjPMb&CfQ9%x_XPEyWuTP0EM_@lNtxiMKo_*2oSPz;`U#i{4?8HpZ9FW1L~yA& zhEaAeHrNsH^TH@W;_yB*>7jfywAPRvftI2>juhXK#*-+b$18qtTCy|#__)j zw3ktEq#ftDAp01Ub!u)U>(WJ#Pn}|xOp;BApInda*+E{Ytg0I7Jq?PQmtdi*A+IoY z`Q)QTl<`@1n*PyfVT@f)NJ9%2;~QC(_(nBlCeDa&(eRbOM-W46d^mLx0H=W`$92KH z$tadRQUXPhTGDip#Uh=r+`_^LpX#Ef(f)yIH5n>mP(bD0kCl=Xmk*$@;KRhEFS=u5 zGB-)%0vgrxw)r5)tKZt`s~!~c>?;%>iuOfOtK_pgPR@&LUbL{97q%npS4x#1aFA46(G((5MQq-9!4cohz9a zWy9YbUvWopq4on)`mSv7`^rXLc$I2L{4nyR|gP<$$j`(B_?5 zv%n~;qKA%6RY1LAAIXk*lA~E;yum>d8D^_@B%_h*GlESRWDsI+4BhJUP za(zl#wc>l8ll7ma+XlGDah^DZRv$iZoM~rM@=G=oi3shL8VO4S5#t-b5sS)cA#P#_ z*N5ljkEec3J;@uyTLu*`l8nuX2X5b@iLgwgM^7MCH%Wb%_Ni54z|TA~fsP)}$uen- z19Yn-;GwxzLY`G0&nT40v2X!pUT{%B`j1Uus;Gs7SwlUghiy9QlRPx=Zpoq~>_IM| zku~T8bwaG&TmH3=vt9;Ee8=I8-;X5}fqbW)pq7n?p_bH( zXw$DOKQ$iX>|Wt(yxs`VH!-Nv0EpWx3}y6|^MXU?7`H#>%EizmpRnp?JYm*ci|1)2 zAQm~v5zPVt<`++_p}jg5j;G17LF(bML`6_$OcKZI-S`-!b_Ga90@}7x-??Fs!YfL= zj5J89lg1AYggK@igEW{GVo{S-24jP=I0SahV3g$}$g-w3-EC-N?&(l;ISWTGN!Q?|Cd^}5Y=Z+| z-xp#QHbk+;HCS$Gp@281(yq^i;Y*5uVfYjrtjS= zXGOms^bww5ecw)Tva0!ts^wKY&`yuj2vvi23{ao@Cq0DbcgQY6>5*2|gx3L4_D=}k z5R!a&Gfkf`Riu>|y2^m-%9a9tN{u}u^(yo!qSA9ZKnjxx2c^(kLvK(7-9BGFq%h@h zqn7F?0_v^}&F{tJBHh3ani98KmjrccLcrf(Rq#?4Y$sz4b`Gu`YzbS}@TXggc;I3jQXts?>W(2=%NKcf*bb&8&BQac!azPnWeeL8NE+qda9gC~HX9(_E4lKV zqac3QQ)cc6YzG8Nc`=E!G-sdZ&D4Q6yYrK(>V>d*b+AQ2Nm^?lFa}SKW}iw@ECf8M zQY@A#z@`wpUd0qq$-2KYT=uDIP3#IPW$(}4D%M@HUH08BydBGLHaUO554y2~q>VS) zX>5&)WFl}In80q&AheR1iCT&k&ihbENcdH`!8BU)>ow%wDD!)AT|2s;+F<;SUSd$a zi1Oxd8XfPVVN?0D{6@*|n8QqGXbkoA?_hsdWR{tNJIF%@NU;ejMroxIrB;p#+?|gV?Z-fP_Z9p<_06x%1-9%7}=}X zmkGNd^*J5;G|$g?9cFIgQS2bf!SDF@^%nD8q8Kjg$%>1{P3EdnhsR53v__Hk@aGfF za5sjqmH!u3T5`_E`gpMC5?UZg8hZUOLpz%3@j+sEZkm{^S7w7eZZQ^JU8{Ey0eK_Q zNoA&1H--oK26MnvdF;wL=Ab6)zP>uslg;*cKU#kJuCb2H2eEzbrlb?LYowFbK%@1BPan*?@PwO*( z<2OIPJXn#JIqBW-@iXrnx@g7ykV!^lAd_0Adfj!~8&z8J``bw-^_*B%@z4ZMWZ0#; zzi`)GXD(abv+N(DN51@y-?;X-HwwA2NHRI;6Q{0~TW7Cp;z z5BIZ5dnkmVSPAAxCYdr+jyl{em03e$v%J1eGLbXh^$!*ECYLK`e7}M{HCv6uf6fDZ-3_Pr=7BX#fCF~y>IlC&Yn*kx1zN9I{B_^KJkgE zb!*P~!1^`a)95FwWiID+{o31i1wFrVJ;|h+vHj!*&(PQfnPmJ5WCFE98x6)TZmY?C z?XJ7tymEQ(anaYl_*a)+`X7H|FfaGe{JZLekG*wmUf;C1pRi13NG7}H?%VyqBh%A} z&Ezhh&SARB{^299oO$wpe&?&J-}u2#pWM6rRIxBMH4@)7(E^zgo`3n5xF8|=%U9et zUOf-rV->hTp!FNH#|jJH>)@O#vIhm1@8-2s_rn<;&f;&^hAU5Gf2KP{9ELpy%iq{V zOEQh`<#rZMD-aI9jN3naAElybV4#3cOk4V*k&!Sw`|RksD4LkS7pd(%A?H$RDQbQj zdCIjB-}UFXINS#Nr$*ii_Z{yL`GzVt4o*dfk;&HBhYth4oX8}OwDrV!jukd<-g!UVb4OyCbd4h1{c!hw znjCrDZTKEGWRl60q8Cx0lSS;}P87$tCE#BctV}31(;}0tkjWAd%Y>%C zrDQ@)yx`!7jH2CsMjkiePaPD|wyAB4Wh-7xWOA+5xRgx1Y+O&A=U8F$=Ksp~Q=A*U z_@YS3()r_V1TlYRT513!DYDHBn6CiyN@S|UMZ!%-A*$3a6^1! z@pqdOnMBe1-+#v)4s#-tS6_)HqO+cj#BM<{iS~j6hmlDXSk`@|ERLEAR&`O=9PWTGd!olF+N1CU81_FZs6;j9ATIDUp? zQrNq$>axH zn>iiCGFcEy%H-g}#6i!eB6p#B#{z&<%$GW2TeIh(v`I7HP zf$Q=S#P_6Fz#SsiXVYC6`Drh~^^l9rQe2+niH^Q;o8ET?t?2!U5H9IJ3GqsdxqDb} zj|%8HKRMxf!n?+BpNI&~Ip0Qz*hPH48k~c&fiK3-cUwzWme!_x2aLPhMf57Zn??GU z*Z58sU%0loHh>qmBRo+m{*lKUJbo)kv<1*(A8Bcbc@`?_>O(~ls($C5c0Ak|pT$FT z2ovJ&4R?c;P9sQY!<*X+F##FUSnhM`jFk7obK=m+xEq<599mr=)z{)B`~n<;H&6&cI?VL z@uoKkHwW+A2j|*rn+2!h`G8^M#jP#l>PXa@et3A5M;trua6e`pZBT2o9?kg~bSDNL zR}LMDp0jt9c`rp(h79y6(!_jk7#IuE0NG6-2XJ`g>G8u`sZ3Esz zhj2$li%f9uN0aBVOp;)$Oa@XidE@dIU$QbGdUrR8TM7;*lhLiEQZ_q0JTSqVHo}P(4iM!ES0A0H9WXVOkg*Z$)x&; zqyKRI#D&^qBBB!>ZuS%0fY)^?Vl(&Sjm;5Y;TyaZZkGws$h1vOwT>+@jE>rVQec@p z_+Z>mAQPJ-Jzll+lV1`@G{*1n2>CkA;lPHSEvUG~rV|}D{FEHy^3AYybtXySsg#wQq!-BCB$2zxcSbd;B{WcJ_?&Cxnk0B>&OH z)4FBF#Z?VI>=ZdIwqN`lxd`vH;n>bGcD=`aoA36|4ow^QEKOzDc%mF^Igx%tV%Ing z*V8+uQP7*W_=T}}#Lns@)+I)q%t2A(a;B_Zy0LbV<#{U4B4GZ_ zgah*RN%FBlvwcf)?dJp49$`O}3t;7sA&yMo*ti_S(vN=CXZ?rJA^? zXqci9X_+0V#3i8K9?|;a_mSY3Gq!+oZcAyM4*YvTJeMsA&6FhtoR+UbKqXN+mBgS9 z6HaifcxP*vQKU(0)28{RcS+)o)UL&#+9Q4e0HMtx_Xv<~kz0l<7d%Y&Ge}7nGx)*Q zFs~HX$Q9!;WPC)cK^%<}mPx9aPjK}%$r7yC4^W=y;7R19Pa&t$_<5WGND{-EI5LLT z&!We1VzDxq_^HGqu`(Ebri>05^ddxQFj9+zjWO$+B1oObOh7liv8}qmkgt&!*)^7Y z6Tm;TK9%uJ$^TxvLn6b&8)lhfhgqz|3_42zjM&SV^dDBX(opy5-sBozvQ?YI| z(@KbPpkt4#%sxddAr+@`3ZE4-N((+Emo3YRK99sB#lR-c;cKnLy&|jLN9DC2o|h+b zb>A*2wh)z?zcz2^Pq}kyl`H)Y?F(g~TD};xdUbZFsRI!*IR{e|jTgQIH?w`jq^K|! z$Xpsr@))p&cGR>$Jh!_8Imics0Ui{}ooi^eyA*SU6A+6qFd2@-na&t|+Oqh`n@Lol z1nV3$W!f+Cp%)eBUrG{9u(mb{C^TGa0n&|d=SPzMjCc{-XYt1A2457AIb?Q9%HRkj4(VoOlkFNu8&e#hz7RH=*_xo*BLF7l_4tq^fTUXr zym)mH`a?vPbd)$oT1w)2bt)kpZ{z$VBAv%U7&j%bo{&$@GjP1KctLemYRpd$%ERes zgGH-hAtWG1m(Ma(K@Tu==vs|si)4jc1}G!9V)aF^&*1DRAkMU*d51*sz(TNt>sg`= zEuif?_oV4Duu5C6G_0hyp$*Iqx?RgnODGLEI~(^bd*Di;ngEQllWKE%VL-4g3c%&< z9mimRoPMpLiW36AlHl@_)6Ecyg5&t9 zgTbQXk(bb@%qptALB8DrrVgTCQI*K>#}qHYm0>>bFV126C!uNL5*2UIBGX_T6o#;? z*sLlsui`qC9RieOiYbZdwD}m&O$7!goR^k1I%GX^Qi#=#fst`Zg(pa=F(afM4y33A ze84Q2O)(uwF$2=jD)ZRHP~bJKPLG#{pA~kN8#Ed-zLj=HjM)=L_(>5cb(YeAY2}2- zc8@8VA&tQDNKq;cVPgV%KPF5G1?s-Y0&kC3q&&WdIg(~d75a6nu8QUZRx^=1y~`Al z8Ul%g@fX!eQx){x!~d*o_LgL@0&T6Jor_609j8Umt(&cO2o#c-mmFT)Pn^(VHaVpD z%ok5tc4f$bYzWXS!<|&c2`vD{;}eHm<2{DFjNi~dYha?pEVs&uLRh8qhOOUK7f_$k z0TjkiuL_K~&&&!|!-}XX+t8T4Plyu+C>u^-No96hrTtN!6tDt~r06Qp+{0n}3dcy811kX|IkYO^|H?L3 zQ`JUVMjDD9Y~wZ)hHf&B3n!2ZVM{CCEihPz6BEW0dWZr^oZu!;p$0$`ASHItaYW!6 zw5?c)MD8()cwgY66?+s%QP@iv{##@!2=_xw5{uZT=1ls{W9@MxC836J}?Ozkn04>U^wJ+OK=X%k_a%I z2`Owj3QHqJVo*p6Km&Xp{3y{7&@YP5IU&$0r9sI?W1y-qo2BLyWJgOREG$$Yx&(~q zZx9tlT<~ZJ$6C^zAkF67Jb=T_T(1L8g~U?2!EuHIY@EsAfPa7If244>m;wsFJQidybNs~3|b3RWnhU*z< z3Zo6cv?kUB94`}>fTn|-r7{gk7?R9Mui7Q&{YEv3_KL>&4UmoX1>*HI`4m+>hqJn_ zatZcvWnO@Z)ALQ>_ZXH@u*a6Cfr96%!kYq^ne=(*2v`}5@%lQy7fTSu*#d3X);*IN zu00`Aw@qwqC_=`1<4)QJG?-y}cPDPJAi;mM)O`j9kRbJ-5&&hzDoTNPlDyuK5;XFa z#-XMmXyNx0tz+b3Fo`cE1cZ!eCI(zTqP*rY$rv(Bxo?E*>e(c_Gx&{%6Y!}4kwJE? zjo<}D=vT~~5F15+U6gzCV7MOSBS!cYTOGcJ!#0;j@coxCNethkN#T12^5G5{u%U&R z4)V0*oWbsegrKpfne0NNyAT7Le?W?4;7>rhy30+4i}eWW2zYs0#dLa54AXoWY~zs! zY1W+(0Tv-8-wS+AZOq|IHbQh%c`YOGdd3`0BBDiuG(X2(C{B3CP@A}#p!si7fIFh7 zRUe5=d6Pm*%}Wc|uboGJ&09T%`#lBh!*H?Z4IAmf zh>xd&)t?RfRM4djb*O%tO_=TC3=y78o0wojAkLqIg?fmc0Yj!~`ey~h)p^MpT-YXX zEIi2w-$x6UJnvH>Ukz6D)i`4olnl6RO~5-AjV5|f&%7kfT}J{_KJ5yqPuGQyA<^KT zRdQ8J*%SoWvBv@c#6pOLV;yPTRO6Bac1SnuSW&?n6yC~HF!PQ8J8V*SXb^CWb&s9b zk6q+4e*#+KKk2wZ1|$~^6L*OZU56N=57h&^vuhk_KY(#~=`L?@)y(vWDV z6VHe1M8+2lPpfQKz`H8sX8s4Z0TK&qo{%{JLqkTF0O&p4E||6Rgv#X?@laX%9ng_{{y?@2B7CldS~(^wOD;~7UWF^fkD+RC9e`yZg1X~L0i zM6yl8+Si~)zXr1+ya&S82~ozxg_>Xzv`fWktAc>TGah4ndraC%AjxJ@kufBq;sJwn z-?*^CgGg_r}Vb{Zd4h#3Om_@LI zXMRr^1Po0hm^GSu;T(Ka2EK%@1|C$YVyvN)NI4s)3(HHJU%97s6TmK|rJ+lKvEPGA zz!vbBk^F`R4uwM+rD@tWZ3vOk`g~%pUv7jnBn?bZxQe+GsTHrfo!U=bw4q+1Z>gy^JuB91J_clHwxVpBa=eRTNc1(psOEJwZ?`im+P*J$Sh#v7N@} zcxg6)+wx{64Ox&DGem$C8%RXsVAi(AOQo~R4}wh9>f~iL(X%Po1%ot_k+*EUn8P{> z`7}*|naIpYzNG^?Asc;AF$Yg%Cs13<`P0-UtGsH*uOEP{J%^D#|*imVv;N?w&#&X&q zQd2yvyA=&*Vd`dXyJ7dk*&1JMI~>Sjj|h+ZUM>GUYDSN!)k;!5nl%I-V?}lX9@&gv zGazu*WGy2%#6$~TbNycprGD! zU1sB+*`T+BgtGi6*PfDl|JpCU=U2bbz4}K#80`Jjy8rEi>rd@GbLD;iLH_u$x4mcU ze_W?N_RhDyJO3-iuJu_F_HzUn|Nf8b)ZdDX_**^gYb?y0E;)4V<7Sm7yCAx$*dk5uv-w+!iv z&+g2BS$`awoL zln;6fG#vTAeb&gEuUOl+dFwxQ=Kt{r!G#xgp8cQJzj^hU4?g}M!Ng-BzFpBn2!iP)IOYynY{rg9viHU7E0V=M>@ojP^oSQzI zYGF#?JZ$rT=m?)bZl!ZcXr5_p#vB8jaDug6XpjFzVf1J+8MQLWWVW(PJYgCN!k*o2 zhxKQ%4OE1a%jtNMi48}eOv!|81Q&$0w;PY5hY`i`$a3hA*#B@8B{F&LxroXhIIK(x zBletk4FA*0WWTk2I~*Jwh0TNzFTU6fhKWQbk&SPM4_?c98pZiyc=ev5RG5$F7%O-m?cXc_|sY zmM<64fdkeyU^pJTCJrZ)DL%{J9J~HUlgWg$Z*0aSc875NRG4|*498&e`H7vP_>uBE zeAom6FS+;80`OZl9DIw?=LPH?*?v*>w$&$`9ixAF(>){b#W|D?8i}6ene&C6m(F)~ ziU{_(L|5Act>a_1l(bjSD(2e2FT!n8Vmrl; zQqwm0#O_sA3S(C znLP0XzFFWS#Z4To-;XGWYuT;2HL_V)fJ9O<$y0%cI|&`l7g;ZQX6tCQ5B7>tDcT*q za&RFUe);8Sfn+sd=lWN9PO*@zzm8ERQ@gE9#HWP#_#;zO`(P;unM6mC$$^)mf;ffd zt?vC%A)rM?H1hP0pS>J8nf&eII$NO49`P51?)~0rU8BRJhm%S7err8we=7pC_Y?k< zCQ;?~Et-1&Pq8!SPED14ogG zb%qP*C!nBmPa_Wgu*H6T! zK6Uthg0EP-B)3kTvU`ejP!yIIqUhjTV6{v%etUG($)q85Qu2t9*YsffLb$PQUwb&V zPehnl=Y?^6x3f#U!-d=J09!z$zaX1-jpu8Wzqx7Oh&6Kh`ASp1IakZ)f{}(-Iu6rok`o=-IdfPPLFvZcGz%Y z|0pbNxu@FVQ@jFC61&JIPhXeD>#MR7#{{2Mc*4FAuDsze;n?2r25XlX$HN}+oEnAy zmBL0WvV%rZDHV zZeqvyIG%tVSK@?@5oN{s^k>yHa60?NxNVtt#&(Q0J$?7&v|yT&utxq%Tzr=;pXODX zCvke_@!uDO*BHlRc>|vR7HHdy#9-0^&0%c=T%RB2~>Lo!(t{hW2Vtz9pLxa5QjDSXtVuw)*I$Ezvc|u5>EeOLE)IGO%uSHadzX3 zvxyiOET|-^>HGNsr^Z`Ar~InTJqjqzj$3H{{{-NVM-jElM^U{$aQ;*S8BJ@b4O-$^2Q+~{J+b=GBJ$fy6Fk8B z4Hd2e0jQzOnw1K@RjP{LP~m(S;>%+`S{0I@!-*1QC;Ymba+j?6VF`7xeGn4>97USl z??fVq@^Y*{IN_$DHCA(dkR=y47h%IbJ|q;Hrl!NAv5VE75jVRC29JF)Pl*r%2V5bd z=YgecC{GoUNDD=o@{VPlVsmNBJ^{;&dF0}wVMz`B{PaZf#el^C;b~6J$Cl>AXb9WD z8Q0cjIgCl%BIixc5!K}I;s$dc)v&)n+G^ycg9RA3iJS%X^3o%EM0E9Bf zbHSW6Ax`2G&P`TfyWdUubsftDF)20fN)aosCH?ed4g6CY(pOBi^qtC*Yx#gQ{6SvM zXpf=cSyiQcVlW8s(wRX)k9Ub~7+Yv40@y4yE52Qg5OUn#60(`2mho}XPzT6uj}Q7l zu1VwyDTXsZiSR$*iY+Qg1*uMCM*`e9Z{mQalIR#72^Z&hh&+wMW`UN|2;dJ^2U2(l z3)BFf_6!5Z7JI?|=RFV|VAGBkY_keLhgv!ii(2&WPdDE3=cqdO~MPk_0VicZ7;WESBufyZT;2I;%k^g2!qOyW!7oS*lY)L0=y zX>G|hhwu!*onR-9tpSDMvR6>1#P*gl1gK0EJ!K<&?Q44W<&4%gX4wKs6n&k#542wq zd3gPA>oqnLyE^4>2d5C}u)+-HX$tgml!TYL%$@{NJ+1|~IVMikq8{2oFU@u^B%UX6 z=GA$Pi)n!riPmdam^g=olWRCk7Uu~9XhM!um$M1qz^M!%uS70IYbqSfCYPp<`*z@) z_f<|KSozo>jiy^(??3LJN69;dKhb4a_N4Yh0b}%lcgBesmG?d%!BX7(EM#2H^2974mZ104wh(+89@ISynz$u*HV4Sv4i}O3j zu3QXf3?yqF+lICLhDEe9N!p4p(Z?fz$851kH0IAN4Z6nT-?#8Rf^x~9rp`Ewe56`X z8#H_n^Q_?OvV^sc!f2%h)SRXf-1-H`7B#VJi#Of@)acc^ND-$&>+>6YgFL~_Kx*^j zsXQ@B{RGt@crhOm4SiC{;W}s(!3xEh1sbe5lZhi1v6+y>zp8dSdtw}*41p3=5QJ!# zBS7;X?U|l}>2|7OPg& zka2E$thrK@8#Gix{m#5e3!I%dkqZo5GQf$+y6Rc0(D@KWhOw1`<$x5jUjtrhi7dt zZ`TBF0&H^3en9~xDr}QP`4#sUBSK)Rag=y8&QFUa7LxMzSShe3QpK8Rl1;jf2*x@d zHzX&HSL7pQR`&MbX*Xc%tWHY_2Z_OGO1OhF<5(xVXD`AOU= zC0GJ(?DFgUbgMDKqLn29_!ogAR-nf@rh}!(%6Ij~m2zCo2z@;wG6Bpu3_5luFb%=x z?DCH`1Yw_GYuZj}YI!xSNS-t}VU7>Svbo&5lo-@`ycex0Dn>aqiJYsbaNo)gQS1Cb zszD8&VSt3yrZ}JKSoUkeo9>og9peQ9MS=y6aJM4m$=cG5zjlC;zHnnSOhP+^r+~#9 zSB_8oT#b_%#+4Di^XcFr>q(BDPg=)j#-nb2FAdw(OvnwPYEJrndhq32g6-N26K9BxFvb(G&o+yA*9KKq8{vL0fZtet zLks-$D9=+wJhpJl@tS%`NVCe|Ati(&c4LMUJcd>Lv^v0s?QqD_kQC6YdTo|%q&j@m zlp`6IUD*{VUum60stKuCAI5BJ$29Orm%5fFWSRxKu~rsLpaNmcOyukHy^#8f&N&?` zh1p73Om6psX^L1*2#>D?HhkHjpE`*Xj#(VzSk8PTP)U}=cMK8%fW4Nbt^mRm!SQ&>p=ndz z>GEM0t#n&o(AarRP6|C1mPq5z>>n5L_C$Ic#5x+Npe(#P_WCWs_=*w1JLKg;TyFQM zS>i)T07k~I+ZvOATiz3RK5sarPEs9Ho!y;G zvk!h~Ca*p$XzO5kIRUhi*^o|3Di1K=4%oiM>}(Ux&j&3nN`bW6?*K1GOf%Sow3J$v zflAopgbZDa%OeccZ!T9fk861wTJ|nHK_0&HAXCPTF)UU-V`2{;bsJHMQ{()eJ!8XsEZmtEc%jD5$T zg}uGbhS&#JIdUz_Es0G+vA(7BDs>DE4WqhLT0wfAq=`nsrwnqg#LGAiH=3D5nr_41 za!ORdmjq1`ZGAZP02+L0ua2XPzO@pz>G-+O`b3cu-Q~^B5nDvQ_GA}L`IUONsb__y z-1EZPP(H8jEegip62E|X1Yx^I0 zQ-1a#lF4m1_4dx@ayjo7dk1yqYhMi>x~r>mt^D4-`HrU_Sa)#u_`$CXeR*@|M%d1w zpDg?6@4YU+XP4-``P5r)J@vRkdF75wu!mHkxFZM}JwezFTAE@Y0dinF^pxAMD}Q5U zhwx@%nPjP-R7hRC*~(zCLu7BcamB4UQJ#@ER)@PQ^0?WRbF*b%mPsa*KbMJlG+Qjr zmUFpsS#V{Z<&g(lP?pJxHxK)AT-{d;W^rlovbma>%ayn1I$#@0i;jGeqK`o)zz=uj z>@4nG%vzavu0G*?X|@7;OIbD~6R%v}`^a5u=T_WyUD@s#NhYRNu2w3uA2~34-}fK5 z|CZUxmyX+6U*wyD1ZGtb_CO|1M;NS3c{@YSZ%%l*+$V1s z_A0VR@|}{j{i$Mh%wccFZIQ*gLA;ZR(_2g!2HYt7kcm_SD}&i8WKz%1nw%%8pRi2C z$jI>3j>KOoc(3CFxy|#L3)X+G2-jpE4D1hxE$|Zkd5Im~M3=oAE`|b5HKvL)-b&6WlqA!$Eu_inYxQj<>c4g|?%|-TRle z3ycA!vsuCC!5uIig@Qe!{g$^3FFqIhOMspCbNdq9n>Ra|j2w5;z`**ml8gzwlvhGD zWir|-lRV=pocQ^OmdX39OfvMR7jTXk>wx3`Kla`RO0MHN53KjPy78tl#JmBA;E*7x z!Wblnh*lnXAVTFZ)h?{{z2`|F+`ko522 z2h6LgTetr1t*Te=b=_A#A9S)*HdEXTuTv)?&jWl0;h;`xwasljo6V)AdVQ%_c1b7o z`k#$Xe(gVQpp*WWe*f69pSV9`^hhm7XKguls8nZll;yp2EiL9VoxDnaAHIOB@Hg^s zrjw;UKWJ_Pm#7myQxagE{KWkt!!hjIF5u;tH`mG0qy7HHi-S5@$~x1ZjZWVCp|dQX z5FYdU>2E&&%J0^ny%lF2RZ!8%Xu0!^JzLaC_y1%0kJ6vR7{ORc^SSFszWQgZ6R}~w z^+)_UjTN1Ye|5P1Y{1c@XU|@|I5>9|tgtH2bsIr!^Jt=67q@J0=;^ybH+;S$>=$#p z#BjbNxo3#J8~nzf2RST1*e>`mgs$hj?H}>&Mn13wOmuu$W%i7e%z-ov;nVNs%^^h zg}onKo(u1$e5V$YM|@id{4BjC?#XTLI9+agm)RSF&gVO7u}f4qzcHi>=Q|Sp$lG-U zzTLzZXSRGZIGYd;0YmL17brb!3lIOKa+BAPT*aPIKXzAU&shH*v0K!uKWQ6Bd|kM% z1((mBgdfQ54ki8`DI=T($u7dMKSW(o2cjRQFwTaIDSj`N_u^ev&Q}a=4fGHWZAyH8 zsPkmeP7>!gCUNZBa>Up#O1Ha9*vCjuw{z>GA%zao*hGqLeWEQ~hs??X}ot{ovqQsA9V_K3=th z^0UcV*!0wDqoXq4(7mxZ?*NrKa4RgbT=a`3A!F}C!6zOPj=dhDIwz&qFw zuAe(PRSc_&PSosPv}=ehnC0u(*g4V3w~IOn%O3vn$6DF`?Yimyw{hNFA38apV4uZ0 z!8ZzWThJ1!_Ecx9cD16TCAPDA_0{pO%6(aMQnD=^%zGQqFRovJTVq?!*ALRk(DDx* z`~Lq-cjoNg_UyT%$BJQ9(aHJ#-hRoBRA$`pjBUooKFfV*)LVki%%Csj%NhOPBDLpT zS(rG#)&Dlm%IyEH!U@x&6S&Zc+Riu`==~nKPS^&HbOPPH5uM=dQKb&PcAi`JMs+gV ze?R9}#i51EeyuoHJv-h!w#D4FRGGV2A2x*gXGJF=)die``fP|Loy^dBxTur#OQZwp z*S`y$sDe(mJ$IcuHy~RH`?>4Tp`uPoAshyK{H^0#H0RP5y~Na)pHg%vTG!l`Sy6a*eyoUgtu3m$n6&k@r7`~O*WvHUAlw5LwWFCrYL?P zHk|g8V&~{zeizynTM5g#jC+i@6Y<{LlX0eVd}v$alit=cZ}S}T&(3dDzOG-A@E%X6 zcuv=Nr{~LM6v_?xdHOTcvav;6r*23P8nmf<#;}8P7M&{DEyAtZHNwUZe8)ZA+buer z!)Uxqg=P5+vug}4mPy0tWml;kSzqf|F0h0(^YJ_5Q6Y_MnKu(v-<#8usA z&MbHFLzB-t*foB^+gcXd3?;DrqXR|k8KWZ-pPlR2_33VT2EQpO*iAD1!Mt3Aa~b0L z`r((|Srfi3VCajSO?r^Z#>Z6U0Gf<(85{P3Rr{H~%j zT2$d-Dor(?Uql19hDVKpRDfW_EAb5A<@CQdWa4__xBQ>N8b>ueUAHY^g78)-qEiDB0hLtGL_4 zMuOQMOeF&sgaE23#uOmR-AKjse9|rj2Wz;gpbN07Sc%-X70jhD=UAx{ijybhXbPd> zaI81qV7_M+Chn}=RmtI}Q~bt(U+cl&QqD>Y?+qv1fDe`fjw``mr!7F_jZ&P-b&6d( z8T5U*e;5XDbpoav@k=ut>TiYQGWwvB%UH`BQ{KD*#2^i+0r>K9;M3!W)j|iFQ-cDv ze9ftI*rmlT__ajKezho46LXe}(h)`3G$JmZSMj%~@v}IwjjLGCFGT8rnL56-KNG*0p3cQQ$O8DbD3^n1ZKL(%YkxYFOj{!5rw3+HDik zV5-&o5Ej%H`Ij$`WfgjM%Ck_J#OSq0Ci};9$Uq-@V)#Z9FOe))zG}!JuaRfYQ4qBH+)B?w1gvtU? zNpE90Ib>W_k-f8wjNd40)$)Xa$M?2W9f9IV5jHte$2RN)yJ^y>sg^C8O#dwJ4~Y`D z7V|zphn|&S$BEIh^(Melz@}E+?f2s@(&}#=r2M0z&uV9k`}U z8-}c#I?6d+p2R1Z6}DP&y-bKz*wROcI-JC5>;%GR?0KUf2^#%oWU`(l-iVO*-xxLN zxA9~VBxQ4nrzFLJHNU%6WZq&!d6NPc@YE*S$0VFx@Xf^6&sS8CzAgGfVSy=L6oo_t1 zicx3lsQ2bI&-#h=SGH0CyJLb}hrrQaY}$Blfq_Worw0%$+N@O0Oq2rvyQ6zGX+O2hLm2A#a zRcK(r#!=usyFQw=vMuyhxjDw*XQm=zO&Kzrmm0hnwIV+!o*9GRSf~-5jEUoqbkrFa zt5MdeacG{C!kIEnA(k$OTzryUNKv676q)dEH%2>jP-Zf?E=XY8u>8m8DMP(hcJ67* z<AbZStO`F4O*pvLfW-8~ ziN|rWA&6Z}ogrC^iPL~HHfN@2#&n2u*f(WJ^<6#z(SWvgCYo}pL!Nz3AAyBpWiwQK}%WY&WFgjV5Od1r^F{YZBB6tj*>bY_;v75=r~a8P#-&ach$7DVhw# zTvE8SVsD`V=i~$Jvf1ikiIPm9wtL(R!NJV$4!hC)0qzY`Y$-_C0Y!O+fic zGwD(WClmhu1?5I7nKo7OhG-d?j5Mv|_l6W>AV>jyT$zz&u7Z~@tsMUM z?0ynkYOMA06*x#HyxIwfb=wGug(Gm5W=9jN?k}FCNf^dI6RKv+RI8TavkL-tZHEgV zF$&Tc_cfuxJhdCM^t8w+RGcg4XpKXC3;hEn{M?$g3X4fzL9c-%I_<8h_0&><#wNF{amiE&wx4CP;NFnb z7GioDh-oe#K?G83Qh>$e5!V||L#mvwA-PY+S4S~#m~VEF9DNRbTtx;!@RhoZN?T^1s^VG?w_pPA05$-Y6!nO51o+p5+GseFWdl*|9@6P|pr2q~~v;9&h z4$o~PJm*lxG657#7c#6U?Ho3pOB($d>J%>jmVpMjiA||E%PgK#xRtC>AE3UXQC>${ zCBu|AuOgdJal==>2V4KQ0W4--DuV9l+*<@Bxr5}iY8~EIPVq0IK@oa!2MiOBVEN8n zf!69z!d#t3W%l(BO*KG&ja0pdaG*Qc&*LKMf9bTP)+XU#Gw0dh5_bP>aTO1I7Lt!) zv@#WyI-?JJ^XpLur9c`6t>`#~f7r|*dUJdYb!$9L&%acm`R4lCZnfVX#|WWyKpYG- zs3WmnqzCdt5@k#rPU_%%M#JC>iGnV;K^0i9tLeoB-nwn>O3-j;0BI8^d(P%da~8#xa%qYc61> z0oO2-5Em5kO(0yrW-%oM*)oVZsYm=Xkj9qm#J`&xq0~;jSGM<;a*FkSGy;Ycc=bZ* z)|g>87yG_sUJJiYv{da#G~l7uTlMzdWLPD!I+l#6HK#IAc3QPf-UX zFB)7i6BVk%lGPt471PsdOkMATPjZ%lBjbF=dk9ftG-{T;6a=`crQ1Au6-2We3v4W` z6>ct3#7vxWfnCEfVdI<R{yigc|G; zzPt=*_Hfj{KluDzTw(R@eXigX3YKu2rg!qWZVHNaY!Io6ZAu}ofhMjgd`dy>!-80+ zU7uaDkubtTP=+puaxW>v@!B?O#YRV|oMp0PHdKkojP6(~4xJ1EBoA=j`V*wA1`d~% z&|x!)Fu8P-2hmB*V;_&sMXOVCak@3~W%95_@A`j&&pOQHi?{ipcI-rWx>CjZW?>D} z9LiL$@cnIqt>4(Ri;Lo_=K{?O$1L%lcM`!+DfoFoJCIvOlb|I_fQbUqcP;^iZ^tol z7@S{K?0)zTjMrq`mgBQ@k?NRc5$V z>Vq^Z#I2UOCQbIm9cQpi2kQ1Ghn4ryjsn76609Fj8He$2pM1XXc-hKMmORNIe4J7}S^Phygl4xE;n zps7dBkS`+A?FKzle6N{{K4@xYcO0h+ZFShG=y{E7Tg?=fhRvjv@Jn~~ucIY?zI%@I9Yy0A{r@F^b3DB<|#bOVmVj zdd~spVhm)=_1(oqwT>HZ#v{1$4}#COT;~o%xBW;TM z!Xuuf&RU>HnT4+yEXr1Ts?)~!ORyF$2%GbTPNJGS_2lQ*I>)d2*rRuxZZ0fM-xkJw z2I-Efwe!obH9vLupSIuj#3vrDONAt-W;e zTuf`qLl%y-z%I>g3bE^x)_(PPpSAi==%~@8H2t?7Cv~frlRZ z*sj_s-FCiy54^StTf5f9RXceGx(GNjAL$+g+O(hoo2zI=!JjoWm) zgT2|>fv0u6MmnL&wz5$uI%(Bc{6>rZK8cudXJvxNjwQ ze7T$4F}>!?RH5u&=zZmp8-L}OZ~Vcxee3OG2S3;BJ$G-fduP|Ro?msYb*j}QStN~S zaw3UWPf!nezT3O^E7M<^*y&cG6P#_?bB&YP(Uu|K_yop@JNe`vVw^n2I;kbM&G~9) z@OFT$-fI_n)4%!YPe1W^^P!Wq9hkc?ETczz&DBQYPMuzTw5{~1)~BC)vFA=b{mDA% zgnC}|Z@;zcI?_<<{_i~Y#4|5Fed-rG9XHXt{EASIpPPA(b@I`ZKijLFid(qngMRwn z*Lu@mIq<3V`(zY*)U=2ai-#I@;u zLOM{bY;coKXj#*0G~YSXQ*mQt*Y4iq^&LBQTz8k5n2E>I2Ub?Q^jO?#-eGYr=aW7e zhPH$Ij_>^5)i=KMx&Pw7yYX93@7@2|_RbH#*qgqyyYKY#ot`>XgHGB>W7o)uX5vUE z`eNMs`d7^Euk2i9ozUE@qwvM%kGf*r(aYxgMKirhcueKda8yUasZO0|mUx z@8QKh`-Nlqp3VBjF`OjPA5$}jn$2N*ITzP(ogJGk?W0~AtGzr`kAgflLHdO%rEs3$ zkn#Y(XM1)D?Os}f$q{f?E%CV*kt7>U_wKzoEC<K{ z-{Llos=a%M?8;ZQG3r6Hq7w@B7ZynV7uL@o9p^Ll`XB!3;W}AZ5S`49Er$A4@MAy5 z&Ng*&=;F2gbLVcp`Pi{nFIMA#clF=J7);xjE!B(e4-O*;ai^L?Ad;QW<5_KsMW_W8^3L- zU%w38AMiT4@a?1LL?<7)A9e+Uwgn3d*pCjK9Nj=Cmo|4Ds$V->e-{SSQL(4l9aegFGs{#NrGpPAOb{<~q5J*bnHUlyG#^^XpnyXM%YPwly@ zGx5LClJKRuZi;Or^Hsjw?l7}Q{F>rg1v))N;Cw}uP8rQMf5b=mElwT*ANZRK&6jeQ zZ3HuW$DD5xW4(|s@j2Yzv5@3Ji>9y^gg`u}z1HVmFc zd7p(%pE~@LFLv*nytnZfJvJk~=g9$EKyobX5%(+DBWk?gA`zGD8Tow0{e12s>=ql3 zg>x0bf6dPztkv5`nGPGl!+CnxGbZ3e`N5`8A?)oR`Mk)q;37V_^vw7?`AZs@SHLJV>GOy4}C~@hJyKD z`CUKGJ;uim|2kWh1xUWxobjF?Joq<3yY^bPlJ@pzYJ5N^Zg6{>^>FhQK?fkJiE00b6$b*bGWznmuQB%<9wgjT0?QOdX*>U zn{VFv=?ndfL+AVwa-Fc-KlatA-``p%U;2Hy9|nB&s~`A%wt^4v?LB{1RQFT&zlKwI z`?Gz~33C)sIzny;aPHydzqGf1sDJI!Z9g(hCs+OR;A5REo&OKvJVmulos6lBe_N0* zeDs&-j^`yhY#1k5Ei_JBaD+Y z-F%#2k0!Ut^dGS}7cAmc| zF`$zRMF|c;?bU0qjla3Kuhub6hMwoiwt)bTlluAZl%y}$O?5IX)6F2yz8ELt*35S)r^}9oysvz)I=}ilIutyAbh>dSF--A4}_+ZcYjr@E@xDy

    c9>Rw?93^|72yq-!K;SJ?gNbN^NoQL4}_qU9(Si$`FkN}tY;xzdOIeh^5HMg+7ujZ4% zZ4^p4Y!v@Q>}(!Ug;nbXKmO=yg@&*TkshEG{l)Ml0h3&ziG-SW(-O4|q>xlraULeb zkUxbjqfDND!)5_7cnwnxQialT#OW13Q>A6tPz4#RD%7UnD>f(FV}rh(la-faMl!*} z{Mtw0D!z~>La3Qgb5z5x8{x-hQ=;YwTg!!wuRaANO;xj+2>cst2~{1Jx_dF!Cclyg z22dDcE6Vr!VW<{oivfstOZB?ko7dD8b2i=$l;Su4W(xEHY*=eXX+H?VR>E7>9XVu7 zCMR38CGU}fXoYIZ{WMC$?rES<3%4`-2Gr|Bp6?K;uzXGShieX-UABhhD>?=c)E2@j zd{o>6A2iNTl}ZW5DLDpAz&AdTkM#`x;(X=ta3x#i@Rw;6y@KJe{l+NuPq>>|mWuG0 zyyF@EQZ4T_XNw3*wyz+ZD?cRl7=kT3h_SdjpWGQw#x0#sS&MA!5`$Ywgx^fSX0V%p z>XLN}@G?Ec1zz9pc>k#c01o7x$rUSYLT|8vQtY`5mwUBU_=f`Pb0DPeC0?;=XGuq} z$Mei{Dq?M8+O3nc6>fa^E^%UC@MRFMi*N|soaWOTDPvqC#KkI|ro_Uh`RD5TT%;G0 zXflOZtS{E`6;*<7&u>aFkH{c17Zh3rmm#^K0#uZauzAp;O_nW#)YIb&v7@FM`#}m~ z7q%!tyoqr@nLjUdtqS~x>yiuZg$kYH=2D1_S`b?~XxNHoTj z;8+O&Ciem~z~aN2H(uK1#HcG+Y5aX_gI)iVbQ`{Y+F3(E5_$4IwJ&L_2IV-;)xZQK z`NY^9Y^8wEHRiz5J;9=jI~^f9wnl^P2IVl}pd+sElOyu3GB#FJhgaK@q*`l1C`E-$ zDH*hJa3D3fj%N?LZCMkKP!W+?IieQS)ygeUw_23_bez!lg{vCa9z=>nmC;?6M<9_< zpfj>lc7m8!jM7dmb61c}j1PNpTm05-vhm~iiY)SaZvdlEAFJk};dxrOjwcabWozHz z40Y}~F2(KV32MX z$A(eGr=d_{n3w{EV`0XwP__{Qo4{{D%OKka%RAbjw+K7$rX-B+62+-8Ji8phWSn%d z+=vo&A~I+OEfyz~9!aC=$WC*1P6U>us-a;Q6!Z5>QkSg7+TgAA9Hb_-nG^w*)xf2O zz&3!sA?-kmuyqn+AKBq|h;^S;63!IyU~^g4Mz|rT2G^N*KMkDj6jiq46fA#B(9}Nc z9x`f_l;twIG3=Kj>hkNjblw6i5|DVeLa3-wh3Vdkqh%{v%)$Mh&J!E6!}bCYxdI$^ z;s>?R4`iZI1NCG<7A$!wxdY8`YL}5SI2hk?Due$1pzz3@Sy%W8s10cw zOPo>mu0Dg8geeho*i2ONyb~jTBNV65rPtBA-D=+cqJJ3>yLrp^Y>Ic&ut$vDexDYq zfhi3kY2a5unz%=dfqak~al$T3IJ)#VmjJ6%v$6g(MBmEbXsOzURG zkf_PkbkBf*Ed~ka!aAdx{6mX7;R^1|P>vu?_T!bdGHY`MWp@GUD4J ztqK;At5(k?*X&NF*Lc-Klqt>~^-EVm#V^BeT2|5*VOb*h+YBhrdcWn_BgV4jHXhiP znxPiP;ipv?gjT1^9Ad&FAtBP(ULU8pmtYlQxyh1MaZ=TE!{X*UTn;ni1SnJZo+`?N zn(#)$d0q2Ta}dy>qh4_qy@A3e>2gxYBZhRQVIpQ!Z(6xEg=JM2s;6w*3dVeGn#Mon zU@mHK(?~F&a3jU=a4=O`E0Yk@$bP&Mu6>63#d<~Z~O7*BR)K(M2o^j1gpFwTgRPUa9iuYEcOb4rH5=DIA zfEQvj*_}WHRHgVN3D|I^PZ1~fcTcOc>I@GGT)IS`s-bFY%x9WtvD6p!bMQnW+Ax?0 zL1Gmh8oQ?Ux!wFeu7wOR3t1H(wB8Ds{1z6Plw&*DL${Ym%ph>ug{4~pE%PIEMV1Z! z0!@Ma(^0KEmGrEpcA7PstND(TQjMm#UU8B-+qT9} z;3KXF-*rhSHHG&KF-@8*2GmKlw6jmcPb&{Kb4IngA|5Jl*%8^sbBT_fZs7?eZnqpJ z+yn;xmRFTARsxt5FM|N66s_YnJu_)*!D;L5o!3L8@{BE(n}h0PZ%6dV$#<0B z6W7msPhO>*;0CD-&dXJZ3jH0upQB;VOB2B|hIEQ<1yg02zo?OzzCzY`&R2~cm6Du- zyyBo@AkvTrJ;dOVkK5w{t18)!u)K2hYycR4v!$4$e51I7uD6VnWJjaLz7C5o0NMqM(79&q6mXEC4=i8;jxRCqcNWV zN|cyqI}y`n0(VtH6;_MkAeOG4yk@gj?3>MEUM6N%2;C??WESr#9ziH)Hy6~!@g z=h3&@D8ZnWP8Kgf3aL8(%M0OH%t#Q!q?nqQ@n3V8hE#ZeDn5P(apS<3eFmN`O+fwPHLD* z`8MEUb6b5zUeHF%Yzk|L8E+EIa>zk?S-Na-jiu_b&p1w535JP8nqxBcUpzP@e3Q@k znI*uWce)a(go5T!x{SgBBn2}eAoA7YM69#{#4^$Pz9-u7H|t?Q;pMEHcP}4ue#aJY zu1aCJE(-%QGD+~l9EW|Nu;yI-XpGU%XN-t}987#GsXz>*N0rXJp#-UD6yYkx`w$@b% z9w@8`7d%+N%QsxXa)g(GQL-A&hztndkrwb0pa|bW@M!q)pGn&|_nI><%V9%IeqZzB zwOTM^38JLX^$Kfi>fmwGsCD$y&8E^(yVG6;SDotO!0WP_%2i!4!ef}|fPlhyslEGz{GI(vJe3kIW0b296zpp_9 z<3+94Zl6|>`HB0UOV#u%*Qnn)pc;|xfl1R}$3a=4$HmDC-kHQG--Z9ATUs;H^8rfZ z5fwvs@)d(7-r}XJz5+S?#7>=VjXL|uQd|LHvN}wz?l`IkQQ&y&bQ1}>*CRiG6Qk)F zj53T}6putHJy)q{r@|sH_SJX3-U?65Yj_p$r0yvFj#~83oLYU4TR#!<4SX$Jsl4Nw zblYgC?^XKb?zmm(r_nFv{xY~w{~@OmAc~kLABUi4h*WbDi=xJCvuW|f`@S^3(~IhWIw*@65^fVW1(ql(Xz-STUrca5EzXwxs^K6PL_jVyJGSw><1p2;62b48 zBfoZ5>n)OvJ8?>)2N7)4e)Mw>ed5%q6UU!KB^=Hy2U)4p&mU}#>}ibr+;^^f=v3|0 ziRXH~l}79Msng$_XtorS5it#|zPiHq&# zmv3&Z|7z&-!Ddf%;#$WKt~HZAjR*e4C!YA+V~vkJmfOzl`XZJ|;xB`XYH>d(qvN>o zCZmp&$h_VM<^D?N2Gjvj5giH0J2 zsJBlSbh6gMIO%LSPFN165oUiZuI zc@jF2dOGfG{#?bDBHcdMQ+sx`4(+_=7xwgypW<8?`o9i(43q#a6VKdL6m){5Jo2e- z6V1oJuc2$ClZXEB&gm%Xf9I#abL^gX|H*aDZ+-Ur?u_2idrtMJdBY zoIKa*8Qr)k$X0YkX!cfVoSZ}>=+V91Tg!lO;8~sVp*VQzwUx@!GX3~zI;ldx~8{~yE^olGeV7u9bb zEuZW8>d~d8+1YLAr2i)CWbwjKom}&~*q2XpSN|HE)062WpS!AORh6;#?8R-(T{PZ^ z=f8PaEMEZA(~ca+2V8I_?vLa($Hbz+^sp7HIY@nQIf!P_&!zEH89BA;1^ zhnw8)P%GHzX?4xL`my^|cjoOn=JOaQ@5VWey!U4z75+jxwu9vKumMDv@;zLLXPZKA z&v-cGmr-%o)d)UTOseAbB$VA;Y(|z|2 zwe#?O6!vw6J))Ndr{6oN@l7Mi=RR+ay#>4p;m157B__it8l!*Fx*?60JvDDde zo*P@@lT_v3kh#VjsI$Eu@gc8)_$rcH!`v$7a7#;kX7-lpW|wFMri$OP7{%+?HwCqt zpVPF2wbEQiYEi#(-kd;WF$_!}KgVai4anDjSQ3leB^#Pr?@}M_w+u#!BAl-;lI2e_eo4EFXQ(j zYB8UgJ&O^B=pDKLje+jcB1^vA5xh>Ys(L*-dG=X+w;;$P$IbnhK_8O# z&7HeG{L^9X3h|q&L|yeGe(p+M_VwVim&*2kaVO$ilZ! zLaNKo+mi7pN`FK0QRAL(yg3KH!kLspe^ltHw`0_w^yNLOHh`Sdn4@Fa`C`W!axyzZ zZ&z4yow!&|RP7OSSF@|S6i)K=$AkNY&C>_F#;iW{JaOIM3U%O^0_0rA;Ify&_K2=! zZ%|fY8RYE@yF@1@*eil7*c+DY8aZ7a-UrVYpE+YGU9?X5kgMi}&&_+j!kLm;dMGF4 zgLn=jv4m`5)*h!u)z~Eugf9=-{`Mq zq&EgrC1h~8#5VXcBp4V0&J~2Uj7zqu0H25^j2eUXtPjZ4v7Fbdnx3{{aj%e{+<6X24YmSv75eW(xk&=D*0~UcTa|$}*f`M`Tv$ zIdi#pI~d;QOzhwwQW(7C;#l@lNM)Q5J&aL>y?rW!njc`1YxR zn`s8$;Bw1SnhZ(sRubWWz4waGt0Pjbu5^UW0x2q|VbQoA;l51mnY7YrFg07STbxjX zwzn1~tkP%!o73uC6jzQ05Fh762~#}*Zkm?kt?tzP=08W?2ri^nFTIo zDLgUK@&lNocqR!w#a@;aGNyRT{I|6bfz5P0Nl88wXH&>`GR6{MoRc@0k9n=gU@qYe zi=1Kt#$b4FHZU#NaBGTyHB`f9%Wa@RX z<&Y~z_>jp+Yl`C?vcZ*Urw-SqRocyJZ3Uo$kgbC?LtkWZu$|LqhYE4=spz>jH zwk)GeEgIRlI?v(T$>mBI;VQ#b35*+fOaVsrx@0QHgi`>mQaV-ziAmoA9B5W76tS7c z2zf#o-yhlXpgs~g)O|#0Qk!lo$M1m?-XD#>dlV~&A$w7HJW|T96iXY9O7E*Au#SV% z^UK6%z{^s6I0<}hzG{*xZ`?L1iE+1aE_CBm?Y6wbhdVCz!$3$=oJOhZU1SZOlZ|$W z=61BKHL=)F$E{?9x&k)4ZVxtixU^xAUN9*GfLvTrB_Q%E57`#UQ69P^7wR_F=0W8n z4Kjz1^A3W=6zBbL>ciTyVQq&&GRyUrRg5L(1uY#aW75*G!yP0*KAT~)rXt?vLL?Nv z6q3`_kt%6ZxZpAPZx#}ID7N{1upvW}&AH&v6y_8+yD# z4tt}zYy)J{)Vi1`@ju}xJD;eoMS=uBuh7)VIjr~M*r2t9U4NR_W*F>XvHFw4 zsv|ALwd3i)Xe?x=z!Q7+So5=AN|O_>a^fUEOw!=aK^mdT!@?(Z(SBz`*Mz~E*Pc^c z9vtm7Y}_C!NzWTTip|v!gefoG^sYUcLxw*oF z-eJ9^4o!O#I`X}X%Y_LJ9{%~Yxz;qRFJ;}C3S5`l1mn8w+k*vEI^)3HRl=fTffUC8 zfHK${&9ReetbHT!TiX$K-#i2&RFr3EmWVYF)Tn|jg0(9wiU}*@1V^{AjRG$jqNJYe zrJQf$yvndu0zkQWwE22gH0^GYXKHsKnx{$_mvUE`rivJoxcwGyh4J%skNJ)1acTpb zK_EULu2WsQbvWbH8u*myt`L(`QSXfKfAJ-Dc9_N! z^#zJaw27t0h-Y@@)D84HYl&8R!fU5G*;i298GtAOzB}&wd}2kTa>| z06yk%#6}n~=!S%*TZ4laa6)tO?Y@NuC#jD<*p*6X^(*G=$kZ89gKnt1*NI}m<#0Dj z_>PodgE95C@51ZK@dS)NMMwot=8^RY0|_}DBce;n3^y}LZlOB zbah%~McC1>Y~?6*OlJFxGS)$lQ*@Ergv^Cjeb7RGiJn4(a4SMR7V)^(7Q50pz8`G2 z4GdQdw498FD5t|k(7S?ms-0@!P%qCX6GbP)N8ROzI88D+s`wp6Ep5;OxD9T)jJOHz z#-W^+T8S|f(cU8P^I%7)KcohJ+ zj7U}7&u+G&T35)z3XjvS<>^tdm#4YI?b9yH#XB1#pA{G`^T>E*+fWxeoFEFyaI#mN zIHUbM!DZ}y1Gn&Kc(pK7@}y%R$&q~u-v>#fmc}y~ zSTB1=;0eqXWP>9RaC8zzLkRmeM}Gfq2vfYl-k&0PNIEZVJdp@k9ubBCz-uxPBr?>C z`|SiZ)-SG$IlEGIDlnBr%6u`Pu$q`FQv$623s;v$vGLFQF9QlZRCKve8}yu$Ngn^8HSS@BFnf7`Fa zi)-pn)<>lB^&v@s{v-RI5`GVy!O~;lendhXgqjO6?-pk{gol7qnL?klxWs&wetu+x zd4$g7AwVZs#9f^ENRp9Fc%_!d8*wd7%c{nPnDd#aD8R3ef;^O(Nvw+MDzOVlhZj*+ z6cx>GScw9%-fy<&`~Nnvw72B*ahbeC&XG||HC!~?H*9q&1goa0U; zQQR+SNI8QxR8Stc74RCjP_7GC_Ds02Jn>HMVK)lliHX?6a+oiwOZPP_Tw9)(q z2RZ{{0Cq=G&F5Uoe>`RNbX!HcrMWn_ zjaj47hTcUBFC9(OIN8_m4@a`1SKOB2NSk<0%5U?bbk3Km)7O}!L*?KG{aZgH{9fT~@$o&1*O>nVw z5?r>4o1yK{cu+h9g-_wDOli`HJG6RsGAr~99KfBW&q?tNp2 ze(v$>8mCU}c>eV1iAKvE@1Afy)o!<%7$=Q}=$dlqedeG`#&rb3ity9nb++$CWPEH&=9lN;Y zPW0*;Be4(Idy)WWzQ=VfeDC+e*C zSLv51+X5~r-8s_9(PMizOaq^}Q!`D{S3SIceBmX^XE=;)b1d-D*^ zyZmNhuXuo~64cW8p|H2TjH>MM1I94=CCavdOGuvZlx~bUeAsyThe>b1^#CD8dgRP+C3%6vySjeBlZ1?E%L0FS_rMM<3fzM@B zIFFIs{Cq~rt2VWe+hi(v4V<-M4&N~qzDgTQ=`#C8bDE!%s4h|-_+TSy_ydh`!Ol_A z-=)%bCpw-F`BHg!<)x*pL8P|)L^><)R34R5VEJ{23jID|@6T^!KIDUV)JLhSekd!m3M)T!r|gEe zR#GR8Zv^|g+>@1&*(b72QnqIVd>bjOlbtd6y)3wGcYWdH?UVQFRm$uZpAYgsd{?KN zPHVkdu$$bAa$z_5cC8=D+s5ZNE=XB}n4PWd*kH^uYDdp*6t@wbaU)L7E8u*e4?u=3 zQJox`=lGn+P4fWib=b)l?aVL#gWNv=$*(e3^yTp73}Z`$vkVnvFueV@|G(95SQNo& zINj{hEEO@B#nRX~tr12?$IrobyJ+{t%!77d9=qJSIw^=FIW zn{O7meB^#PBlqaB?djy=Md+kxXMX8AnPnYZxR8Y_;t-qCL44qw_=d�Xr7~bRu#d z>%*#TFpJqf>=i{P{nB>{HrI(-+G3n6ZurfR4buQOme1}+4Y;qH19FyhbBgPbK- z1N_=lh}w!%Ci0(MNJ`W|&+Q+}h?j#;a?6&p8De!+^&5S*65a|{h37!IW{}csPFVK@ z!@5MobRMbj+jXo=E<^m@%)dFWmzxJ#19XcJUyRK*w{Hjj_Z=nHgyJt!iYUICEy@o+ zA{N7$-_BD*Y=vIrWZ>tV0iqyQS6)}84MC{r;Jf2ZfUOwCBsCL!+(VYdZ*A89Y~fl) zE+~tO_Su?@EX1wgs)S2~9}%`lbHxB-lFgn1R&p;R-`OC!Aym<=z4nhh#Z~t~48fKR zgBX&;76bY3e~PDqVxTDKdSF-vcwmFN|dDMRRm z+#UN}nV5r!EA=ORlpXeo)JuY^5-P~r5?dcabKu`TY?Y7+Z5vv$-W4f2-j~2zY@Cl6 z0#_vfL(6ixhvKJH*sl^IO~GHtfXMs{QOuuXX6*bB$AdZ)uHZKX|0clP?%=UyI^YV| zjHH#x=mQcm0}|jZ53v8>IU;nV>aEtpxy)-bH*{W8qO%9vE_o-E_4Kq(gckZxwo{Wk z7h>^pvs;;ac^6b7=Wc+-6Emy_c8Zd%1fIoa8C`Xk_l3mHyA=!@LmC-5#rvN_2Ar9N zhrf0grqCh5r_ubks-$5qo{Z$SfUls1y; zC?jcxLH?S$VFS#*CK`0p_2H|3C*Mh-HtcN~LbgGk5$Zs9^O)M;K)@+r&Y(S(83ctA zI3cb;~fnyELU5UBxN&>^&+ksUFTOTzxZT=; z-r$Vp*5E%v0?{i9cYW&(jJV}(&M^VM*h{dt;D%mu$&mL^ncRQ{+*TY;_XVch3g7C4 zV?Ra_LNueL)6)vK1_3k)gl9=@=d9wURqBQUBkBT{Lz6NN(>c$#uGF5NhfyaLKQK;g z;aY(6t|^5Ow7%obh2AaWB+Rp%75!O0RgpU)mfyz5&4rrJiKD%=sqOUVD2+7;W1MhA z#I?raff*prx|)P0sig+m3WV+t~yNS$G%nM|gC*bgPA;d&7n zR=YKD5nl5m<@3T7njr|BFHdbQC(3rJURlZZ#snRr>DRy5K$Y{EA)c0HI_ti^ru zfrbPGu?xZ{g)IFUTmWx-J!%v;r;UKYMT?7jjZ!@m%YON$yh((NYw#HEI_g9wJ8Z2^ z`7;irn;2A)!AsN=SLh#~9Mf!TvuDFvZ-!3Nw6RIGc6@^>$_?#^CY(R6h2fOnyIMds z956~kcI*q8dI)hK?48V${$3z#7p9Uo*IO4G#oEyI#9?EJ?6(!L+w%U%+h>ygEIp}( z7vu}#WQoH2#~AyUPb zVQVrmr99J9vrWRCG4=K5%XScQOZ~)za8eRkWFrn+1jMMn03Vi7Uve$GQ=@d>!`*;` z88UeV{wm$OgkAsbAZ>fd6D+ge`btdueM}O{;lpw8S$zt9uWns(O80IDG zbuVF?%zOGJ*V_`viPy+EqtriEJYMoyJ9vD?F%slKfWzz&M|w%lfg@1&W$nz}fGj;D zOJ>70`G;BP5)ez(ZB9u-=JU3$7Wd&K-RAdOTyf zURK(|2T{Z0=*s=uN|u+5SV=1~ZMZCof%w;fdCI3SPgJL@tw8*jU0Ee=4Oej)ms+;k zj{)MGpB=Kb%*N;{qrvZywn-6%@asTW{&vdb3>(p_2r6*?g2ucOB6GMZp#taKYhK5h znS2S;eo+@f*(PvrKyq&fDSLHo4LQ z$sa+5!xvpFZ%jH&_I1jnhr%6h{xO#7n1Kx4gsh>q&8gbSoS)sGBzi!Gmu~p$M34Bx z9xF7}*;b+9+d*jgGUa#Y^ecQIH07LqBfjostZOkhQsD51OXw7658QyPv+PjGOE?ug zrA6@J<58ip^l`AJsH(~p? z!xtFU;~1|aYxUD&6X*r!p5;V;toHiYk0E~kxp=6A%$CyCe1Z!%brfNyQ+(2N^&k6c)r)0XmnehFE^X7 z#nbkVi!`0QkknrCDv&b)o!jAc5^{=~^;YzxwM zrC#f`zfR+1v3|O{Dmr11PFx4>6{lgZsC+wFwn#TbwlVVu8^Pb!5B;a{r2QL+jtV+a znI}t+Um#-Aa-sj0PRiJL5C5MR-qJ}G zfAKo`t2TE9o4y65)(tI$;Yv)^)=%iccCQ*=aQ&MAZ_C%6Jd)_-@HWy7b2Z&c|7}j& z9y0qzZ||tG-(NzWY~MKV-9RtMLToO*ed0@V)TT)7!_SlNPIP|mVmQCiw;6VgY|nT% zpVtUmPPTjeycYg#Zw|ar1%vfT&3<(j-SIro{89MvfZMj$YhYY{=7xDTl8&KlPa0s&*v^m z80F|ZpM?}(nSni{?%sFJz3Q=GSBd!PP3##r!kC&}Y91Xwr(dkST#k`5RnyOG^DNuS zImBXdUADWvG+cI}O4$;*jnL5fqh7DqU>P)y-4L5#X;!_T96l+q_GxuN;jFl^f`L&s zKM84R7Uop>`IS>sZ=~I@(VJZwA0Iz=@U?}CKE>|xisxUSP7tVkGU5_(*|(~cEwP18 zE?%s^3in*|?4~*yQx{k#OV`deKTz9RCu0iV)yQ?yJUX^P4Ymi^Wu7~C^yuIGX4!rh zCt&0HwqM?^0a!&R{qq+{CvTu;{2l&F!xlQJy?T*!((j*Z_BYo_zyE&N%Poz~)_-d~ zzA!e{$G>4ZVRx*L?`q`s!K9P^8(HGO2C#Xw+1&A~!{@H6Kf9srX$94}>->d&|BZ~{ z^qMMVOKhzZKX)x{s*|PJG1dus{`$YyTk3@7u3#t1;bX^Um$rE<`CE7kZ{g1jt`wqm zIYXS{7C#?Rgu_L)LIqwXRq`B;tA4mjd9yL};YU{NrcB%bSP&O;F}ZhOH{YeeWUk={ zDZ>;K3q8bo#2LYt>4W)3UD*!Juo4rtNGU#0P#)H5LgoKqOAeC@xazlxA;G1!vy@$i z;nV`q0#hXdwUl?9+A2MVDOS;DzBhzoo43{e!rCY^Ajsikiwh|6Z?vQ;mbv$jw^f5T z0H1%h6QPWO(s4=vDqgC5c|7E{jc;h2gc8_vC-N??k&m?*YZ2bY(5FU-!}yggz)DOB zh4x3`e*wkN*o~F6s>=N)p*-p8FtHAl#eA+pEWwEgJ!~GaZEQLyqA4|G1P>qg4i{7K zdxT62ts7`4^(Uk9k{tPrq^o_*XSU|!DsWZ8>w*~`f+q_MKq_bo*FhLxLnr-k$lZ2B z1m3OEgnhW$Z-n<9ekH_LW#seYQCE&BKt`D@k~kgH;}35*#bvr3thH6cs2;ovk~7U& z(xLnyW#nRfsY;2q<+KwTCtMaV&<9mk;*e4U!ffJ&5oSaomnw|vm=Fl|CD)_eN;83I zT9h{edXg8zFH+$e&D*E^xie`3ig5~76^SBOUD+9N6lbvQlT(*9RMD3i5bx*GnUS?A$5Hx}_n|9pk_YZJvhO6Do?P$S*~;*Ya(CC&C> zy&KXa>?*zh5q~IC;QdkXSP@Gb{vmJP(H3kcf~f`nLT|Wr#@Azr^ezDdeJ7y!)c`Ty z*{C370p1~6%HcAff#1Ss6)d_;7Nf3xmYq#A+9sShe)p`WMLzGy6sUrn!X4GOb)zO% zP_3}G6~Z=Q?374mS;FiuVmWwX>s@hdft7ucvEVlF8;NDVN8-mK=pm`eE(Bh;aprrj z_atD5JWRpwYhwz_x&rusG5ql!C4^@ThmUv$TdiZ!hfGbG1X#tN)he&P6LTuV5O z=Rgxv5{LD7WSk0bsbW^`4=iPrv}C<2eMb6%Js?!u^wsjM2w3(xn5NGww(Qs%++}2y z2!)%iRFmy~IX?qxs6paq5cJ(6Q}9J=bTQNT8I@v^HQ)VI^kYqEJOXE_{y?k@kqdN$ zLJvung_gbiHS)(vI846GAFfH3U5FCDi6%KZ&5Pq34gYtZBAp_nFILNVIm(rR9xlc& zQBE90!~;U^Cseq#%pPWpZ03l{n)0v(KbPeR(H()BWe~hP`hZfcw5%3{w&U?a#)S+5 zY?UyGN-Ft6L?OcZ2)j{c{x=*e0Ztt5@j~OQLY=cGXaD^ZVZpkw1T&?5jNod9JTX+j^;Vry{x9}F;!drL?Z{aPxg}3k){_;cKwftpA z>7c-2=%jy=zbLA{GWx5AS1zkk-c%$rZ)CIlC7}M%1n;C6x$n)vpI00Hn!z%?Me1t!QCoWg!=+6xBlz5e( zaQpOaRdPnrz&Sx2j-m-8bpf5*^nCL$^M~_)o)ufqLb+P&Jp93bDtM_?F${d z!0{b>*t<+WUteA)H-5nJ*0{(9w{rx)P=xgAi$Bj!{OciHa2@g?7ZuIuQIh`mWnShH zSMpZ+2+}%c0`hZ$@B>VC&QIdq|4Q8WL8%MQ4?>%8t`8!@IY8n3AB157$#l5?^5=Pz z6V6nUbg+~Jo0{NN4h9_DAJZK3>Al&b7nu?hyVvir&wez;lpZiBD;C6V>S z67uZeixmdYX1i!5#nEz-MRuUq;Uz!Pjyx=vJY1I!lw))rHGCJSLDm zoCT*f`LD=~lHgP^ne~^#U@mYAHIJ)hK0#GloHFI_hYrQz2)mfjUkDhp3fln!BvrQ8 zzEI0R@t%lzV(r7RdQXT>$37C$s5f+zuVtyF%_u1R73oDtPh<@Myx#+VlE#+uE2cM@ zFGE3LRow}OQ#0h%+!8a)JEJ~cpp^xe4K4O%U$iY?r4*_ZZpWW16NcgvYCMQ?4Rd7e zumxfcw^77!y#6W{cMAdBe_bIs2;K=Ga>Y;B#q@quu2e^7Ku+OuqtI6hoNn)(d7w~} z*8^AmsD4(CEf5P~X|Bo0Sn36g9u(oE#2>;o~bE>60BFiJjg&j1Dp}`2DG-gkwJTB93xuJw9 zWniU5?6?V=KW4<5Zi(9Oq%(P0J9~t=*EnmW;M5#I$i$gGk;3|RYr|wKxkM<% zK!nsv1I{|eY@AHyiM3acl)#zMn4${dYx0vgtA|K9w+q=ArLIZjHiN^2q?GFXDe!}! z2%NJ}ijcFx_`(9`jdO;-zR4s&(}W9dmdnariIKk?8N?a z=tjjY<8bFf*l|=S*El1mFlZ;tdA`&5ERYT3h`);{h{dnDOIW(PHouP%Dl&*2_m`{w zF0PIu{4FBR4lxSF0hu_h>nik>;!IEzjq97# z1FTIxvx#*-no^_@E@ts5cBGMs*VK%+khjpaV=pKgUi7Qa_;I<0do_dSH1=SWVD~xi z!KJz`2!})5jKUXzu>06VHk7$BoOexu77%3OEcuKjpOqC$%4-zGH)8>)?0An9Y#`hY zc@pR@j!epu$rkW%Q?=W-kZ$f*xbYP^p)m}eARA}8)F;qSQ0IqhfI`rb0AI%*FV;U#Upf@1YMu7@CZfZ0ww&(#e=s7~6=diC6 z&(pfAO)1-M$`y{PQSF3_n*36iYfq~PNx_#gT*(P2&R8@u6jmMZ@|D7Ed9l!5Gqm`j z8snq49FJQUxlOtMI2Hk7Kt?kaMj2OX-bw*eh!q)w;9?tdMsYH;{xz%HQx5kaK_s>l z)ZeKlu06_wQnUaT(W%Iay(-^pE$3X~ohB*~#d9hzl|2p~xvh1SOp4T>V;YIX6fFy* zQTq<$W6|Ma*&9nWWUs&D|0JR~anN<+YRs!>8%6$&|DV10fsX7b??mfXU-ew|$fGN{ zXFUF!k`RMz2rJX(0WXtGNyua2^=@RxZCEEcl8NJ(Y)&2yX2)+&Ua0PA&-BO!G-hlV z7L4p=Vp}9Jn`aV&*+pOM@5C@Wd&nIl&{$caZfgv7;B>d_3{l2g2-rKE~MuVN* zeS7?q`c~Cf|GxUZ`giZGx`npiP+SK%w2BXkNj-{TGkAD3eSS0kyn24f=1U24sYOXS zs*>otFsBSpAq>mFDWCrNA`*11Gb$M|e2^6&K87+E3L)a#VmPL^Z^;gA--`GBL@loxUUJ~&Ov z;>RuY;}7x;s2$Wz&1Q2G7d8$HSnvwGOgJP+OePL@V+g;dF|EJkX^D$D68gg?j}ieE z7l#X?XIuvb%(91TvqKwU!}qVII3O#j>l!SKav2#drqSPI%5x7K06wU8Q?;9rNt;HS zlEBmfK}K4AT2Z}J<&}zRC3lhpFd|SDv?xBpu{6urOv{Cj;vprS2uh#T-}QybfJ~^C z>J&YrA3X8Ja6wdxQx4&X@9U`9jH*!Gxk|D^>vFhb z)_4-rOnHQEk#+EGBYKp3U$hlTR3aNmLbB?H>oFOLALbK2r?3e>hvY(;2dI?S85?3@ zlgh^-7%m_g#*iMkG!FmK5Zzb6xtqlCwlQ_FR=d&cNk}%a4^m#$3OT61F>d#z&52Cd zibo=2tegK+D0ZHD037F;J(LhYkwa)_RjToN#-Xd2LlbcL z#^)p|yZ@nPdBY;)y?poOxlQs{Gdm;4%v~qtc5GmYLuv=}l)-tG>!|XJI)6*ri(32AWoqMOusUPaXpvox80}2+{!gVYrD|rAyfP8d8U?*WSBnT~=cGrpv48oN*eFKFDMIkD_~D|= z_1D}S^ITVXek?0djd8`LoXUn$f-Msj2l5ES;xIoibT4(yyAB1h$k(viLp{_XIl9`U zZ0L4Qcq?*@9!`g<1t2?~mPI->@yhN;_K>W#Z(O@mH9o83nK=b+{Cp2nX=c*l0y%Oj z^Ye~(rll83%Yhm8!sGi7+`P@^G3a zG9g4EMY_g+hWnEkLyyohICeK8!zPQwdx+c9aeFKf)9rs>LOZs5?4N)k8XC|xF6m=bej&dJ^P@bZo_ z4GJ;xbfuJL0*90|(!7*sWJ?X?= zOND(eO;{>!EV<%lb?H&Hz3EeG@Y~sm5l9cj98LDQ?t&Pz2QD0GyorRyCuXnT^Y-|cm6YXD ztY1K@!S|17I!co(OsEFc!8nFm8h1T*yPh1KNZ#<&Uw;2dGM}d$Ci{XQw7Gibb z-%%bqeAltoQdB-vsxGyU9aP&6f9!($FKHfZ(!6tr+kVOY_a8dA4L2*ylN>FhB9cAn zO6U%BG8?7j7>8Fs_Th`FT9@_G6`x#cw+>SgsGYb*)Q}nyoo-f+{miAy z^Ij*^bSo2Os%H&dadhL~dcY)Amy{tZ+$@!MS1((ts2#}mT~gs3iMeGx_zQzx&qL z2Gt);+`VMx2g`9~YAP8l@1SBfxqQr(;?~Ukg!2FLvD+(Se=_#!yRLYwo$T7t*2j)j z=$^6BfI#X0t}5xMtQ&X##;sp{{!;Y^A9&v-e>D3FmF%pLPAJ*;@7l8?x$nr`2U7~C z%IGYR8H$aPMgQXWR*&u2)x4`wJ=Sa-K78=rrDnCI4j;Pzvmd#?b@JsQ2ViCO?T)p^no7|{6vwYy(rQQa+Ml}RH-7ck-t(*f z(p~!gu@(17=|fLd7JtxwW%SWQ$<;Ty%P;us>B^-?|G}$i7Qxeq+6mRDSH{Pmc;fi+ zj#^z^t%uJP-%zKvcgAJy^CkWqbZu&Wgzh><9xpwuP8I#}oqM*_YqeXB-*{qpZ+&m^ zGsh!CLnHX|GsP_B)Eom-Q`9+@Mn)cwUcm(a9p!-+qR+ESrRPk|UtEk*#Fjp&Jb=4v z!gz&0)vlt;=g}c=DXxcv&A%n>A)kM4(#)zk?M!X&@muQmt*+LNFMObW-@;1mxH@s- z#KH%hX-?yhq`APc>YX*x$ryB^I`w+cNv&2VS&p1pC(n0kH8otHS{T_!HLWr`+kKWu zJ$!bXbaMQb6E~iEqW(muQ(q1KBm4HTP6h^qpI!{?+eh+wnsjpIFEPREWNPa2@32dy z+xN|1oPYbe8(WfVt`qri{y9InumA}Z!<+$|>SUUyyEd&o!8$q7sW1FWXYay7r{1~o z#v2zt;NL*0pc6$pS$!PsWOY?^B5Br2ThqzH^TYL8XSlv^;W^UD!oqvY2D)mKlR z^g7vF)X8)E_C1F$xj*`7f1SLrZy(X0er{pm%im^#*U7$pKluZ8sY{OTTex^5*>6Pe z!V53(cm36YiZtmj|Dg2zOQ91xj~-!soRl)yoQ|W;@bOzZd+RrLR#_)2oz>2br%o;W zN*slDBH#X3Cr*8Sb!3!vB7K*nX}FzGdS}2wX}De=?$q|pKj-_d?(+a}9t2G2#P?lK z6#K5{hK8UMiuwHWIW@-%Q&Xgq(sPx{kxwuo>$}eRGP~6IzcsaR@yTMG0)8Z&eEvJo z$=2d}Y@!oFlfQ1LJEvGD_1Z1mcP-Rz>D)LxyznbFn_e^GVB)MB#qS5gIX+<`E}#D^ zo{{7I88@}6pRUYSo}zHjAI`#IGsFvYG6&Tw@Pc6_g{c--Li|54aaVlA8_o0MHN3lK zRrO)wZr9C<$E#hSn^^CndDoL-=W~0ycm!`Gi!Ws70(k^?FeyBL2~1=l@sYNee9liO z3&y+)Li#@Z49*9F`zAK^et$ktO7#3=%5TIoj})Kg+%u!5x=bot+f1m@TjgAz*_-Gd zhcc?(PPY6K2vXovvQO_7wEPxM)sn|cI~>AAKj|iJG^;ocAk&8 zZ=T}2SDLOZAH@?JpFhQK+(F_j#OHWAoV|00RGa-|&f#pH+gk0ZNj{?|RsyVr#72M&^2@2;0-KHGNj^g3a7?knC_?@wwHPg1o7F z@*#KojfR>9@%F|^;>n*61piDY$ozJ-cF{H4)SlbbGr2jS_KHB* zxu2n7W#RQa<0tQ{9e?x}$X?HNlAqDi54BFWPM&*C%z+oU&j*H1fA?MQ@%Cahb#hY1xxv<$8q-m?PH23+Ma&SsKUUN@wEOqcP878h zMRN|clat45_o*kuLqVP!#viWB*-*-dDLpMRq1zVRLlDk85^uBD_%PkrK=vEaFsKlz7m{%Iek8ym=eBl?+i^5%CvI`YB` zdH9nj{k-&K|8^33FMjRQO5$#vgm#kaL>q+>H|%3f`CTlHz4|f>Gwf@;m;EvE;BbY# zg8j{&{fBDA?p!@X&v+grmt*%krCN z7u!WPTXqukmDU{G@?Zy$@P)mCea)`@hbS`kDYg~T>l?mk?q@S*x4t`=>%%eqk>IBL zlRJYw#KEIjaVS>$@{Ql_?r6n=zQtcPT*wMXS>KR0)-dzX-I#Q8j%Cf z%WUSda*G_{g^kIm8SomW2Yrg4Bj=z`_uGvSpeMbs79m{yk|`C^mKB9^JIamAiSNe9 zcS1(lg7G4DV2-c_*j~bh=&y%DSI`UFOYp+coYp!C^@Gh8O22qyx%<0*S)s<)G`Lhy zLWXGBTTEmn{5nVsm#=sOqHew&F4*hv(g3ePz2se&M-JPUfNsGdlY91 zUgv(G;CL}$j{4M&^(`du-tAFr05+qQRmo(2hJUuZzz&%jPECT5e;Q+XmaSUU$&`L0 zq+M(AZkm@kMeM?#iu~8S`2*=z$wEJ>yV11~FS@YsLtXam!r_7_mPtvJDtiQeq1|u* zg|GjMG(fj(;wmPuVDJ%;338BpIn4Rr3zGD_g|yEM$;}35Y*R@)g;$))k_}%(BrmJj zJdI%SJq-3Sh;o&1z{~8Y(&=a*W=ThBYGZ}HB>bW#dIl3joJ6)0f#)L|Tk;s;Opsn0 zM;gmm79*DbtQv6pIX`MTi!>IC=DhHzej0JbQ8c66Oxfy#|;%1$*X~>9Rr-TNq<+?deMRJe~(Jy)>`?0+TTuR0|#tJar zbV^6sQ7xEMc;-v3c}8TfdHsHI)gHrOLz7XgEU}c??xF~5rz34CnFph>Swjk0wg_Mx z-HM>hc9{#lID?Q`ZSvq;UBrT;zliQu1|%00DDlcb7$0^qcXL{7YQzONXMr^A*oy26 zl{dFq719qYE?vPpFe(X!k5RY;%C~aUi?8Zj_rKQ%A~?>=IxMiX)v4TvqBWnK~RUhOY`WOl&$u+knVg9FnWIN@jRH3ZH@m-sv8Y!dumNr8AVp#PV(z z-#Kt)JT~G6tBRNIkUx4mDywVrf-f%os98Vn;2IgMoSg)T#O_Jfg6x-9LQ5P%0CT;( zf^S!Ty_rKwISekT3}TcMHpC9z<5On8jSz&tWuRxYu($$|UoR+hYh9Qugu*smL?zjC z0iCZ@+AGM06O2535(m_%=Nk$Gq))Y zjBh81 z1n8J!LWsNlL{?f5CJQWD%M;vC7K@oh4;J~FpnTY6PjQp$gvN{w4ftBi958~cyL7V& zY-Z$XSZrSxOU%M3@HHzrrcxl~`%I(Iwg#x3P`~Q9=uAhevTX6eVIER$zDkzrKy|-U zk#B%pH}p7FzRPILT+x?FrrPlfIUS*bHYre*2MY?ThMX+lBVvLb+peir&{d*quOw~u zTHi-uO?W7eUJ)aL39=InQ93JZS@Cidf0zzM@S*66oJHkKqRY^*yN-`DV!K#jHf7uEfqdIi6&f9hR7uRz=A*GKyh%t z>zd^EnK$8HARQ;sR1Aq&&1u|n4EeIh%i2x2FGdZ8;?AatS)_E$QM!AE+G7p`&Dy5F zhncrD>J1r$=e`Rx3so)h76h{Q)=tV0`l5f4kM>&gMT~HnheU!58Bbj4T%`^+vr~MJq8gj-HpgB1=&E;49RfI?5j&a(Lz=k#RoC7d$*6OuC)}ghW(ONhF$bkih0}a$Q#1?o!2+ z1}_(Zo)H`8(cQxMZ4!jUiPA4>ySU8a=OjYbR8bK?+-wV6pdwnG3|UG#22HDNmMU(n ziK1E&zN(q1GR+!|+$vCwPN=V_;NCNhshMayX{dW?K1_2sN({9zo+O#m5H?bk-BlA= zcCBPIDdE!{zJxk)Y3y`6t4jjn)8S(jQmLqkH&9CPV6?>0sY|>yz;!!4oHwH;cF~Mj zq2RaOzb^?(n9l}|ul@^FJkAP*5XV?v!?4ssK#?L)vGUhS!Gtw*CJMom@`Sf@d*@Eh zq3V+0zHjDtr7W4`N}`NJniW&3nwSNbT$!YapJ6E8+=cyL={TYrewHAWNN$6a8Z(|` zSiHE=zb4M^`LN-v3wnmttlo?$ku(bNP|;#2^B}w|6N7(ddW)D=zCh}#GRFj+`2FKx z;}9DoWVa4hjASOWkwBngc3bVYM51nYA!pVGH(QL52e}9QhBD(sPOrA`pVw%AO06Lj z>Bz9)oO&JPy@VE-9#J#M=@r;S%zLJyS?aE-oNn}HoCS$DAJkk-c3VTqUSq7XGo-&* z4GyXy5>kX^z6~<$c0qug1-qN zHbb8bGTKF7O}Y<%&WLW@wzeC*rQe5I@- z66Z(pFo|vk#=%!gGce8b)^G=gw9+-$6hCEAm<40?Kim=~hct*d8!s@r=XaAEAl$bW zAtH)7zCux5?zb6ygUhk|13hx;BQ@7c=mzGaB%+rJ?L_;Y+UdMCd4TSaol|$VY3{w! zdh*$J(=}Fv0c?$#obue@5v0e3AM|NvlwKHzt5mmspqXJ+2ETxH^Ea#333n5$Et4#d zG}JLphs1BdwDY4%2;~eL*=M(v*&WYd9&mSDnJxeJDMy`Ig{I@PBMP@m<}K=2GJ)sE zmFp>nc9R*$7Y$VgVr(QtOVVmINiHhI>MkmnQ&LA^Dh-`bDN3y=Op|pBEcpOHRf@Qc z0xidZ+(&AG)DXkP{Hz5Jr9!38={@^=qiX3JUe7|kudc)?c^JZ$9NCP zJDYd$l`sA}^NgC@wymvJ@O?O{^K|pg>L`;M2JRf%rDkTQ=q3WULv;6WrLpSDNZk-6 zx-v9dvDNuD-3ZYrf3s>XmnS*J)EPT#C|yDWZXM zcjGrF9NW2|Z8|kV{jhJO70$GZVnRCJY>GpUW<1Qyo zn(A7FJ7mUUwbpRjBFs&bDxFp8nX#)YI-0z4v|gzgJ*KYzl?!(K>i*Z>aQ*k+S2_KA zpZnWqPA@He=BZb^XKSkcyUUYz{O#$F?7002bM)ED?N?OPuGPt~U+k_+?!SNAwnK;R zsvfIEak+8cg_m6N{tq5{Kb3=SIWa@waMDgn6#nCnRn*~jiEf@8y!~dw=-%cM^%rW} zz|zvOa^wb>&Vu9UD(J+|JEMl^r1AQtrN{Pll?dz9bvg04$uw$nF+(+N{wf+D4Z$AGkOU)0z^|EKK`e>s5>I-B4`G5aE?oS@8 zCP#N}zx@i8?E3g5Z%`zB?EXu3+=k=AlC+&V!;}zf?J0PHdU#9rwqD zdV=V1G6K`2lO3Y;~+erv~<)U}nyQFmzdp*!7L<52TIj9q!>Q0KClzy6KM^sBG@ z*6N)HIVdnR zJ2VS3`aJI^RKvs35yeZ={d(mLui|Tcc=imFvKNc$mA#Y~i|7>tkM`0$He5qn#DRC! zPRd&0snRJ@6IPu!nCJdk2}u`wzt(t6jMF=?<5^4(83O`f0;^0(Z~Aorl9S zpUfN$@q&M!^muP!9*^mi?gfk99_Mkp(Yv29N0xSJe3tz=9lsxuc@o~!QW7iTU-mur z@=6)wzONeG6#qjePQLIKGxDanq4esvn9B$8IcOD3V7H2U_cx|~uiY;w_h)42RHa{p zd9#vzjknw7pHs3Pj&&0D@L}&De}a^zF)B1es#5s5h%DW1?RZV_)Mk zo8KC@=u<53$Wi)_oSHo_UeVX>b8ufn{n&7ANUi_2L+Sb9Z0{HlJuvV>(cK5W-|8M7 z>owU&AMeCiv~>*QBM8Gq9=5UWHwAiz&H7JDw975wGw27W=Idv*U!Lcjo%%^kN9nJ_ zLoy8kwN)4{!Cz~PXYKgpLxdSwt@hl=tmN@dd_UlFjMugC%C@)ebDhrXUyrecbaL{{ zI@$h-E$gI9_QSHLTHXE8Gj8qd1`U3^bw9)K&lep1aR!}qdWVS~oost(-+cJw$<~nT zqywE`r(_4o)_5*zW1}tiU_|ZIUf=ma^gYqZ$VuK6_n!K@ox1#T#2a6D=)3!r=;W3< z>7=9A>EwkMFpbXfv)}9gt$_l3X;!;RHQbSJ8~o1aFhAHjIy5sUofOha{6y34>V*T*(q1xy=oeT_gcS6^GXMJ1hLC{H8ywG>;dBfTE zU3Jv!f*wmdbNdE3qfXFwZLE{){%UIBZ2GQxC)bIBPN?rfn+ScE(P$||`2h_{=(`ZM zzV-C~$H!ZKr|BcYiqs7H_kv4_xa;m~jF3;kO}-<#hJ zASq<~5jTSClh-r71VL16IGk=V=DJjRDa$)~&E5Zq@FhEwtk%Qy68a;2dOT|gCRj4J z+qju*wvxy75&}#w0Wj-QI_GbC2xo-rCG>$)*bU}`8eF=Um_lb07hJLb(7IEIgnlsxTm?#Zca>Ul$FpqjZlu}9+ujk= zW8PE!gFK}BWAc2uH;=PJF|&=+;ZS|~VtCel0EdgLJC4N=Uh?$ z#3%UueinIH&Ai1(sgThyo)@xj{*m(>rk7B_x;~o;G5;GcBZbN)OZ$uAq&Q4A!X4zy zbQYl`lT7Nskz;T8Sp-X1@@}^a5&N~g0>$OlqCM>P;gHr4FWHw8Y`O?{-;UENNd-UH z*MU==@1&I@iN(3Za!uI>&CT7s0-FY9mHM z^x;3T+!9g1I3t?O#&yVgGbb;O+1=Q@wc^Cx-N;QA5{y{N-DZ9vWKL0@uVNb3Uu}V7 zE|gS1aJ%y-{X)X6fc2MUfNrD*-2`4#E9EZ0beTBphiyq{?ADuXwT4*_856Hgf*3n( z6cWMdMAUVgNgu}t&b36!v{0xg+i?h%gr0@)Uo9A+VP+&mvKVqwYx7VF46vP4t-&)q z7c)=eO$ri$YJ2EHvE2QFeWCGE{{*2dGnht(YS1@>91G`vZ56hU3kBgnF9YX4r#fOW z03#5GOHonS_7)Bnc{+2PVGcsr9i=y6@f|4*dlf!U<%y=ERJErmFqYjQeUTg#la~U5 zlLP)@R73UvNjPJtRceqdH1;N!32pHeG({XY=9J^G@Xdi%DY-?EmEAGmF+!4AQ|k)F)4i+;=q)8mB$l!m+{WYKxY{GB}rQxMMiQ0 zLuVHctl#cUy8N5oFA&a%0;fGSn_Oc!6{> z&f+sGWSx{gV!S7xm+>-Q#>;paFXLsrjF<5;UdGFK8872yyo{IeGXCd4#VS0nls5#0 z=a!y+RL`)FKjR}lH#7gC6?2;1pAvdF1Eg>k$klJ*^sly@_()|YDyH)(iLXW^|5$6# z5l;Lm+)yFCLjK-Vs`Md#R$n+Hg;VH*?3q3u7e=9s@dt7KNEGcdVpf&##CbY4ueNX- zU$#H<=auB=pRj-6sX*s&@lo-oeC6B|`J^9})tknji(=SQ@tGcu47W#|uzNZ`gI#Hu zMKW+!2a~__&?LTe>b~@lJO_oF!W|4}eE2g!*mTO_ERaQ{<4%B{sF{cGC=~Gw(kY$f z^ql*G&%fQ^_z1@)g_~7*x*V^|RO(#Yvasf7q_9sPIB&{XE8#qoXwIKMBIlqeHAwWt z=b4I$fZ4exe=6stI3FMBcv-M4i|3`>3gc2Ae^6wp)Sl#IkcRe_D zSu0$~sF>$P-zYddHs`57x&&E(#>U2O!P_pEnvQ!YNB|!=&C1w=9=h#zZUM5_bt9x% zOW7)nvj9+E!GwG$To7ePT9Pyx676oiuw0qNeb%yYbZAzo3}}|BHBW%-((#uz?je&D*p?(9soyD-2he zpA1XzL9EyKmXmq+IJEPY4FtX8n7mpxo7ABI*GphXykhbRh)(Q0e)m>3$1Kt{d@V48 z5#E#hnj2-+oTQ1!N!Zfm{)~3`^N}d__mNNK) z@{QHP*%#}Yp(r5r%NbHmh#l4`SxBYvjjfbJau~$GxB)-wA~kJOHK0P*4I!{M?0gll z*du(tj9FO3cbljN*=eihnTHYf!In&0U^DGznM01N7QS)It=3WK8P1x1DOSPY=mMi= zv~}rjt!8cFCMF|Ex2+BLu|Skd|sW8LE=TE(5ka7Nr(vZRG*vp1j4dXSC3eVJZ;~CBvNg( z^<}Wm`uSWUeG&Z(uMLjyL3*qN#8_eH$;orcT2q>28B~euc-F zQ6sOAE zZU|d+gm5rX_mW9B&w5Jrvi04Uq8qtJF&^&5s7kicdHb$A#zO2XUCI(LP{n-8-`L>V zPJV8}jyeuW4GT3Zc12FK8nZp~gcV%Cmr$wwHEp5gAT;|FMh23jPc*gh8XT6!h$`v| zc4=7gOr#Mz4%mZ`mKSU2dY$T#8&gcM5VZ6UGvZ?G{_&nXY?rGap%<=jRT+2AQ*0cB zBTo87##`_U2r`309Nehx2olBIgjPzH!=!2|RTCT@T4Hf#Kn%*P*@Sh@XABNd zr?h367%XUoZ5;L6As{$U95obDmrm@h%t#EUnuyU`#mTtS&LVi?oQ&)S0SYz6C5a2= zwNb_r{VeAqp}6Km28-1Fh;MWjEv>^Q?BJ@s0(a5HVtRuKrntN5D#jK6;IEU zl;G(DL=M?jv`VN@x{@R@{3Hp6M4-Svra7p&#Nxzu1TAxjR4p=T9G7YMv6K8D4L-yH zV=?xugksn%)GYmC-oYX%!;Ki)QW*4_7_AiA$tp#|=X?}vz%CDk8pP=Oy^3e-i2Kuk2{PsvGfRv4wkX+j6pf5fLE37^OVDfGaI;fgd56QN&p+(XO@ zNz&#>l-~Sorb>K!$bv>SPAyM!mIF-Z;xY#*Kk#7!S&hZ_u`Q)Vf3b~uyrSRL6G%dH z_BYEHgcVk-TDDNMrjQt^n#Fe=@l29pI41?srcKwj;Y_@YHL2dXAqxX!sLYK2!iCl_|_v~ z)&mOj$Zaeo#gPoll1jDWc*(C;Ul78>xErN>J}znFw}N9|jGCrNih0;j(J7S+uw{rm zrO(J2GvwmMnT=MvB%Q7veZWx2`DK!tTc&8Kw%V1Di|5DUw`g_bnVrsvl6Vh&AGudzbfAt@&-gRe0r(e2nI1Gf$hMSd@sqKcrK>IxjA(VA(hf2Zyu zo`*0B!pk&x{NOQU3{4oj{ghM|67B>N6WLncf`#NEzN z;lUYdfascfeBULi8HXBYXh?{$x*P&50K&()$}Nl)R4M0@n}uEC%5kkTbh(f2KalUp zqMDQOL*3*PVC|=o9RN($o%q>p)zV=V&03?(t=$8x?{<%rP-DCBmQ7zN@_04sI= z^3iHt4a`qH>#8)7#}xQjI%mh0$gl0F7cex{SV0eRj*V<%jR!Kr@o5cyj8_53jJn{yQ`QALqm;8;}y=rSCL(6bd4fYdyuos zn#MC=9REJVJy6bljFM60I3op1d2zoV2tbSc*0~4R?cxEdGhEY+5J+Ko8z3$Pfobdt zn};CPla8xF`AIceiYt;;nR+;~_;gv{eE_;v<-(WCoy&b0=b_qz7#QCut#w)t@cU!= zwik?bCE%2_wpa`}J<_Ax(XosiDw(GTQ}0%jdNRU?@_2NNZ%8UMjZbHiHL4!gjgac` zWqZ>TPf8-4lZ@=XWU)@LrBg;Q?V0lVI>dlH+2%+gP9-PmTiXR$WFCl&eq^aB>P%%6w zlquhu2S}%va6Lzd(PB43B!M%`y~Gxv5egBs@6&b6$C|OLMJ2~%$i)0uqlj@886<6F z2Tb<#=Izv-OgTM3Nm`*;Z^DYbT^?e3~mGi7f4Wg!E}|xPR0wvH+FO1{cc=L{{552uIi%tW2xr{nVGn5}Ly%G;B-D3I0Odf{E%iNRVTPP+I=g3bjMtA^aW(vfOV0%mf_Fu6S3_C4fBY$hk zb0CI>I*3Z8PNy*gjX0>);>m&WueEqo(4{5{U6?!&r>SNGiKXZ*D`~Wd6R;w~F+(Om zrjc&V%=lcK{9yEgpAJe=A;DZFfFF$^-ThpXt8BV&?A4GgvlpX_&%2mcJr1PN)? zaK)$q57z;ra)*m8kh|d!sx)8%I}VxwZGGYl%J}?#obx9UxJT-bu95>`-VqW@t27Bl z=ha=;&IW$|l5hdgbY1ZAmStSB)cNV83^yjwR4xa!4za5sOQ2YgP+XMVsor@@D&O!x z)G+tt>o^s1&!oL4qk?aZn06G5qUY^hEn;9TdF2@0 zzL)R##@p16WoB+*htf2iqS8?^X+!#4iH!sm&mYLZIY&xp_(cuA)q=MJfr4Ln|Fhfm zW7n!>erv#fTZiLo8aKJv$LObVjE9hO6N1ZJG({#+;DZg3NXxNI$_*db18gMa3h5#( zWA>cJi*d4;8XMzI`PO^XSkkIiXh=CfM)X{H=)2;W=1nO#E-4SZKVLz=EoYkN(19_B zA>ts-^Tt?stuoaZx{)X!2_dU0fi_s9hQeF7hPdN6z(jFAoL_v?%0xvqH*O{smPa|8 z1XWV*0Wzg2wc{JqnOJ$ifWmDZ4WEQopJWCq<}uU~SlNRQZg9|m^3!G4YSJZ6oT1xB zITSfT7z9?Bf^t;HHAXdeV7?GzVxZ+CWg1YUa<1Sj6Fs%2%*x#cK1HRB+`UvSN6l?j zU8$BaN6>Qb`2Q{~edF7gUi;^b6uHp-e@rtv@>}7C;aUSnD#s2+hYvk~b1vNB!*|{O z~FsL&kyeSaI4u=jcq%2l&PJ> z|MaoPD(b!?=L9hn+6m0)uGTTizTC*%%g2@+&h+5JHz0|jM_<^!bh^Is%sn`BgQIQ$ z=hF^G!|QPAipP+qTl&;vO{ceUUQP`-$qvMKQ6BCLD zn1SZuqs^t|!_l^Z2OdE7hYz`Lyz}6tH|%)C*Oq9fPM*DCa(@1VfNGCA>I?_R5v zfB21me(@zAejiN;qk$dCDCuP27e4veQgY9c!-1cIPT1I9tuCn;I$=U|*RkccE5{9$ z>Eyh3J$u*E>7SW=rXJ3_@kwn4hfC0jP9IxR07`0s!J=UpRG*(_50owyE{q#cxsTL?>AmgoOtZ9C!RQdJpZh#30^`79{xMA;|EkH zdZ4uKTf?ijsCws#+1clRv-8BM8#^az_o?IJGe3oEX|^=0)O-5!0E|2*=dEPu{^T^F zbW0E6>~W!-(UM*;j~-^-w`_-pXS;dmMNjyERq9lM{5!Z}I@?su=@x!;ci=3I-s6R6 zK;QIoovicUKqte)+dr{hC!LyFt-oXT@#p`E+I#9mmrnNK`t)q+fZF6Nj*;i&9EpHh z9pCCLqW`%8XM_5Maz@L}A6qDK@p@!jtNmy?Sq~|vp}U*#K9)Mfm~wRI@z~R&RYqn)qB4Y z{o-}fxscCjQJ?zU!t>0_I-MNo;$a=u%gCdbEajwI%IW5`8bdo#W4I+fTb-=)?yHkZ zrB=K4JM%mnE@Jg~2YuJ$=({>~=%nNOng!{*4m>@(5f8x7keo{t&>8O4Nxv1dXNT1b z`HU9z$X zQmjm2I^BhtI1d@l_J}`i;^e8DTnIw%; zoB?t^rW2!|MmWT;@Yy5l>N~q<<(!o`_y_lF7JkQVRNyr{%FAhILN~8s;z6sJM$T^G zJPeIkPbD+G(6s7pO3L4LlW@CIUkqn;2&F0Kkl1ALHL>1*TPrb>vD$yzlkK;W`@WQB z>XWR&?3|MuID158`8!{JG4D{k1_bqt zpUuE+6w(X%obxYnCJM3+XS8gDTl2Iz+^xBJ;pFY{v0&cRYQJ$3=b-pAS8l>f5g#6O zET&Q;0k6LkgrU7y~Qmxc+C zXHSU>@O{<%d_~Tj^6suMgbP=%I$6WF{zJR2tIqLTp4fZxcF|?(*z5CBV_<6NB+RR>!Z{E)-wJ0ubshZS%Q5mCt_Ny0?i1^?m~YkV zgZy|oiEAf2YWNfv8>ctEk zbfT_Oz3t?d<9nZ|-6A@9PiN|-YA4rJMn)>He|_BNoYI#T15;`Z=2cf=EQP!_ZztjW z3^D6xlZa=)tKEv zJMlWm}`{fl2o;DIMCLihU%u^*BAu?KKE<#>K?-%;-$_VRtj z@8SDO1ux~YJ%M50V{!i@r+0i~vlu?4U;Yj+gyp9wKfi!g6!3#%F9#8L$S6mKYZ!1G z*@jtUbB{8f&cSB<{>Cr(J%8BSM-lW9zZdYgWM5-r?I8{yt;rrem}({86IcrS9t-;) z_apw_Zfq9AhrNQOFYe**^6I;zM1Qqq#ShobuqOeJPBE{pVLgvzS~9Vp5ux-WIi1~Y z&%57K8F+xXnBd7)A70z!{&%up5qmTjRZ+H?jFVf54~O&-{*MrND_CQd^#`=*GM6mm zjQMA5nAo`?gaH-4N?A|O;QG9_Dul{y-JqKYhE{{&+vqPIQa^D^(HHCa^z8Y+*EU^fN(mcZRYA2v)c!NbbSYp;_)3n(PBE=90!VDLqrN=sUR#f6z6x;!Bi7%{Xu z$KP{o8Mc?OF>H^!$bbM{^9J%iOY{*;e|Xhw4BP~nUZV7S4EW0p6JN0$c^%N+wpOsP z>}J`=A=vWY1?w5Hl`LKa3gr~67qjW>k|-{a&lde2E{R^&7ufa^`oXf|jq)p}WvN*o z#r35TmPeoIC2a`>(PePLvg@Y)s8}zMZn$ozw%zU`LQ-54ogp^!9V=R$>urFq26*+Z zAlx+v(|BKi(->!~=!>vKoYP*R! zkdM#H$;D=V0QIXVi(xN?%@C?>oj>*=uasO~hv1SQ=0a@IvTtfKlpjwYB}C#t2*Hf147jFLsX{un{iSu8BG5#9@=kyZ2avho&T=VxKF zG1>vIIE!Qfn=FB1i{f{a(n2IJhNZu>iVho3v#j5NVEO8w!2!Gflv&z3EME;@qj;yn zo=GfBBN4<_Y<`be3Rd|-m>}g20tS0nCghA&01THk!4TEU81G zETu9a#bH6JmP&6@pXZ=1D3B9j(a|K%G1D`2CI12K+L+iGEbN$9SSwB1T8tiyxl}FU zu80J;6E^{=6 zwivbH=~4rEY35m^a8b4{V+-K&#$a}u>X*340dBaaDa0BU5RB0g5o~ilLO-DGJyd*3aWP#?BHprNQ{7UyyK; z(f3DqKM5XvGsF0fWf~%2=C3-b-bSTjg;CVlHp$R<&0s|QQg|15 zMMj*y=YUt_1~|B5pQa#_hT1lhQ@4OTBH#*kW~!Jg@38PBE=XGBfI)sXPch{LX<#J} zJb%LEgUlin~;A$t;grgW-oH4?TRu6LNoWDJ?C;)g^ zNmONwi58b@oxYOz!84oiB?c*mKxQ453&kA!=I`anWL)BNV!yRT4alG+K~i5oe40$N zZCvLRSTROCXw=4NuBj$Ct8msp!=-IQb3n_wGz}76@{P)P@}L?g9h;Qreu+t{YK2Av zlQ>{SsfRT-^BF$HfSTJ9DwZ~%rV3@6PL1+cKgI`a+d;l1s{9dVJO(o`XlKU?(VK}H zce2Plw$Oz$-~q*GWo=`3QBGS1S}hJ&0FQKCsi3J;L_q$?B&(PcL%PDEI74Me;gxLt zZ&LA@d5YHtu|npgqqc^`p&`SwVx2VI%n}XFOKqB>l$zQdp>kD{aZ0+4iby5qSE*7D z0Eh~z<4-jhD)S=g)JD?(+dGlChP6uCY8j>D#ne)*As*4MQM#zw3gf++Yg%WW8K*R; z&RLX|(oEer!o_wli5*IOkK&F{HZf}7xCpxp8%AbB(M;@Mg10f%fI=nMJf>_q(N>%^ zz4;}x?mUbQz`baM&JVd;g&U(J+m{6Ctoe{eA!`%CR5I!U(e(;D;}%z}`13nyRW6e_ z6qW@lY}>kWZiWSOaLoBG*708np8}!sRPjc*oR(v!(h9n{C@H_4A{dmF(wspIkTh{? zMhJyEsW1aJJ~hKhGUE}RA+g(WubK;2;w9)CR+30J*DRB_NS=SsE=0Abc;cDt`;0yg7GF*vsk$E?Zneb+BBM`7R;98g2H2(OU-sa zvfH8ZL8eHj-c_l0UN>rygQm$@Vs{-;x@;4=^N+bw$VmBQi;afj1suD*fKV9#bledy zsZo$X69%ul06t8?EY0qQfb5gk0aG}mu?!CHn9Kq%Aw1@K8jeIg*@tjAM z&{Q0pBu2GpaLX4GppleKIBDv0K@ty{>3EvT$J5J2<{GP3H11#8y86F>G8RcZoeYi* zM%-KjM$sGCP>VdB)Raskg9{S$wW-yEW2`#$NovqWQ5sXzxRY6Vv*$e?-wr-oggjif^dI@Hf8Z?NkEf?f zbpM;uFq3dEk$0y?;q9vCP=wY9O{k7R-b~4g%q~kQCcH1Z`u3P+uIU(hK%A;ONCDj> zO@ZSzsu&p1IXtm70qqU)=I==w#NcDmqxlo()O5_fD}(C}6g)ZQDbxt-Eqir!p0_ob zB#kGj8bk(uiH+2p^)bnNE&{(-G6nf~FBX6`+0CIRcSA>Wl=}IND5_YY%n;Ww#YxEx zd^Lpi=B6kO5CPkkk;iwVhwJeLPwdDvT{y2@t zQnl=&$;EMGQC%A(WuGoVM<#U$Ft*e0(#iRvv0y4|omLv5!#{HaR}pB{;vYj5LQ+W! zR3MV%6?bjk7Tjuma)=z0R58uK*)YflIfJ|ibOC>NokIh`318ZN%&Z&3s;9HibxsIiCZLN1~X)KixIT# z0jKLG^*H+w2+k^>WQ+i==y%R60u(75LCWgDG$oVq7Ff<;749F`A@VncE)Y_T(|qW0 zKj_|?M$N(>XzkM&6N8^iFkd@xOR3{A=a!>rnPQK%AGTEH0ZA>z?6r_;l|^ADB{{8H zD<8H|6;r*n9Vpd(A9DK6WTd%x9L)eU0NLzjtaUy=Z(FZ-yDuQWfwy)PVu}8AA#|Gl;i95Nb8O!Nj2cJC^@|gSa_$eCHwYZ=h)u7#|V^({R;7Ig$bM;KO6lgV7s* ziUttl2BY-jL|@*P#LF!#kkLGLFxb>Q`78G}oShY(8a9Q#g_#=)lj8A%N6v<8I1)jc?xGIfPFK|K<_K>0D>Ru-t;O8b*j))}f$kjQ#tNd8)g?Q2 zTvR4pex&`$^P=T*n`&(7VY|(}cbjgJfST2%N=lJNgHGNs(JrKMw}sDr*h*q`R0k}$pfx5vx>c>hEC55s=Sd+(y~&TY$8IB;~Ud*(zZ zjcsJMD4T)DD*D)=C_PlcZdlTZpOZ!}l$K8Ky3}1)Enl(&WEFIB`c!4|t(QIGd38Vc z8TZ-Oe(zs}2O40V!;#?{jk5l|fAfFe_soC!_&5IKOH1Fs=U;ub_5G#Qzy8|8r=I<@ z_q)fww(`sm|LbF?m)c)@-)}coD7-u5s+U}HUpdySlXC}`%MI4aKqKB(<#v#^moSIk zMzUx^7C#(vU${qo`r(+G0STw{-v9J>fBDF#F8%$xe*K5E9h(C%Ag~7EMyiUqqC*>1KLiHgnS7OIHVObL+@2=?6Hw@0l z>Ci_iL>>sdR8F5>GH-p&BZ0?jCYSc_`H9QR-ks?b`x_gLLkC~`8?XDRTmRW>-|?TW zuH5mpH_d$Qqm|0-H%!id?H9LIp1FQ<{)Wp={k6XIgOB_;bmH9MgUL^1T|47s?fB{w zPn2w^pmEj_XuLF2v@S)d9uZT?%;Da1Y@}!qmRX zg4q0!vL5&J5?(5lN>cWKnkqd%wQp)ZxMycc2(|V51;bifmoydjE}lGz#iyrEt*-J) z)XwTEeygj_;ESrQe0^_iXIC^ zx*A6suX4wNPLiMK-qMu!UA;Qlx1mlhys+I_7`bq@-l=y6R^J^OipSQM_-ux$eb`R` zJpFXHPeAF?Udq{{fBh+yx^+_P3=B};RnSSTwwX?hp2iENX17kzMnor;?&Vc$EbqH0 z3gXGWMP6V9V4!34(5Vv%`y2VWoO-*8rf3$pXGTp;V4^$Sf`77~zfZ>Lg#D4DNQctH zp2IOpuWK)1Oaa#l?#!I^Q)u%4hKZA>3Uo>btBXQ-{mt1e?ql>kegUSoWcq!Fv;KBC zPlxv{Ql(A(a<-7S@Emw2cdas8;NK`IWIGxQCitk_oP0sT>s>+o z*n>xgzL|!kxx)U%R2~mf9(aU|e6szG7r}j7t3CCaSnZeng^{|$9=dTd9^Zc}O&KR+ zHG8W%l;<_O+3+rMqLwlzfHB@c+rsFg));HcljLuwzz!?y9SB&D$>CI}Uf0 z!wxREPtp*M5$pKzC!T=2G^(y87T%=Po5CKMKNq9U;iCtzw`q9Y+-Y`5+WAJ9U%2qX zp+cCc`QE-Feowc16NEmZqrj6-b9G(*b$qLWW-jABd)In#)m6#)8+^||(satLt({WK zycq~{EN5k=C8ok|#=PHBzqPXR6ioAO^rcT1bRz!ib%I$OY%<4ceQ z9bfI*gS8&D%YH(2`tF@C=tN<~8Y#u3V_4>sVx|QX^Q~^3%-wx=3#QjeaZbbjHP%2r z_6^j7PC`4Woy0hw>!e;EKGmr$bh2_t=ZLR+5PtT1(8;Mx#{mcSZC)3je}1)7)XBbu z-fvZuHjUqf-gfft;q85O(t%Fuodc`AKHWIk`PKJqrW3k-bL<+VKg__!w4Z5tvqvZH z$tN*hsFfGsF0IpvI{BV;I>8R)qE0Z2$aJFXu{!nLHx>5xeb1ZhzVvckXS7()Gl?QyEuo14h>YAV5tnU(?oD!Ab>k+La#&t}= z#C)q;Cp#m#BEJ-qjZLv@*^9si%)tuAYba9lzf(?EMS=J?AQh zJ%ic)#&zc|X8C3AA&KYdG;bmc_Au_`{ry`3$B1wqB6w7v_i3HydGdQO$)C$s{bNtx zDQ4l!$zXE0?CeM{8;Z|v{T07&F_?b;qt5p=zFDRaKHlYf*o84$&@jO!2>uTl7~yO} zoTq4}O=coRkIo7eT<8l2|F-03GhP_&kgI857vVBs%j5UP(5t z8TLE28!U@_|Du=87YlTsjv=$SpV4>wJiY9m=387`7wN3vII^XmEGo+p^6UaWPpz`s zl?;8u7I5K-t2O= zv6Z1P@U6qH4W7BE^@;xXMvpFRxAV*hVz5QxnGs&&%5|()n#P;9$KD&R7yWA%$`5`>X}EZ!(HW73GGx`YcSAAQH!z!g#W6lV-5 zSqc|L*!y7p35i)zczDoAYQ4 zsf`!SoH4dFX?IVX>lcrbp3)T+eTdpZ!wAi>7eTE}$1%-+OIKC$8EhK|QR!xG;ol|oW zDv$HqL6D7w4+OwJlnYRl)jm#u-nlC`S_}kuc_HdlLA<-yi9eK8S zt-z(RL+y*1SzjvdY8+L$D30}Dij^kmoY5Qt6GK_yj>p(&%RDDb#)zULWvCl6B)GXG z9x#pw#q%;>5n#~a^0gb=&+B%tPvML((MqOb zg%q?nd33;9?bITa@3UZox6dd>-^MQMi>djEZj2jR5|~wMR>~YZg+QUMBN0?wX^R&7 zV4|3lj+>z#a05kbhx*JhDM&lgLn_v!2Z(Wn(vG3AQSxs>lotFuG7SqhT5dx7vt>hN zS))W9s2rEqX}h%{)GJEu1~fOTbv(zFWraepCC0L;rn3~xIg=#Rff(zXh4ZQLFgqz? zxfsudvvO{VEELyF`mY#YF8pvEC(Ed=pk9&FaBr=`*E29sAh_lpJn>s(5@QgPSTdC) zZ111|Ye1C0vbf#o5dqC#0%~I4g2w-B&_%+M^Wb&820Jjw7Bd~K#7doYYQQLrM3$Eq zV+3u*Q%E{qQE3SqE@DVyG(t+SnRJBj)uZ$Zb+?(IK`kK_4O$+2otjr>k_sp1J36c{ zw1_FA4R-os9uZqkRN$Les@0`bQLVDqN;gL%T{^>c$L{tLuKc8rbG8UCLTQBK>ZI`U ziGi;TD49PoOO~mron;Xf-)q2UgaTV;7ztu3@{9uO2}{0ZcT%Vl?}t~u|KY~PqHCzI z?U(vHGzF7RDx=#%(`wxPu6iBzB%(FxwpxiEq#Ch`+M+L``tBglyXi_kCQNgaIjxr- z)XtF-s1mFkq=fXio_Ub;*(CpptIW0?zZ9i^XPPYTF(a|jCv)?d;QH#*r0km&)o!)P zlIZxC6EitcN!mvLf9$;vm>k7<;9cF*Gir?nP0wnzEc!=jvc`)-@R|ioY=NotfPg(u(&dZCBS@)z$UCs(b3~f|N>#?pzfO z40F|Zhpog#N;q=Zt1}FxYB7@#(3Fz-s-;Ru4th}q<_q+1?`b#O#Q^XUurY|B1eXlh z)QExEUj{u9xIl8~HK6HD&f|w5@+xD>;5GE24}o^jE1*8=mHWGN=ysl(XsI(;6A7l! zy@wjQ)RbwK4RH=Pn$tCU+Q(+i$6+o24<8UAe+-kuAdMJS211$7`Ou;Sv|y3_ys9jt z;DebIVoj><3*_~%&^Xh}Dn1*Mie2!vkSD=Qzs&+2Ki%3Abj({IwP8k89`Y)7gRIPz z;YS|#g^W~)SOxLbAOk(LO&qUu({NgAZJzkRY>#t-uw#4w%c^YZk zA%hGD1g1^v6i5LwxXS~Rtopiv(MYIV52Y8(fo}=n;ztZP%kaY1Yy|bLUro@1InKfX z6`?5+!2Z9g%`;fsECV6OV8?L(^D6B;h`fF&0+x-=iue##+BwGaQnmaGp%hiPpe_%C zEyO|@{`61m7|8EXgNh%(#wpmDLXKfgS0`RjP*-@_Xh>yHAi2t`$D&!~a1&RP!BW%* zvB5T@b59M6GouW4tH%l7?4Tb^vFq@TI@eh+cRg04Sq60-&ftD(LR^JYRX7n2mAxt_ zqhPhFb~6|qi5I5`e%%qY2P-tB38Lc1i*x)9Dp_Ng2nmO+;EM~48zObZR~3`z)cK@` zqRGT{K$Y`MXa%b<0W2zwqc!q`#FOCau!1$q$8kvLV4#Xd_#;ukrZEz#lJ*S29*U3) zHeVCq(*clWe)UR-=3pkLGW`mldp+{2ssV5{ftpuM&67}=s*-r~>qKRcdjnj>rB_Yn z<LJFfcv zF#OnfKNE$mo(ETsZO4cT`;oD2_~`=yiBirL^%UC=t{5Oly~w+F2W-Bs^BVBsb&|Tf z7_>jKbHCNIe!7(VE-RiIvMm|2xp6?C#`XTKlgv3DK6MNKt1)I~= zHjl9e$tXH|K`8WZCTNAO9KL@du_IECJQDhL3=U9_elmbtaI^{#S+{!ZgbO;6ItQB{ zY64M!QyD@fs8}(y2#{hkglQ721As2nMgscJ)aM=onB3?OI>g|e@#!oTIeUdfVO^}H zHt>5-9U}FyY9eX~p)w9)O@gXbSMn|LsTKA|JdMr_$Pd*sPgS)o096PC9MbW?w>otw zM_gJd9l6F&qNkqeRlV`mxZ_PSn*?b+8VcyW5JA~7xVBJV#wq}uh_SkUi0Qk?NqsNe z)STl904-W-U&a77d^b7oj9#oSSY6=Wo-7GfOhRf`Imt12oj-M1oZJ>NON+FR*nwdR z(pCmZfb_%}E;zP}?GkOVSPhxpTGJTt>3VMM%+-bJmwodhSOp>>95vpk+XKGrW1y#a z=S|=0WuFwiRsT=l@%X*hS96c}gG>&VdSGssm1?R{RUvp+jE?^iFEcJfpZ7pBdF!3| z`+DafBni=&ko(>z7`tK`yG#hbig!8C8->*=FXv7Ak*ZOv7#qsST<`#sv&_rgYgDq* zth>b#v?an3_5JCMtf1gB) z8Pl1}aWwLSSY)cG?+E?T0EB`K>At71(6RUzi*pifG0f<;yV!b1WSfmircb)ar9M zy<~ynt?Os`6|C21)o^x7Jp$}kVQhOY+^?&UdPG^PLOnl%ryu1Kn1;dFnrXievPw1C zN#!8#pHq*|SPofV_g@;2XjZ=xpSDG6Bk#i|Fo7qhun!6I>=Ayx=+ATRAFK@Mmtj&B zmYOfAoC)FyI3D$>FcJwJ5GZJ=lW4zVe)oUB>4k^>dFQi#vHRD)@ysLJUigE{zuzaS2S0b;|HQ99{K&qkRjW!5R6mlNl>6_0^2rCLAHMH_d*w&`$=rTuCzuhm9YBNKaxHBa1%f|HTkHyU~uX;efHeiZIkGKa&q^~LwEK)Ca?SKw`cDBi-QNg zB43hfhMb!`{_Pq0+`&KpicRhizrgx?#36BmB_OF#32 zKYP0$?(5C@EEkwO%3zuJUf)9x_2vA`s@nHYeCN`4op}47zcBN?cRYLSU5|Y78ynvG zr@!}x;~#&nI`@0o$(-uDazT*Yd*fgI^Us~v`{T1S`6oZ>Mf;w({KU)?fARPSF;6|Y z>iZwu_r0<6uYKDCy=uynQ|-iuA&_N0@yLcP`}W!Wj+*ZUq-WirYtpce}lsxpDfFTMNn`MDj^-w*XdvVD`fY~;SdDV3Jz9(n_VG|I`z zJHoYpv}3T+cgL;yTW$=mztP(T-FA-s(ruvEc-<9G|r)6 zWn;%6?pL;;qs9G+MGl^=nT{M>1+Y9X!a6YX6OFxWJWk&bjBpv37jo z>00f`5mxd25{wS1^`b4%ZrWeW@We1Xu6GbIn67gl}B z+HIL!`wqSToFzL_zivL0$*5GW|BYg;RhgXiI#<#;Ntp}}t1{VX^jMcvCh0ZlZ_;a_ zJ1mn;^LNb}JMx{{p>4WM+_+dh%iv`=LXI6O>oTdSG8rzu>HAn8YBi@!YC1H-(@#$n zZ~W$ssr{9X;JWee{!s7JXgNMozi$4;7mukjdDF9(T+(#?x?=qYT}kJhi)kIUWwMbK zC$1d+F(<#8(V|R_sWM6H;dNIgcgdIPp0&m%%G-3`<;JDHOju1dr}9~^u((WC{dasu zsnzQHuKmocsMn~ztG4dfuKQjh(RzxHep>HmYB}D}cO6rG*Lk10w>cHAlI)Z2hM!tO-^&Eqn)%dbC z2%ihIzTpekF)xY+g7S5GuR#Uw`>4Xf>w+=#mq%Sf9Gfp$nAAzzs6`7 z6P~NAyVfgY zrflv4T|gBK=raavjSu>Un*zTtV)8>OP(Na`*iPQfS4H8EHVCu^=vxSzZ^3=&$5`IE1NGC50&!yiQ@3E zWP5AZeGl~3Cu$QDhYuef28}umXPMQROn&FFV`u$|>Vckq;t6(`>DI3Mi{Zk^ns=nf zb3MN+jOej^+wJHU`)^J5-?@@@>>Seid?~V^C%AKGrBXUvE82bq_DL+~OAzlmhDO$W z8a3}MwjZkDWG9Yq7~sz%`oog=9$vFm{ecc0NO*b$mFep$75%M>VsR&%d*V&(>9?4@ z)toZHy%w1+lNy!@+`Cr0@%!~*R{4IOYt%EXIQ#bqUgq9nIXsc%v0``rNRu*o z#}Df?xLTBn?*-n}*1(Ir>h@Vs*0OA^q9z?%4JQ0-*n-1q$StZOi`z;4SgV=^#v;4w ztRgFI%nuvAGXF7{15At@I`pxR>2{Ko3AB?;#``?9lWZ2})JY!K3M1aN>3h_-lkggJ z>!3`cZLXvpm8R`vXegf_8iHI%@_2Z-Y__4S^PKe_?WCPZA^Fr+$z=#-l1y`_Samz- z{m!B(MeJb6WOO?j8_P5K!SmSgTkM#ht*d`=nPiK_iPA+;NXdZR+ciwBdDq+{Dr7J+jIAILCWXTAk2!d5(5- z|5$g^{}gA)BnJVQ;1PB7j9r`OX(Q2R)bcNVithmbR$tNR`hguza9_rh3I5>(uD{us zAnwN8q0EMT8^7p<{au%d*<;eCbu_UH24QNs)myatG#Y(G3HvdsngHhDF3DIG@^}k zAzVQl=J6uAl{68-Yj*oAFY;RhZvJ=VNO#V(k=R1@=Uf%Ir9` zB9U3*F0QGoMwmaIl7JmZu1|&31)|BB#tqMB`MUYx5)pWGZ_+^1nga7DaBv+(gT$r5 z-3a2+3WWZlzcrC=D*CJ`oY^4_&JvPgE}@w$!9E6CxMOEx^RKv~80iX@if{!Blgxgb z(kl15gd0;d$sN{QR>#5xVCl@4W;TDLE9x2d{t0Npt_lwAi~lnu?nlC%dE z0gkcY%$Klk4v~7UWmhc$#>GzBIJi!6h&dii80lJ+j5aYQI9?}28WUJISjpHDi|RP{ zTa5v9iZo_je7P~}gO%nF(N5gh=ClOXyr4*GN1LN*LUh%ao3b8qGs{cY+3Zubb5`-~*Q@9?582oOR52m8mc zL_vQNw+m9STBVh3v zjQ)5>Wfu@b?Iwk{9peLeBD_gR6@GNrw?80L$Sirqj(>@8x(AvpLZj0%FB5r+xUJXS;Q3K~t>{y2 zB9fu#<;w3a?=c;oLUNs5z7mKC6+2*wIGYuvNG~B*k>mlJ<-KrUfU|R;NYn{b1ze%+ zvA_>;3olp;Gr)uVIQY}x54w7m*%o1qqktQX$#*lQ!GH0YqR zQ57V#ZCgwhx!R~51@Q)j=s{uzdvG_f3pQXb;4FtGHbN|S@0X2J7hqd7QSo-D+id4> z3M#h)kWQ(b#%8&yHmcJ3SUNCM&JxPX2E)6+s#bF#lnog z;02hB;@8MyOmNsV68xoJ`b%xZbAN#@(0?)1(uD9OoX6YWAW*@;gj508TH<>tIk#@> z?vI7tA>mNLQ&f+(;L6$*kVm@avruJ#fbL8x$p8z-;01gA^vXlsKRm-D?pw=EjSktk z@y3hfi+z|>_Npi1>O@lwuYS$l|ryjYFN31L}_x*T3L z``$qa3nC$5>n5F@0uBLeC&N|O3DpJGu<8VdTWt?%hB_baqIxA29f2W%W|8(XtsG$U zW7W<^nVEY?9`B9Heh($xk;-;|T0(*Z#t*v${IvvTItN*~45B=C2;c$MeCd^X3|4Z1 zn1?b9L3e9N$5`bW7^*ug42C!X07q3ckyb|2xeh1$a7}Lpgn1jGNUP=rs=q8Tc-jov zSdX}G3V)YtO zmtKnk<_m2a#Cq7vPeM-wYJnP6%p!z9)D+^ZU^~hJC>9u5nO?F1chnu@xtH4OI>+8> zRJ9X5JJFRoFcBB(Z%nra#>Y$zGZh)!5Os5rQMPD2z~&KTW+9Y#S|W7G!(hP~E=X0a zWSj|Uou!F~s$5)O#Ca}geAs^r0(;$Bi5E%pi}OJ^hd)*CXTikH5&2ehRLtSX z2!5pM2{;?{=g`iT0XoPMgW+)4`00Dm$yC0M;S3TG%6u8FQ#DRPHHYR`Re|$gRfk=W zay5;a(F$I3S2Ix3)EiH#f17;BKORPp!NUZ{eBwHy(Di3@guss)56V8Do`ieixQc%v zeuIFs8J#CwRdNQJ5n%~hK)?K=k2;(eF=!+Vnr9v=;Q-Tl2e(t%Dc@r<0xCuTb3h(u z1z029>nhLiGc@*V<`G;kK!!9xG{C21@Y^tS+v*xMm}!4fc~Iq@`!NBvmS@z!q!;4D zA6$Z|vpK&tj>!7|SDW3#AyOf`PqN<6PYD!3;McPcW1dE{A!tkEW_fU9bl=WomhbbR z*Ajy58(_V@=Y`u;FC;ID;xy;6DQ<$K&9Q@Ogi+Za^#-ty39LF^t;Y(gU=g4 z9$mpM_Hlz5KPa=AAoSjoWj*j^6xCj%vaS^-Bc=t9aJ0t>4`}oiFsP7ili^x=hVBGK_VVvh7zu{I7>dcD<+3F#wPBYjYdpdMfKGmQYCp@A354Qm+SM!w17-Y;4 z(;pI6SvIKWU#edGtU2k1f@HX$7Z`_X+XLg;gINC4Ax=p7OWYszd+Ztxh^mLXvZ^sY zKPQ=Yi2W+e+yhlAKEIOG91sV1X(xoK5? zs&$0E;IC7?9~Z%`eu3qJo{$&VYyj7X${`OgJu!D66T@89v;+x9(=1Q`*{gcZ^TtB& zYS5p`4GMyOt{VbCWE}`6{udlegX#rPTVQ z&ft(Bn5yIFk?ed#kK+nlKQHmrm-+`O{ia;vga}^!pdB6xLR@~YF%w}p;E5#{=LQ}n z+)RSph?!PlP-Dp8b=3g~CsL0mEV%hk_Z?L26!w$5D+)%R8ufi#{KE8CQPj8~^>k0#8FSu z!1SagR7K#O6~M<;*{pY-52dC?+aXoYr$RLw4A^DxGd}dF0Dq${ACuL(nZP5Z&;k{a zG1ec#-dL)YU`<39(`4-JeKt6+k=tE z(2jQTGPOs*;KEXo(x$c6i}mzT2;cgT;cCd{ zKJ%vd6n=jon%i0k3m2&<_Ihf7-NjZ5o(a!avjK>MI_!e&&;G5|1yz$sd=#?b@+jbJ z(i=Yr>&PNZhmNc^@#{`t3+6!r^8<8(c;SgLd~Hc12I2VD)#}kU1J*bp#@v+D?@rMV zun@(5FJeF4>zm)WO;q3v{w@~VTw#oC)3L0bZ&&nRsz z3VQQ?vXycjGIbt+f9)$mmjK>-U^-=EbnB3=0FlPT990jUH$ncv8(20v7!B~~HuW$v zSopDWedkbb^LT_tg9+`~3a!93fB;7{q~NORaU6mBVu!Z_*cMX^54w>(pT z`ilhc*BimZ5m>-xO?bmC>!OaQaDZtaOn=rs;Ow~eg2ofoLvc6@;<=-of%U zcr~D|E<96)9L||~;lX^3_2T<6q$-|d?-|_onDC(zl>(4~Pc>cFrjDV^%#HbB5P$w6 zg~X!`Pr^G?0QQhp;+a{=gZ=V8m4ga*~(#wDUg4e(K8{hceHMbvs|Fdg1Jd<17^Dyh3&8wNT-15vbk7U;u zKB&rMia}N%IH1ZTyBafBh55`KpL^!^yWjAc>s2q%!%Mx;PE;f(@6$SX8Bi}%ahrVL z<(K_~JHp3xGVo$Bjh>>dYz#J?1iKgH^Xf)&)ib~L&@+7>eE6f_p#9^;Dp{NE!m}D*XIY7w1`TftkGaK5_T&zw7qfFRZ=W&pg!=maHTyQZk~ z?b#ZeJLrE!jdA|WMCpGWy<{YFNvXt!gY|O$meSi-8QJdKd9Kqr(J5yXjsh3zo@|BUm0wE|a4* zosTtDCa>K1BJ;$K7mCG~zI@5Zu}f69KNhTi@Nlt+Wun{3TlG@ELx<{b{osQ;>&j$! zqBe2O-i7y<0Y-LSRol7q#&5dvc1+aj^&S(>ZlUMcIkgGUedxYSGB2Y3#xj(N*7-Pk z^vNe*nfQXrbSRV0-FnH8EtA4Es!Wo;tI)hmSPjbLXdLI^38u=VgT8C$Rl}9ax?gkU z?U-QodXEXwhh0gxEVl2;ytrI_m({~DzbQR6#ciJsxS z7Fj(<)WKt*yQhqv?eI2U`QIMDx3l_^+J6A=gBj>C!n<$yo@*SA315ekwsYKv5$_v~ z#d?l){uLXfHoF1$U)-VM3@;+k3||5mLpIL3x@7@sK8 zx_K<#3vm*D(m)+QW%!_P*dM?XAzl~zyVaPXHb=EyBCHFu;b_y?;l60^XZWLp`L^|d=6KZ!FgC(=5d>UwK`x84WR|Grrge#YEm6%znU~ zGcg=q1G-~Hj9Iy?YTmH=XMf6z(OT%q7+EUi!B341M_D1tM z4x7h*5X$86!*fs6*xtRv>?r6XVqDY%KnahAc4aa#Q7l3%e~@Q$pbW0kYBv0B+}Eue zuDZ&U$?(MMp|-g0YA)RM?FelWnakww*irme$1SiQ=`HLit4Y;Pjw=7PGQL_>Co9Cbgp6TT|_X4L|uLEAQT|`YxwT@FNLG^D=?H z3-**x%Eazxy|gkpT+8Ci=go%?wdlJx;{L_T*dBN}vg=@MPoxC1gGV29H+F!gUp`(A8d!wF4kZ7(faFK znhpClGPbts=TD0cgM9>-$9RGMsm9B3Ew}qFT7ASE?(67zy)3^?7=L)(1Nj|bw|a~@ zvqzu>?!R-A?ay{6CIIo!DQydM@OOz>l1E1m$0nlsY%0OK|rgiq<#MM9aTkN-J zP4_y_=n%T$pcy9i^!3`#*y=ySvqfO;EzV;CPFA0X(s(aQ8z-ZW2=ZMZxc`$39Ka58 z_V+q1j3@qgsW^k)qcSDvJ;JYHW*~;V4LZZ&*s@HT5TSRT2nY6i-Q-(QC#=jFTaKe)5oR+?wVs zcLmK6aNu|v!jef`0+>^OS}97C?i}IVm#NVwJOK>zq3z)$qH#}WZ5OvH&6R3k;T?1GRDO8XW!;Z5D z!d8}CAaDt=62K!;q#k3mHJAdK2R0CBA;bqlzyxVK#!y+tJg^z%E!Z#)663?Ky+bzf zWvwX{aEKZBQz_;liyq7KKt|}t8|49pijfBLm6;DS+2f5}EB)=&pB|Ohd6K?>>{G+PWHj=uiRpvb6wTK3YX;$vPayVG^m5CSi57k_2W=2K;i&U>ia}#fw9$ zHsCX5H`I+@+-`S+HaJSu4lJ9Ss{f-~(M@3E7NF&*(*&`PwsV_Bwm0_KY@{v~f?cNt z%6Axv;JR6@--K001tY=qyeM29`S>#3mO1zd)Tsau7Fp=p#^iDgQg^G7J_0> zgS1b-s)+3w!#)sio%B(d5S8R`T-!sapa87hOMBFSZY1DwmKV0gH)X>WuB21AE3m~S z@OTI#=*gUZm9DCGs8@l?e(9k{Zel&i!5Pz}PY@6yUTIvV(f42@2<`_{Ri+Cc)K8=` zuauaX;5D3u)iEm652^0{$DmO~@Gt|qJvKP>2bZC?p&STMgl!|5O08*xmF60BYeFhV zMRHnU+6Bg{dO!+^3+ycrOm1A>`feMVyaQV-^>@Rx=p5Ek+xU6Pmo61l(oIsYuiP#m z8Dm;|7XFljFj*m(?d1h{#WSw&16t0o?spP}@ViQge|# zEW|-+566B87Kq~hK%xv(6`AA$2Yhf5=+}B@_S9UYPo#v{K=7)iDEDbw_Qp47Y|{s0 z(c+P@sc)cLKWC`apsN1>c;FxlB>2+#a~{`rNHunW)6klx87u{baG;m5d7$P|z6sr= z4JR%-kHLYftf^pu!QcArjA5DD%8Y$i0FFj7WgK*qjbJ$vUMw*+Fjm=?;KkKj6JVL( zX0nJH+UBjBX$>AmF-S57=vBR|4<2+s2_FS8K_he8fb^XGCsw#PI2<4%>SRoU#ptnK zi8XS)2;g(7k&dYG@9TzPb*?v=#2X(5_zEY;d$(VN4tzTt)Zndpb~Ukzb&?np+E5km zpk%m3psbeJ+&0du(+5@m7S0}2t}`6l1^%APAeJ9jIXm-MSwe1vk5#37j8%O<%VxOT z#h|-GY#$V$!WASf^|BQzLlwGQ2?Ki$V5;5=BQ&tdxs?sHry ztE(QOT!Vi}tX&{YXE0}MI#6gA5+ebXSW3(}mBK)(TOGs?O+>hhAI2H}s$74SfW_Z^ z&&$WuG@$BB4`zr`=Yf=*&8WPF>HQ4&;u$pIF(l9Mw_I*(To9!YvcrdKUBtRTxuo9)RZch2E_~2y#)F&B~nqWFn`d|pn zJ}8DLoMIB@RVpl~B>+dOUZD?c?qXjD7Yq^(_={rNfx}@yCnf}?QUDSVsE(`G)bJdG zE0N*B9UI0RkbDXqiC%fe6j&d-&IyaoEQuyc^pq*w-&h0hbRdh28=Q46n6iH z@Z`J}Gg~gBa4MO}AagG9^Ab8%Qu&&KRSHu3!E`04kc^-ljTn5n?*VTpb$v7<7ArwaTvZo#_gjWfAE6T?1 z$AJNIfU_)zN>O5ANflFNjIj&G^DG=3f|&X|JOH1%?#cJ$P;Ey?7RNbQM56Mvlzng? zj5fhoPL5qSsvaZdtPdS&gdh9Bh#`>s66#n40pVJ2Wli;=E}_;LOn@FdfTf$jq%!px z4rGb`qw203Kcd+oSeb22Nbt5o^9bkTv{)}bbTlwjL&_|w5?-8Vv%NeDq={3Q!`@F( zg)cjZN8uD4xjL$AIr_rUN1y3VlEG?*>$9rd0h`GQd3n;xOKJ5~?2h15=L>S)uWk|G+EqK#$mD5nYg4m;p88{2|FNyOI zc=83x0SO1Z4$e|CyasLqLCvXBQ%@vPd5lVGNO}sZAJfBSOK?u+BfQq;rQl1A2 zb5XB~-!2(drUdI5$OWn)L|k=h`j!nTRCBzW)jUH8D=;VO$rUso!G;p9&A8TjVW=kX zo(V5bt(taJAW}A8l>504SjTPw1s{AhAnN4;qmw8CTX)s7T)CRrIDr5T%ITJ@$=)A^t`oK*J@)o8VKnok9@>@3dS8HU(9 zZpWd|(OK4s6nC1vT3RAbZ#Jcd^=P}SBJX1rndfn^1to7PFzHQv@bRYe3FLTH<{)ZR-m7b`8b?{uoTD3gq9GoD z#DjEhAJi#5rdt_LokKzb7!g&-7i0e`lX25)sC|ib!}){3ML#|^&TlD?NAKY`gf|UA z8TG2>GY||^L^uR-#ca~=7Y>~V#pbDrL^;dK*ZtMhp>4gDcRravFslYW_eBR!8!-MRdc4TEQASKa`h}sesJyyB0KN$yf3TvSz&Wh-$*4fTJ-y_ z&#R8Y!>L6bIFvuHrl>XzD1}^}&A}ujlcWJoq^haxs}WXCi7vf9euc#^aMk&HTQ5}N zNfq6FaGi%!A-GJcf&}l-R56^Xu^X;^PtbeW!1e5=i*lR3KKSI;tMB-kpZLz-hyCGr zPaej%0oZaigs-IGbZCr?=Z1dv>wW(+*Xyr85DeVSuD^}5BHMK{^jtiSe^Mxj51(dZ zxk+d#4DYVvy+&sRo+C3DRXgue89${rgscw^pX<4IK}u5iVan1SDuKORrUd%@N`Lx! z=s|4d&P&~u=GpXy^t4N7E~uPJ&XQ;3NtJPV)kuQTFwb}8!isW)ZL--exPj+SajEk_ zHFfF1Ms$E={=4>m;Lbbu-gD2MTlU<2!=4}Q`Io(S-}y6pPrR~r!>|A7h6^h@@vjPFzWxCx_c{%1a4T|YRBHARD__lGmn&wq7LoNd#Rhqo=NethteM>g#D zgL|cpi|SI8;a9zz!|Kb|dtbi61T?wnkbETfp~>949-sOBU)=xro;lS{CMV_ozs8g5 zek>CyS3RmsZ_?inI(3SDd-lHn_RB}^x&4mY@4ox;J+JKj+%Kyv{)rPm3b(Aiz3;*s zM)Mb6JRSDs;xY-pbLaR&Z~VY3kNoJ+GsVrn^NrexLnrq9!aJW`qsoN$zV7_>Gt~or zQYO$`;KcjH$9wyNVE=xo6A<4?6f^IE1CZwdbV2BU{Y*XxR6BvlYWJxbmdn9Dm3SS* z8|6p8nm>5$1qY=rJXIzeo`vfd!(Zp~{@L4RQxXXW?{6QNdHJh+{ywuAq=)S!r|QG( zLmyui{rOW<%BXr5ubFfPj~wQt_ym%QB1Y|CG8^Q!arY{fFE?%M_J zVsf7{B_HCZozk3vNj+r?{K0m<@)dF5Vq{^iB z{a213FCLyKdS0G=lMUDEhUyjo|b2i zkBropiTg6A8@el#VzJXQ0o@2)Ch9LKhc;zWkfo6?T|F;U-}U0{fBri^T=Nc9CPIq) z@7MP^TwKF+-zCt0d3SN*=&%eYjtn2KvAwmzk5DsH@=7gKJxRJ#u47^%uJ3gW*B0)( z&ia$)WpeCT_V}S%yp@__-RF|?Zt1S?8Xk7jQop~aMVE>0ySgb8Ko0`&7M!!~tmjvC zHx;e(qOITnmINOCBu-%Y)`+c!MFV>7Hx`@t2*#2*VJv@18CDN5u>P6;reBcqH*e%N zT+E3vvv*-~A6Fl;?@QY39?)ZC_&TRP&P=aY+LF4b(FX*%pNeW=!0daS-<;jP(=odaKU}dXL(iz6|_Xoxpy) z&Qo&x6G{OZ^rEo3m@IjfgQnGY1f5E-|ANUACEqxBNASE&LuB+2O&Y8&=GZT&I0ww{ z19MZs@4HJ(-!%a8=fm*}3OUf5e7j1W-!GIs@JDYIED!pSLo%~-Ua;DG4^7lYMvfeb zzPz(MD*yglS6y|q(zKI2#BMqKu>Ac)6Z`K1t)Gb1o@MxbXTwDEIY{<+Gd-S0o+x+L zw>Pr+ZdcMN6BFg~;TpTrmFIV|!*6Rc)|B(5=DL$=>>sWrW8CJ=1^i8?bmXe5v__%n zvzq<0a^%=fCMPCls=Ierc4l7O^!1&)N2~As;@EE34^J--NK>1r-E#OAC==LZ^Y9_b zYA=qZ+z%POdzWL!^uCMjcw%>(iC9ZE>#xW!f>LSs?q+48#(~3cb7sB3?tFSL--KfE zs45ZEi9`<9Mlj7IBZq6ZwiaeKt(iShp;bOvdUpE=+cJV;*$IngLhRIj!1>DicVh!|tZNGd@ceRf!~h z-S7yexlmwwU)K)H1S`0$=uJ#ZEYAxx!C?3rI_(bM!_}shTU@!d>u`e4TDiq>U+0GJ z${D-9q2KQmqi-0eR)-zyF{1t=rg?_|vt-i#AsctcZufOG`!L#YAY2Rw_km2pv3iWL zecgEsk>}}`JZZCz*k8ycn4jX>Zk*%&8?9;O7FTZVI-E@E9f_vioqfp--<7kl@RRzq zd$fL{98K(SjQ3}>`isoyEABG#WdB9fM~w9tt!}1p!YO=;3-G7+fs}I8$U%?M$ibfI zGp>9#UFb?q8qyUkgtU*_&VydsZqE|QVi2xinQ7?!+TgQQ-*9EGI`N~NNC^|WKGvT( z#37taxGOkWh%Mu;==2~Sa&a~F!U$K;72FlHAc;|Tq^1|0F}r37bKx!#uE4NNwHy}Y zt62c%aTpK5ZqLE(iR)m15ZtroBmwY5*bOaWpzi#LD_JJEJqbg-5euwGP2t-C#-yFQ zg$66`xH$)tH!D=mAfx~cW|miIoxLnnY!BuPv0ta`Q}q{IM4fG6>V3okwQNbohjACN zT$BDmTm$d_mWHT53m^_&ym?#@z($A?m-RufpEPm(xcu7b3}0?EL;4amk^a5TV^ zKC_P&Q5Z?VBF|&vsG7^ZYq=(|gudop#iS%LYOq^DWUk*0*^ zumypJ9JVB>Z5&ERi&RlZ0j%YQQh{AB;gx32?R3y*Y|~+z7{Slwwq(;4L)eof=5;on z5-M2;LcMkLUSf-qd6%^<`Y;4v=I3k&j?Vzk9I0dJu1GKV(quu4M5D$F5c2Y#cq=GL>~0U(&J1*zmxtOTTJK9t2oM z8`MG`JLs}ie?IuY+iJ%E>X0gi65c5AVS@zyJBPkz0qT9pl*D4~;|wz={apma*twg? zYMrf1WWCk?_<&j^zTTb<7Vdz-9@BXP4G2V1$0(RK+qk8XZ~!lud%kaC&!M*&KqsiI z$_-nJ$?*xcUJ2CL9>Dhig!X3oCmmi~f*`|o1(qm;orR!P!}`Xo6$ABoXxoQYflTl! z^>!9#adLgLwq=%r7@eQeTHO+37(Mti883}lR}N`w&wL_ngKz}~nKISiK?%Ww{vqBa%%d_; zpt_WyIlMC{cwr-OFo~HqZDPhYj=Ji~xoH8u26)yByW{H@ka10TOg5)Xx; zPcZAi!AeqP9urG2LXB0Qw<=3>$ENNc3tjm+9sNGj3TaO;x&j7CI5YRaTvMHgM4?@y z8R(B&1gxN91AR>a`&pgE7>>#+eGPs-#Avd}sK6mGnA`fM?+OMs!3np;8BFV}l5i^E zQjCfGqIO0X<);0>vfqdeOj{?8H3$9#+RF>5#nn}nctft1*vf@)9lo@cTpu9~ww7)B zd2_NDOkB)d*b+d31uQEEn>11nazWyZ2<6C>e&=odVC>BUla~3Ms-Yo!S5ysDE^L(ZYq;{vr+E~Pt7|Iy>&_O8ryr>@hJkO?j|9d$&?>%B6kW%| zt*FBY_SP9KUBM!ec#Q8OwVkoz;&p;px(`h70}hFY62Z*ZrC*6sY0)Pz-vK{H48P{! zH8PGIG!Y+0U5y-r1@Eo$YFwyW42f~k6ACegGYM6QYKX#(uAv_@9z&dl`yR{jz#mtw zB@AF5&PH!#;ms;m@F>|lX=zf?kdD1M#)H?QOjFlq7N;MNm|E5V%q2lA!Gd!vmF7`& zO75&R`_PX5m{#<)NN~~5Fot;+KTa~dFdmc8@S=WrfZ?T55UNRUDL<>{v@`0Dn~RVL zKgPwk4PFp=Q{mRK#HGQqdVPc%L6M1+)5mv&Xj_sA)+d-EC0DHd#d>?^aK|1;M+jy! ze=CEJ0hqOx0`ILy2SciID0!CGrOBw(gC~_idgrGUzR5S=q-pEc=)Ng6I0gN49>;zT zCaqF+Oz=Jj`#ba>!t0p;Ys~;x)Ak`Rlrq?=3S9JtT=jxMz_G;R+jK<}{{jvWO+0aN zq{?6M4Rw;P7)y2kh){p3>r&>RfV{`4?flr-&?Kk`)_K!d&0ZvcwMkZYKIw7_ga{O0wg;8By zt}?%U7~&2|bfk-+e*Azhbn0iZXhf}yuba)8B0NGkj&nn@O$eE{+n_UNYeS3LPkIy5F8~rU4jZszJH#irgSKTsy8C8wEYR?Bbk6+z? z1%@2<9xE>qKdar=gb$AB?SEFg5r7%)MeJlssr=;UCZ$#q=f>VDlC^`(9$n9e{qSaT zx=aa?5$#oB`HLbAQLn+@{kLG^_q5a`Hapb6zUHs~@B=D5;c-4V&?Ke84}UsA56)Y1 zTm8CvtW2Wh)exs>g-XuSg`)#pW$l={JtewwVV^wZ@ecp!yHuoywXQsOBUXi|>F?$I z=_f6FeY!L7{g`ZMl6dA9CA9IRAZB?3Hk?2mVEkNj^6V&a%xmX8wh(cvnj2K-AW6qM zmxBt-qn6GSxYCy>C|0JqJhjw3E1$f8jN%Y%&sDHFFn}LftX!-+_}ulluGhZ#wy|D& zAn9qd$mS*~(4KEv?O<&yut6Y{_Q<9Fh;vZ(nV(*>>*3neX5sl71OsSASuaq*2(pK9zaSc@u=EfP zRR$I<{}N*(;o}~AzOQ)yEB8JWDtfWLGsCuVOq6-S_JTHGe`B(%@`tK!bocDJ-S-m* z)|`irazny8BvR+e+)co6{$?55lkUgWQ0SD--ltT7PWIV{wYmerHJ791lZ(!?d;X11 z#|eItX7byM!<{5}Girck zt*VC_7U+lI>!&~WI%vQjKw4jaWTsYHt9Z`pkI-UT$IvbF zhx-x-(o*nfe4IOjb>~yniyDZ94#wBE$aSMHBfXSf-=nPIj&*4VJi;&6LIm1;^QXQ? zK4=(AOrYOul&1_X-R(`i4lJaETN%0q z?8%-^3Xvu-(HQA1G7VD7{a}Et&lP@MHq2lo7sD1kCJ`Q>)}+;r;?U9 z@>>oef6jLP_tV1Lv|SC|e!gI4ok149!?R?#IP=v03t0xLXqqu=a8IjV8TV5R`@Ie@ zEwyt*k;kFAD4g~Om3$8$`Qmj`rE%#lbRZ{r&3HjW@!KbfcMVI<_m&PumR_E=JKueW z`7V1(+5Tgktm29ql)^?TGxxlN(zh4X!=wP`rDY84M%@VtSa+AYs|cBz%C2+0sMBRN}^;-ALKWaV(`Pc_M9cCoKRS-M`RG{%c1bJop<;S{%@pvrq}?=0fb?iQLa;NVQE z5DU+*G=5@kS<=KI)zyPgC;Du%FgBQ40f{s2?xIVA0m1YuXrRu`n6$crbe&=ud;I?91!>v6&s2^Ls5^SUpzB@w88AGCL*Fh4;m~_OyP!u_4YK zopH=7#+#WZmg$km0Ke@#-t8%HZ8Irjr45Bu9AG;i(RH`? z>ztGaWPZd!YxaBji?8;ObY7s34o6+_zK)q5n%)P=3Er1Q*NQ)oN@5FOS|TT^)1n~c zp%I1sPU^aQ<9ds%`dt2=cXD=Xx+bYTG#zJNw|5i#V^dbB%^DRkbdhgB@+YpanNrE97WakR+T#JCZvPe{$jsfRkP*ECkScBMO7bbM5) zY0`#Ua?M%$x_4nU@B+z4;u7A9`fcwp#i6d-JyK_g2o(@CN}xS7yr-wwMdN1L@Udg~ zmVrwUA03J%Qh#{iiVh`=_W$Q2$Rr&4cw_jh=7o$ZV<)$T<6iAKwa!qQq#)v47gpa= zrT*S_T0VywW7>!|JQ!6qJ>cX@KoHOC0b<; zTge5PZUWrR!q?ej^hmbVg-dz!UY;{zN5dSWPg3hi}GIjRRH+~DXt0s zua^P|f&fB605dRF`_cJMW#G2i#hM|-ngd{h0P2LZ!2hrh|MoB}A!<%fyVN5xS*kfc zY5b@F8rG>WDXhG0B&l4x{N0e#BeIy>RF{_<#EywGnD$@7`rofHWGQEV8yIcU8N!2i zg@$v5PT$858!I$lemRVkS7?d<>DLzUeMDx)R{H_9ayPQz={$I>usAbe8VH=J$M^?d zSNP!Oi<4;!KRouJqxBsH*g;2tpPXL>lmAal{~Nyl{h5%ia`VSmp0&nt^2Gt<$^tBa z{P&w#qcYyqHI=s?F>M&zDs?9L0P}vCnOVNOMG#r{sma3MI@DH-e-Gz>cjaHt!;&xO zJyV(i-a2i)tf$$Nt}z@dtLFbOCwKL8c6wJg(DXw*K%>Q}j%wknVO{0lkb{upWugLr zI#gF>6o;#(ZgQ?S=6^~D|BF8CO&l!lms1^~`|!qwH!vw2n*d*vQ_gwGvIk9Rk7P{t zF5qj=-ztODbz2u?PP;~v(2CQM-|ov_t||VH7XOF0VOX%P&}%bd5wUFRV#kx~uqQM= zg#iF=%IXY&J5L}@_j;+O*+phDnl}>vYCrFIdYLbAC9uo%!M;&cm3C|*@XpA_Ea++s)p0R z)~;kyT|nlG54Z*?w8Vc&D*uAV^?j)pOF&LeQF0WL#!hJG`@?2X_>*MSnso~QbclpVt2<7YJoe39db{~n81>D?zH zzK3)99gs$zB*nyKbC4#S_>5)5u3%{UhIa(r+CmF8{{Kej+Q12x&VN<>&jCC2?%QD3 zX3_KLysivq$7K{;s;@&)x2$H(4!LXYo5Wh`VQ;@Fk>1{64si?9bDGGX2b95qoZD(P zcv|8t(%PmM8ki8T-f7T0?w@xvNyGLtlk6#r{eU%DQL z$$tYp+3?dJOBV>_mXv+|8LO0gg9sOli!CX%zB2X!*WV6{!+HSj+8px#{JlgN(rUGY z^v!>8%rAPU59^d1JPa351DD1$xBuZwWLvX|@6RO77-RKD0JT~;o*yihdsRt<(%g)PRpf549>MMF$GS?U2j;R! z;K}qk7q%?nhB4<&DQrB|85&uP=n#vlEmGg@9LxEBpEsU8#RV#8-7+z2mAA?NUh=E% zcdN&AfCdzZ4)>oij4mL=xt09C81;9_dp@wpD~9jE%H$~l{a1|?Gfj+MuCqymUU{+p zH$+TJQTxCdwy59Pc-~vkt+p3gxO+0lhSsfL$mk-s&Sp`BeIHHtwW9=0c4k}t-~RId zU>YKW9ZXx2m44rJXMhzlxOGWgst(2)4|-nTHY@d8h6Z_xM!={Li*$m%yY(GTLbK*N zY9r06cX60DT8CNcJ0DICcY+@2^*EQ&O~_RB^b7eINU9#Vwk_tPiCX$+$VFb5F#61Y z*+H{_#W(sn0*}EQWu>vkW@Qe_76Op%--~741iL|P#%91_P}I%8DsBFdWUtXm`=<3( z8v-oq0{a@6;@^37hRXcxprNLq&Jln_OA9UknP>`Qi^+bE1bhX4Bk}C{M-s?y*i%x& zZXv)KLfhYIszKJPX>-F3;#Z?Ez8t` zA=Dc1Me|5;9uY^VC>lhr(~VHHl2z!N0fvrn#{isPBIJ0VOmZ4Xt24SdN{R1bvF_ZT z%V{xU#975s-)@~`HUYiOR2rvkR+2)yLKnwFuYl!#MDEJ7Zu5_fHQgo(utN}eGr9#y z-`vrt)E3z=*JawZ1#lDzZHeWUYz!l&a|T(8640JjUtA$~zM-@FNIto9cq7V+8&B@xIB*$j1-13xnV!kY@BcROiY?f#X3Gm-432Tnk| zEMz$;FfRa@g;;sN9YNb3j_SPB);$mE4D~c=FMp!efw zlGPS~ZKqZZPJm#(#CEZ43;^H%bD^p2sWt8%2+-hg%kQX^Q^0N)oiRMCN z1tq#%f7Cq)*g2^D*uE$|PM4N9jW5k&H-Mv9#ruqeZg2NVIBpe>AX9u6dm3GX5;OAY zN}B}m5}Wg~vU|@QWFq9M|CvMy2R11*va{cLPW%bJ?vSokX>#qY;sw^pyYjqM02e#2 zjlO7u`(XWdW#<~`2!3lq<(Q!LyaW6I|Gd=kLuE}cmw;@U&$kAyz4AMWkFGYs6xnLX z3VWCMA-C#ujX6HSlt~uC2r{~LR+oAZgOs$i#x=bk_2= zf4S@h3p;raVHdXlE#Q&<|D-@%w!M#H7lJX`K5L(Q0%)Y)6PF;mJ7}b#q%8F3*1DYj zQ@5H3E?oS!HIz)=i40P>C-1|_?X#EUoVSGq?URI_^$hN%@tV@Z5re}Fjk|@yb($2n zrBd<#O_?Sx`ykPpW;~~f(P$oOZo++dxnj4k#Xv>Twj9ygl5y$GCW7X>YG@bQan#0104KJ+ZEeW`WJ~6 zWns5Q0jl&-YAfj#H^f951EntlgYn;}sE<)9J`x?6BgwR>F3?=acE<@k;pj zKWF;>#+IISm^Bj<4}i(5r*nXIH^-KFtnvZMU<|EU$}Sg`f^zIjOdLQPSidT-e@1-C zQ*|np$cTF`fjSYxT{6Q35vuwQB@>FW3zo8CrMqP|=?2i8}!X1EBw_RO4QW;w<0FM`?wrNeC(>WA-m@c+MY$}WG z59Q%i__Pp^nq2V20GHjnP{2dnTN`7E?#+N@ais6m4t4k%%V3UEtgo#>Ex5Cj5k1|EasFt-z(8Ajy!yStLw+w|vLGbkFUl zIP@afxc2d_Pj_;ClplPkjHmDbx}#QXVXb8XgZ0>#wB!hJU0X%}TA~c&`Bih-M;i$ zGwo|*fP?7E4e{c}{6e7m3XFWr!($T=A@HZ#Br7UT0ne**iROo&uRLv{i%M%-8Ku^G z_>u-L3{8>)9xv6E(_%nlDGDl+3^i}##{3#`#H93(lU)N|s-yC@_2l}oZRc7d=lF)b zid2yIwvLn6ZS~C1Faen8=vAo;iF()8w6Jp%gidy=0c{@HC*N^7e5{+`yUVPGAd$8v z0GsYTfx5h`E%dyHHDW8wT?2gTUC2c@xe?oUF0E*=!={rdeJ|s?+vaBV`5i4c0*<;#L!ynnlxh*{>s4Ai?=coI=E2+x=?O z9_ALsR?fERf(4tz=zusvDveaASFEaP@d~?9FY&V;u8%>7Ap=P}yH}{_38}N5d1f74 zf$?UZQxC*KUSKuujAc_YBcm(oB#fTLEuVp`CfT9&D@5uHN(a}hQO!vgT`rs#Ml>xsB;YOZv_taC?kV~UD>?i%D@|PJ&RGHfr7SEOd++(w zoYsgc4zq3Xc#G80ubwBv-vW`cKYl2}Id3+~6? zPFfuP*C(kXT37GW;M;BV-k#ph!B4;0{vh(OKab;m%IcS@dV7Pshed~SxhQhd58eHSz1!t zsjGQCx)=ZrpY5$PS^vjYxt~T$sJ=CP@JXRR5$;S0g~kg-ssiByuKjZe*5G7p{%-ZD zp!E=h62mJb&BvjX4Ihl#K3ehpNyC?!kZ~mVcoGEhW4s<; ztlmn2`fScZ3g5d?qp@&LUN4o`b%v%NtjDTF?~wd= zHi%2hWZ|u<2{?5<2)*WjR@!$ooiQA+dE)haU}8RQXL#5$luRE~3vJ*mR5BUZa!U$h zX8f7IC*PQajvaa^9?ix8Mqn?k z&vW$WbGXVUk!m+T5AOWOlZVfozG*CcB!KMm!&OR!jVkLQVY2i`MTqcIu{d8Xd8=IJ zx+UNw<`TS;IRS%i%@A;(M<*(^rIjyNQKMRC<_o~Ir zt&7m}-;C>AFoQ3|owP5AewV(-L;$CQ`)&91=d8lxj*jK%e$grQrB`&P<4;;xyM32U zUCpqT20*=ua#;Nthm0>&ldG$%{84r2^l00=36o<3J-70HO0Vz8anY7VQ2Enn8v3GU zrXv&!z0l|ktauP_Z{cl^y@4vobK{`7@%Gz77qE-Q!s%vRTH5nn?V zg)akrlFVOmPH zT7Cz2A>t9c?9lfM3s-2o{GVtk%1C9E+yFK4b#=$%3hu@nI0mwLxtzX?HVsG`Z+6Ck| z+1Z0!SlMo$7h*bHdnxl%^xpR$v|Xk*d@e^mX1wo@&z(OUXCKs6apGYSVDI!G zC?<%{Sf}pDwf`l}wMVP&lB+94ZCcT(P3$=Il)*{F)^-tDCwb8|&3kmJG!5rOJp@#3 zclo>kM$=X`kE#%@W}IVNYd(hLMhgX!Y&s=!6N14`gj3w-54|QE?01Cjul)^ zuFun~@VSwU;lIzf^|{g7cwO&(A^H5c&w0i^o@Sc0L{C)s`s2=2@CEzX=dMie<5=rQ z(V3Ir%hQB!^pVe7MQC=|^xN~VY+p=;_x)Z}-wOj7(+>vOl%KF2AMi0J&YLgiG`_E6 zX_xYw$1&a7H@ve8r0&I&;IM#nr!61arsnv}&6h1MeGqZg$Fo4EZt^zKqmc`Xw@Xk! zS+>)Jk?_h(DLql`Kb&fhk$8gO+!HdN=QIm9`hY(x#%AHl4zC4^DBJySLEBU&>`!4y zk1E-tLq6a};f#NC#Ex(lvy?UG!vH3fx4;PBE*w#u5Xv5(umNH^xs`AqVMAJ}`3nDm z_~%%S94Gp=Z`#SR<+`2q8vkgRQag=PdTi3ow$#Fw!8{iY5wUVz^EkIvR4~u=KTfV^ zeSb%HY$~92Uo6HS_|-#yjb<=IC`LF8WF!(TWf$}=zW~Njyi&q`oHZIxDMCy$+I0LR z)K9lVn(845>D5zKe`5lx%mob0cstLx(%lVK>F0AE7Ksz33*-}X@1{meVYv@K&WC!n{W*st9=#L+-;e?*fwi4#u@ z>Y2_Rzn0IQbJ&r$qUOHu~#xBRgrC(>TS)G$J>qRhW$^V^^ctEjz33mu^N-x;B@ zKKm3SqF6XVK0A^7Ga^-LR=u)%cNMgG7N{&OO~5Dg3B%L9&q;oKpDD0Bk zENkfkVXmY(%DY>-?Nwq433tqOA4Ke6jcNCg-aWkk!eu?jewlyk029QhtT-DAwI5Ot zcKoKRDG0R5&HfxNnC3%gtj&ed537>(E z#l1GiGsLe7O$xq#xn#p&Ai38ZFHC+C}rd2DY{i{%g zI?}}>T-P~g6kF=^*3-^srT1T&co>K z5Dc?vDIzDjBDvf_^2XMaPDx?O*S@Ns$!&buw7?P#bUZ9jc~JT{+xE; z9>3%2h~db5M4MDhR}PHPG}hc#$koc^HCOI{sZ_(NuevEgKaj5x>Cef0rkSV3nytU^ zobie=-qJRaU6zoWo?+!lGX-Vs%^?+KCvF!TWf{yE8 zOcGt$iAzfGI@4Z=d`2y`4UfCs_U!lK%89CSuZwpkpC?R$CcfuCY;!MFuPZMC55Hu6 z>OX$#OuW8_60dwjp}t>yc-)Q(zAviTUKQE4y>aUKSbbc)cB@@$d<>5T_CqxU$GoS3 zwalL@F8LrQC$PvqjACK`C@xO{J2Q@aq*7a z*2>g=USkS;-+broblJ}*d9m=3S#$Bcd#|c|e_|3uGp;Mn%Af(2x6dWl%R4{DEH8=b z*Xlhb`49P&jGJT>GJ$tznqr{!#V6=-+l^{Svg1HSRby#neU0;V zA!I0&C3u&Gwvv%^?z!p9HbrVz7=`u|ostA10$09P^yenN2HzXqiiBgf`jNHm`3Mb+ za-Ks0qc)yy({+I2_z&5a^g^aM;GZSAd13Rm$2#7794sJOiDwhz(gL@iOw8eYFO ze;?PLl$9rlymiF?X+2;T%sP-g5g>}8&s|VfO5I!lEGk_E+%YpFi0W>3U+s!;^=TCs zH!(c(ZJI!2xe|U$3S>!#(L;L9%psAW@&vp+y{}t~U+BthAd2hdt+G|NXk)0iEG5^E za3~H&&RzJ5oE_h}@EmhZx>f*K-kwSl04zjBf&!~dKLNgOqZ!_z&I<9X6g;lVX9|;l500`Gt)E2 zMeNHh=Ba(yJFls#b2`$nk;NW^b22~{z&M8Teq)ZL^p>ZVKe=DTI$l&x2UVyVR2}@0 zLY>F0FY7g*^Cpm8dC1m1F1@!RF#tuj=eFAGHJCP=ZVVLPTen5eL!^A7lU`hY^!^BlV|V{2^2AY;W?SKp^@sX5hw> zQ3T32S9qRQPU4BGnY9r2(?uH9KQ}}g{M(FQCx^UNGF_X}J|1lio-s|v3xjr2QO;)N z3Z=e`b7);_#|?Y~ERw!X2eEe24!@GM>L3x!rRmCon68YodYhm7zgh{CvtEDmLFTq{ z+U}WBO1pfu-#jfiZTf+RoUEWfR8LCxLfv@y)HD7-1*c`_R(nm|xXYbWUR^1Lq|Dn% zi83Xk8<6qF*wKX3@MzLkQF0`nLglma($XZf3|WW>VAAG}-H?KQ&HgN$lj2i3$i}gI zh;w1HRlzE`f$UBNm94heG}kV0kb#{_IO~tkxOX1ObR?af z?Iyy^sL{)K)*rbpgfPDuq*QyIRQw1(nIZ!tnWZm_uh^JF*>EjtFrJPPW|vq> zPa!bPDwD@z9#liBch#!<8Z8vy1W7p*ooTOk$&C@S+f%Z8qvF=xx9Q!NyjXAXECo1> zuq#BC-^njClqr)O_$*-=9ukl=QUv1Tlej}; znQ`^@OJiSA5(w8M5^$DWz8l))!od)BEOU=QPL}dUfg&=4pZoBBizor9c_bv0oWUK< zd_MA*#!TK^+OZ!){9apY8f=;14-K~JhGNfo#fc27zz5}qMiP9#M~eLl&zSN_AkZbg z0!}Z?{(~)brw86^7D_Wf(TchRtNXrUQ`uKyffb&vUDX%7Dk`xI8S$sIOo1k4o4dca zKG-ry8NX(e>LxNqgO}x#j60_A9-@U5&2fdCAFnY7ilHpIWE%BWvt;$DG7nfqlLcXA z*HXgDp4JrC@*_;IXt6>F&y(g{@rG7T5jq&@Ihy73R7xb~jg4-ibgN+qd4O`h)YAv6 zqB5wZ<~;XxtR?d?i8=143rrH5_(~EFAYh19jS4e02QugTtqiRdz)dTJozTuRoUNFt zPD^92nJ&hQ%BO;Eg)%H!QIz4f^veKM5!6S>Ljr=S`Ezhy3&=$@JaP&{g$~9#^2sy~ z6Yi_SJyHV72J@p*c^-5JH<4c z#H9ciIfaP;9%6MwC0iYc4&`o-H={+s(rr=o8d`Q04G6E?WAt`oUsHGamK^}hBB}j- z)B&l-SvC;x>y*?wE9(q8+gWsk1d4m_rvd81Z93oY2?L3F&=9?tL1Y(4*0+hH|VVnIpTw_2T}_&i?MC z$@;<_`qD+3?P?0SF|}O;QAvzveP<-_{o=P_N6o1n{(AIy-1h;CSi^*D1(0 zbwI8?C+31)m%K}cl8w4k7{{R-cPD3bm#}hxA*H9SsUww~dB8?g+w8Syo+aIE*4ZI% z_&IoOQ$!Sgh$_j$soI-)NoGSRk0<^YRk%a%63ze}r_dr{?6KFsh8r}YmY3fef%ogY zq%VVp*FlqS?Ohj;Suua{q}>U9-}<3$DWO{Olm$M&JsBL{!m`;h3Qdt{N!(D7DCd%;FM?;|sm#XsmS)l8deR5+6JigRT<@0{<3t^yx63Ra>v0!lZ1=%a^8jriYV4u!O4|k7O8GE zPFdZYXZrXUL(=?_%iL+(`0wFk?vjKVQ(vVSY3B>?IZqdDf+cD5h|Shu4x2s!TNulp9^>K*>+@|LAUkL_kErzek^<}iO!Js@oCdF zu$vMwup0WRO2_`gY1B8h+OUJco!Fc?`T*{zaw%n`5ZJ}wR--tajH_Mdr`dNJStxBX zo=nIWB`&zrzZX@6QN;)6bE#$1r0(m(FzdEfIP!bMN*XbUA?!PWlv))|Op}or@Qjd+ zD-8YJgZV_kEo&nG$_>#3y)fib#Swtcs1}DipJgqJO-3gvCZ{gC1Q{6lc3e|W6%0jr zDAl?tzh6&imVn6<0%hW-6mJ!z{s8tU3rsHQZdg^Q1?ywUVw{B8S!x~#VP*Y367B1g z%^XDr3uRI(VTvgYU?rog$P)ybG3zNo%1%u@u(sk5_nI>192vYMWhgGeFnDT(;pIfu z64r@m;Yb=&sZcQMLgtuy0zte4G`8uZNEn!dYcI8d3uDg2oqz3QF!!&9mPd15hCpel zzknRjCo};N!5b7K_4X8p22oAJ6G5fVqGhS~Wk)8O-x}+g4JGK@ekjq)X4y(XJN2gG z7d)BYM!puzU4_>APK$Mr5tmf$i1r{z^ih7f^v=2r6hv1Q-4B?GGN~6ehz3Vj{GY|W zw8o{|`vB|+kA9#`SzVM>_d!3@e+65<&OFUSG9O8t&xi_%DyNR&Q7o1$b2R+44t&+}8eSK%; zOdWy+4g!FNO9U{)Ax;-Id`c5iYtaPG{GlnJ`6xg#n!MWK)-2HoR4g#v+8_+kpj9gU z5sJXi!Yd2;B-lVHuedzL{Tt_R(E$(rv@`8~no|~q4%a4@Ggld5H+%qV){v-@6r%?A z=M|k!LlT`ocV4JwI#|)l89C$S>jig=(lS z?&ulAP*Rk%!bIgZ-g|kHyfBJCDgKb;BpfCo8n_%l;*;Z%9g&jhiKyRjYZ>NRL2yR; z(P8KKvb2n+0(Eh4Pt0dv1tpJfQ}as-qQ8#!UM&_;YA;kz7=dPYzsyh@$+uSO$sh=pwc&3n%&h2fSX!6zL#jtCH8$!~AlKAkbPsR6eKk1}SE^ zRG8;TMx`I_fFETjV%R3DFJ)}1-@(bXDP>R`oqNXQPTw}0%q~3L{UZ}r1V{ar>-(Y- z-XwrKq4d*RNqL@fDD@Bcc>6ZB-*&ArZ;G;vRrN&I=6eyFclDjWMYW&;E@B?Py_9yR zm|&=W9DEEUFV2?dLJW_PJGF1-_hd)V8Cuu$As^gK$4xuF4`$nEi#hPSf36gxP>^w6 z@0KvZm>c^p&(pEdNEt=LqexXt9q=1F(FJRAucRy9INw;BC= z5Wv#M$XmrwdKupb6CQI#&sN-~yW^+MP5JVD59&A1@WjA%Gy1$vCsu!(;S2P^J^kBO zu@vFXzz#VjKdfgH8vj3(cwX@L+G!^Ag3bN z_^4_3p8jdtKl^{URge&J8rr14F?KOr#%pDB=3gW|fGPHUb1zEls+jukvnvmprihEh!TH#H%&^7xIbKy8ot4drp0s<_2*QhU~B|%+4FS z>`8uk8KS-^I{JIhA+$}F*lJQ^K^zV04>>82sIblb%?WK#9AQN=Dwdbba(}6I2N9-_ zhWs_QVC+|r8y)KxYA&n{U*a>bH~Yh^KXwKQmlL?%CGxitq_RJCPJ3;yxzp#*`AI8e z97e@aU#__&eS@!_nO(3Ws_R3{OJCcGwJQO5!5bba>1C? zoQhoG30@ienQ5Eo-TKK0plj?4d0>K=j|v}Ic&W~Es(n3D$OoF#CO(9p8ov`@>HSz` z1h3uU!;Or13S^G8Ey%fz6b}K5>hZpETD7wBHXkKr4`p@iyZG*%Sqgd%jDrR{Zbng0 zFNSp+@B`$RJ|P$8-&0XPmA`~D)Y$XQ!}BlDF`9z7?E0>s6x75t%4rgSgfvXP&jg+M zbZ_MeKQ*Zj0Vzt3&|`+epWncc=5udD8v-kYA_P|uHy zwsyzr)1LQ3_j!+(2LKhy52OxOt{U4aX>kSNAA!Xk{imBLES$p5oPQs3iIl|ix6!wWLetP3 zJT~9{BG|Sad-x#}AJ3^lifxEmx}l~^bDjYV@b;9v!pYjOIv(Fo4hK|U`;BquZHgz4 zL~(3bw!WT)+~D(O7wpw)c_EVBYWe7JwezR29``8zKu+9GWXJqw}h)~CKqW+V1T_;+f=_7_Qi^)Ej$8%HxOcY~8h&q-3-bEuN1Kf>tP=Jfm z7lBRr>EC}%1y3+;e~Adcr3EM-tMPn+wi2R~UY;y(pGXc;Y&^_nH#%`rPk)@O*lQ== zKEX0q=@4bZubJb)_ySI&M!KVjML5Kjv`yaH%Z<&)#2TwbG*!vL;klHoBkl0X`VgNX zA46iCPEBcUG8mbtrF6C%c)b0n;w-_uMV{xJ7l}Ll)$$5wBp67QV<@wCW%V8RM|&vD zN>B_wT05u!s1ASFlwtj%vwLKyKj%Lo6p?18qSRj20tIR=%A6+r>b(xHmhaseQq1a#`aV4k>S*pZO4_P)I`cXv@ z|9eqQ6jJ)F^i~+h{R{F9O;$?fQ^}N^Akid+&0tuBapt`{|;+ez*I}yzXmr$i>{z=OQnqbUA(=TS0 z_&Sv*MxK%p7HrxdX@3E#9^FQBu7)`|6bmv=OzFOTY9&X^=({*$J~LcETtCHfRR{5}nq+(Myt9x~H(PaF$zXa8BPgvJWyU?^h5b*G#7Z8Njy>>(Iwx5he{GGis{)CY^s zJDXBy#uY>nn~61x9xFa4LT%NrQqz^8_G!z+LO z9{`O&a=$BE5{KrC_>fiP7x;*GaT!JBxGPu~KJes9M}X8XqFj9DCp?&@mX|AC$;%R$ zq+z|UbdYW!$;tQ*T%!k!ySixey*(K8g9kT3VV*?Ttj?olWIJJ0Uq$l1HHCx~UYXyu zC9Nm}J&g27w!qh!=_*sAd0cX-FphB?Gk!0ue{3Y4yv-W|IRc(f-N8Kc>DAWcj99NP z(YN{ zDCbF->*R{XdvFwU`XQQ@Ckwvg$T@9Md=3_gJPQI(qB1R}p(T$Kt(9prS|6lGUs~Zf zIvhX-_!|`V%Z1Oa)-mo2s^~fPxEXCL2IcYs&s7BoHj!3&p8XI6q?<)dOqQPDBtp_Cd!WxK{Y_3!2J6~h+oN3+mG55o4zV7m z5M^aUG`&F)p4S!VqAn=<6O>BfsWdB=rUHiKfyF{~jdfpmS;iBsx!^&C?>GhJ8?*d}wc@S35O zbH(88QhEy8xo*e*J}3Ams>YqI=jVA<7OL6vbu%2X17y~DNd#-|wk08|<|D5|#R%3J zq1Y~a_}x6JBXeVbWeVn7IX~?y7o0NH)xa)h@r2`a1gh?I{W1%$y+H}s)K&Q2(E5|z za@nW!FziaNhQZFYCI6by7Ru=;RZ@XK%mazDwS|bN|^t-PyZq>jf)6{PYDI zR$cqp!}mYC;hzc@z3JaBf9$mveg4Gj_YC>|5zh7N0$As{XeWW^Crc;r=eD3Fjbl)o zGdu7~fR2uyC#!qwnK&>nI<|ZmGw?4wS$8=aI`C-ya$FwRZ3q$O?Y1ZF~=%v)tw zwOTB;)=2e<&WEvkjtX^i;DUIuywL>2F*)^#`oeJ#*Cp+Lhe?c zuh<1w5ACLTjOWsPMv{l~9L;>j26A}*FTpX+{=b4L$tcy z)}b=#CSRKmnG||>dA~!!@Gw+|tJrd~<^*AlUM=kCrjB-7<;(DJwK`kvs6uA8kO8;q zzT&nyJaxy8Ej@ULTx{OTJn1BX1P6LAyeLYvPyy@2np=fcKw(Ftu3DjM_5cqIr&5 z?sn1qM1ahg4%hZ~G%iIlczwk6?;0Gh`09qe+MT-5T!;31B))T(I2Z5l{;PH;e)}#V zl$HznyL75Vuzb5MX%GARM?D9QZ9v!phI$?`qHD5ek#|^91XH%;xk7K@>vPP`zxv6D z2gIec4qbvS(o07gL9tAbkLC1n%W+oq+c#OVxX^o=Eo%?!A$~rf5{aq5m&?;kYk2hX zOTGYq&kKd}UVwSOu}>}SF&+8BQ}ujBK4$RX2K@R($Fq-?QBMlX{=t?sM_9f}twhoS z6$Wc?0n;?54l^=R>3PE&JFxBP~w+-HaNST0YQ5!8`a{q@diJ-lcBm`dV5i}mh zkr;tU{!hOHqtJ2)0uel3xm?@2b#ASctwff9NibQ-81*&5B)$} zL^#5n;%G&>BYYj2beAZ)m)nwNa3dK1jqw<2LOY6cLz;m-$|wyV0M9MIY_ap!LeQikj*ra`?u^=JNuej)#I=Uf4$lb^^rZ7p=^33*)KQ=q zr!JkTbt{;D2HllpOfX0jSEeYr;0aiQPw@5Y0DoMc3v@|U0lpQcm4dH}w~=59HkT&$ zdZ2i^Df(vcpfJ%LSs{0W`==yqNBK(z_keSPYQ)Wn9??#=77kgt;Ym&*D4Te4+kxTA z924Scd=D8~fOihBeBgL|9m|}DxSV6WVmu-Vta-03sYBI#3h18zZ5jPqXbSWRpvcq_TFM|~#-G9n zcSckOK+V!p9s_#vsM7IN1c_S9KscyxuR?0UvP=0LcRT(aS%nRQAY72BpDj-c4tPRn z^@_d$vYr8#=Tju8R_WbmOJcUc(Ao~GWDsEEmU}8#X32o&wsFq^vqw@Ex%k`yt>;996eV;{bG^?`fl2BMc70HR z=iMUx^H@FtUaokVN1NXyh9h^{k`PJ%;Q<2n8Cm$)Qa^=+(jC>QGNdcQcf3;^%;*9) zrbwbQGa^iA;OTJ={pY#fdek<22KY?@&0KUnu2)RSxE`g>`XTxof*=T+&!}#>9OlgB z5o-`XHgPOT}TLlPyJ9XpM`u;ctv(yS|1{>R~s}KTcHmqr*^_yL1LlkDqfLo zkTw#mrCjP9$s?khgW6C)r9C;5_)`vak^{69io=Znto~VP^wW5!!s)An{HkxhR(} z09esIO|SJg7K>knO+e#T6N1}v9SNOxism7rZg#uQ3=3FOio{xDbRd`KI}*O%`;h-~ z|D>ZY+OYBrfDKcVSP*qiP}vne>N=s}K(Qo!&@|sI8KYQwnd$Rtm6J3s(KV7D) z#`JRk&Yh>{cYWo|sXzI|a{m+8UZ4H_A5DngJbCwrK7aa$#io^?BAt+(ysr1=Tl1c` zZ0)X{XP>q6H?Mp5itd|(sSCUZ_CIs~SzCVoU*YwZK3y-fB_TDP;IX`WH|eAdon?}j z)iu``otXU>Rb(e8@BHBYb+1L8RCiwT!OiczeCms*PIc}6a7`y-`V_o=tbu zhdz9BZ}tZr4_x)k{rB$thXj>ftM=QH2J~E@a8Hf!*OJ^?+8Lz?$L648Zmv*p_wz<3 zyX|>$=>hI&7t5~)(MRlZccH2o^SVt7$RpM2Ea{|&bTTvm-fLbH>ZEqBd+yQplIxv=@o{P|bn`W7XUJsf zB=;#>(!jy!1h!Dwg?4i8U^SN|9Iu^do?__UB`kN4-e0MP`Hgo861dU$v9gXg z*L5qQ{H_^E&gfk;n(K_!<||Tg;>~(~B!&mam9M7$iqZq6$1utHtVGb+a&3De76*q+k!dJjqpTuPaylWEs5jkZ>-wKN7^N;7T=17v7{j_RneH9Bo2+m zFw-B=pW*9jg}M&?gA9Ecc1PSKbx(S(wI$67pF>aJLDuB0IPh~@7b_YhdCeY{`O1Td)Wk%^|YHrl=-o)aEv7m;H^&mM;F0wq)^eOUgX&j0!y% zQ=6pN54M#ua^M2`CV%}=)Ih%=H(2a zU4T4te4~q6zK8i)wA)#V4lW-pw8_x+mo!zb6aD^r<#|TSp73Q3#(0?i7+-S?Ch4|5 z{w)$`Kv~oLlA(vjBP$*ud?VfQW)N8{?QY7VF*s-{op={_(52DyWI(P5 z=i}cam2&&&8uWM!*ao?@am*`|1#qb*AzkRFmF*;;L7_DZiOp-2;nAb2KWtBFX@t^_ z3%y0NEKbk~laf4ClI1*JG~J`;!SkdZ1Zk=*$=8xxPX$tWq^<;U#E)zVqiQ}>hZ^9y zZ}fkTE>8nyI}!1BBzi6*gy$+A)Jn`mb`rA}eA2^n6^F%)Gf}~SuN2wCZbdWpav&7l z<7S!#A%G^-(Mc1o8l6zt-cPCt)OZ)nCd*FN#nxABfd5COQGjQ{lQOc6Fe5PDT@RxZ z+z2!IMmpLsAu1wVo1+z?o69ZF-Hqy_tsOIbJIVD?0h?kIKzc1hC*9XoUbfrscft1r z?Vd>lj*2}*OP|%}+maB$Pq2u>6H53Kpj1}5($zIBE9XWCS8DP(Yx2~;kQ6Q|eLl@X zuMeM!zR+e9 zK=4ntBn1EOsYRr7QeegEyMmO0recKbF)AvDw1~7grQ0BU@ z?V?fW>vqwgoM0eu;Z$n&^s*zu-3me6wLV^Ddn%{UTyyGG8Z=DevDyXH28B}fP zeuSDIv2V#spA}prwLtLE30-;>6+_t`?P8%MGo-%(YUYkESkAN6AbYT6EP_joHPVcl zaQKSTSV(RHhhEFk`f33cpO_AK-eW*Jr1CRUS4AyxmXF(#5YP3!4txf^j9(~%EEF<+ zF<`UNV5dMsbApuPg*qv^@Qvc2#*xMck0RQ&M!XMxqrY58a_Bl`Y&#B zH+N#*=A4QHnG*%gg`ZgObmsk+Q(0Cx&0juMa8DDzwRX()-S@xuJ!`s-c#A9Y%LlWQ zmyBK}2D>im69Z#K?q?_uqXReBsnP-+cB-ul!T^$>$#bgOhr0-@kL?t`Gd?J5!(ia`o~LK5+f9zdLpJ z&R5=j!(;ou^RFk~|Ly8O?EA&P@4WcF@On!h_kY@wkSnk8x4msJ_@n#{{?nTWi|1@Z zoot4;uHv$)rW42LWEqD^C)tUg76*&D{m-o2fBIFM-Wgsm)X65_C!Iv?w^Kj*;gv^p z=Q=*|-;aIbzrOm9ANW*d_RG%Zvp@4h`RNBYJihTaTW;UJa^uTB@U`EXc=WtoJ9lne zd&?8YUa@i4)$8`}yyWW39)J6;AMV=urky`{MR>iXkMlNLa;PZnIP0~iRWDp{%;@~9 zs$70Lj`L*c;!LKew0-#W(`g=~9&g&yQ!4QY*J`O`d?@4HR-U1~RWSHWIMXp1Jb&v~ zmv+3aJ)JzG$HY7PohP9uvw41Y`(D;bhx4T4RQLAu&`z7AvEqfrVs|&T$}>GZLqnlX zFy_ApPDs+gm190+OAZyK(wS}Pq*@*3y5Px``&SO1rFHW0kI&D~?{l7f^2zF>Yu8?Q zVJ`RG?~+a~ym0N>y^qd6mCK!Wn)6-fzk7yrk3RV%>EydFz#8u_6fb_+RekmF(d1&@ zV%hcVvs89{{Np@(k#@+;b$3&VMIl{w(QaE*cCk)?=B`lLm8AJ6D_hR>H}eu3+}b=w zGkC9J-Fr`#2iHQs+Wn0?c{l&9OHEy>uPV0blw&f05@` zt{%C;RXpF3TM5#m`(vNQo-etCS^c0b2{G?Hnz(u%W4M1}AZcEq8-=lX#d9RLV){PM zytUMF9zaUh@#3!}hjz1k8>sx42kW=N^fBaK3DfTw^Lz|Hk{??(K;dJ~_u%*|<@BcW zy9bWPbetZ;m@b?KkOWqpYfC~-IAQ8zLt8pJhKKKX^3@kWvX-NwaI$hGAXmyt$SDXg{=ymOl>FC-BnSZ}T@(ODmd> zZQ#&4XM3rbq_Qj1a_zwrPWaxBHg4Isuczm;|NZJ;pLW_)TONJ*Tfc5HpUTn+%;xTM zs^9%hrswr7byBL@I*CuY;63X2vbk#R(V+U>;o-d*z_!(QdvZ_KeXFLL-FbZ7-qMBD zXwS5zPv%}*5>awj4HYv_l}gTAy>DPEwV2Czr#6|RX6poK(OKsd5)D+tnF=+yXA!fL zU3_M2u&}7N6DsV6_qt?Vv6Vhz^q`t+ug?-d(6T<6t)Ba~ji?i-F8}Ri-#YEI%$D54 z%U<22cV_EkcFPtA{sQ|N50kXPPAG31?Ib?MG_(`^?{REbJ>j68z?`;|`hEz9ay`SP z3u}7|rlcHl{H{Nf%im;67E9fCu0sb;2&B(5121VHg^A6u%%wC5!G*rh+p;!^>e@q`8Pk01(*4sqSkmfl zt>jA(wd`Q+SM3Rz6xgXkk`(WeR0gFuhx zhr=yQlg#sJgo~gN7A7Jg9PD1@4Jh-2s8AVai8RvULM2S#4si1D$?sR%75XS?!h_HO z3et>XL6M;-IUMyVTe4VM<#d}>FC{RhBlRXT-Vj)2l8Ay{q$7Rih><6XzW3Xbro>8z zfI@;LTB=8%)>6=bdcnCSA{kL18l!_b$*0KB&l8Knii1lo4hgapQKw{%LdK;w%A}Ah z+mZvIpVpxMDK?oj4pAm?Y~V+2Ok29i}rQ&@5`yj_4*4n{b| zT4I`ok;5t|M^#GF$bQn6w1uh9HO3#xsLmBNJ84k`%g{5(8)^%mN-Tl@io6MCQD0V& zuJz@_n0cS?@E(QW`&xg%*BaNpM9_VzEm??$=h7C0;d;59Dl{-MCeUUSE0!#b$v}_~ z%@U}NH=5-`f>>F$B~7V+)Wf<&OKV3}3pUsXKie@H49(}>BklPlgowwH5Km^aQO5Yf zi($&FFPa)+N=iyfN=iyfN=iyfN=iyfN=nL0ft3rchhmeJKyP!+{wDE#PyG7u2)RKl zUc34#HME@eIf=W`J}6&WPWz)c@YXOsJWua~;+>LxqpXuJeKLD($wJ&E*fIN?#P>tt z=|%BSIcW)TaN1*e@E54fg9{wG4{Yahw zergNaK-hw~XwJB9BniWH5<9v9dM_Uf#RK(&UqtMf2##zyPwN1P(Bpt({E;Z~93-SG z`k7(IPEFd2<(?ifO!FUU1fI)(0qu*Dpz*>0%l^ccEROgCTaTSdR?1qm_SwnJ*F&!s zFJo!^`1RN)qu`RK^I(U)huC$t9bOo13dSIKTrmA=(754nTyXvP;P4!sDlr6$885te zxSrNn^+^q%MgS{HXdZo`9ckhj+VVu155}~@ZRD_*4~e0tb>U-(kNcJSNX`iUXx&-x zI0(iHHET#BJC$=p~dddR`y37sunGfjJk|ff}qn-l2R2ZE*1m^w@ zX%`hRIGUpNSk0}JIYZ&OO5A}b?V%w5 zRW1lAOu_`P;vQSlifFtRmKU5e6h=3`6$%BzY*doY80+OY0rl#P5%^psgrV?QCZA6y zN$E=%^(txxCA18yzLy}2!F#xTc0bFKf&b^Wq$R38SgTONCqH`jX-Zq569@=*7zoF% zy1ZsY%uaa14_OOAC*{fS=rmYPO>?SSyr6(F9g4)Gbiz5n1~tLwMFy1sj#}_NkuV#PU4S=dGGERqSc>(lAJUkCz6%3w{UIO<-o%B=GpkU5fe zl&|y-oUWrve@W-$w@kX3Vcg}Hr zRV zdY3I(1hPJ;_~L#qq=jXs%9(1hE&RyXC-dppS*&Z$D z!A;@-oGdpY%4Jm%E?wW%CgV(@jTC;Mu9Re3!E3C`E@7O58-r6;*i?1bp9?`pC{p^T zRK=fm;ieq-?;&iTv7RVN0}_9JuXma9HwmxQ-JQ+Ck6m}vodiB1pld)ED`HPxcTY)Q zP;uS}*DHs+PZiY}{T)l6;B#!s~h_gJTz6$8*_*I{E(c z?6%E*@krJY@K#Qwtn#&$>~schTE!}Y-HQ4ziguUN=^D5szv(;K&BtE-hnHOP^i^-$ zxoh3A**fbj85Q>|MA~H{`bFp>WA+?Z){UV z-P*Xu?viEQHd}JYsI75(!2Ejk(5tI6GsBpAS5?kEOdADUWhH5PeyK!qKJuOdcKp&M zv*0(agQiWLY#gfovQ#>uXMTQO&CNahhSF8Ph%YuwG(EpiKzXL{2D(r7=z#${e(93A z&Xyc9+SSSX_Ttli53jI|I(c}<<+E++h1&io^#oG=_A%beQD5rlK9ANHRJ?D{ z)p{QlH#|SQZ+PC-vU2rF-2>;+edxZSeCcy++hZhbGW!O$z~13#FMx>Qp&=}8>^h+( z!^6W=HsvmVeD6a&Z-DblrRslH_dPSO_mm6wHOXX#hiRV=E~Dzo+v<}&Yw?_><=fJv z=b+cCe`?>3EyLAngHEc$v@gRVbW+tiA%D-q)m_DT1^f0@vEC+0ZNHPD(~1|;t}Foa z`$8E(Iw|Z((*7sTmuyM9WI6`2Yu7@9PD(wL#XtO^EpNqM+O!NRmBQmxWmmV9O3QW) z?|T*6N&L~Tvy*z9p6(_)ERxtzGmOM&g<-*m#{>U4F@sJ=d@ zs=Dh`wSw_abj8573wnwbLPmvp0-Z;lq*+4s9KHz}o`#`O>m|QMfVFQ{{)>?^UGx&mz><&i^{^+<2} z3J*p8mu@;KV6f_dD_dsprh}4&gEzSyVm;&JfI((iIWcp$8`4coQgg)XxS4fhAVT$4 znbmUY9a84~uKCmlyVjK~4Sqvv(YG>PXq~%s*jQAfr2Qc~7W`~wUYLwxvL>7dY6>-} zX6fmDPiV$t0j-x(JE=|=T!l;!Hs9h(W`XH4&4&3-j-VS{x`O(5?3-i>THwHM`if&PW6VEpc__+DdLg$mLGzbR+o8#GB>-WwPS>Fk7$Wd z747LS6jnNvEG0o~{yA4N7jzA9lTwq3SYw0iNzxeYJVJzY7Ha#T)VDdN(LwUe2@1Vf ziDpgbby&cV&x^jqEJK1$1VYVOp*Ve#f(;*WC9R;Jw70YoG&9SoY~!w@!LiyT#0(a< z5raze+db6mgdyLi_N`G61%I zMJJkE)&$bcNE*nZMub6Da7k@FA+?3u+557Q;xi|Y)viPxHwF@5*XrcmV2$TJ*x;FY{FA1UIXOZF7+2|@Od zD`|j?9U*pyM-n5_E^={^PVqnhdDxM6qP8(Y=g}ZR18Sy^p6I2o(~g7rfL|+7A*A5 zewjiZrlyx zZwgA2Fk?#u&1pG=O?sEmLz$;|C4wPKEG@)M(r~&qr zjYHuPb@r!!xK%3uQQirU58rqZa&l<3=N&D0<@@$e$e(^L(z8R~eC$y9^9N-tYeLZRN3Nt5h?8b|qWl?U!8>mv z7`T*+cWF+fckuZaGr^O^+iyCQdGYJs*w?k+qtq^^O_0rGvaAUw>kb`SH}>eWV-FsB z@WJOk`P{QszWMIE9{l^i{JX!8=S>J`G&Vofe0=7GuAY21+m$E(t9f5D8wT@(%9qPx zB-Pb}CD+Lkf)mEcPUK|bD<_VVeW{(uNp*#j1=R1(7Y3`p{mm-PgP->`v!T11uPbNY zGdo{^>fpTF!#2VR?vhGi#^aMUAgsRjQclo z@^>s{?^hwz{1GvhhV-o?D(Lk2cKGVR-CqMuGTdVWpWF~RGB#XnE`TLyB!3pXK5|gUgB*TfnF4&Ge;zmD22dP&^ zM_t)#6PxD0ufrUibi-LQ)$V5+INA2ri+?5Gt@^~XBK68sPr0(!Cb}jD;$uy9LU9rkwm;6g)s@six`HN>7<2{4t9i~U zw^?KhJz+xIDqD2@UrmxAtgE{T8z5{XdaV&jTElLk*aVGYD-m&F40f+Zde=CKsr{yS z@^Ga0TLqNe4eEVaVzBTvpJzdnDyRED4yl7h+}Qf=sXY|qv4GY`PYk+0>`E+Zu58K? zF*4*7Qo03Hw#euU6VfgjDzs@Ei>h+&Iu+_@zP=-N1I&GCdm(GP|FeVs+gKaEuFEF7 zz&9eG3%EKGxQ~CDX}|GmeJcJ8GRnhsaKAY#>EO{`gLF*@S#2k`>RgGyrbk@KQXy<) zTpgpm&J3bR4MP3dE9odHLf2_#sM13vLvTtJ)zOoo2&u?`_AE*ay8f3dS$?RgK*E?B z9zW9xy2jO?Mr5aSlt(EQYt*~8M%S;ql13<_!Btd5>Diz&a1~a791dmt^lZ%$cLhMQ z92JHtk%OGzAy*v)E`rf5qWKl=jZLSylBGh}$e4}LogIqWtsYQCavi5Y(1*uu*EmHS zEzxH|`n01Khb^cb9@)GQXfw1VsY=IpTuCDWCb@|Tbp)H94Qi=@3LFbaPb!K9PQHzS zs@@tyCUc!SY8uT)$#@^Ar^d92EC(7S@^|x5B&AO&O*pQvO9VFF=}MLvp|dJr(;Hg2 z0*g9L(UDLJEeHU z2J5Ftl9VHc&GQ?_pE}SC`6K3OP1EM7&C$KU^}AkW*rj%KXAA0Irz8d4^Io&yQ~@?3 ziEKq`2-mohQyo!5pIpp)t^ZR1L5}+39AlX&)6q_1Gv9r!D>y)L4`?lqi5N&p^n z1*b3qY)NtiZ}k*LIr5Xlre)Lr?MhBL)VjNh6Gg-7DI`RtYWY^Mf)j@BS6s=dhHAC? zyv~)K6bM(~AkMZh9|d2;PD=W43AADx#S;Mr z>wnLcEhoHav!_)3i8wqbO)(*+ zhl(@}tfHl0&D%%de6-u!B{Hw6+vXR^sJRmNCgmjo|(5TonwWL3X`q{ zY-4oHGDpIg5uxj8MBpK$!w}t^9>wa>An8GqGN3LNMnbKN<4}S{5*=zSX9IglBoXSj z2Jv^k8ikiYII_ONq?%34cKIPKY=B7##Sr*VcsCJ%eJm=@gB}oR0bBSO7c#)G*+8jn zk)EYPq_IT@oqL3;Txrtg-D}e!ih|VR7i^RTCw4ru!4gwqO|r@d(o;nTio?nH<{!TP zN4;HN_6eWXf0h9U9Km!#x`g*kKTQ(%k(YLRhdm3z` z1Zj`z_SPv3%j!NytD@CLRg43vjy{Idc>5R0HenryWvt;~TAkz8h7t5Dk(_F1C|2SU zDn;+DM4;pAuA~v%Ry?yjnBfL>i?|llL7I?s&|f8qzT3u> z$)_8d?3RA3u0Rp|9OY0xucFN)XIqtHOk5(54n1bQ}>dj!AI@3gINM-bp&i<5eMJaZdJzBMp3%jZO;H7w+WP zpXGXa_1blU32z#Ycu8i=FAsI#RkFzG6eD*!#!6mLr0MgcsZlRnrM`!;FM#*d+1O8} zHinBtwei86I?r_=84VnSvM9)rRhXub^zo*jW$?2_phkq!A>HJGWlrhRT`H3$o~8WZOfVjFd9b@T@Ova< z#WB8B=FrNKeFU|WW@7LLSI`s;yZ`ih(c5J>5=L$#jp*#@3e#aFD+MNmN2)MD8<8s1 z29Y=f35nV*(CI<{dTc;=*7GLOMsnn)AHN~cK0l~)azOVr%EFTzdSL4px?oFyD%@!c zO9XlbTuCFWv5{1FK8R^bb1i6X!mtfc`!B~NqS<&m#QqfC=AMMf^i~#l6W~h}9|;5_ zJDIcf9h6xB6?sv%T*O95Vj9DTu+1qK8KskhGxxX>7n%_-#ig=TohmK76yB*MkMg;| zTbeq&A`*Db7*Y8o3wrQg--1f9Ra-Ut^a|S)X)`i`2jz$-sU&1ls0=&D?*i7Lyyew%EsguI>w8ajQ%|SA z!S{m6G3@8^403sZ@-bTErW8mo@CpovI6Y&xy)_l!PZ>*%`2mhidf@pE9OMV;F>+Gy zv@38SE2tUX0ogB~pQzkcNYnlf+&h5Qg5)%=Z;t%~71p~U%Z^b((y&g3*eI)byziBn z$UqmGuI$sC-TWp|+H^-&hG+NPAB2qcUjkWQZ{0jjUO^3F4F{o31( zAtzE6(=Vpv^Iyvif3-k56656a|1nd3VEyKgz2hr?zU?>P{%_B3dSHEJ(;vL!@9)gs z!}>3SvkzuVneyqu!9RHSH|~7?H-EjluY1k&Upr^)^y(Wn{NWSZF8QsOy4QRyyM62m zTVDI4XU=iFUBhE4Ge%@SJ>uhn)m!Kle`p!zRgRog2df0)q?-Q=Ja;3fx+hNXh@8AsB~El> zgq-XIRc6w*K*5pRT&UBN!%9QuqbI2!j9rx<{F$GDIXJoDV^esackk=IN;5*796w&& z_ZMY-UhjL7M-|HBx%@L&j4G$Q`hw-8X}Rr-P49Lk4XD!-&B=W9B=v)xJLkj6`Cle+ z_Xu)=Iq(`7{C|!gN86=l0N;3{-uI-6#*ISK6T=C-kWkwdOu7;mcHa})&jj;7Y15o0 zhU#aN%`ry#0r0xdW=4W1Yx|&N%iOO$Gu)%(Y}XzLZlnRpo-qn(w5Y}$Siagf#UDnU z4t=(57zQweejV1*w!HSo`meYW7k1wh+RvoVXX|ZxPpOQY`1iW`LGN#ZbuHgZ;mx9a z^SNDYS8N}YE3u+?+1wu}k=%da1Es=1pYPxM0l$Fdc4qgKWnUi-2d^DCup#Gnj@*pl zxtK46qS{}@qz~T=2UOaY*Zw%`*IY>htc`NRx$tB0E+}_*n=7iBx1~~DJAo`x-L)g? z7RMpqzVhwz)?2HC`6K0-8EVG|>(-;bEI;!eZ0He#h)dp|UpF}TCQM)SYlDNYAG|0* z_G|5IuhTVLF6PV0U*GsaC|gFL`t-|VS9R?iY;i4eQr_21PFaIfNA~HRQ0h6!=VxXv zi#WmHt0v4}rowpM_QuABeMuYOaxqU%rvLiGxAq*tx-y*n^^eD{+PCj4+5@NV+8O1d zubOMcNq#C{)okdt+=4ivy8mkaGlmPxi4Nm=+Z$cqbR`XNxtK2}Kfd@s^c=z3HJq$| z`wxCFGSbM2wq0E$)tq4U)@z7{=H#sWy8PO~GZhzWKl64>YfgSGL7c3&Yme)xDW3IT ztc46i&-yRMLY+TNGf`AN7wRQ3`7gd+(Dn8Hjj@O8TJHC-*HM`MSL2_!*7_+jPJWJl z&)PQ!^q~GZ6W-^hZF%jFGcU5SZ2_o9y~=+v7Vf{cNl5wCb1fFA>*$|@(x@s=mPWbu zXEbRyXGzde{&Q)xg5{>3(*B9?bj@FJgwp?9njXjdpi?vn1G^?)GSL0ouH=*e&OkB0 zg^V3zGM=b@Fd_4|u4FbitD2vPmwUQ?eMj0TaM8qiwktY+%9Sht!WA@Nad$9_)v#1$ z=uhlVFs{##-)}M0@q}R2k6p>EkWPAX4sXQ;-o2griuhGR2h7Gy+QdZkmmu{1lPe)` zC&UP&gD*|GxS;z|x$R~^t^N!FO@?d+ZbEh1CeXSXmMSq{#*qH%xZ|~G+aqYbCyfC8 zzb20?YB|*1sH%Yube4R0l!s$o^^kx*RC{=_Izwsf5!)t6N7TL>`WjGs3}B+ihcUV& z^uZe=5q>+J^6;ETllFkTfUYqmj+n4uOGyOQeKD4>_kJv75O~0Zp2Xt~%Rl@^KrcUg%nhX6d(hd z#V>nHX&&-W_WG!Mp_ikkhf^tYb^_W5YyU?Sr8y;JH%x`AS~KxZ{4a-0P?T#Cwyd^Z zTQSndbv;Q^FrjNs!MR|>BL^(~q&QEGS6QWjDB}=vG?;i_Fu#-a0QWJj3JU0)49P3p z!$GH{iNuM)ri)!k3{?HxGnF5^5zQ1W!YtikX(J{Nr$b#S8d7Fh8MaE5D0r$l5tvhH zCQ$t=`?!^Ju0k&?`#eCx)gy#ppsR~bQZg~f{%2Q$?Kjn@q-pI`kJKawz$AHEVd^N3 z;sZ&yGwIcA!0WK4gmSi`f&#UU$f)%zvMqf;Z8n}B2!dn%oW3$Zg1V$Jo%jj7eoz$4 z9<*C`OGt$v)6$c)c@SE(X)ksIBmlh+yOJ29)dkcIX=MbV6O@!T>O!h!9PA|&r7>r$ zUDps=V?xr44$6e*pAF6Uv`@{($A2AyY95t`T76xFpaX-Bi?P*r3vFj)kGqn3Fhd5b zP@LR)(6|RuO1hm%F5|f)NQg|9gbH273pvsg-5y{`+VIdHc9MC8Wq@a($f$0Z1<&nxXf$U-p{@Q))& zM|1LMne!ZMg>wTh#dRJQti2i!Z{m0zQ(WS2DrT{t7Bc9?Z}>EILaZrF0J{G?iqdF< zEI_FKk-1j06FRZG*%A7wY++22xtOGy^1>kubUoO*wUAMaN*jmiQEv!_uuSSSk*?Sa zOf`0ZKZ$3GBXSrn^)9-f{3m_ly@;J&ysQhLgaW@8!aNds_ZILrQsG$4WKR7acF$~m zjkd#v$nTfeh4#KDGr}M(O_HinXV7t`=9D00gQBPzEyWVRF-l>=-%62&`}qhOq<%cz zH^QM;ytm*1O{3p+4_<;+>s-#u@Lnt{#9Khp`a1!(G1&3*%#0Zth^nwwV!NYfuPf1@ z|1kH=j+a8@Xw^&*K6yvYw>=Gs1J*AoE~TfnP7UtsQ5vB)Bta@j9}_^73u@)LIqPNV z{@^$OnZ~e;on?;|Bu8y5+(uVvy|lR#fwRu2OPW3q*(hZW##J4GUbkihJV8#m>ZS~- z6AM5_zd4GaTzk;uP-&@7HZ~2t++Pj4^az2^JqWk;20i}P46PM`&CU>hYX)e8Ik<>n zPwN=QhUs_UZxTV^!+SWUeYH}O@KUHVGG1hxBh_*(+nR;;$$W7jddPo~Tzup&h%Ne- zH@2w3bOBs?48p)C_Z~`#by$5MMx9K^?-swy-$Lb!&TKB^UN)qM25MwZEtUlMSx8s3 znz222p9nlbj0Ya`#=%RYmU&mli)?eO|HWEd;{Q$hWN6|cMf6E*YE4Fz5mPovic?D( zl!dxRF+veRukf2tM=Vd;%O${W{95|z=))zQp(iic?NAQBwiKvYu? zWi|uZF`Drj4<&}6Lz6uLSbb$(Qkr{En!1w#S}n%YWvrJis>R1P9xDm6rPq-CXpJp+ z_vicrFeE7D7q0Uw;5|9vJK10&EN&+)DvT75v#vg`AI6`;Ox}Kd+PmnBAfNEC+m#_> zi7nd$$lW>5LMl^YXuKe`8km=>FSEVDwntI26KJb&j4r_|DZjfaIEbg7v9 zD(1f}w^mZ|1s~+6g9&PcE|=dTwS5-v7JowGkAl)_4|14Iz4f9nDPWQB+&EEDkgKMV z6R&Xls$)n>XW_2yd&i5%zI3qT?$Va>i|I!@?w-7MxRe&Jm+RLQiIXgG;(3Kt@lpwU z?ma$n_Tf*SGjt5ulpVMI^2lSEEl(cmb}R6~!{2@7;y3^Ng%5t{b3fVljhm0WboAI$ zw;%obXKpVQ;kJ@2{P4RI|M0cbF1x(&FRQ&m;cp9v9=!LE{M2)W+wQz8)poTOXn$-jK- z#fh`mA4q>|966A;-+tX=$0xRY?XHG=4}9Yr-~Z$6dwV|m{m;F8%PsG{`=u?{&fK0` zTi6dw7W{Mn;D=97eD{eh;n(l`m%@FQoc*aob$J1r>{PA z`X#yN64ajbj=K^w_tb=uM^@e3)D9KjH|zY=R0?LMrm&s2*PeORzUqu}@TtSC)tmSA z^b`uPuDb^YK2sf>$xrE7#x(y_%{-ln|AxVu50L4H(=awku+K(f&~*JD=~GyWIcK28S)veaWbWB*Hptbk~rzvx)o4QEGOD_X-*n!SJm3C>a99V zn(bN@`OXcMvgOQ3@I~@htP9J%pUspqyHq%$L+r1uAA&57T40#2L(~4nSfRGO`)lQB ze@IHZ`Cu%-_Bj~7x^(YjVFzq8{)yWFLpfr5HP$^g^58A z)vH1%VAKy7BY#CV-1y;bhjm(qSXGBZy-x?D>%gqB9S8Y8)~-(<4ow=2zoW$-ka(l_ zvkyK|{`Ir4?r#FQ@nYoU8kpQT>ciHXFf{2brLP@0(3|sVY8Sm+CKLwZ<+VT7)YeUn z*@yTan)B-5j+yF??(XAgMyl1R!5x%+Dt}}z9;Z|;y4poUN#@T%zWXPsRBEdFmbY}A z-_!Hfx90QM=8TN&Qzd}vTvc5^x@2S1e~Y4S-I>3cnHiYbF#|h}A3siUn3`EuPGE2< zf7xYI@Rp}P^*d*t`PQe%vuki4aT0mZVY~F1*AOT0mMG@do%zEy76x|=0_sUO#UZct zBtNzH2zj)bdTy-ihLX%*LpD^C)Ro;G9i%5dwITGXCeFc2{%cB4VtswL?#$od%wTn9 z$6yupq#OIC)oNbr$#QXmLqO7#;~g(|oPXw-{*Seu5GR_4m#RVa^VPMlAx?H5cO@2T zknH(9BQWNrzm?Jcg&#BFn@sqxHa`bFX>T zCSY*d&%3f&z+J&9gNB}X`+`CDv#xAb2=zyy{wxQ0EUqUtE(m_27$Iz$b3Mpc9k#|P ztkr&u2VRRN0kZodS2PE>D_AmW6J!Et#!KZn> z97W`1=nsjIviVdWCYy!6>$R7JP_a6vdK=e6L&6YTq;mSS`=WN9#Bb=K44#@4tl)Ve zIZ3E|^smPsA~8xlERQHVhM2!jogjAfD^(35Do;h-P9+4~qwy zPMjQM*13}C7Ur4nwt&#VxZ2iF35>*r=n%>baq!qA3)o@x zl$rWd4E(+d8-q%g_9`OJ2FxWwdOI3O?@}^%WW)R#%Sk}%wLRQBPr5R7^T!3CGsPih z>8Pp`s6|F`Xfo;mk?%9qo+0HJp%Bf9U)0Y(TayLCw5hdsaUy$YSe1gz$tCLBsOIvPP<@eNH_k)4kFX zYaA)?$zTaJ8{G5EHq8FdQP_c}LT`FRsereRG6;AUvK{0E9D2U`2@2{bahpm2`u?Fl z&1=!Jji{-NRNEYH=OQI|5h~^+x4G(4T*t8De5^=nj8ITfiV-OjMFJ{VW*Fy?3CgI9 z=^z8LUj~rr%K_W2+agv3ym$hC$8AMf4xqn3C-0yWVGiR#KnwCFNKaOM-j&$f*fteG zKbkBakV6RC78z7nB~zrmb_3d`gxjkKRLjyPcogTF25c9&KDB!(C=xm4R9j;ILz3ZQ>7K3{a^$2qef_j z0|G6Ylvcmeo^O9_e$JJ|K#JngKTkap=>*mzl|;E21100B^Y@^*2zSt-$&P| zQnpa|aqRq#0}8oR#c4g|zDIiwnDViS@x1}elESzoBDgOazPi1!{@bo32D&Bb^E`fh zyo1>^2H5YE(uU+0u}EO=K=?4`V+m?^Cp22rT{d6Z)E-f~Cd=;5_^Gi+RXkCw^!$x0 zi9xFF5smB6N|_N!hcQ>43h8;%oRF?SfyU?-R0s!p@aRnRXIkD0{UbbCuTB(Fn_NkR za%KRiRwV4E5Id|KU{Zu4gW*~a$^j2yeQQpn4Q)ipqWl~CB;i z$9sBmK6Grycy0tb`ek-Lx2RM{ubvwqlKJk@o-bYuz0Y@TzwF$zk?sp%>zKDULsMJ? zy_skFA6*w>zl=J`;B93%_>`o-VWz|1@@RvFYkRD(t%2jfKbUz8ZBrT>k{A74nBM=r zJOB8(+`WHw-}RYe`*T-3w|}bq*gfUL1)IO2Y77Sj)#eyZ)EXZen;tlN`BiUy=6!em z@sIBOgRg(`(OW+&F8IJ3k6*ZV&7IqJWiGh_v@5(E&y;uX=HaTepH3qwsq|3_=ix#A6H@A;iyykOwr zXT2Y-x%2$XGegJ;8Z=al-E88#UAeJK6eFl7=VdbIWe9xT}dM>ClKvrvK*XLtK^zrtwOh8`6^t0!`9_2qA2$jMl>+R@;(+U_{(E?3fsm8?-8)!Soa7TW zzq@xHdwicLPKcChbyeVp$VvW&-i2`j-~Hb&B;Vi;NE#=>g|5Vc{0M>k6(PI;d!NIY zSA?s`-|*AE4Z%+J)}ZlBgb_3Ri-+7-(;N(>nTz^I!_?azD))YNix2DV_kwx2X#5#5 z9jZsc_WYi5@BNuluxn3Q?faM@oJM1irU>-|Cr0}!V&$`IU^+{Fh1S22La5_}_G_%c zTn{&c++fpGPCSo6KpQNEHx_Q*h@6CwR^JQ8Uom!_D$o9|o~K}RRnWiw15Xta#);SR zdDnG^uRBbBIXfQT@%Z52-o1yftL_+i?5dCDj|?7xslg+Ihv8v>!-w7L<_o#*s>&NC z2eAMAy|t7c>6(F#w^XYPPNVH)BfG_3dedO|&9@Air4sP;f}^76~y ztYSYeAKV&ctiGK*x1u)V*YayW1MtnNYDV&j8K<{L|G`IN`7Vw0F^~Vxa zPDW6<+K&;xM>QFk?&%GBs9Y722m;mi>wM{g4k3E(*8b>xvn#PEaMiyV)~|d49^vDZ zep-jAnQbtRNmjP`edS*$ZE{XX^Jc^sbYx{;sC2oc((trR`(hk_NamnFO<@53w9cUX z8KL-DlV4>{2F}>(N)`a_3g!jr3TDT&D`*Dk3fdX|eD|Hx9Z}(YW(Ri#b+%2+qXY-a zXeAySKI%$ZpqafEt{{SR1qSYjQ8T@eX6QA5zIi-@R1oUOolh$Wb!>iHizvohlh+*5 z(JkH(NdngVcURH?9*ave!AC}E_s-Ygb+yf#)|tSM@h6Fc3e;Z`FPoy+ouI89;xZZX z7Qdj4k=7mEW)S9M;S01hB8xJrM~r*)I>}g{c|gB>a=ar1(~G9Vh(Ku1lMu*TPm@K* zNZkZB_|himp{7)1H_+PV=qSWf4aSBhq6!@q>W1W?U$fdetAm;`NfWEheU902yrCZB z(wT@2^)(}+XB)PYMJ~?i4?p>=O3cUdJ58Bod9h9 z9aquUA!Og?m=M3l%@(NFNn^)ZV-VT6<8yihYW6NBKmD~UrE<0)0C zlD29f_LzDUXsm~YRVq*oG}$f&^mvTgdGfyl#TX}E7*kDGMFu65TVEu~BIyB| zpvRJ!TNJMaIgTwpUC|HQ%I0D$P$^qtz+UG{B1m;d%aD$U{+!HIK;}3=28~cKz!sbL{i5jvYXY@e3V?r9p_j(E zP_krT&8J*RJ%V1WRb~hhSaV~(+~WCxKV&sT+N{ESAR6;2L`2a;T^^Z7se`O4Si){8 z)S&QkMIyCQx}~boO#EQW0pvIos!dP4utYaQmW-X$L?r^WpGzy?IHLz`c}BSpzJcrc zB9vd&=UW_f2O3}l_-QVn5BX&41Fw_y4Z!OHffgzZ*9HP}+y=@^s7U;L0eDgB0{nDQ zmtzV_3^x6qE2%-?P3;H0BO&j7T@VgO(q)2KuV{Kq1Z05%+U1WyuMm=UJmq>1K^(1{ z?NXtW8V(EtBq|66Lyhujz|SFJL;2tnuA~l<{?DOgTXXucN8|&f2MG`}E~Rz%Sj+ec!*LvQ1VMnNahMfg)C)ufzcs`G zeVH_ezLHjwP~XN)2;>9l>oi(b*^waob%yRYH9==Kq<$6lMr8><(w7Gq6yzP+XCeB; z>H^bhU&r}_tdXBFRozEnz{AS$+u+k|%%^>0A5zsn8_(WBKg}TP^}8q97nx{}GZ$*^ zLE7^;H#(8xrGRNSMzUR;9OP>@jGU&a@@A{QS@2oV_Ggk7N)u(;?RtMnrL#rIjs<2P z#+(l6ikh|JL56-!V$jq2{-SX*Z1pbq4S>cY+&TBXwR zybQ>DfK_rCUru_XznvWm!(a6-&H5iw8ELPu?&G6IDEnM&$ z@BGEhZ{4)>n%Dj5ozNS6bewFL=dDuh35GU5Cp{@h^*DV#U_Nq!Cg^ide`w9B%HO_! z&A+{zdB-O{^R8QdeE8+HfBy0>-16W9x3D){etEX@(0!L2eeT)p>WOt2UUJ^V#BStd zs5g7K!o1MC>%8;V@GH6##EEyzl~~Z$h!|9*kik@5iXA)N`2|V?4BGj_C4 z2ma%azw>-bpD0eKXxjg;I%VeryM9{ru$%dr-B=ChlmFJ_{FOUOw-aq@PZV}6{F?ZWO_f^1iKo-2uA0PG;*0-8<|o)`MiKMVslq;t{u#_sQE z)AIm5yzz(OS=x_Lm1n|iJUw(-->BJ#k@jVb_Tv~T_uh||YZ$bjV@n&{e(3u(S7Nb8 z?|Z1m%+%ri02Iitu{SjSjWn7wrxfh|jy63P_6!^dxvw5=(kvBKo+@`h_SL0ZJYWoO zl)r$t1lt3WI8nbd8QAn0SK^`*hJdyJgzAMyVqVydzSuR{f{=%NcmKY@!6PsTFYN2? z&SYMA;e9i2n0njP%*@R9rkeWuklD)XEwu6gJ&D;%%fMKIS%9Pr4o-HSFixt5lj>lV zIJxSoefwr+^zO?Py7>u;6XiEoO&}+m?r|k9CUJ;3GeevlIU$@(L4KzE!c_hU%s{#S z$dO8=TsE9sJah3>^JgYidQWVrNE#=bzvD_8fTXD2>51Z`njci0RA;Kh$q#?n-)}hi z9){m_^AoDXiS{o=T#_(OE`QdQEEO3+$MiAf_ek9#@_R(6eHbzQ9+h5PH)-A-h&F~7 zY`)2rEfuflbWDlY^Kpvop{ZU3@=K)jPet;DgS&zRfz9IuArU4 zpmS08>#G6b3ThCppuLg)fh(BPOQ7?;*YNI8Z ztvG~%F!|LMP%W>mgNP1wP^9V-Xg7%YmDN7Tw%%;gZ+$QF+O1B{cJ1!)b{0K(>u`!l z9AskyBxw4Hq<6+@CaF-FRE9dx#kQb&=}(z+(J>k&YQIVjYT34gpj&VEGb^|Wgo(@n zx@|*q^V)4+$3X3=1S?8xU8%Co&mU>`1ysdGPnbU=M$Nl70BnLm=OU{;*L(m)nliLRoyzhCa^-mF}@}we|;wnb!;Oyb#!SLFxTU4p7K!q4QaL z-Q7C$|0F{r6fgbvDpxDS%CArRYZ)zP;epxr1k?QN!B6M!>Y`p4@RAMD^ZH6&+u zJi?V=Sf}m&BLJTWc$q|{Q7-8ni4p?vPbfO=b?i|cre+@DyD0s4I$I-rQD444s^ul2 zf~QMj1Os+2(a&eoy%n{Dr(WBp?8NXiNV~0`hND*T58nowDa8z z@Pt~*JhJq3z)N{QK$!!z>4MsKNO8D^&b4UYsf;G7qapC)2`V)vG(Sufl10(xImd1x zObVt}GS_M#lu+NsBC=4DLaMVGBz^k1pfd!=$PCvfZDI8f!pt=o2pN|n8?>N-;KJMq zJbt##(baN)Mj6F~2~Bm;W*7kkf?I)p1ZsLH0qPab!&ddW)`P7RU;yDMB%c38_LUUa=>z{z$EYGTqKbtz?UO zlj<18tGf<#nV{PML(a8~M|vjIF}f!bfX)Bel|+!LjwDqrfk*a1S1_pr!Iwr1L0aND zpR!6Q2lhq|B$nh$X8O6hyw-JSzmM4+A8ghUl@6g-)2(J(F#3J=ip1baS5Sj6e>O$% zsi9Xk+{zu88Z?&3YDO2GkSc1cxWhgh(x-WXlAs8G3t@_4W(75hp$8^`Sj)_m=Z z82X`t_afC6Go~pp`;DlXr!vY&8AwhNsp!~GtD4FJ6ecmv%1p`iU9GrvA?cvc$6<+8 zi+^(~HTfzwogAcp-<3olL!?0edj@)M5=osa20k?tl*ZaEg4ziSc;H92OSdPXT2@}? zQpefgXqL8Jl=3zEfuT_t+a;J#W^0(qUhoU{vIL;xELUP7qB~yb6!?_3wI+dlu_T$2 z5c)hkC!r8%DP<~qlzWmUaI4Gcpr`iE0$GdJ-b89wi~ZUI&j5!wsY#lRXDsg9n{XlDVYm-Hu@zA)gr{>v(xlsb3BbCj;Zmg^d? zfT(8phc`M zvu3&46i{MBs&umoBwk~5P*f^$gn<63t)!SIqB3ZYPN{c6NeE7V*_E_Jn1!A|zh;cV z<2vm316u8z>M+D^t8P?iM^h$r236mpQ4Qt;`qBZ#f(M~#r$|iSDU#$4q>%bYS5kwT z@IwRSQK}6}l>MWqCwAkW8q`h#*4nELPLYdY+w=%wjwV8%*31MdgMrHCbMyW94dY%; zSiZTRqVtq!U0fTY`Ly?sL=Z|6yFm&3(B;R;n0nRR340;OiOdtSDRopgQP<< z^W{LQqg{LxQ!GpSJ_mAA34)*q{n&+|oi=2l;XY|!^vi2KZER{t(7Eol|sXUH2X5?Tp;cw-RYD=YDJQ}YCoh~&gls=8Mx$YSRzdHt~`GG{+td80fJIr&&u@F(SoPj7@(_ZO(Sk@Sc~ zDp2UjLK8jFePOfx52L)qc{a#oS0ST+l*yc*4emMpzaN@7-Wy!P4t?sgQ>%aftDPVH z-3R(Bh5Hl4NykTAi3RBijxH1@SXbUN$jR<^Z2TbBUBn61*w@F34+Z~xBS&urS4=~Bl}0Lq!sq=rB#1l*I37flOsnC zA3l5?abo5ID^8YkJ?45&kn|avot!*Qy6<--tw5ag&qGht+V)nyyqwg{9k85S^{MXe zxBS&rbL=JEPMGI{bD%icI~ylfPiAJ~da|sxtB#Z7iREO?3$Das$WBgy-m*#ec{u8b z(xt2l_mq1-i+$={n7%(V63}}~HHf)ptnXLpG1v%%jQg_d8Lv+QNFqFrfr8mAmn@f zfUWoROBMJ)seA$UqVByJyXl>tY%Qs!=<2$<#h4fYICm2K7UOi7w*(TZppo$i4&{!}nBTNgq z)5hnAs14V91Jue=p|*%c|oLolSd$Z3^~bS7L#jC@uhA(VWZ_ zbKifd2`B0wnRbVhDsj@ifPJoJMoh%zL?^2>s3%TT2IA!5BS-Ri%}L(u@sI?pZn>tK z-uF96jmL&%Qk31ivt-=?QU?Bs~e|JwCBe4ZY`v zKFID{)m9Aw{@T+y;&S{-GbtQmwW zc&%geU$~Oxf_@Og>xIh$X+Cg*%72y7J==4q`9i3V4?|4Q5VSUU;I`eD)XKo{&+p zPl$EeR~0C!ZtU}Rd-E=ajTX>*smLfz6JO1VW&D;?0IB6`Phu4#YtcC3Og2Ke0tX^q zfTY9h<+Uxs#gDVKBFL!4r4OTk<cuP(49ZXh$z(B5H5Sl>eD3C&4Z;;@1kyw} zc}FT(i8SA^Ag)h+ocWL|nFq9=p*2lpz35K>Q6jjqU6MBmu7oW7OErEQO3iz`_u zd93>*TdNxVOB4d&vXT}hl6s{(Qags@2N_&3E;L2ID3DkN! z2}0Lm=cCuEVMJ{;8vqac$lY@Q-b6jHWry0pme+}d5+}}}oo?nqECjOlQT~h?<&rEz zY5KEeDH$A{3^oL7GT_OAJ-<{Ow4H|t)?6jXY$>e0+Lg?Oaj61NQ)2Wb&^y0*>^yQK z34*LAu1Uc)>!HWGh%OJ<_FOG)-RzQvGymF^%mt1g>{F#35qt9h46Ms>pR)_bvO~eh z?%U9+1!E$XZ)s2-bafz37~K}h;wJUSu4GQAW?SmeQ{3#PPkDILo!iIYyTAPr@rHiR zx1STN*`DRG>y`){!^>Q3HX5xvp>YBluU8e>1^Wn$BNv{OtB4cwXT+QJCL9x9{^u`$ z?sGeT^4RzPqWbbJ@BHDTx7>PY&9Ce}`;ujw3s-)AtISGQ%D_Jb^m!JP~^_BePuUx)&hPYX7PCoUi*9s>a|1VdvSfF}fjpg$madHCm1UaEq zz*_odBnMr;?MmhX`59(Lf-gq?h7cB)}CMl?S z|0vsj<--qOS*^~@KyeFHkC2P*5WwINS})z!J6A6wY}>Mo?%t;aHXm{&bHd@|;VZ9v zSoy&Z!ItU~=$!0?p(>{GdoSNXEx&vD^5N|!toNILO`<_hG$%zU0UVix$<88HQ*lL4 z7LBeyaV2x2K~J>p8ltt=j=&^}idD2^iW7b^I7ynGY~1HcUKL0uoG+v+NCLWA`p2J4 z*iP<3ov;>~e+4U89766&P8xU=QjCuE;R;r8%HUPhlUgG}F*??VuUYg|T*)a4-Xfkr zY<}LAED4K#<0M>x3t_@0`m^XSJw?&?zg)?p5PJ%!pVm5$3+I9t#hTQ)g(`5_o@t)C zNSXEEPXvT3SRA-I3eA?_aRO^d5>;LQ!Idl(&1!5}F`xt5G(DL(?J`%gSn%jDe=Nkj z#bJ3r;rzcU@czM-EETnS5;ft{VcHpiF};6BGWj5ME{`F$&JA?1H~&18ph*_)3Tmys z%B@^nlFJ8S)48tX6oqNy>qRwglEf0b#+57yR$rRj?z4hPSK>lOF&@PXnrPb!RQ*$o^~Zmf|urOi;gm07Z!A?1~#mo9o}ui`!W=I zwRAi$L6zhAJ#4$69+)NlX4&s-iq0RgyxTR>=f_!G;T6*)n5!-kH^~+~u8eV9=rVJUoF& zd>yXfH2}GOnb&+i;dl+aRP23&D>=!KuAnufo1hPI#N#L0AK71ZC5wTXzEC$&;Sv+J zoXzW**+vvn#8Y0}tzkFrh|)Saq`$sl21WbATb}vC5u|c5l{OX9l6dpNxCuo})_@8Y z=}B5vx-7t>Ed_=Jbt6Q5wl>FU-*+X8g|sy@-xVN9fk?AV3lS(jaz@akyB5NTTDd|i zUe0M*64cK0P$euQxGT`$uAmW3Sg41v5wAA&$QVY}(m=K&Qs=mmWrV5b42HDwa0H=_ zQkl4WphkxqYDgQBDyW6;^?4cG>+5poq_e%yweURzmK$^3hMeOT9piy(p6U{=RaL&%CT&fITkYphw$eb-fG z5$M=&Y)ZM&c4;uR$|s{gjPNvuMNL$5TT}_AX`ex+7O|Bh(4Tpp%9XA1w=Fg<+gfzO z-2S%TCC#TLB#=7L(L(59hT^3WA+6UIC=Dr63W=1yq_tB++2WG+#90rxk|m(NX3V0@ z0T*aknsil#35RW35=YIA7NP?Ul{#rxMECLQf z_dc&X8^JI@2F%8^sEIl13IeoS{?8(JoaLaC%Katj(VG+Q=51?q(Yof#g4)9kVM41L zLDPFbVu9}W`9P?nr@tu$wD(51M|F;U^+qi*==nKUvRLTt7QC3fPPa4%Gs2y>C}S@G)1gXiPAxE0U@!)`HNTT&X2BB+zi& zmygajH z0rsSr7mhj}p2)6(bZQ;it`0AqZZ$qhq3uff=~dr- z{_4J5>fv0bG*IT%a_8?)i>JJIJ-pz(bxvWFT)~oI*0{~*L9NNU50BUWR(%!)TDv>G zE^cjo+!kxo>Sb{UF}$_f)6>;8Ha0LYHb!X)S6ty_UO^lYCsoDCt+!53%UkQSC@heZ zYK#-wbL0K**PQHAOBg4Kldjub$&z6>dFGj_VuCnnTFVRNWN@EaaC={#80qPG|NE=e zfq`n3(kFJ!tCNkcWt%S?A>srSCuF+pc7B0$W|dV&OrrdPK{k z6}F;BV6%+{eKWMgQ0=GEDj)5$qUX`_FN6@_P=;@*4-FRYvyJUDmKTp?S(GxN*0T$sZDz!dLuG_%$JjWgVmOtv}l6b6lZWK=Qagr=Of$LnsQlWZLXu;SJg+6CI znAM^&VZwU<#>lU6UZLkF#-9;j)6cq+rNTa--9N5g3wD)+kn!_`u~@voZ8%N=cl{ja z3ipqz@XK`33RZApaN4vhSw84zyLwKFnp#&EMrdW%cob5Mj`d+;u}Q5Bds5K&_+4W@ zy^L1ZCK9RRu4MV36+lm;!=q_ai9<^A8rUD@wEyZ#P7G8ZX?Dz&g-0=I zQ#_FhwDv@-`K*+{tGOq7;Lk%ZFpI!Hn%F2PsnS*sstAEfMy76rtrrk%;hcC6XZx1+L->j-StjV( zRif5Lo5hmmE zM4;>4u4I`Y)e)<+pYb^~C6Fd!Lqmd8Aw3Mx>41?>qf|4KiH)G&=#)t(1?&!2vaE>O zhh~Eiryd)!I08egYUJspqIw>EhqlAoPrH)k0;dC0M}14r0%;?)sdhFZjk?GHbtI_J zEa89$9ApO5_$5V{hhc0luw~yT2#l@41I>{q+ts8&sKK*OlKa(UJ({M6%rJ5v)eNaL z>O?>ES7@mMPH8m@dHX$>Cel>C#Gq%{{23h-YB#?gc+Ub^pDgJ>0$C`(&cYE@G=TA; zmy$Wuz)oexI^((89GmvLlBL4dzi~UH$*E{vrtRqlFxzejM%u#sVdkr5LYNG~C|;B{ zZHO>zO}h}TK}{hvY-2=zbzInV08D6`7wK7Iu;wSOWO=~rV%+Dy7YQ6_ zKP?aI+&FJTjfc8WnDb&priA8RrG53J*=9`uHZK2r?4t4%#d@ah5Y{7`nCnhf^(jHE zBOwbI#gO`JQexVKPTG8AElp)41Ksa%CCh@qR+2~ED4L@<_u#Hy-TL+!OB7mvN1c{V zsQn=4;JnSimVI75w-I&sGdA1>oy!1IKNo$0;J^KUO*%}Td<>D%NuVB3-|?7tdH7~Z!3SRn7N94Hiybxwaw z9wu$si4g|RuD`c@P6u88TI6Vx9(Ub>nCb_asr_zje_!Q zoE1BFs-TsR(0u<^FgK!lTH$1YIMWp@8|GV2x4vx)W)y5%9Sh?p{`W6 zr&Ly)fbnZ=4XKXTkbfi8`8Uot+^GE^lY*|lb|p*24D8(tu=o2o*i&n=c6V>DmSJbN zo6p4$B4;btJ4mO=`)6k6_;Cyo6l#CFYPEaLvfB&2hg`{0(To$A7boAhoH%pNTuvxu zL*nF_XX3frA8VKW8TVksiAMKb{nfqj)>ZL5&Cps;t}>iZFCeZb6jnidLnaDcu3)KX z;H0}BZP!vbv3g=Tp_JxC>xq^m2Uni(cfYM*W~%@bDjC{P9b;fZ1$q%qdUCHq^BkD` zCAY-RCjeg1b)G9bS=gonS>QTiLl*_E=o|J0rPv)hgtARbm5f%7ZhJ83{4-a!f>##| z&Uo0BwFT(y;tE!9vLMg+Pp)VMuQoO>`@7#IfZOLRbE9s?YQnJbN3P_gLD&a}z8`BH z>Kh8rNXArZNMA5SPdEjLkj|P+NkaGkbR{Pds{bl@MGQ;d3we`A3c^Mr+N71JooOtE zye4gb^uBuidYT#(fu^P8YRN`$6OyKoVsLJjwiD(=f>3b%nq|)D2}hAMKvt$EDn&A25=D|bc{C~}B%M$f z5fPMEYBl0EV-gUaC|~Tkp)Hb*^57^(+r?w2BXH$=P2Qw*gZU|hIDNiK~%%8(p%-{?wC9`wHNq8wmV zKcz+Dy|XxrGUeKhRx1=hu0%>blD2s~g1yU?oGgTBk3z1R_oD#}Z0#9;cPMhR)^OA( z2!pWKhhV^uMBJWA08a2a60@Le`b#W0N=>)_^L`)A)QXKG>oMsAt&LvfASe%$*vQB% zIjRtn)cIO-mMb|~po;aNf=%^M83*NrPT(7KECxm^L2>GG`H=G~JoL;U(I>Hls7Xo; zHoni5oHW?>8wn8tDGI~yK#FevdQ2!!`rz*85;2B1 z|H#LO0s7B|VRCO@ z?dI&gXIxXwwm6KU*gzgdntzy8YG+I5I1o3nn2^SLi@O`26g+B);vo?_^7YQ)dL-$>k_U$t|)R9CXq4w=?N zc5~Rt*=#%4wVv#3BsfV1=bT`_fmFoFNw!dpRx0eN*?c z(c!G^y;}TXo|&ymbu-jg=@vbEOP+o zZTGQF2}g&3rsMPj)#gT7$9?LPc8TLGJ&_Hkl>v;5kBIc^y>LT-*o=pcdtx)x?^4O` z>EWNRPGi+#w4#WQ50l$x_4Xb}!E-f72M^Jec^TC)Us@Ihb;) z1=yGizW_tv2DW2pCq4HR3!5-pG7Q;+>%jhf50_!o1Y`P+xF zCKVRGu>FwY@lcsgZ=ne)HzB+;h{5^+)Sr`@y)AZYt374d@p|70i@4iByR&HD-H z+z}#prTf8deew)%5M^mKW;4Ylskd*Q*fz$?jX&f$ckEL2dOi|$5qe}5FwfT(V&zrz z#2SpY-%oN&LlF{k;3^OxX}~e}K@2*7`&2Qe# z4Ls6}EQ-L_9QqVT6wKxS6D`nJ-#1-vHMPsk&tp`{^ag z6IC=HN;M|gr9b1G5MpW?{T1<&yVefd?y&w!-AJ3+)_6w!=oQIUs>QNvydre0#xn~% zv(1K-A$V$ANY%!X4)03x$rKY_3!+QS5oXFWWlTg7?iws`orqp|p^fVfb=p0yRdnf4C;Ds@(AEVj8 zu_EAP-3YxemGvKvytC}bJP_43?1BM-{4;kJWAB4Fv&Yk0TzEIuOVuwlz#DqEQ`Ot8 z?0Z(@muq5BUzCjYdqj*t(Y2q|FzR{^D#H=U>g_TJcHYVB8x7FF+NIvei z?QeqnZhckjE97lih>0=?>C6mi{XUUW<1Lg>!DrD)_&(@%{9_~DeKG1>Q7bVy+R5}6G~yirK!)#Z{TSH>b5^+SiW5? zk!4nXdp2#$IJ}?Qj2I}x@K5koKQ+1Ay%RccMY&k#?*=;(Z-3D|?F6;1nA+AqA|Vhr zcoqn?or5{^A}N`fW9=>Msfu@)5(h4{267LXKC$QZGTAttF{}Fxp=~ql+kv}(v}CQv zB);HVX>N=gX#r&l7Us(&19l34zry zMKQ~>n+?`DyXSw3fy(;JeKko(wYOE52Pg)AZ#TA9XeZ8u?619OBvz!LqzizY5y7U@ z+R4E6p%MQvG8{7I(aOvleDe0v&`5NfYVp-!LzbP70)7@bh!fVR(agKn0sHSV2b>~# zHh68sS(qOdE^vc?;IFa@h*WyP7!l2YeoL6CR$r`{cQH_pQpy$N0w)>PImPT`IY5x$ ztFE+R;)74}QGZOTbr9qIUqCzM z%1j zwZ0%;&Wwr*tqcc1{bhX|LrWh~%vLqSe!0R0l4i-T4FNinX{gMaiffi+hbk~b&1ZGB z_itx_2F`ZoA#>vS2fRXrhP32B*>ch5(Y8K%hnYY)7<6|*+t?(0d$CoRrKb!W%Y2MBuuM?!>Co!h9SEfAXRrpoHH**@I@vFroMxEPHj|lNP;zb;j$%# z(_@EnFXU~Vmy?D`^97+gQLPqTT6#@RIYTmzXj2`idS6OHJ2w^MDfNIwR%ZJuRDVqy zG+w%#+ilBnSO5myUr*wo7VR}Fq`CYF;U&(}k_Cqcx^jFN?@L_cbFNE9T?MY)a`e_; z2YT%W_0<_;#h^~mwS?xxKWQV1{;r3-p0HCfwUm~{EpI6wvz&+ol^6+5xZe+mZHp;j z)PFbOE7-6_RJTZVEaHLGtgK-xSR2j3qXH|^SvjzxcXq}V_fAmeM~ghMDceX>>KFHN zNd~TC#qHmf zHRjupF(>4_gE~y*xP}^!=083br5j}GrH|tJ`?J#X`@^rKMfP_xdaUl17I2b>F2(bG4LkEB$esV z{mb)a-0<)VSRdTNan(W5c+dg;OTs?c1HoAD^oda)9PsrTtr(x&+1;qbT91#rLX@58- zlz+Uw6w|rx*pv8s`>w^Zy)R)&CyY9=dBS#A(0(5lRqrDMn>S~ftEH8mPC)HuTD$zQZ&e8SfcCi4(Zzx};qr0ou zNB^(jpK8SSzue)^xwREofpaZ=qx28Lfdm1=HKR0w{%gzsF8gZSD^n*Q{(K+W+qRHAr%>RC{G0*Odw= z#fMf_?_s4p$hf@sJj zh^1!@AG5-WtPQ!-xB|w$6!_dyK6a7RzYIzC*Eak+*V{@;zCcbmQnlb}ZL<1|Dyd(* z$zr`r57ssycE`A%f9vWoGj6`!e=mC1 zZZ`EeIRt15h~_5FsZ0BGmM9wZQeW$qV!`Pq zU)1DxckdvEP#p$mX$5cfojXmCPq|{D9y)i~9KZddt$}uy@$@)_y;+OqP*VCHG-`O> zUq$p%+EZBD$>FHNZciN#`1=-tSEgoea$?u0 z7lZ9zK0f{%=KG`k@$ulu9arPu20(F*yOAQMsR`lcWr=@n^6;Mh9@P zc}G}#@p0fQLDU7}9axbmM`{A@)HsOQNb~H}|y{tid&36(|{h`=` zpL_j>MIER|ea!pHYNw&$F$AVv58%A44H(x&%4`Qij&pJHa*~_JVXsOEhu<$jlFgM2 z3uP06=XFEhtsS*-bi5>9sxlGA;e@b{GnDKwHP;L9A~>7hLJ?qh|IWH3da-$Yn-ZLG zVEA%K;j5s}ft9g$#oA%Mt659f2u9IDRrX6+nvD44n&1?~Mh0sycYsW;XZgBQi`1sO zf7M!wILB-i5#>(U=@tvSt7&4=vD(i+=@wR2OnyZPA-O%YmNula;Nb-k?a{t<*QrC1^%JogKNSXrxds1YC1t-%B- z7azr;?ot=qI|=A=i`>H6FCE%4+h4|Oc|SsLM6sj!w-U(nK0(%<%e$j7`N~rjxp$0o zqi_g<6g+hUR{7^Wcx?NJyudbU7%XfB(Ab(Y69L~UnSgjpL95f0X2MRs^)YXXB~;of zDQenoj{I;E7lQJ6OGO6Rq^QsE1g?FHp|S)-yikSg7JIG(VS<*V_2Jvth}O4cbRJI$ z+CHE#b#j`9HSf_4ju`%8z zS3Q_FekT2~%w?qM0hd+qt?e{*b0c)#Z1ZHqpPZ3Iw5|SpQsbiv-_ZUy-)+*>DM8wK z?P+)P=B*7Mxg^f;V;{}tiMt!{8EC+{PW3pRt07QNlw2C{m5+3}HV3$`sX=xHfa-Nm zk<-@R=W8z&T}keKsFpa9!IP`U-s+cglNr4hw;>vjdeyYsQDz8i%n3x^gEsC$UCr~a zMsL0bR*Z+?jBT2`okU&xx&iZviHX(c`^K?6K31cTfi=yFT0QZtn637PJl$Y$_KovY z2SsV$4~6SH_7MK@Jqw{B&?NpM0Zn@A;ZeIO5)X6M zhD*$PFOFvR`Y!*LT?ms$bB^vMNY{jlDN{L_f*(9D?_D!Fb?;vF42~vw4eQs0Y`asu zK5K`zi1RTx+9w;2GUSU4wp3YE=|Ad->`kJICm{MizYw12dK$DnB|>jLv);_ z;*oBZ`3TWe#b3;;TXl8x-eEpW2m^rgqTH-7hvLMOUXR->)tyCrx zgiZNFi``?f^(&_nZEJ<&VsN=tZpeUmn9ssB`($f+L^ziH9Uh3X8N)Lm_h&Zd)?q$F zum@8$uJ!Mf+zkYXqr`AIMT0ryS#r*Iciz*Uf&JlT?OV{D+Y*blkk8f@_)o|d>$91L z0+dQ4aV97$WTRychH{pI76Zj!hvs+w%b9) z8Wf4(w=;J4AO5ND%6KafZHVnFP=8fm`T(rm8F2WsuBPv~TB%M=_-n}-=%9Uhf^>u*uck9~zM|Ye zZfm=$S6vS(1r+Q-ue2h*$F*wjvm<3BQ``h9)^x7(XajN1L@*rPteE8qj?vTV#M&f@3>@jf>s4ex10~50lLzfV7^h2pJ_B;e5eCd zuYLqOL}+NUlv178AG5-XfAYa92sR>-6Fvpz{H;S$H34SU5nmL_th!(4difQ?d7DYl zkuY2US!Fh+cH=k@k7C64Dqrrp8wXIMq_S)GwO4&T_S9`i9%bN7Q+J6fF6ULeBv5W*9BIt?6a9xISMfK&jgN&*(36bDPYeL%(u?k6?iWi- zAFD?9bW>XIgg4iyTo1PaIIj}K&-LLch5MJYMRl z6vE_WR!R@nv0QTcwmUtb_A&9WuBNM&#-l$UR@kj5kNz+*po?`K3TxZQfl1V8yH))W zr163DJvjZ}BR(a~ZZZ>oe}m>Ihj2xwfuBJSDY1-W+sT?!mF1}XkOJUQ2IA4tv{=QZ zC6EJGXe;gDO4bZlY>Y15j9DD%+YZESm%`;Unt*yM^NC_ySTg>^sh21H(?ALDrd`GM zS3SMPGxQirz3AmYgB!;B4}m$iwA4<%RdYL(5*1z-h|}765D(J}jG=W*K0QW|*VgmP zz=)F*a;5D~c&XzmijgGFb0SO=08HDiggUK8ravJ0`c1p1=d4Z3-Uy+f*Q?Xo&57eB6ODx6=ZThs z_BNlDX5!;|NElyat!3E3+F@lFb>u;7ZtGQ>`DW!LO;Qe{p5NgkGM<{Xl679Cw*;)1z ze1eXg)a%1PP}=GW>Wydd-J4hQoFg-O5~14ReKUJvn)6y__N5!Uk#z>avg3O-NbTtWMz={Q z-?QcThxlucr_*BaP&{A6K_n3#;k19O^YhGGKWteTnU%j)^hXUSu3FA(cR-Q2J$YuI zpo{dtwnVTm5T5h|`*C$O3eVSOo;4dipx-OTPp6gc8A{F{Uoh2=>}_hzQkJe7Hk5cl z%%b7+rG)-7&56-r;LR0xxF&mpL#=aarjJbOceI3GtLvXupnAj8`_jJ)tWvqkzA3!q zHC=CSyEebWIJsv`p*TkYGrGmJ=8Nuj1tL-)Pl*tfSzDjlEj_9z+ho+<#LrmRkiLwrt+Q!wLpWaqf?z8%b zu+L^Zh`WI>nJ;uGXuVr|$zdo#37YH9Ny{D`ULQSQO4-k-cj@QUs}O#D@B|@d^7y9` zXOYq8M3=L*lMxI#?vnB-r=7=eE1GxjU^5}1Z6IXKiT$zA3v7G0lTzC!%6w*8<1Xrx5LI~d_2yx} zu*~6@#Ru0ufroGHCdxe}F52B0wpfsrLAm|a*`DAilTgVVqxH38UdV?4yn zbJCFF7^3t+v@TO~mwb z8wIr17c&hfj+S0uHW{m~kV|ZJYuc3nD))7oGJMj(2`5_jC5NmSA4w26PV&Iu8@+>H zp~5zlRGvtbpB&$Pt#uPF>VvqWCD1|*Vn`1vMz2n!F4p?FvD%lFD(_nyFu{Cv??z79 zm!UKUJ`vrsiY(6~tky3rQ3y{zFg!JDN*T7eQnBFLKsgz!lWs)mbRv~J~RZI7HEegX-X!aJi+~gR+ld)yk;o|3z zJeQbt9cBYFoc(-W4>|k;El7N z2C-jQ5cG6+_N``QENDM97n=LaU9z%aLT}?N`K@33FKP&Ur)?j#M~D42pEddnE0%hRUa36%-`07Yx^`5 zfwU;!=HaS&68M`0|7s{Iolcvx8is)2H_h87ybE4~2>03!Yf)*F-_bzv!AacLGl2*) zE!5O_W#zUcLY^}0;9yO<;&)OuK+}L^fWbZ_>ZpIgNrH{0m0Xk<>W8Fa>#C!K4)@`a zj{S9!JH${JM<2$#QiFIEmSNlBTX|^H-SuPEQ0~I(=Zq!gVc2&kFXV6OoLR-ww7!M* zjvoTz!Qh>70mPp$`7pfit3`I47)QiIzcj~R60dJ!!+u97$cZ_(A%!Huv0W{0_ z+#`fVpet~w0H5A#VTpdM?Mw!8HqLGlY~^J>%Vmrqs`uZZ>6e!=iK&Ju<)05puB@eV z(dr@sY&ax2jg;2;rN-nMZn}7`qOp-YVs&#X@1V;5-hJpjE`zZEQCevB(Vv`L;vt85&<2ZQ*t_4BI}D(#1t z`^oJqUwvD# zJX;jZ7FlHL@ZBc{78MsslZEkmKA$L?R$iNbV%gW>m}+AtW5 zLSKCS0*j09TfCs+sTC~4eNYiyL`}wglaPo`2Et68U>wIz#UP6P$hk>K!Nd>5XxcD4 z3ukbZ+JNR@1`LG|7J^BYxokKQz;*kL{x5eHLS1dxQzd~X9*VY?pSKWtrhO<#`ZU98Ry zUvPzt$@uGL5ohINLbm@m_Y}Fi0$KSki&x@-KVmZiMR5Bkc%F-F80x4*LLM;23iyT6G%fJ*K z^aZ*%s=&{={-5#c$X@ocQ^8gzSWqh?=z%DUSomwI_f%G9rKX)-;VQuy_mT9l)eW{j z=ks-AjVox%0BB*I92N+Q>me!zdbg&>n4?bxu6dVe99aG1o!B01u-5_GJ&gO?`a^Iu zWX#N;KxjF@y?bE0bx!4Piop{$8^IF-?w!Lwf36g&9kAYzEurUL8+$DDE zv&69nK6&`LRCvk_kccJryH_2?$P6!3y)!0K@0pBR98V9%h*7Ou_cu&BrB^X`v;Kpp zC~dNn9ewy7P5b05E;;<9l&P`p&X+X?&=YOlqhve0W@3E$dAhNDJCeFC^}7y0@^^y! zNdV0EomeE~VL&Q)hX3sy}ui#LILz33bzJg9s%o|7X8% zdRppoq%Wl(Ygy6tKO(Tus$Z6~YS0$@= zu4A{o==$&zVuhcGy%mewPZ4Ob5rQ$NQhnnOM7J_0y>YgDRhwoQ&ch`ml+Vlm~4pp6_n|7Z6!kkn+D`|IhLl zu*@oE>6Ve7Pzv?h^6EHi|6RLacCXOh@yU*K?h#H`gb4INm^e!yTV4QdRKd~zXsekb ze{0#XeA-(u<=o4Jyq?GjV=O(Lh)(qsOLfhq|Az6SBSG?VPTIN8E>l#X4Ab7@JewJ> zH@6>3OcLmUW-bTijc_vLuRREzNc<#H5PJW06`{Dwz*$l8?4!h9>9+!l2~hX~!*0Xx z6T1v4tke8+%$uIYi$JqCPr>KtFl?kN{|)J%h3fTo6M&y2$E63OEL51y7KMbBHEN4q zI>A9CPin*CvpRjj_{&xs+n|};9d?ZRktZfMo}IQ$o{YIBP&)Z5(+(RN zzAaiv0igHU5=Tv?9*)~R9FkqIrCKK&X|7N;4BSsLY2H97-*=nyKnV5H?+0;6Q*Cqv z*O&dFqZ%-q$Ui_InT1f)4&E~U^X=b|TyI!;SPUz{i%s#;*ZFt!P&T9th#U2fPyZf} zc>MtkiawR6GjG}%{AZhH5QA;yMpMEL`>1nV=|wtI#tE9U!M{F@fHPDDGYzAy7atq= z{wAz%Ry1{Tu8x<9EzUu9Ju7QRfl#yIbd-LUV@D66?tZBF!*Mu-p%F#62C1K@YPFO2 zV6?aF{yYJrA8_*gj0I0bU300Oe^45jO;mtBJ1tk08=j;9qGL0f)K=ZL87kj*tWspKb+?Y_ zbRdLTRnmxY;Cta;`+lvV!Z*9yCjo%STFM~Q_oiCor!v~BNXE#)DJSZgJ=+EVR`kY( z`n`r~DG%3+QgsuX(+;-JA~Xl=#rfJ*P3oZeFS_)~)VV08uRsFmjyRv(FGzAfD#WAx zzj}v4SE_xus>K7$Hmbw3YLlG&R+1?H(<%NrCUewgmakiA7x%^TmMBg070PLk`Gtkp=8D7*mIV>hP|31@ z$cvSn$fP>XI=TXuyiKkQ@bb@3Z3&(WAzwys$EQh+Z@Mlc&#h&!0H3(O%{Wh&7WrSL z|D@_mnKGA0vJtb>6#S=&6(8)z(e7r4C1BEGVPQv0n^^hQAQ}3-D<|B}zz}02#By-` zk)cuK^wI3l6t7LuV|cqYd15oP;h>eY*LsFKk~}_ZS=mS2{?{SGaE&T{48hX<6+;t5iY;%9yVJW~6ej?3Ls*DT7veFz5Y#7XL zXWbAag>x3=av;S+>?GL2RRQH}=)4?z+&BBSKRfJP)%ocpFs707h-XsZjOk7JP*60O z?LW3EZv|24#mn|zmd^h_%PcL6g6ExD8N|9aTY@BBoYs=kOk58F8foMY7A&eJ&clQu z=jnWks}=3pd1eV^il?vK7eYH7F!!zcBu@Vxd-z#t)^GkH%iSoD<$6FA@Ek2G^`UmhKZgY0tT0G^0GFkcUF!i;a?=(8?XNl ztp6;%fPIa$rS7P@?5%7_S%^w;&DvW{hBhDzrAo<@baWhi+j*uDp-D3xN5O+>nuEQM z%WLpiRGw;?&RT~5)tRR90aG?I9e3i~^xRd_9B_YQDqNZ}@A4?n5>MpOg#6h6itD8H zI;enHx6@;SII>19>pg#+be^o}R7#l_jsgYES`OMriSdNPUR;QO(H0IXU&U(Yp={b+cU0iHv>#hx?QVn>99r^8ZSZ4i@;>sKksh4RRD4-W*MYK zv|O=pR&*Y}VSJyoU?rKHOH#cddH;;L#C40KJf}kjsm1wMFHybyA$_$BKTF|7*v|y` zJ$if;&4Q44TBNbv1QgHVLKj`ZksuRhj>gR14v0Jg^{FdKopRtePfY%|^Y%?Kd&?!w z$-<6dnjmTB)y@e1otuLIIJ&czJ@Oa;8I4!j+?&f_=Wv_$*k*KC~=I?(iEAI@T}9Ob{K%}l}% zgneE?YTgp4CZ(08L?nt|qT}oN+y=X=!ak$J3L|06m3vEJ;jd1{h|4;ISh!W;!FVVd zr#@^Udlphxc5*mBW`Lbybr>8gInU|)ZDtkq zuWrD54W@De-c~T>?Mi>%pfNn<%9r==#xRnX>_4+M&v3U@XXkzua(h+%m@u@B5Y`QX zNJrdxTZ;ASRDcDH5c}^6(-L7e(o*sWZ<0`~O}DHDO!w?y_8)kKhCSESwwN(Rg>6VN zmY3!4rJ&EBar*v*O$UdYum%tpUVoi+ZnGdHUM)rzA4hB@AKL&?S7*t4E}@litB@AM zt;SDe7nps|Xym2D>%>|A#DU_iqr!1lD>2p52d=;nMFn_@y6|z0ogQo-)8RAq0f>rC z$_}0y%5kQcwQRa@+V^Nrw)k~lfn|QfY&MMQC|J-OT~fhXpO5pw^@~Nt6ESlOUa(Sl zKp_}dvQ846@7Dt4Oj7f}^?a5romPPHpd!L1KWLj0VPC)bBRxtis5DNtR9K6h6||Oo zYfCH>XVc$SekiX6IbUonjJ9`feWhcmR#XeO#rUJX`L?9@QY4xc3wO7n>c(I+joSoP zdkD$M3S6`W;YwG|a}IbtAKxf(kl6XlVNlvWnN>6BGkpK8TS>Ek-Nw|=(L0%QUtYK= z2Jg}Iv4ZXI^-az+A-0GjZnxo`D(^5Lv6t7lgpvqey(&B&Rbx|4n>NNnGA36cFaPS( zDG7exovK&&#QHCHo()Y+t!eG4Fbja$%liVK!hyKFGj*Zm%;t?pQBv(Z?^7S;YEEw@ zm2}{N;wIkrdYE$Z%X~`;8=kj>#uV2zTD@5huLXmRnsN?{%N>I#ZJw?3IpQSLD_BNl zeNNe4sBmMLEF6BF)Vz4Vc*(HV^1k~lYNik<4i681zdL_8^l{M3&S4V;Be6b7^zazxXOvEvms-R10aDmK%R(HvDf`o871$)@kr>gOg%Lu!$g4b3)kw zxzT*^vcS-6?>Q`E2z@_5OW~{+`g??}Zsc;S35H)-;fz72JbI78nz%cZ5>u{0W%pzs zC#M`swW-l7XMU-Y*cBAtQ>Tc{MCii^?PkAckqYe}6lJpy2hT@)TL@Sx`9AlU8<7F7E0K; zezEtG1whJX9ccq7A;c#5(hrXgH|`&R$6RJr`M{6Ic&J58@} z5f%e8K1zpG{B#)FPp)_&zhR9x5Ue%NKFENcI)20w3sI%5KB?-&@GYz6HVoIcceTW( zJW91jP#Ep!{A9V5t=KB9cicO8V&zV!v&xx>6}OnK5HStzvUOcRnDe#x80}~RFF$XJ zCaST>Px4kC7}yPZniuuAft&8vSBCE+!ms(I>bLgW_6ON*>%lmLJ)$T!V#Z)3u#feriZgu2*YEBPTFeJR+ zT8@9R7F+f81)!uYxUYEj#1-DQ827f?(bFQp<9AD!Y_QLn_-3$V#D1+iIsen~o*J<+ z{wHmN(gl=&He%mmS`f>7VgtMjpx4_oKG%>>c8`zdV)=%?hlU3aggMznDAZp2@dmh4 z1C1%4szT9L9;zc7UixM7GEhR^>iq1yo^mQ#L)!%LFV=(U-b1Y9MZ>;I|Z$hBU9iop=$_`|B!-e z)1kGniqg-qp4JYg-M}*0^g^lp82*u1!0~OGkHx@`b;;j*@x3UNg?ZD6AYQC3x48dN zOud{HR*uKC%~~pNo9!cO6~o`@u%(1#n;~pcMLP#kIhm?UmV7jIPFfRsC-Ke)fHT)C z0L?A0Q6u}%x}f@6k3_xGREIvG*IUjcDtt~?mh;-kkKK_e`;xO5n^_Ua=m6uJ-7casfdXKA_oesSs^Rc(!@h1k!*!~3UuHUrwl?dx?sev5Aj$(*F+WVb z^bFgwE=+zJSfugq2B}2noOoLR@;hugSaBh4}Z(b!C6$nlz>gz6%fW)SdmY{w>N367(T|5iV|1` z8gvqQQ?8QFCh;1br?$n~{XKhMUzBf4_aqKDJBwU2>0Dco4 zgmcpF)S#IB)%N+UeWvhm=1Gf)pEJufq1MaW`tjQ@rhH9zCapGbrwXJNLV|2U5DJbo z>gzaexwFTuSY^GJ@`L?OSKwm_8tcp{Elaxc#r|C?JoyHwn(S$x49aH&4q5C7aTaUe zrRV71)FcU|pKdJ~a#{dg74EUnJyqjRzs?l2IB2<`4E%S^(EpMt{;%TyDDZz2_&*B# z9|ivZQ2+!{5!^UvIbF`8I$0y18#<{%LnlLPI^s+~*2UiI8Y^MKZQsmi6ZPwZmW9f3P8%cL`UT}}E6v?xNl%XGzMTE<<6YJe`<#=Sw)6iskxQ%8pk#>@WMxt zM_S;^tA){KH$Ny?;4_jReO=*dd*#HCT^0xV_~>%8nnzdJ&8>`F^ke+r>|q%mPVdtB zUn{?iHjd+GS1}ej5?kLllHPB85;{eyJNK4VHus8+4lNV(VrU)P&-Y=b{!!Q;NjNK} z3zA)?^}VZrTRU?<{u1u4zov2X=>r2D7J}7iw}|OOvo#>0?^abyk4}w$0bc8tZfD?y zzKYsGn5cHavf9C%+eW5zSbY{dH-D-5hfaYNvvXIi*b%}b^{b5MM~mE$$9C?+$a2&J zvkRNHZ7;kpyZuPk;_rL@v&lHT%WZ-Oqat(3gUgJ5-2>Tque0al1E2COiJPC7q^sBr z($a$}i@>fAmO>JOJqvUvAi>|KQlNYpvJ>yP)Hex^F-dgEIFa5z(dd`3Jwia?&M zx+^qTpO75dEG@ZH6E)S+kQ`zH<30GE(bum@zwt>;(+O=q%%5NEGv0Py!7$KUffYq+nDA$*- z_poRoIfz{-h-Q6H#hu|JOsCkNeVyzinE91@`FQPP$vtp2<8g$$)aIwcJ){P!;h;xn zWVjo`v-$L-pMd4E*}$%S4?Hjx&c}M-nzOLloiVv#W!yP`jU5o_XV<4@sksub&!mIj z<$lK*H!NFnHwB-Yb{OC3EsSq@`raJ-ki57SB)-G@M{KvprIY(OizykZMtHrQD)&Z; zAo}jc%*WtD?AA>Dxy9tP^kA2!wil*WFXPm1dVQ!+6H<8qe_y1-F=M0sYeNok`iJ!^ z#f2Cxpn|1S(}>MH=OzYzg$DdI7p!X%D`EUnw4xuf_kizu(}DD6=GwoKG_qTcN0XKt zYdlAMoPOR9>fnBOTBZZo=zMhhCU&ve@>7HC`QY1(#CWr?=apUx0zN#VSvj45KK2v5 zOtrrpma=_9ZbkRtB+bCyAMxeap~taR@9WKsO){&tKk3Oo)=^fdHAl{B)lTlMj28=4 z@~Hfj%zA2&)N{-3!G|C**Qn;*srB2A!g;RAO{rI1sq%GG(m!Tg@a|JtTb zvTgMHcrWSaox)}dx3_AKe=+vo#=ACIVuYD)%zqksWW_qwrSfngX&oygx z^=?M>UOl_kdQIt;8oL4*Y^_UCU?!)xAmDz zj_&;6+;`sHYp4t3UhNrO$>@B_C%v}6jTzQ1HLD-$68n~tyo@7;xJo5 zPO0#SW>IUC(tI^o3YW&+ksHNPzWLoCAqVtqW&eg@V&dgj&rDR^tF3Dh%<5%BHgq+F z13o9gmDD1k@~U6;7aGG!G5&x2WGrOr6VQ7YZP-w7VJ&2qT5DIZrqHi7YOE2D}SXXEr<|!V)9wL&HB}zBJ%p{A#Gl#hkQL(Quuz7 zw?OEYaP@hzZ*pjMScu|jXj_L6{ihw`=Lg~G2<)q6{Cf;w+^!n|%gr6jfwvVOTeqiEW;WXk zeIp5bTPxX82|Ucm#w8W zm)PHzn3;{O#nk`p8{->qX2^~@DX((s1KXhhhvTrQKYTH>r}TgVI?E%vIm@*0>kp#$ z2~kHfNs2lbr)chk)$I`{$8~hCsnjITO3_?tHnBcDnVEO79(fLt2%2F+@ri*6o9Kr@ zh#UKI_R$RrWIVZkIDiyPPWtJFG*MRZo-&LD`kmCak)Qx5cI|l3FQX}H@HoohM{^O+ z(>!!+K+f)p89!JvljG+yUVsUO0DQA5z+Y}f*~gd~D;*~BrY)mu6p8#-!m%N`n5uJ; z4&fdN2S-Pe@0`scsLQ?tPcfgN!f%lm9|VAhf=fVF#csC&L%gc`M$=kl=s?rwnbh^5 z&>)nO%?%eeJcR9iuz6$nACm6i+&D;~gw8n{4{Q3--@7Qkp4h3CwDJG_iy-G{+dCW!#pE`xFCHZ&EiW(cg+GoyIlb(BZRbj-8_rBRfqOd=+>3Ix z>gm?)RO`I0O^RAHIk}&QzJC{eeY>%~1!&@_=2Cr<=8~roJwf8lS&!r)ktW^s*+2o7 zb5Tg~#dmWy-n5)L60?M-mbU42zmK5&et>JRp>RHX8 zBhrK3tp6n@vvy0biyc4@4bJoMlfU$2XUZA^oeI|9BNh)p5#*4i-|}FvHh{lSdjX@n z3456=vxRti#`V~=ZqHs2dt=YQTik$CRRC34(PwR4r^>#Pj&rVy_^6EdC=IKj@jbC2 zBPDsUs;J7G+>D);x>8$Ods1f1T0`X@q_$91RA5ey!A@IVrY$W#DMJH`uD^NAO!5N!kqlSAo)odYapchJuxFAWdYb>i8(ntkX5cN{SR^m z`j%P)U;O?b8X(64=<=@-`R&kZ@ny076m}2B<(8{In=iJGGLBTAD2~(~xP1j~vA`_{ zxYZEF6!LR>WfgSIbOVc=%<5Y@C=irdGByfQ#;G=9traE>Q?J2a%#ZG&UxYlK?mI<3 ziu`uFPtnWPjugrj+(ck5t`C$2g$BhH5=#txe zvhQSlp}6gS%hmKq>Bwi5wd*On?foaXGM)o$=ii7-TdU5S#8pJ7p~(lt7+zB91S&~k zS!1G8`@~1L@o~5DigWP|osZ+UYmDPIJ#@8i|G}sovFRbHeT(dTq`h7HPew)OV zes`XOl)Y}E9Lu=QBvf8eU%imS?^JgE5gmf3!=f0v`v=?9rMe>OKP4i0?tL?il*jw| zGk`~$m!f1Yr6;E*=k>v|nJ~opIMWy{^!HW}4|DE^xm(E<{@~;9FYqZuo(ZPy<-N0{ z;^LABPYto7KIl>b913@16nXYCFh^Ag=G`L~!Q3PuBwvz10G#Ch*CK^wmzgI9-Q5sO zDP0jDs+{EDv7{Ssee3Z_$`U%Z;X@8B0pORGUkqlg9BN-wM3SQdt`y3_+ zMFS(K;qD8V)D1uG?4WLr4#Fl@OIoXwJ^Sw3*MW@mvL9m3*?G-B)6BVw#C@4Jo(Gw= zOBufv6p#k%`8r@>InPUma6bY3Ol}Q_@@MH~QMrSe*4)oS?d25oFpU&G)#uNP$|`dQ zvu!N-*_rHadq!$l(90hJ!1^S2FI7p3z)NWXatDB0%U?M4U!0lv-JBea!!$J6{~fjM+I zyUo!@={E1MPdnpawY57o;B=*RN1kJI5g9bGpZS7W(B!)x; zKkWV+$}|Brz~_SpmLFvAqWvqw5K9dT5;7*@B!p-Q{Y*p%GF%I`-zB9k5y__0m$QKXILiISRcO2V<*_UJ2xM=B8x%tzV!3m`Q9#A2H1^! zlsut12L{+FACz1u1?@I6$0a(UzWUk(;ybIEatu(KczS1Pp>`U7O6E}60M_H-QemGI z*&x=~ABDmh-bj#By*yZPnUVxK_^F4xPP799-$}c4eM+#!i__@EauB4G&&V8zOzejX zrl0feHM6F}y>@g^?|7uln_X7&u*eT0g&9fmuS9-rufJR zemILTz__QYBGSzYh7c6 zFL6CKabyf;lRKFi-nACQEOBSEbZR1m22RRACY{`*Ol0MoR$4|1y5{eCCg9yf&7+Co ze~TDdYXIl*TS?POe0+V~i_{QRUhD2ZVSux9q~s))=5MoYV1F!*k&h}sI6$>Ab=SHF z0XUNbyEofLzbFPeg9Dv`5k3JYF<`XuUg|Yj;1MC0EVR(qJnr=-O9%nG;9?S|RgR(r z`e_5FzS934V~-yA39;Bt2J*A4KG3a*7&xodJSK$#=dac^MI7K91{|eTc;{o(e+Ozy zIW^^?3q5)#BRwPn#4ox6A%Kv^JTQm|h_*a%Jg}gq?0P^DjH>1l z4GcJu0HeSVRh|H&pa=oI+2k(fniJQG?SK@zs@Ao*fO73oftp7hyQwZzfzGTfJ!Rbs z$>}6kKd-doA)^S@lt*Vb>=p=B+uf&kqy_0UX66*mzDWdK%Hfeh;Use|A>nDAXd097}H!s>qeB zUiM%gVed?U=2YPW??j0xE6U7(oPl)=YgGS=EfRicFk2!)ORGHmr&Tgzvah}!dTK;K zWsFEd-LhG?jILcWV^Y_aBRW=O1a54Bf4_|QVQ8UG{rRtg!dBgAUDrlgCR8l^gK@Lk zU-;xcBfY+o9lMbezLL+zt5;2uPHot2kCvLQ+7Sj{k{Pk&&H={EPQPavTu^%6s0^rn zcS2Azpn<0ng+y4Z{eIOEyd|&uxh}ZN(#r1rCOIhl{zmw$vU0^w+rx$So4j9-~KqW6;Cg~dp$VYTK;J_2H%$6snAz{N_4j9PkMA1h`2 zL*F4L^2XtQsjTktkCaIJOfa>w1s*&Ab-3xMct*t0J)ym!{YM2=79(+EN21^v;K_Pq0RZb7FYbQ)fkf2zUe8(xp=|^v8VTfZ zt@CcUwAPJUPr?JuJbUUQ+?=V6d5qIzC<*klWXS6Kbi%3he5s4PC`a7`_q2%lV83aR zEEFP0EB$O^5gTa}*VYd;ik(UTccT?`p7~XW!0mVyc$m0F9EML|X57vrJ>Cj{(KaD5 zBr`O02U?vFOxmibhFN`= z)7fa4$9?$Zni4<*xCqm;r3B2ETS%GZWWY+v>?PEO82!ps9VXOh*h)1HL-d)CD^i zZgaCMtK`Spol?}yX?4CnJQ000XmuftULxV8a-P(OPyfMks{i|;#+Nr$`R7`#P5KR; zK82*UgLxU5f{kL}%DO*nb%*p76PsZoIV|Z`0zMT2VkTMmg)F*6r-@{TiRCq!u&rVP zlRz-4+M1ZXMOjBOFp@BiQ{B0ii8T?qw4K8o)2_+J4tl?T`c5)eHGhP$Ll8~lB~+#{ zYY>gL^NNG2Et|$Ur&?MB`l{2sW!{QI784pptGrXlAUEp(9jx(M!%A#Y0h2&4s+wjc z3KDQ^Rb);4;WOc?f5zs*st+6+H23*>;RHg(pw%a=!15h*8ZZek3CzhstMt^~ZcN~6 z_?gjvPU7!a7zyzH?%jZN$6i@M>8{CWh#?@OZ|jG@WwrcEU^z391eAmiF)tA|&YLuV zl@WrpyROiRjqNgt$Xplhhon#7X@(RB;=^v@!XuFg>18s$s$9$iS^0%9k_2BQ@0e(X zy?HXF0`Qu86PQ!=BQIg9i50i zBnv;00*zc%I06<`1z@@kAaXVcrgx%a~GJ?O^w zcT75SCRcSAjIqNWN8_Qy54+vQM^Z>p6He;Ghc3U|sUFIooZBzI?|oQfr)3GGHz%W~ zfZx10LWzW>%EXyYXTVOHZApw4-`-K5R5a4^m&Pal*uI%>YZKUVfh+oCMm~5HWepOM z*se{DV$G7d%$(PW=DI&^Tj&Hu+-3@z520LersiG~5_$yQDT}H#gH%FK+!YhZ_UV9;7n|Rue zFiU!s+^xd(WWH>>36L$Kg}E0m^tz~i-FkqaxBW8?)W0uB;;!_wfCh%D@!rQ^W`AuYFqsDbxr5~M<) zu}=G_{w`#Y*ZTlk21teToq3{CAtx(GzH~{_fwB1DKtYWC=EauwN}89K;TP=L_e!dYP@pn`8CZsphDSt{ zmjxaS0pVrn;;)4f>}jZTGlL$ib0e3DY461XnLqC=#s*>5C-&hVXnl`-WBeFT52Z|P z3Liij)FtWASx?34J>TMIabKcC#$MndBs??cWkgFvTxMc_k7ViCI8oRau@xNXeP81F za4ZiCBSWkMQ^2w<<{%a7YE$ah`fp#@1y;5nO_5h!twLQB zyM7HJ5vAdcWBi$I%XG;gv@Tdk;BaqFXERX&$s)}FF|%IaY4Df0F9DwEZSku*I1%8; zIoTm&j`5WMjaK?Aa8fWbfw*1ZIDrj+&WfiPT!ZY-OueCNyr~3 zoWF=d)4Vip)(GTgb#`|XNQx=`h?__LH9s_J%Dt5(r+F;+@yQ@~==H_ z2&4;4hSIPfUqhDnFPt~u&l2=!Gt~n>|NQb6t~PJTc0E7CY^*;CW${#qK*Fg>vNgKV zq>>?eKmSTK(1jG|TRhqJYi@NaU{w@&}abPdG4qUPwf?ehrL^cg> z;7m`i?UATR&zttZWK@n$JWq}kODGs$#F%9|B$Q(VVQ2l}I|#tZ0+|nCbmy|dtR<7$ zPMk52t%BRIDWoTHM$3Zx=41K8r}E=-gMill4jz9)3GUgfLEePDtbS_x^4_fV?@kH_ zZA{OH5tTZk&$=djT#+>NWL+iD3E!xQNhlqcdYiC7wrpigDlMg^rb%!fY$Yi^1 z5z&jGq_X_OdRdU44j^?O*}uu3Rato6?L*Z`?;o?QjIj3 z&Q=dfd0O4V~Bh!qT?{TnfX-faP+}NQtj^!6K`AyBC>CvEM{D?^}XU4k#N1iaz zAReo%lhTiao5Gn<8w>NBSuamNB>7w_w!!5AlNU$ z$!}4^ljslmoXM1H-6o&1<1bOvK%LifomPn;urr7Ql1rsDFh1#f(1bH|DgeLCuBppr zwl!mGReGl4hdXPV{6nGyDkv+$l`G5dH_NT`MNl!6TTIdS>P$H6tQ-#}XHahKShC}O zp4Y=VHqv-BBK#8)aU)?eQVxQWOS0C4LKdji+?Z2A8h@DI;EtDGEJQ-JhGYUQeUM(q9a%nrVAsvl0B3Y z{Fy13(;B%Fu2+#Xe0t*mWXUC>a}wT7t?`>DubA6#lS&L(fw`dDR$TNhaYi58xg@PP zbDSkp^!`@zq9gEDHW<B-f8kFxAj~3)2+o&wE7RA96+T zHIb-;QV2KJ35vb4g+J(@-;p}Wq^)1sKJ)EPID8MeM6^DtbEYnaT8I*OhSi)C(OXRf zwfLY4XUNh6p2qAhzvXfpPVTp()gLXFC1?vb$8?m_tSo~7*>0FoPm{*}G|lLAN$gj~ zC2TXF(2AILdOrchB{Hp8a`2(^M zuz>qpuMY36_ryGmukUQWKK&@6hha`5^==_KeGV+~U`Z)ya4&_nkR}-W$^#wE9ptr_ z?NVd2NzT_~PZ<($IkDRGW?cJ}!mc~dz*zP#X7_*+b#I&!^xV7C_vJ%K!uEEGlkG%!D$9)aU z$iyg0>EwvJlMeDN+IWSerp>!P)?bN*Y^5f+pd7#j)f=(pjttkNCG7pVgJx-2NLfdL z!hLo>6vnlqa5TSa$^ZL33bHVV3o520N@`!FwkKfw@ zmZxQdVj#kzA88QZlncP4(O6FV4W!HHHZ}nU#yL6D;qtHKf>iEYBhJ?*Vi@T;l4GZ# zJQ~C6J4)sgwJSSB_85Z6{BSapW&Hg}&~8CR1D4#pc)Jv1HF!sMIwM-#Q@@jkd32r; zcn=y~bzO~0ftRFpY283yR`#t2*Lkz*R&xjt^BptEuJ#GdhO1d*JXaG3&O7MtTxIK4 zKaik#81>E_U1*!No^#wS~ai!D1)@9s zl96zMW(~pt7S~HT1tLKvE+;tVYnhN|;7L)+s~M%`W~(bY>GRA|z^@YOJ!6sWb~pka z4`ZiRY*DQWn*j_=kVs5%4_I1Wsdx`pbe8(+tv$#(y8s|iM91D)>0P?`j_LeY zf#sCL6)xehvPlnvRJPpIC0uF3dt9sK6u}k+j>}bjX2{r$PPJ0Qh!AP_lG-Pg8iYLc zYdaD~8wHh&iWjKL|5o37;M1i06ji;9Kluh|e2xX1+KAdr*e2ib&mT}1$G>{Lw=aoP zY%`QlD=^HlCaW7epuy&eZuhhRz955u(ornKQzr(AAsoH=dfIgDhDn@9xT#eSzk1DZ zR)a`^j`5&T=|k7ogSRh#_7WP@De^(GpPB@~juPXibozjNZO)*FW8DOna)Yq;pO%BQ|9ef-*T9KdRPB=PNQzuUz(Or+X6D|KW?`hdnE@pro_f zP`Kdu;f5T)cJD(t8n3pRmaoZr1D@(rLq-5By@^)rGff_FM=SQhJ0ZHR_kp=#HLH@n% z1SAN|6hj%?>wb{VFn#M z--(GkewPgrC3IE@FoXEJh8jj>&oGc^$O?|cHN~2n8r2y-?~^8RBN7?*)I$i5v9vVg zPdiH~nzW_-qJI6cGP0Clru)KSqo84Z>6we!|Kh1P0lPX^;t&9uxg33x)%o z6oeuuZIN%|D+z0fCkK$wCAXEE)23=`S&ps*e1=9vIO;b-tS>4yu8SdWL?Tb&Z>)zZ z03J(N`bq*^0hGwF5owt7Hc?OivH{nx&#cq*_o7+=NlZDEoi=E`6QP6iM2~$5>pxGJ zs6h@ntn+>W^BRuS4?gd0cpdRL%QXD0xxBbTefL0B$MSJgp?1noohEl1!=r6O%Y}|- z2bicIk{)}XC)E(|K)le*_(nEon&$I1obe#zWrS%CbZHE)7kJWhukJHu@l@~m!g}R5 z9~i=7c>xTl0H!bWkRb5MU~H!`nJZ(+po0!wmU=-WznH8Db>fM@+FYQg%=Qt%!exOE z(o|q1;dYRIbG3SHw(s3vlBuuayN@))Z#jaXw5^`%hi!M}ff*Wm(Htwhd8laD+IiG| z$8urm6+l&)V2Zu-4E~g8UaRULUQsfC(ixF5ST$+ipMMR-d7V4*bjuYEK^aA+e9#bb zzZoXjjX0}ICwSBfUuG;;oeX*>C7%a)_*NJrM80apdsX9~K{ix|yr-Ma#MxPyDG#)>A9<)gbBh zUG4Ta>*&=qdCv#c^Bd*p)%YCTw?#*7jUh8_{8Y0P-EWJ|+8UE)+We_z7<%6pUBxx# zF|_41fe(-p{3SCL==R3s!V z-ltcUOq;U%0yPZ(A4S4Hs0|1KbqoxZCoVv-!npN|uEzWk5K3LV{|CJ(Ys?dxvHy>a zw8ng{Df`?1(C9IYRirH4=QOjf6N*CqahW};$ zA@`-zZWz=?$Q~I_9fB*+OW`|inF+e+yGVbAZYXWUz(MqOHJGi$T_J(QG1G`nKAPj2 z^Vho?8ed2Oj~eLWeKGU6@q@v8W-Xj8bb?G?0bYioqu2q(M#@+e40P@fp4}=h(>dH#QI`XsK@{d zi`j4Iq31gT2CFNa?Zt)IF=oo)j^!X-8K6Z7RSj1=s-o8Yf-9+ZDdF3tz7o z^vj4Uh8Hv-v_3X%%0V)JwyW`8%Ae7gv~fePpCK!Cycn$QH?}Y5@H&RZ^v%>Odty?6 zt6RDeE46!63-6V9R4VyFtNAWQVpbicV}NW5=wDwvDurGLXxF?^$H#ZLki5QDx!5aN97_G|>f?7JG{(hl}CA z?ijakdS++#IM2W?tC#tL)sFS2*l{wRQDu@myTWu^>wg_eH$x(bVhV9nzJex46*x5) zJ~HBdAHa>%;A+#7M}sE3feB1Crj)lwZm;~g#+7juDk;LOO>LT@nM!27VPQM$5tA3Y z;>KHV77+wJ{$qFm?l%Ls944V2`7yK-6hyfeMS`Xj9UY?gTelBVU~oa;Absd^aI+Rv z=u1(M(T~`21Q=&pUUz3l0tksSrEah)Gh3$}|3KZUle|k!hz>k`J$Pc;v5^XvhLUJL zb%`8m(rJwNg&Lz_)hmWmh$hU+qv}PF56RZbrjODGG`K}UaE#m7eSsy#fu(5{aWP+t zX`SlQyV;ixtk=RDzSo%dh<$U|7v&bG`g@Ld&$cun6xA};2n+6oc)UH-^00gFCu=N( zs5h&JTnSvlcS`|>9-Wx0y-%;FA2&uFuQSj)vx@tXF^?orJW|#>r4b*kk8g+?BZ?nb z?}}xK7<|n;G{~ zn*lMuQYn%edbNV7)ZLX)Wv^iJE2u@-Rf84eQFvIzk2lcsTi?^=I|A8uGc=1)G}~!n zTD#S)2Gy%&NNdd0ahxD4=fcmLx$%7NaDL)kgagEUgk_u%&y*w2wBuBC*S(W>d6o;& zmpciHTi+k3QdU8TKP`Xil=Ck??X&T|R^@+6CwSFG*4KD^jbv%4h_0e0RZK~+7#ndh zGvyv944FxxYcxDjm-mrJ^Q(vuoFB}k-Mev=d80{_af5cVU^ltJ;XhUQliA*lIdpdYMu9e41DN&C3?78i(w-crZp zzH^6RU@MXkYoaJXvwPq9e}1k`cY81#J2*%F&}3nqo@nh(vH zoZ)h?{>z*9Ysx3PEBd7l9-I57Q+~|!pswHDqO6fWtcGY9OzG-m{N>if3z^6RKD{^|nl4!zXL zZV%KBbGkxOl@|y5M<=#>s*OyZP+hHLW5^(8X?>!}juKZoQKJi#u`ota<3W*?(yE?R zkoue&>`ajo-^l=bz(%WvPJ^GQRWd%GY9E2`LF!nXf^nZ_29KS z(|vsnO3>aJGb|G1kp)V{A;NX`$Qq-4-30&$c+!%nP5=sh{hq(aPlG7vTtkAq31f@B zL92|_6}Tup0S8F<8s|Q+BteiGr#^P(Yig{lmaO2w>DFyl=4);&pB!)sS^%1qkBb>n zG@Y>Au3>Q;W1e2a4;H=EurG=}0p_{LzcdOUSjK)0TKk)@MTO~w^j{-@1=4}QG9U|) z#6?&dnJ4yJKLg8`j^47z385K8#rG=AQOeyJ8kS3=SGW?4Se1y(m}c`Kr$M&|9h5pv z*ldlsvDzgi>AKjmxchT{JM=$y<^HPA?VF0SVV%U-)}6^<-Go9_xoF2`$CL=+*p99E z>cr5x8q}?a$}^hF0rGBdBq)T6D=-z1L_Q!*rzg>g3j^8f?a(p#gen#kBREbxbNU$O zN$gZ7!Xr(o)$$zHvdW-I+jl%dF213YhA`nbqbFEj(>#*Hk5EGun8H!kZtsjHG!Uvc zy?^L{V%i?1J3hTh1$a~qW*T|E{rrsE3R<*kE0%``;xoZBJh!fQ-YutUzcx0m^j7w?`j>p|r zhWDp^xR#8*ZKy0BdgdxBWQw{BO=Ys0GIe=@ii&!1QH6{&drG1;4S9A&vTKFPT)K?3 z#T!w-7HgDxe01F^f8@skQk?RtB+)dFVtNL;BYa#Pu8;jsmPiFYHNYk8Pox;?QWU zPwBOEEG)*_ru*g%BN^x{#KhbZXiD4)z)b^92~oe0pKor)aygcbZLO3P43Q;O!FQ%r z*q0FcEs~KFy;PZ5sLG?QCc=2AcL zTMdwLQ+5O`idv&ymUP6c6_!uQ2&s{hsiOqCB}|v2{DKw&gwtKK`(~6ZCc9quoqCsp zJ42dGIca=%)*WBB=tXMZ~|CDn?*rxZxyoWpGDPw{(v|+fnB_ z6nV5KOsz_2HCI?XH3qs&w2C9^@b<+bTBvW%nb?U`fzNZ94h<-9m2uu>)%cvv@Xn6* zdMV(@vOYRFqArrMMReKAC3U#15V@#{KIXN&Vg#Co%0O25K;<67`rx2B!6Iv`)7bl(kNe|Lm^+?4JJYK&E}t#<*2Y=@pG3+dX1*r90JRNb28p zW5kRf+HfKU*Id|9BT|m6$xzRx7NraiXcLtTLa?;JgC_JOu&_acCJe-|sB)nvKb68J zPX!&yRYQ**3cGxphLiy|nA4DB2f`kV*{Ywxi|fE-jNX#&Pbp8D6ya!di1tdZ1~lTmY2MY6&+3dt|&43O2&O4ib+=yJJ5@-d<> z`?}Vs)?6WI5#=w7j&P+Ys_Ke1`lh-wNEXTYr4RnM7pIShs5An74E&p52rx zbiE7bJ>RYe@z^Gsl)yZk)?DB0;;|G_q3k(|J6K$=lP|{oRHVf{s(S7c1qyT2`0LdY zrgy>X$~dobKjO-msOV;)8qJvNedpO&%h>EztJv2ovg6kER}iGJd;zJ|6!t?& zz`ThPZVOwAaE=7G9iS)|wvsGFRG3mXOgoo|}>YVsppfB`1$s zKHBjrO$b}Zag}&<{tr}5{0k~6{ROFM|ALhGBV?W(hNb*FN`}1?o zeYrDiUL@fVEEP>VW%enVzjxC&MOTt4)5JuO)5XsM;t_R;C*ojbnl{h-B>gfJP_TLW z)d%x|Ftn>hlz*HZW=6|&jTe2p0yIgEkQTP{r_MXDZ!_6hGQ#Vb;?g@~hzSW=8+Ls` z7K&YG#ypsn(B_3{e-8N1j` z8H5T7Lz%?|k zq(cpw6X_tZik3NWzjs$4riwi#IOQB{zKhs6mfpk7REO*HERHm)v=*OZ6D}Xg_?*xf zqe*kCRxPzAM2q27qCs|XOoQQ7qe0dM{MjzW5|Wa}>MivCcFy>t0NTg>nx&tup+GhiVPG0oX>_$`mt}5=Ix&MBQ=*UwflO+r+_9|N#*)7L$VVFWydO>a!!rPC>7=8 z%xh^vZKdB)g=N8M3;urgpQPwuQZPYNRr$)h{EgS#O4*+$gTZUK?;lnj)-}QF{F90FZw^7nh0VkCQ$@CNvCuwMZ81KZj=$ESX5AP@&^E9j|%MoR(S-m7mkL~?=`+#jo2$=9hD&mqCzMl)! z`dv8cAukNTfkuO%R!{}x*Q$+6Cv+-EtS1ovOUN zUH+Sc2VJgnv0%wub*-PS$-JfOkRKfiaeE`pz!uEB!uDSgR@kc0M3X z;qy3)+X+efBok(k_t1b3O(!A@d+5Gfg4X#d#(3w*HKHX9HmUw+d^LUi>_h6=1x4P1 zJ)7_pjY*!!AKFXIO@h^1V+c~36zZvZ5L z5!Z^FoKkef&)c2QJ#{R;E`N5fJ@y$09hi zhoOv?!Q7|vSA$cbK2iYitYg4U(3Jo~P`v zG5E~@mgwu5c%`>^x5xRJhV55X2sNI+`r#bYrb7QG+;(JB0{-EH_}Q@R3G zA%Ec894-R~yq!7(-M{(Zz1UoE)1`w0A7pCT@5|-G3acd+`gbhZ zVmM8ij#Qm}h_93^-F!$SeWN7OYHhZ}zQ16L26(4f7yEG~UUYg=gRi@=%5^AkF~C+TkC6 z6|26Ao#wRwOZb~3zO_Uf>0OQB`Qwzcn7H4S6iy8k&Xs##^F1ejeLsL87aQPsJBEKY zV)u@{SZR5Bbw_tljQcB~D%gO%43Il4Bt1I>E@?2rX)#>pl5twR?J&|_I2cG;c`zr7 zdb5H>^L@6a!~PccJ{csyNhIy56`6 zHTTJtaexE)8gsk)hjYCiqs2EgHA=H*I({0YS`Rl2LBZntZ&UsDC96`zI!(U zg-+pPsLEN>Z$m2|kOT1-iE*z(d#*b=cSn;;?QxMW5kSfOo_?~QfW!l%HlgEWEG$Ar zeZ79}YY6*SiI@>%n>RLJ{{}yEIKpaQDqr@ymiKygp<=-pa~(h9O~sZaSCsmlKRPja z%eRn+$^2-zJ*RQMgJeClOl&>koLEGw@S&K9Wn$ zvX_yI!zFkA&$a}w4?i*#33CA^@7@A>(aln9g%9VyZ$4gf9Ucs{p#%J^c&8(Y11)dT zdV>nhD?@y~OTX}?Nr}ltL!8{Rd6zM}Df!7|fa|hUfyO+yVWYZz0V>Z%7Dmwj=+1`e zr=mRhY~+^rj#e!%9wg5MlSOrGnA2kuK<%o+9xP)K?w>(dQ!xN7hvN|r#HF&GA*jH+ z3`a7UoiKb)%hkaZgVOKmO@YJX;)%U$k{`&z$k1R5qOYe9&`*i`CKk?3Ilq+S-Co1| z`M9jK3dK+Wv87Q*2Y2R=n>dAv<^sWo54X=Z)XMum{2d%qhJ>-Y^NH9CyLYxpCsyKC zjJ*VQ7zmqZj-PbSK-0gjNbDrj+s^6vb%bDYZ;eIAm&Zy@W5>$DPft_<82!$J;;n?iZBdji4zN)N@DRfLbyVnonZ~(%>{6l+A`L z-37_wAoh>`5#Uge?`Xhv!)d`d!@cf6?i#fTT?RV^Cy*UIKwDl~T9u&$C0m%Y(ogXhF=T6I!>pm@+n;Qc?ck5Y#i3`;XMw^G`>&o?;lgW z{0#CE9Bj9N3FrW(#M8wLKY|GE;O_x_Jyd{n!B3b{=*VxglZ+Zn06?qIOjGFA5#tK- z3|5Vck7#@CtHKvCw2icV<>e{txt*%rmt`TuezaBkOH+)TET}X@h z;lbyK;ou_C68U94@~34d;`+X!n(9+hOHpk>(tTrZEhU5VdLV=C-w-gnt;~KH(LY{w zw!h{(V8!OSrDYWrg5!|TXywH&P4mzdtT_@Ma!Oo?lYTM957p32c_vgpov)mQ-G|Nf z`Cu~;KV%61nK7^}-?&l)&3;p(AWS~f?04`a(IVeq%>Wq-Y0A`> z0B|PtC#bA?UdI7yk+vsZNYtF{L9$qassp0yJsJ+1!Wg5OCy$2_RPkf9wsxxoR zD*Ogjlo>?fgH~~nDA*yh4S}ds{va~bEac~^?aQSUecsp@hwzo zye^50*8#fQ5d)(U$1PP1vG#&tTr2DZ;S$?nuu?4}6~_4X5!THsKdl+o4ihXL7E0EL zzzG4oSQrl^m=}m3;?Iex%Mxlh$z6sI1h2qUkfm%SOb>yUx#{xcB&MOd&?lk@N~6-< zPs!meWvAp*C~IH?UADBF_fdw|Ye~H*Ch9cY)v1_Fn)2b3d&j{CAZC)^!f2K?lXP5$ z%wm4fQl~p|1UN;X8T0t(g@ZxwNluY~m9{HCuT~u__+c-Ev4gXA29d3~o=Wg3F|L0|R-U9_B8^U@4aza8K`pz+MaWYkcnpe->o!vX38dm zH>l|A8bpcI;%sxdfsU#ua$eDnC1e~uj$(x6oRB#XU0}+y%^YwYo!OAe(Q#Uc3x_N* z2(7b#@1+Bu7d>F)^51CNGy>!@S*r$jU@PEks)URA3&r^Qz6`BPTCY{^u;T^&o2}b zmJVLwDI~tw42r6e6&Vf^9Cmio@M{?M%MKW$VZsQT;5hY!@&n*Qc2@`>ttL+|ULx{*^;A8Wc zW7(Vn$6(*jU`dct;flc5Nbk`|AS=Q8&o zx*_7RjLXRCcFFNQL9N-=mu^lbA3UmAwG-{ZbC!YuCU+O2JIwkDe$iL})I+VeS35z- zQ1i{H><`V2DHMd&O7Tm+MTR{&*j0rHhwIhdj+h`mf)Jt}mlsf{)aW_2{lm(7-3Et+ znIz2y>;5W8=)5o0>d0A2)p4by6Xstz4vY9=W2Q~Km!<}p2oSjvb*Vk!0)3(R8kBpp zcN=L~1j3pzvj(v?VZ!{EkS7VzXm4Vf%@P7ZGF z9Lq)EID*Za>4jpMdIna2#C8g|V18XgAUQ`+A0GA%sF5|P5q$70-x^K-ZPYc}cw`Cw z)t84V13%2K?nc0yZL%MYgf@`w98339P18T^0q)CO#lwbaY8KAoD6HJnz4Yy1hQPQB z$=y-50RCMeMhdgjaX3L_;PyFUbrx} z;LK!08Lp=J)g~;LM)ih`AFRWFHdfG6ac%rrTpDZM6I(&cE*N`f^nQFueF-?3l*`ON zEpa#cMx(sQD)^#lK@H-4+}io|)ni0^QSC^JMjrv0fH#b8(ch#xpCZM`vXoOlI}z$L zcm>q)LeUlhL@DL-6a}=|pqYJ_8m``vgnpe|?+45?dJ+s3lEO*qtnuR8!|)%&R`Myr zI0{D=WcW2Gm7CJ`MJO$!=QC12$rZE&;(8wZefk4_G>ZXLFe$j{d4cfyDh%+%xMD&E z?ahL}F}NjYbjb*=EM9r~1=0DxMm!Zdi}+>-peG*EJ960@cPj^BZ>_F<;9U=Y@cZr( z6jQ!62GjvyD99$naf>b9=GF2F--vJGu>eZCQC zfkeSko{xNPH{5@_V;o>vtN4-YH60;Cecq#Uu5*QNk2XBDQtQgYeGHfXHhnw^>jsRf z?Y$LYweID5>fAV5*J#_;yciAvqm6pdD(05yY&_l`h1^B7-}=HvRUt z^vg1qk3YbTE!(d>PXkRC*H!~NHuz4X+>;Jao|K$Gg2NxPyqPF&IX?q0XC=~x4WlXm zh^2JBF=g1MpD!wxjw6s-Kl%@z*vKec~&gGUF*-G9Y<-t~9fxvv@QI!8J1s*2H9tm-?+w&3Fv z>%*SLZZ!%B__Zr!>1&RAF$-UzH5BXcfa$o*!RIYD5DLNF?TmHh{&7E9u8(s2{|Ft*q$lH(I$| zt85rwhtbg7(2OxP`pa9nw-URZi!QO_Zs;_%RBS7^{c)<1i#M#QEkq3SoGbtL5!fxP z9HDtu@vmfxYH@7~z#)UFZThNj`bxY`4NqGDH$nMea!ra2{c$<5@_j9*yT2P$B;f=n zM5*}_r(uZbyKhZR_G}XAOk{DAv%P@qRH*%@7iT^>H&*8}yl7PRY!nd@DSNSSK;Dz} zE?{H#VwKz{=c3SF0Nmrtts3n9-n7LkesuP%=kkwrk+5^P-`O;}2Ef2GW~iNTqF z=}0zkmOq%NS~9|e+TM!dQnG){`XLGA;$P1g5f$qO6{}v_@hrEv4A~VGT1y)_T~WL7 zw~y*6rvL6b>TUXB$}jDEqjTn)B|J6iiYwYm=>0wM{O~bH zNqm4A4{eg$&smTWdf?E-{)cBo(fRU=>4xH48Mz)aq5#^z{Gx}r?Ae7y$v5AJ9gn-U zuub2#%Bd5e7~FeOt{a9ZaVfx1{!v%eY{I&k#}0SGoWff-Gx2tC&VTY;M+wUW~v4r9(+G13xdO8!m1@}}>|o9tb# z(M^zO5MQ)^-(`8hTuinX@JG&?hOY)@6VTLX3tLLmzT^W>Y+YbF?_Y!3@hFSFK{YU^ zNKBb$9^&P5jhihTxfGOJ-utTK2}TbHAM#2AM}PthqUkJ^UvUJ{(s|jdlnCzMvi=fw zudlrn=2&B02@4@N|7>KVI)IC2h#K>(-W4>}O?yF(p>xrL>5ck6uM&p0ryl{@w;T8A zG#6^1c&?tDuhb_*FYD9t;I>KflLdr(gjpFu_C9vlPS5ztEthnypRdk@ldNP@v^14@ zm))%Hk?VTUuHuFkc&XVzPj?LBe4k|4Lnpm4!RaeljluPIdNAjjp8nT$DH}`IN_Vw8 zX*FiOTTi!R{5sQYIp|>HmF?W$U4oQKs2OV8=KK+2A79s=GvG6D*gYP>9R#)KK=1i; z=654#Ju(21v72O)76Q_8i8ji{GCI&-y0Y6!;MS_ct>-4n4iR*8QW*l81QscGmSbBh%dDzE@@VIIF1Ic`;mY zlgq(_1B2L?#Hg?O~Zp zT-YU&Hpq{|FyZ^d=b(lkuKa3#y>y z=|F??(OI%FyGYt}#0p?Mjl_+<8W8YWeP+(;&-~r6%CRb@=3UKsofpOV3cPH31SKAk zxpi`3#qX!hO3{&+Odnh34{7|23KSZhN5Z1FSLA!@qo0FKd-j0h>3Co78cqx*rrYIw zy1md@-Qy>i24*8-NiJIPXi+@6Pb6yKz7d${5*Z*(roU&@f+(nszgI8@&Wv3w1`&V? zwNLcOQGP50@!KE^2Z?F`C){FW2!K9i2>JSqf_#-fy23AaM)1D-Ee0izz-F&DSm>Id zt_ho8;N^*pwA%nG+X#&#T_XD`?NIMxtmyUV&X`3TE1gi<@j6(H&3>W1FCmQ6m8CbS zj&fGPQL0O;uH2sA%+Ybh>CB>9^LcUyLx`6S zh}9m<9mJe~d4oP|e5!~&S#uY4z+L#mGmilX-Jp()ec=5aGypWC1k#QNmV=@*ncGb? z3#f6UVMn=aR+&_aOd~rgPAc_IG6M*{;0k^q458VR4`?fSv9+>4@}|^*g2O5Oc{mbc zA21~<=&w6=4@`+dAmFoTc*NzWiJ>mD8D|~Rn-3lm$udoA?8$W^1J3a4=|B~{KVtz$ z<*5>NQ8*Ly6}z`8j*8q$l0{fo5wryt_g9w5)$JKBX&v0R-^I|?EN?vl>m@~!tq}x+ zfbNx3B@;PjJ=r{*-%$i$phSO3qm-r(;q>nf)x!F)6th+DD=_9oGlKu%^2`4>zNZxb z<{RY{|38Si=>HKShq)}Hj(is0LmX+wSN7i$yZkSSh10;B*^e>ON)?6wHDnU+3r8rM z`uT$#=3!TQFY^vsZ^s$RugOy^ZS5|B_Oo5_1T_=af55DhqXvd|MX2~0H`JhEbrE(G;*L6pn2 zJt<6A5wqUcJmTLmL_F1sf*1!x<5-(8gER<0kakKe;V8F?eL!~?j0i)|z|0sjW`me- zSZn2h-Z>z!bl{5FwmbMhZ>TFhiWF&)>;s=TmXpT%lDVXk@G43)>pPH4+=1pfDCrfN z@CvszQ)aXavymbBM<3a;(~JBvfl2PiO&!-Uj^K8yzAJb#BUs*NNMf$~ zFYVogY5exIdp#*0O&bCI*)EO*yyw^*aQUlb!Fny3|0pOT@NBJ-NB8kW-T!GMjZ^A5 ze>Hy~OIfdD5<8&rIU34S-NsONJ!D=`k`a*Wf^TnFlv@-)fu>=<+)BiDvW1W8~ zZ|%VUBW}$<;x>ycwjO5g)twf)blZp)Y~1~K%XjLo2I>U6cY{UfKTFC#hJy>X>p{q` znYwocxkQ1%A9bKN%+4QUzTFkj14K>yDNdLZiP)$!1WzQxrQGo+~0o5P5$W@f`>%w_|e?OG#v^H zB}5Gu3WiFaAqf3k0XW!pln`JctU8KWWDg1CT#Smg{|`gCGzR=H<3v=;3HJAbh|C)i z0Akd&ep~y^-U~IGtS~g&cYlsp(ty&afg}! zv3u=<eoMW6tb*(pU`FYVV>`uNRf^65eIK{?_}l-8II1HJFTd1x*fKbX*=SzYZyBAe4Sz7Smp?n`Utse**z zRguvtL~2|X`W!rTCZ*cC;awUnN_>hdbUn0r*m(>DmBMzc3&PDj>_aLBOr%Hx6~wddou+Rwoc+4qA+M%Vt-Rg}YG;bA3*7iBpH z!WQ_D#|-VX>*&2Yd%BtN>M#BtUDBrhiHeg15;%Zxdl?~86rBcnwdDWjZBK>TlGy08t`f$PED~`ZoYlYvaBIt^^2rO9*=$DPX0tB!Nag zm8hR56bnZn4ciWF5>Kye;sCCO5b0L#+8 zbM@tX*z%Y^$s{EdcK3@)0<;AqTs27`gkI86@$f^u*D+>pc@Bhfsim$5*H|t*tPh$$ z1`@JYk5XFyBdnH_7%`_92zchv3Hfh2{idgmzR7W00q?ut`77DAoOf99EK1BVU*iX@ z^QL+oPLS0&Cf8VV$OwM2TP!(W6b7_>{4QkT!=3%OmQd~$eD1}bE;q3s;8v{3kRv|Q zQsesuw~_|6H*ZS;H-H;z&5++NqiO1wCum^TM_Z^-{9yT;zn;Q6^q{{+`Qg(1bw651 zv}o$VH+X~Fi8OAA(lMfkQ(r)|1+%SE6;kzPl?|gcwz1$c+`@}>$k5G9vbMo_nsXyI zYDQ{&f`;-eJ8mNQi_`%cY_1&CGn3CYpVwrlX;P|X!pg@4p&bg+;I$adz~CJXf0o>G z6Za!9CM##Y`^<<9GaXqCVG}B%gk297?DANn{wJaDxujli?`6viXPb({l^93&WT(v# zvX<(SPObLfr*i^l?K$3m1%(;fsyCm&qoQS?{ z*73s_WZn!T5T(og5Y-`>0;v2VI$c(1|ak5}JEkNdn+Tm$KIkv+GsPf%4>|Ihh$%1`A1Tkp&W!R z?AzY!nlMv2q0YXt?{>d+Cw!C_%kXZ`1bTV_qYC0d7wMOLgLkQ<$%aI#K|RNoEqsY5 zz*E^2&OB3uG%%8_D4klN6RES6hZ-}fWuQ)8$)V3`TTD8cr*_zJBl>?Qax z`FOh3tC)7)gU}|`vUwC%Nz57*afS5<9nHG+{{<))IastdTha3T=JL$d%EQ=$%b>>Lk%1twtK+`;^#ez>{eNQY0-CM(-L}x+z7OFIlTSLK3(-JUrnpoF z3`oi(x>TZ$iipj+z-%t*IUfc%CI(35c#(qrC+Rvyl#m6v@1Y0{T&y>IsLHsUC{pM* z5HXZGw8Pc5o$xsxWH3>rV@M#*QNR5+R}ZhW+MpNFsZt>7p+= zv3n1|0K2(fm|t1{%C^oh8hy1}4)X{gqPyq(hUDZpVqtwWsA+a>TM^kL|H!b3$u`xR9ZT1dR2z&8{!kPI3Cy>dJW0@%& zqV;Q-Qg~1m3c>vbE*~aYoxB3(Sj{aQ;GZuXs#iTs>6|??gR07Ph7%8;>@yk>alC!$ zT~_L79{runeOyhoM(!oAq%f^_)XGuJn(u)8WSPQwa~DP0SqG^2YJ~UBcbi|oWy#Kf zg<8T6&_pFw@?LOpZG6qwo(-vHli+b8gN~(O_PW8-UIS&Pz=?1@5PY)U*#F8cfy{{_ zR#A2$D0i?`=iiLqbyjHMhH66PWloX}&anzG#2xLEbgItZZL*aJ@2Bp)M58slgDx7;%CDa#X6U? zT-VO#);i*IjXQkM@p3=OC^GpBAsBgri!m|0PQ@YA?N`oc1aFxDM#B|$zGj8^Lu2i& zpC?O_`Gpe1SJV0?tBqZeXkkGXX&ZPvif84Q?hnt0hYt@ATqJ%h-*UcnCXBQbeWD;#-eob6z z(BA7ysKc=j{VtrKI|wvgjsUxe?KmRcBR1?|rFwO0*aOmM^Q5s<&R-GjQ1V;PP*~tz z`{|_@e0e+=!p;hnh_QEVKU;jZ)n?Cr{K%;8<4QBx>hhye0YNHWqnKAPF9;f)^JDfS z+w9_cgu8+40?j1tLyevvp@wuig~`WHlcws)!&Xox*SM%+_{QE`fGyuy9%WdWtt^#v z-sf~=gW0|*0NNgae-Rc(IJE`BidgMBCxHdh}l5Z3%6TF0tSBHPg-x&3sr4&g4GJWTj!VPC6RNF^EyB-vM3ikbLX zEBu9N_(`&y`g6RaMCDEJ=nj;r1C}ln_+pX-Ky3RWmajr+-{vJ3+pCEX4@vV*+o65f zhjY&sM3N1#(i3aXf||B7EQi5Z=5)|oV*Q_?Rr=n-1u_Q(n8?jE?`oArT#nB5` zf(W90lz;F818;7dH<|E=7T3t;62^&5qUL7^p1qyw7@as}H0YIx)&(XyRGwN9Z8G-V z0oNh06r=FW>haXDf?xVL#?UD&bExaU&0NFP&X zsdJJy6SWH|fz6399r330FFCw9Wh5GsttU#v5*tJOidrhx;Cr)z)O=J8_#%)LG@pzm z0~#29HiT+mayW-3Zx6(4-df z29_%=M(z#%*Gwxyan6*lLgU2#m6jQC2$i~);cd*QQ-3XgUDGc7AO)36WJ$V|qeRec zB$Ex9r)cQ2=|VIa7pdd3nEhfknP+i}bmYMkMU&j%I?iF6$$j4$;Npv<3hu!vX(g2; zZFFKjtz3&q6`ns}JSfg`SF4~yEW?&kqe_Dw&m1I~Y;cnl>zm73okw5U4O{M%&u$vYVeeC9>WL$59Up}T!OLl#Byc9_InE(9`_z9$pV2*RUj&gN_;$|!;O+hKs^+h|WKf-PUmyEXBu?Tr z3~~_$h1bNA4<<-~HUNK0kL0b763Fr5*={26yf=qOL}WzS?9^)VBZYtOZPL*2^_)A^I{)%QuKp5rH}KdgAXG|kFj zwF6I_!@6ffmH@${lbFypW4vOtW4!%knIA2$BEQ*q23!~(Y1B)ev_*qRNRq@8nW z{wn|~967;`h`2=kB_(|ttZM7mNSO?T5K~`}4Nl=L%R@so)gonRS&snVp6^c`yQS$= zv!mnJ`)cL{YS?JqeIHfUjY=fc&BI8LpA&FNj?~D~c4WdW(A1GdmBnOHkME{REi06i z?p`QhQraOMWL8GIMJbB6BtNLwQJ{u!QJEAo_~UhvX|3<$dKVl*xM)7WRi&$|6>X!a7ilXN8V{kM5U_UN&_J(P9-bBY>oBeU zq|e}UtnO?($|CEAv#ZOm;+OoZdx2rpuBN*QHeiZZm>zWT6!--4rWcL8*P>8A^(l#c z=ByrDBTsHcLK(VI_@T)_Zv|s+b8LOYB?r_==Amonf;)yr04qEr zG|$O@8tDINSozy<_`X!*f;Tg5O`hrIFyy6GOV*5N&qZ0CYPvj(aAMM$G{y6MPq#)r zNsE&+C;VqoA3%r1O-VHyhVD*7E!w2Bp!rmJC>;u0rZJ*WPq1<=Tq7c}VwKCOM>n~` zw?{Sk$yupvP`-0GuSk&&z4cbf!GA<*Q$#_j0<21>xgx7>DGr2dNu;TSqV9oa09j2( zLt1e2<1HFg%@VC^A<^jmP6vSTo2u{O*+u3Qu{-m zAuPAwfS|qI-`{t&_KL;b{`h2i$h>QNOF$q6eSPir*y#PiK6%U5J^LJ2x&G`b`||f= z7W#}rprH)b`Ix0MZN-eN15E)v-wv|J`{d)zw^|~mq#!k+WKmi%d;gf5fyhBSPzq|E z48mK&vW7|6kjir8>7+h_F9Q+yBy&X7-OlV}lhhg{JH%*-!8GA25-Si>jKiER5{{JS z>2i8ZK`~$2eODu?6~DMHrQE>2?{molC(wljPsJ5o1zVD4dYj43$F&^j$ty4g`+0Z8 zIcK>m=3S~{t{O%Bvh}r(_$}sv5B4RjLBV%LNq!MI3cUR|jH)Xt!8RZ>WGDQ%tlF^- z97n<_F*{a^teWqt%|K5p)CqrrriRIwISZ+fm5f|fuZSDVuT{Zu(+W(zzh^(-R|WhXOTUd?17o@IEn5B zOUlbHjE%~~8cf*%7P_kTt{JMp*k58RF%{lD4D7Ll)^H`*4-+yUk)btK?v>h*aQ9V4 z#Twzw{brK|N-R!RGB@ydAnt4dMY%ui@sZv{ew=ST){OIN*1A&H*J)!}LAMiupt z=y;uQ^6D(a4wZGY%F|VJ=vA~CDL@Wvj=ayhU2?waiVDrbz!ZGD;)HOz_USt+ zR1B@yc|{P;*m}*a!?d-XG&f3`s)w&`>Soh%v+A%{JnMDV4Y%)c)-AuurvOGc*aPZ? zkDaYKZ%l|43=T$av>^&5sz$0^+^fp%tixo@%Dz6pYmPhqEDAOjmW_2-6vh};WoqaXT>9}gNYX5Fk06im#U)TL(OtO@?mF8!fQQ;boV~?jJ z(n4Wpj$qf7EfiTsNou|8tX(=x(-elAGBsnm)c-4KZ@Qn#=JbNESCgFYJ7u5d_dMzQ zk~C@6Bbud!D8xAEfY;nsZi#UNIOC{0M-jgqmUhcz`JZC>+Z=s=(!QwURwRC^Ji#Y> zv}h4bi|~wr<%Ql)`K$RIsC^*#$t&M@+bb#G+!Z^DRb|LMRQ|lf#ky)`09c>dJGg&x z=8on;mHS;yUG;HkmlD4NkvKj(Fh=@3>QjwX>k_FlFBs>WBed9ne~<6?r5hcgujG^= zs#x|)(g`C$e0%1e_Ce^LP0@78U1;YeeeIUR78ksrHh6g2-vI)n7wc*LZ-k4R>**Pn{Fsh-Fu*^FH$;Bsrd&1X^ny1J7c65o@rO#Msp=W)+`vIjt!y_PJ_6fTEeO zO39MaoGT?sR5wb0g}Ap2fd96$i;g%tWNK)&s1QmA%A|5dZE!6F0qWjbNT4x@*pH2c zNrGW;UXlf2{B(!>`sMdY@1rA?hwbS#M*iqjm*%%RlC4gP(Ogu3H*=@43+-*?FGrjD zQ4P2OK$J-xDF1;r@A3Lz~wq?Cf6FyI9cwH(+&WKvj8)d=!Ls7yhau<`+@E$h4JRKma(V$_&Ht!jjs ze}6OcuWt|(gVgc51Eu=S*XU70kYTZfqaldJz%WOw(2QVE0$E$em_jDzv{6Va;A`2L zgT@l#4!olA1Fm3Z3Q`7wV`owdhY<;EU60}ESpp~{929DR9Q)D&CKwd z0PwdJ+tS!l<3S8K^kg5oY77^qI^>lR!yRo&zEk7y zg{~;@ny$zWxNE^{RYdwcmwmV8X|;^ZL&MyGmE8>(j?~K09F9~1tcEZut!Ibct?Go` zt>T5>t!{+>DJ6NLa1gspT#2HM7eD%c^J#pt6F$~qZ>*U)hMy4PL-;sRVI{NrxUnK8%RU`;T?MkkJ{-pX> z7%Ds>Y?7u{xm0fpbCK4mRPSCF*tqs}sf+gdq|w_@cU~y0;rS=T;ueUFW3_z>D(F zT$jZ6K&dpbyMn=)tQ)vm@F8PQJd^_1V3SMf!^`CPSnRlrJ{MVH2el~Cgs|IwuMFJC z5LTPOdAOrD?re>`Egq=62>M0$;d-nfb)zw+=dxHau#e+-yN+G4HDrp#)Gw~X2<+hJ zpJ*D4oG1c!nVn%OT~{SxiIpRg-@Y0`Tr*f$M(xvqWLsfSEuJz9R(eE|hT|x4X)oza zz;wX-tNlUfvYI88Le&ZOT9uyYaW0Un$L2+lGKyUc|Ec9oBiHrz9$1{6={fNeB)R9# zjfzB1#Lc9fG8HN!gnoWzW%;Yhj5#aq%*?&kZ_&hB7W6LzH(E%@eBEy|Sf1UT?Ej3iZ>@g&^K?upOP-qMJ{vy+*N>pZn@$%@63RA4otu z>Nw?WrLi4DbkuXnk9LA@YI0GkWbO|WfZ4Ljv6EwhJ>1NJz~&lANTbG+b`sMOn9-GJ zHJ$FUO^|8&0SrdY_$q@OUoeO zV~M#*XRxahs`3JVw^bwXB2eG6i*Q>H$pwQ`NZM%%J1=cZNg<~4(`5hZlFsIrI~O-Y zQUM;zap9s>hJEc)Xu<-}_+%`}W&_GPD-N0V67(cOXcox2#|y5UtfOR*{7i)(OYoFW zLlwPk5eRztQ}nYSUq5)%dIgc|@v1}bs|NI@BLJW+0VuOS;rpf9k;vR zS$=VO{zk?LPe#iV6dMs{jZoB0WvMu`ADHKx(3G?pFnibtpqDALYMC?4La2rfE2cjz zv#O-)=i{(}DVw(8L-^`L6PUsA4UF0D4}|f;A@vVe%hoX!sXa_D-0Fq-Ok5k8gJyOP zGT{xz-xXPN6{ zCQG$QV({b?`=pO1n8h?3 zM(sfH#Gli`63UE8&s5P2#cN5fvWrc{v(b(maU*QkrZA;ASS)G7D==+R&8{NW5&C}; zlSVBg?IJC|ou!-xI8CYCMyO|irkK?m8Q!@z19nUzF@AEYoqDukcphQkAa_`3@r{y3 zGonV-j%cBN;WYEy25Ew99)k=ENw&W7pGvz~I#mmuP12D(XkJ?Oy6v(8(O9&MNQe{` zM-^w#ByGXV_N=oFl24P7uCh`DuQgz*C=<41BFScg+%W4m?@8*}ndfde$IY-9NV^{K zYM|vKsdUD-%{$llp|ix#(ApHiDPN}xy@6q$WB46$1S3wtL2mv~j|Fo<^$b|Np=5C) z_2(a0umawQsVF9cOJTbEB}_dbV`5C*sTJ+1bgd~3P2_0W2Mk0->IX9@>>r+?1HMj$ z1bfhtp)lvg8fbHHu*Wtq$CJ<_w9sXV^wt-ymfHMhb7Dw~n->6+wA@^ysoQ21nA}7h z3(MKs{y%-lpYv0mzFpBUi#iEIz5qHQAV6Nsd~82cCknO%C)m)bgq#Rze9|`x#h5s5 z^kNG{_GP!d{KefTD!6dhG*Ny`h|X|GZ_R>uNGMH1LO6h7Af@ImHI!7l7_p%(Ef3hJ z$<_!HCa&o2s**57oI{2bCL;|_1xa&4x#f}rPL5V0hpi}HqZZyI%%PY_w0PKR5a9>1nL;}SVnJ4Hxs(Ph-lLX3 z|BQ?$_S*e)#a0_Ay1Bf2Io~RCPp(fh>`0>25At zWD{{mRO{R8*6;eWV|$mLR|PsPj4&sm<1Vslci)0>OIl~MrliThVHpN!DBACI7wi`4 zX7sp>OonK=%|3OuyS?~){X?*hA`SWKC{9yj>1oVeBXvZ?@t+H?@hgY4{;rK}tRq=ug`=kyfx=|+r6 z;v52^X?ekoN3&?W;K+RMvqhd&LZ?WMW>|)kw~|(k!w^aWkUD9zkIGuGN-UZ(EHcrt zL^G9rdnPlLzFvO0+9 z?8Jg2J>i-a$z}%0N1q+po-K*NM>nLDW;~*Fev&w;+{L?iPZAvl^+*VOIUx9fbIa7T zz@4RSE`#JwYDRUFgbkh_#XL7^N%eIkSbfBe)^O2MB)Bo7^C(I)LNOrG zE;{^aBO6=}W}SacIWQL4t`?LgsER#9)<_8h5?kvVPuqDqy258Nk7%DHuc(1wW}&9_ z&^)$=dt7QbM9<}yYYYTfoOQi^?TlO&y5kni#9^IkC0$rIWEj@DV6TMVla3pwK5MCB4!lfYPVY|z(H39u@OC|Izixkpr@oKM_!eXt!FupJSwE`kA= zRY4Ba)t2Bdc8s8P_^OsZu#T4nBBbOAcW!ua129j&iQ!-?Fe|Ja5n|K(>lm59dhJF< z!0_-?ElVK02EpM-9icwzQ;~s4pV*}4GN{|yQN5+;@DB9Dng4nV^)RM}qHIVbZLq`5 z>6eLPF;w3nC^865UigY@BYbl&SaZ*YSMl{ZCg43dz2CmV4B~>Y1meOpEft0v{1uBj z#CIi<4BXIO0``gHR0fQP^=|fbif+zeTD<>P0D6U^n=8w^S0j&nA9Yku((JfwnL z2o_ZYCBK9M3psb@iec-oA6Y5RFSr@+qg%ts|z!5V|16tEmm8eZTL zrlsnWcvFKO>7=4Y2@;WX&SNuIWc3Kj^))B&aD; zgYm#)r7a8M#ChWBSNO7D3$qDT)$D_nSy(!&O5c?lym}zxWWI3kN|kh}k)fWxO7t3t z7lFFBT0efzP!Q?F=`@9@_h|2Ph@*(#X{8&)#KX&)kZv_9lt;A+s2(>}%MD)V>z{FU za^$PeC1vH-9)*3XRB&Q^zZ^Q?e5YoLlc$_lgZ1qN|8=o;Dt98R&g1hXw-DDyD%MZy z0Pi%BKdw!6O``(7-kh+~)v(mnu=?+7fNG~hsq2pVS#RosU&#VEZRyz>6m2QAx(rf+ zOuifxAE>U1@jWO zYy~J8res!4%h-pB?l7IdEjmyu>m!VJ4RM((*HbYq_IFde+8Z6_1k0RvH94&H)4ahp zb_aQ0nx9kcx3g~?pYS!U^|!MH+OL|>)9uc4ZyeAFb*&S^;5M;tv%a){rW{;mceSgx zSg9~8TT&g4+n>!HOMmv_phv5&PcYwY09ZQ~Fyk`g-KKnLM`Mma8&$NAGK5n{Ud(z^ z4UTnQ&3Y#ogK1*j{tsL47@f)UMGMEaZF^$d&cwEDTNB&1F|qATY-?i86F=e2@Be;z z?^^d$ckgw2ch{-zUR|f^>@)30-~OlFW7;oG7fK!PG7YF=7$ZEKoE=>D22cvIiX!Mu{!*6F8=rRvZ)5X&2HV>X+1lMp6dYl5IZ(wMAngVOp zgsQizHO126u?TK8#i}G^Yuwe^V`#ja0khp>P=2#8>ivDAZFHOuxq72r=rK3oV=B-x zFeL_G`@IuSD^;dNE;;~1~4KfPt0<8|%hb#ANRs`jNW zkFCG$H*#A0_$o-$dWYX~X01&u^k{kh{@T_i`GDuJJ^zE}ea8l&Kh#HdS}b~dAFs(t`JZuL{BK)wt6GKz zd;gI6nF9}jqs*Yd*@O(f*RNQ#tAOqK#dG9@uYbUVpwEeVPtU(^S2?<$3a`UQLVlm2 zDou{NwVsz>*I(DiGuKbY_c!Oq!wH06vHR;v%wOlHLa?bnoA;oBmejyG)z7QfPswQ& z{)#Y*qshO;rnHXJYkthi9DgY zJr6t~*i{HWLHks#pG{k#m9?mqbXAIo@w>4Pn$BD_*V|zf|BhJEVP1ogL&x}G)pnJ} zJs>YNpx!Q&eNdf4G~={V7jMxah{h#+s3`9go5DI`A*ovizybf z%|eI`>vj}@`7le|*|Bumm5>kci+$oyhY}R`AAMRFU)pXjQ?NA_P`YpO7%oPn>2PIx!`18mCpY&y=>FrISX&1_oxF0iek-;l^mC@sA9`%;Kl*;kTk8^I%K1-PC-JNo|j=} zhgTpXm?1MQ4o)-WaeTBh6M1a;9qM`>6Sl6bn|u9V&71X8W&w>`b`8YDM4W5g4A+l1 zb3SixuQyL))nt5Av^E+{vwc4JV;wF=vA2;Nk_NfHrU)rC1cASsM%S(_{O`w$tjo7cr+D# zSD%NUYI{0*H^4sFoQNX+&PtDP>^dAHE5-}?otop_Pc^GVKq zOFN&DO^D2YvaGYyVN+DNU-z%vTYC)*zg#+=)eW`{uGyk2W@}yBy}5Jkt&DwJ|5SKi z{9)}E5G0;uZE5t^IhnF9cnw$=Ov7&1eB-`S-9z4}(E7HE9Tt52Nc4}!Y?GSSE1Nbu zn_%55@Z4&MY(ij0aLiixOWtefg*hW>xZ7M44x}=5XmW|uv=W0*$v%C((H!KSYIXOa zN!anWHb=#DH;%4`=)u)#b#L5m6TI@#RoNzrbv_=z*+aIC?cshN!`Wo+_7^y7(*3V1 zDON8Vx5Vm)?}na?px&UI*X!sVJnCr}4vaFnuV@bJ5+}qqqfrLuH{g!ehFei|mIdPu z9nwC7VjhrI&*)3o?OElE-3}(`4BK-~E5tU!vAP-^aFT+dJfCrpI|p136j zMdEFoUY>;wC4+kkZG!S^FF@(}A{s06M6}ao{TK}H_}JyCu;WWtTV= zQB`L*j+|y`+Qah@v>HP*3$eNre@*GcvGQi*RQ1eZb-(n7ft7cjX%A1qB%fHDzB-qp z0T!!&iH%+lrK~POcH5bY2uHelqdU+6uPucYgnAygXV6Se1M~Rr3gr?P-P8hK4E~Xt zam<1rhi)65n5jPGK^mrUXPR&#ON)sbdj-9!q|yFQFX~Tp2qp>Wi9_?h7YK2BLE9+= zg!w8}4cnM|R^s+f$Ij?1ytw1mUD1*UAr^yT&6Q>#8vDTnT3nwsqMj=YNR0>eXxJxQ zw!(Etzc!d`Hugmm+?ppb0K|;WHZ^Tew z&$ItdQIOuj3U(At9>p|tLGmD;d{D6EUiVnGhkt1!*VY=uVtT^=#&o&Yt(L9fXHEpf z_b#_@A`ULA84(LiEcU#yutnC~HI{N`LliK_E_Pw-N!27Ac%RFxU#2{5bN!}fKP2L) zv&#UieX$vayZxEs84F?N@qRV$tqh#`j3pG>j4#`nyXIUEc`C(i203S~#p} ze*(zJQt=kvWI6v1e~VexXJwM$$yA)i!gWCngWCKC5Z7V_p(skGy?vYn=#$)5dCYBm z^nTeDlACt+PFi_RMj;G_z-$kAws*$`Lx7aX`{oCyWvO*v_O5n0(k1Arls_&Xhh;w2 z)d!1t>4yNjDA;a^?By*OHecZpMmKkM9oy3KHaAlj_#^>zGR5pVPffUtmZAhCugQq8 zTjr?>Cz{7{5t5rE%vs6xR3$&f&!Y+hOc{3H*Uhhn@@fN)IV3+ibhfHI)|QZU`LW|x zF>Fd~+0eJV-+AyX0sP$!dj+BD>F`Px3mY`@&CqO*beX!8w6~A1Jgz_ULL!LC!vY{$ zpsxd33tHFQ$v;)peL)%;z^=vkPSrE$&C0g})S7pjEUZ&>!l9QV~AVc1elXKqJmgSi8!Ruf2bB4 zJ-w~U_+q8$8Kvr7Y06L|1!Ihtha^;RGG-L+*eJ+2-Vk2s)Svxu7Sg7DvnHPUJW<~0 zs=unUDY*&QZQ$zX@#(KlYg6-9g5x{y(|eW3F5?KqE;Wd9sWIe{6%eqT8v(TO80;;l zMAXQ)mS%pOpOL((FD3ff86+XJ2oV+#sc56U7#<&a4y#Y456lj$P=t)kB}@<#b~VNP z_6hHd?muI69*J%C!i}8vzB@c~VeR(&Ivl^=xgJh9x*UINXZQpzz53jz?}mM>@};Ne zRTeHek#5m_y;!mK|B^cR`w?S~wq(nMMch~V9{SGImhHS5bPwf(1kQv%P^L$y0J+*=RH-+r|8`KE_zutx7v z%HBfdCde4lB;^Ywwnt14{4WOCv`HCS0(ARPAkl0N2cD8}JeAllgD9Obl|el9bCx|( zCEKu{n~Ajhnk$b~OJs@V;}>WJdY3)JSAgv1U>?#Bow8|Qsy2vGZR|}p*&^eVXfjZp zGh0bxNt+YFa*H_t5w*`fE>b{iq zGTxplwup1^%T5<@e1#k4BW@1I(-=4C%*KErS{@#-M6O?;h ztc?nt>4k=sO-)!RcDC2n%}o6e&|!}N{X7JVf{+2Y-y0PqjiPo>=Y!dDxZu-YFM;+< zqv2^jOSIW?&gc{{3|qY&CMw7p>=}nQq9|IVoPC`b?bn?SOxm0|2~D+D_%&`gb7PGQ zrAIT5*TBn12j56XwujKW^u8&SIQ;jPw$z66l#bGIqptVGJ}k~pw>fq7Yc0Nnxo-{D zEcs|1-H1sEacU1J^{45jdxze)Cp%5YQIYp4mb6SDTU}gC^D|xidscc0ze58VEs>4( z6!{Zf`e9Le8Sl2d5@BU!>Cv3d*hP;6eu-Q0n!Bo98}VH-?X$t!kd#O#F9ZMSj2m8g znD&Bv4ffpY`1MC`G0&89>`KUm_zAMHC^-T!YGNCAH9X9s##+$5pdp=|mp9%rjlK?^ zOPO83D;|t~NPNU-2ghgCQ7~Ic7UG9(;ov;u$42B=l?mE$-=~8fe|qV?+v4wE2}P0z zD|B&YsfsNuB0(&W##6XtEVZZr5AM8#njrPZ&WL@nOj*W$RPUc8FWQFSAVRh_AQN+r zxFqY|bfLG@3ljVV!Hf!|KpxUi(K~rLs9*dUXed7rh3+p>!1H&bpgKvy)uC<(FCQxS zO2_Z5aWtu>u|reAyS^z34o&j@xAn=7YhEzB6XN&?4*K`p)QJp+&Zq1g&?KxIvM533urh=_eKV z&fEw5A46n+lNE>LE{=4h^gi`|q@eFG9DH$D6zBAP(3^?=_=3xV2?`9C7l!HXxD|34 zkg)803W`AjBBMH4zX+K;Q5J%iI?;`m$_b~Jt7<0|=E)jc!(OVvVF=T9{Q+%@xJri| z1L-oqMi3rXbg_ekCDBME&@FO9(ea=gl^BXptuj%DKp$;Gtd)~sQL)<+PPbtBt&vxV zwXmXIB+!Z~kAX*38|an=Zi6Vntyqg|1yX|=k1i7gS}Vz|_!k7KG5dh~cerq?b=Z+O zS|MkgQ|<)la{0FjBN##%$B=U|fpGk{Whyw9tZl@RI8PA4j8QfX4EuMlEZHbvVuU1z zT9bj(K$O9hN1X)OkbR>w7^P7J^60om*)4rKPBEy(ASizH1Q8B_&7j~taYn@h^9WQ! z;7pH7(+&Mck^V5D!oq@bLmLuq;@v8#6n_+`?Y~c#RkabwPtZ{HAy8w{0&J-88d9q58+vqCv^N+Aetmv)m<0HL++Wu;v?Dh- z5;YVU?g=Ilf4P738LS!x27bMfTz)*Bd@RlF%6wt^zee->kLD8z?Z8+^@AW!N{DhRW zxt59NHa|UJ&sVEJ`T86m{#KKl7Zxwbz>SMoF>P#}?*hZD7bI7%W$^GxsE}iNZG{?x zV~bp{!ai?TQ*_U*ffUnO8^RfpjC`-;cb=(iQC~+E9gyXK5Zo0K5VRxm*s$~OPYR7~ zaTE|(njph9tkAZ%FA`~$EwST9PI2~_WpzAJi$ga@Bx%4#Vw9Rd6MB8>@vS{}vqlj= zO2EB+qm(_{JuF;41O200`v`s4PL<)VSDVc7lL5O52L$-_RIu2^h=DLUri@cu@5mT; zzED8DR~_AF5#EHMnXVQ1W^59rb7bGN6FB3*Y1sec+`2%OWz}UEoW`;Kmd&SN@kDY8 zxp*v%S~-da*o{mtnx#{r=@jtslq+!CwpV|@x-_*T-D~f163nf4W4g4=#JuzaJt|~URdVZI*D61@s;;hRXVWt>wtBI|wqTwL-i7XJBHh!3X#(H>I!py-#Fixo=4p5D*X;kg`ez4Jp};Y)A+Y5KbHr z5V&vD)!Wt0+@8tA%y>sj-|>(e!~eG7*PWoui;WZvYcZoPU2u7}+eV*6{z%Y@AITPE zSAReQqWMH(4vsxh^+8eDETHpw{nUVu&~K|OsQKmUivBmRk#%ZKti< z85``sG}tK(wWug2$>5qHF5v~ZXUNIiO(a1X$y4FU5)$)%*?&znK{Y(=m;mPc2sc*A zPR019O((*oC-Y)U-K@SSLLw;QfyQcm4aREHNLOvT6yDVo+USalKIwqJ1ENRfNfL-* z^jO&3T2z7LnT0wUcAc!ttRk&eXkv^@ma&wRC2PtvwbWTfK0nDQj&+i>(9Mf=>ND`_ z4FhV+d}_-=3gDYtLhzVGGHAo|>MgU^SnQMSRF&@e#jLHe?>&d>;OCFAU^nLBHTZ-z z-$Ez-eyiB~(kW*qy9+1GK)A7p5RT57aBq?&ALGVI z-vPuG7y^^;Gl_np!;gh8OTj{Dkn=j65JniWP$g>>$~D9??-s!<1=mPUlgzaR`g*>4 z?bEF`gVZ&FIQ;_d)^B}YR3YO*#M6E;^${il`=B8p;5nSWs9Y3oH5=8K&TW{(!WzX4O9CT>Mm3R5<; z6>Zky8bpc~pHhXu;jpE+HeTYVf=6YtYlB#)e0~qg9b(1a7cf9m3qU4SwV~$mVOtTZ z$X1ilH1ZFZIK1TNxJu!M@}@Uo-l^&i#=!Mk4m#WqrV6H;Q-{-f5h40Es*hN3rrm?- z@3CAmjrRwF|5qX$5}2_lu?B34mu*iEfc``Gi8+<5&tRtQ!=Ow_H}19Nas0)NykzcB zRT>gHxKa8J0$T5CUV(*c)*T%NdKocqco zCtKeJuk}J9OWoFC+=4mhK4b^(UXJ3aohj z1GTxTXM|18YFW0Gt|n4#gEEy>qpC|yj{ce6WMTLDHbf4Bf_ei0Nhx)`vG>qvg&{*3 zCnTaKQ|$Q!1l~U0i+%QMygt0IS$v$|+g>`Jf7wZh;JnLWh>KiiJPyACw)S+F#2mwR>wh1M6=B{w&QlNcF!@17AHJUz%Ps&UY>V?*9D-_Om+JOQXm>4tvkQ zapbRgX8$=Ue#P~#uiXY>jk?negSG&@{!cG@CMLlKL!HCO_pb~?!-75r!?pJ5$jE-3 z0*!>4nLBs)wGh5%;5UQNyW!>dR%C-`&FWVri2opb3n?#>-#^F zfZ3b$hG~Y`kiF0T)i0ZmQ{=k$`-H%jlbAs}=T#qnAEt))7gKNNfc#mVdw|K0UO%pe z4?kD$fV6-K!Pvl=0*rUoY>1N0hOf)O4F4B7xSknt)PGST!OV&8BtS8L7zI4l#? zJ#t<1VY$p_XRu)aUaltgW9s3YGm+rNT=Tifd%JylU_-@AL105!mOOLC{jeA3{@Vl)NZ+)yQwIjfUc z6g3YTggI+ajLo6_ys!(U)7`fD{s>9{aOu;4pK|u2T0H4p6Jl`Y(W()rood*Q{R4If z!qF)Civ%HB$h-Y1-pWlD`U@2oybaSpp>YilvOiRwW~w`}REJ|%PUgF!tV5sf}& zzm}f)z33$UJHv3CYiJ_|O?$_bfkr-?WB>2=Uih499Gz`Sg zLACujVzNmub0zXlCdlBly-~}c%@B><=ZYO%wd~KnW-UcSg zHjMa4lsN|PJ{M-c48FtzD)_zkWF&DkMjE*=yX9bO9Oh_BRhjnn={x;#sf0Jyi*pRBcLbyr z)T{xzqJf~?XvxhdmJ#VOKcRj_b)9M+MQr`st-Xx(y#7M6SIOBs^#eTKR2}v*X z^s#asZE@amUkjSC5xJtHqWvS?7I#5U+vO^KT90MEEx{K&ZWuZ*kD>|RlIT#tt~((4 zP<~U-Dq6aHifG-lAwm+q`)P4D(Cdyp2+fm`TU1i9-KFkq-FS@~g%OP{H%(hJwb$mF z*2WVXn8oy&E>!h?(Epj14e$Q;&+Y9^$WqL@j}uqpF5e6LeC620!yHyhY^}i{n_N$X zrWBgktgiz$;J13A1U4N?LLZl9f+Ps_?ECp|p^jho$fG5`C-2U4O_tEY&$PaGWWdiK z;S#J+cT&e+Q#!w)Ij!uW6Ety%uQ2hT(p&%3wFZ;ACio1T^mQ13uV)(&-Pj&&P>s79 z=6icWKR<5Y)X?KZ@p!7eqFFwBP-k&d0Lks&4S1?wX{90V2AEt)D z_kbZDf5*2I@lLS;RXj%*tnwF){ARBrc>H&s=_++la)xX6sO3H} zf1VAN1`&U_8Xa+wOqs#pQ6fMFeMDgbLhc{V9`Wj>|1L2hzpQM*zI8K{QVz9OwLvlw zzZQU2=OSi<uS@(4eAHhB0B&xmyV0jnbfgJE#f;3Yk5=_!K4vGyfA?Rg6 z58oJvhJhc#L)Fa6eKFx_|4hUFr&R0T>y`Y_LWNcK?<8;T7+qfo_1l#?SF#nLCN^diUtUjZ{_p)YJ`?RXo^6JM(!6{en$@NGi+1V zZv6_0j)6ftAcrpPA+Cr3$!!S*TqR7Kb)aIsaS9`r@WOA~RD6w2c)@u@VcT(G` zfL2KaEe6I-`i?9_+-nlFDiG@lUo2!9Cb_4Qs&A4HIc^67(r0S|T(u~-Dzheq^krn(0k} z&8>-B^}y{~L6P0|jp?Ni+ct0S511Q`+l{_dhyCB5ID%)b5XzGK*wEJMUik&P8adyQ ziE+C}tM6)mQ`Jw}!kv))yfgq8!2tis-Br(q0s*5@odVgwCRmM4nAPzHV2oVT%tb)6 z4&py1zn^)!k8}rsJxc;EaekFNHKWEPyZF2n4z! z=ttleW~Ot=SSXIrySPJ|LsMUG=D^&YJ~QIAhM#h+qj7q(>piuPBV7uFxJm1HTwCF> zj~%dsUq0JvSOEdMW`?T?-gf*J?K!RMvNdqYuOmb|%Mhh#twic4PdE&iXEbt;BXmQ@ z?N`U{S>v(PoS88Vs}-;JuucGoMRF&B4lB@SL~h6X#~;300s(Y%>d;;ByE4utF~^6f znEKwoMG{k8Q%0nqWIj{3$D(+oiR?s7=&MAPY`1L@V?~OoHBb*pekbLg_1TCNqho^3 zqEK*RfjX%rE?eH9oGB-s!Ldk6LBaMShH*%n5i7tZORxWeMxvwN^MFHLN4VxDy<2@C z1Zim_BE9hhnXiOFouMUfvlxWOZ!c;~;qx-TBC~2*IV2_;9kZA9f?xqmVG(tnI-0Zi zwX8#;Bc~d{q&YBKr@f4*u@sKzgwh~uC9N!C6&AM^u|q=p#3p4P%0%-Mio@b@RDRRE2;)TBoHWtiXmi$1~%!;!s^Kdn;Oc>-E^Z=i;-%u$}a4N z;Fv1LRiSjzP2|N!#N_U2#Y9**saCm{g_~y6HBc8%p16k|)Pol$?*E3*DR}lohE=bs zN{>+Y-e7A2X$b0HLG(6TCYOaidT|PY@asxM7S8|VNS6s~_${{L; za4RQFK3l)+F62O2@OszjY(ZnK&P@1L{q;}VXYwY-7U5xzNiL8GX<($npz#8z_!~C3 zXbm-JJby5PaLj>;k;qNH^Y37GqvJ)>N4 zmd77;2vEG2fTMl>01qioc1sk<{o&0Go=t&#&K4%+$Cea%Mk;+lGf{#~xxhl``R8v^ ziivSXI0pIpw954}H?7Jp*3WD<8~Bx8Jq%U3W4yumh3@6Y0c4!G&U)t5$sU&-Ke}pG zxi{h`4gRw+Xm@6ryT&lG!t=9`Ts91Nb{wRz5?ICaaviyu#n4dy7cl+t$FsqxxI2_a zaXogBx4Q?_r&7;GJP=Xvj-`actUA8s zsf1~Amk@a+ zj7rp3DP{YR-CKWe@lFkZ%jG=uZsnCWGj`S;Hr~#4(ZJvM_Xy&iYrM@2G65bZxThLe z2#UzFhfY~v5*&<%%s;8PBp~MEhe26?6zuGP%&+n$&)D_K_JbsmcPyZ+)TmSG&V8`4 z`!5ePRSS6IryfFes+WN9O7Fw#TC1=3RX-xC{Rl+3PzJIs*K}*tb>O3= zsZo>=3t(o%?(VMUXKwQty#smooX;We zsJT+RCni;m~9?4nX|QhJ_!~z#y2=g9r08ieXa{jcD(ptg}>flxP44&Qk<2Vy`)V%?y$9S z{bLy|MvK>edfu_D29wt8b8b#@JMT=^3(pQ35%Ym>{56$jZUu59owZIlo>_J!(3*dpv zci`kVN^Q}$?mk)2qp~oGQM(fI#&|rN;_+h5SaQ0^J2~3YK$qaaD{sujTzOCugDfT1 zp1efm_PDrh+k;PfTaig&GvjW=#zr?PmUhU)2s?wN>+d*Z?d1ZyAPFpz)XWGV!|1?6st1_42Ug;$R~H5q#uD17s2*m&kUt8O{MIEvMa1Cq zmTEw7$i$h=C`gBV;DpSYEL=&%V$VWj&BQ@YqU1FkJj^oD1QL@{X@b1TQf9>P0n%wt zL8&x-S-&dE7t`w+Wi z9f7+J@c)94tMR8!0^x4q7nutZ&lvEBAym{WetT`2TJT3VpHlAu#nf3jR~?vC&!f`D z1lqMuiroM>y8WHv6Tydu9p-LZ!GzHJV&Y?T`7Nvv|CAW23$3# z?{dZ^9efs|<8Bad8$VTUS8&{dDke8+uU-y{t_&;^V>EdaVS1aIGCp}VN=k^Px_`eN z%q*$ybiY^nnz|VBPs$3WHH70n7#XXOu;%uAJ4fO!N|LtE8SIi3k7S zF32d*Xh&9Jo~`cpt-V$^Qeph}UqrCk05b*Ron0JP34Uis8E_s4YxFyyOB+(& zjvbVI;l|#uYreiwDbJjfOzXu6zu?;(AxTk%4H zTnO6qhJbLCBUJIZM)&VXlR6J|_!IMSY4(ErVjJMgX}^JiruTMzp6}#$d7U$)k2ojM z`X%8g&^?!Xm0-=6y~QICtxAF0r6ZE9`#TfxuZ*`~@kQD5Kp;lRm$}%T0u!J8mR%^i zaGI0jn--REYl*HTW&O%ikd^8m)+X|)8ujqs^WVc27K~t$*5EOOL?h!-+ovbxS>;#; z!pHjc8!=tj%bTjD6z^hjJv$We5f9=<7y-MZve!krGt`q6@wR|J)4K)UnZxx+t=4jF zKVcAsDJkYJ=(!a*}Ya2owJj3-5=M@+i#hLxL zpxRS|4MKRK3?x95Nx`E=@K{{jlL+&7CFWgO2FSZ%Xhh}zX(Z&IDO(OA6JZh+6Pg7< zr+^y5jZUF8fWWw8yn}I)pln18QIK^u?ggJoiy4^={f%*Tu}iF#g{3;4)*vwx)PGvN_O1j9n^5u3eZCV(yBY2ve#@SyYnQSEB^5g4&8E z891wiLWV*AdG2!Guxa*oLE-~vcOwbjiIr$>nGzrGw09s$g?Ov`IuF zc3HghDA38&)ng^n);WFi>4j=K&jH*GMrKU#IFh6BJC=YJ)avSewN2~)Yu<^ULrAQn zd@>@%M6*>?O$cYNkBRn0o$p;6kCUgdu?`XZ%pM(0 zJAnv_MX6mQ2@{`eQzxCLCD(L?R^=w0ayil4g%E$^q*XH9?hpfDFg0LAnh%{LSeu@6 zbpm*@Zr0xE3vo)1vj~l`%PkKmRmk{6MO3*BkB9rfjF4$FBYGyeg=d~qwDKq<$4tGTBly23L%GVu#Pdbo0}tdB(1-PG5a z)p2ni&~|k@GUf33x$Qso&a^GGkuv66G~4&#{PLvSHQ>yj(Th+R!I&kC_?j$2BXbU~ zbnC{ZviE}(NDHGd?8Q%>*+{Wr=^iT_Rdut}Y#q74;*4;0wBWEN_ONLutLxo%=$it% zrc?caNLRgP$K1XB_p_$v5~HePlYisg!M{LY@+o*@&iEI0)OkIt_A#a~T=ttUGIv*D zz0d+kB*wCeNlePH%c%o^J;4jhLgfD6v9W*m)M^6D<0h(v@vj>4JsPqN6(v2el)S0O z5>0DxHR!reIkjWI1E`J%^w>wK9H%5|oXaRVy`O|uL9&)$AA?kC6zFGBa%#kDjc*^P zj~_L@t_T3Qt?n!PwGz%_YBc)F5rlx#D}TV}A)$sqqJkf*vpUKbh>y4Sq_%asL!_5) zFx7QOH=zJ+ZFOe0;}4=K#<63hqbiE5L)wS4GY5*$93x&O67ZV03n)CaTWQwwsAL2| zD*eC~*fmlasDiY5q4ltfAPVv}Dpg z_*T+AqATunbR2%FfmriHtLB-k^B$>S_as+ic#XWWUIh$TFdqM}U9TB!H>@JVFs1 zb`|G->xfx%Ko@WmK+7->vE;GRGSJ18mgzL(=ReXsWJ{|2%KPJFsPAL&RK#4vKaf7& zTG8Z7a^y$x8xx!+`RlfWor7OAKVTK?2CkwJ)-CS-!CRto77!vrwDkq_1buqJ;rmOn zC#_@QxvYr;T6C-+hTh%~5JzIpu76Syk+W}76W}E`b&7_TUK!mM1#98=>Q9ZBhDC5k z{uLJ!)1c8S649U;+!X_VB%j|ZljoPTD*ZmADP|ZG&kUQoF=A{h0wHe1#0*-UCMrIe zbpZqK`(|e7*?FaElriiKia^(2L`zJomC;<;+%o2cG2wi=Q=`UV;!4zM_`;xU!++Xa zc;RV2_=Wo;KwU*65*l z)*A_S@Z~Ql72-pE2C2$PM9!OB;-Q2m2_1A46F;&nwBhMS@&lvSXlkrPd|YK^zIoQ^?8eFQ%guk|c8M0ErYP}dFNMfIA!lyhQN~bEaq8=C; zKKCW2nAHZkN@6f4J>o63yfL|DS(NpNgPj2;xRYq1V@Hipt}vCS^>U?)dBEkHWIz~Q+t`EC%SGLZ!j4Bnkc=YW?Yw;cyv&E``@*C%Kv`jBC?yA zb$0YCIma72V`_P}R#k#~ybG@a9Cib^uG$yI)LyBoC)mC5dw-Tvcwq{w_0k1P`MYrDV!h;n-1D8W4-b^BI(*@j5IfBw~*?77}puIvZgl_WB!T z*|vl@3d-XIgKr18_?yG&3=#cl2A94sLWq^-b-F3~#FFzJ;^cgL6rt+N%1pd6j!0o2 z^!*44cY2BCj)9pqoc*2-5Aa;ahBRS5iV$a>hY{X0H^}G7Z1>k$k$|%*#y+thfy$jz z$~okoT5l?_!8p^mJVWEFt+^3fJ@_7F9h$}10j)n?WJWDr14L6LcY-klo7jIwx%(M% zeb28q#DNg?>0yDG{|(UY+YNAl_}2&>uXEIXb@*)7lL~-0e8T8|Ed)annd&kfb@aIa zu2+!6Qk`cajddq&znP@E}UO0iYy??-9rU{u~@?5@!yQN^5)8 zzLe?QcY)LTNyY4yv|RR62W)*4aNgpNIqqKH#~G$SHH6Ha_}4!i>DmLe zu=_t;ZLpOL1-^uZnTo?@O1@H-ZR@+Gzuj{`enk)CA20FV1eZ^>&DeAbi0xXNOmU}E zA=)Yos5JXg#0b7RwV#Mjr4 zch!x(=L;ca0E?L$BAopj%n8S;t=E!;@C!bM^gh{Kf_G8^gsQy~S zfj5IN`0vi`3ob=2cN_y!YCT<_#Kz^s(J9P(yXnsWL{WmFVN?6#&ZQ-?79gGx`jFiz zwhT=BvQq^>d2mugkD}Mg>28m!^$}z|pm6flIySeDjG6+B1Qs{> zg?oFFI9dn3UwQ-Y4iD(~MHBAlX07 zyIyqjZGppqAD75Ne*S*ifj)XWtwi7JJzMh)eY{P(tk_}4;+prloK^$VaWNb%-rhGa zvkNMC&i=PrMKh9d&*jPZoxbBEV}Sx^C19s7?>$BMpt_f+qy5JCrO;E%ga08_S7><{ ztBGMRTDqtwZ83-Hzx5}JF{^fdKRWtm1F4g90+^Fe9bJ7mO7oEgB4!F|y6t?t^Yjfr z_{YX2S9`eZj<7<01|5XvV&h~(%gRm!0xmh&w`w<}+S-C>-|E@kdg9V{^b(+AoH^Y@ z8ksU#MVuPabz&{CH(nOgy4{UaNj($PRrW!MzjQN1aGRdBz&Qwa<(n4V1aa~cnqz8` z&?EcqCZVA>vPld?(Fvli)im*-Yx!LcI=Zy=_86v|Dv1~Cj)|c*qv?;s9PorQz(BBV zX&W48=N#(=4i|oBK*f<1p;*z57MRI_+|`|{wWfpM6#cVR4H&i@^U`V-3J5J1Gqt?Q z*dw5>&m_5u+WVGOBkylj3fmK==7kKfWxLnS$=TbKe{Zv&xc#;&VQJxr1J>>GEjFzI z70!1uo2Y>bs5BqI8E23NSW&isW^UnAE@J4!cdTsSj8;C{h$GQx)Jc1N&fXuI_(=x~ zjGk>O4~T=moTus8>>**Ig=H9l*&TI)V_K(e`E42vwCx8eF#@$4#O;GB1An$pxS!V` zjFq<2?_6|!(6-a_A==CSY*Rfg9DOs?H~#+^avwS^9WDu^JZq3qZ8t9e4{diHmc`Ns z4xcUw>5%S{E@?^OrllLCQ;_cNZt3psl$H_!>6Gs7_P2OS&+|O*_5QBweg8OT?wg&R z*`4{$EH3+*UC3vOqj8Oyk3)LV+En%dV{y30lAyGOAa|g0%UF>?YhMBy%hA4dA;oMnT($c^gb%CvB^> zsd+H4XAK|E>yI|-*S0Ma_U*0C2GiF$6l)(E52#&IC>+z~-E66vka#-!esDM37|7bD zT;9@H)vRz)w#>diK7G-!2?M5jJ)GMFoqystW^p^t)q=&gC;{B$);SO;#&b1zBi?P zKS3MIB+=rWPkOK7l*oixKHL!ZSlDjYAQ0y`JwfEMiWjbJq{11)v42#MgW7zk51Af>AW~c5e{>hT zdqmY$rTVh=+@`%-_W{}oPpTb^@8lY-)*S`ome&2@H6_M6t-JeGusV*Wap)|D4eI9) z%i->3dOLxA+=xbk93`SRA6F=ti$JMoDITJS3Sj{KL2b2msrkwIR7%$H2S)n^4=Oo)c zwyH1Ae&8RaCymN~bkW|B<=FNo{nE9`8uVFla~&}|p_qT$nG9+0EM0=?o`=P+zTN$_b}mG(7~rH4MNaaP^cWv%8@m6QtLrw6I+f2QB4Pc@+7 z%cBAX-%udZD@jAEsM5|v1BG~Z3@gwOfjYHOq~B4^pny8#g7aV3P$l@ZAvpo1+~GO_ zM-kG|qX3&~zdQi^-;nr`txA!-v>hb@0i^=;Q56B%!%)8{N;VPU#;zzzIuQZao(7JU zA;G8BSq37h5ZOeZHTR~c^tXH*3E6fu4I6g`G?ZG!+jAuSq$G@vO>dd!m@1=I`%%qk$sVSv{A+^Z19$p`|6 zKu!n=Yo3syw|CMSjA4HP`d2;&lLVGvyeLk6nugNX)lXf$GoT>VtSGXl5TTYPCZMl1 zcpz$nuIC%`4Yw&wUDOV$tZUWgu;1_-ZFaIUICyQirX@+e&ck4Vl8BqSXwRQXzLH3o zI`q@2$*cF;sD((B1eug|$+st$2Hn(#B*~WimCOR)I(W!kLJ@Wwv&~u z(ep1r^G%-hCmR&muqNnF*AQoTVP~js#L7G>9^$9DjqHX)y>)!0c)_(Xe8~> zZ=f2JgG9|XW&R0|`Am=~&#<`F)Bc}?NjPcX~X?8R@L{$tMm)VWMm9HgsjA))p1F~KNSyLD$ z^?qx4!->3F$hdn|prNf8LsH;g;8j1J*2?%F$0MD%%e1TT+{l8yw;TvstOS-_g_cT1 z?7wm+S1Bd}$9%e@pas-21RV3f$KrG$=%7adXaraJ1(BK2s65~>7=Ri!#`BsjniUh} z6McSZ3Hiji;9qk9ZITEa15oQP$1qp&$L>!X|E!z?sJsyLI;pA(qlEz)PF2;6N^8(S z6a_fW7sNaTNM9#E^Ob^}4W+B&lI;f+^0#+@P9)&*_RgD=oMK4W1x6nqP)6TV88%fI z>%&99!1v8_5z{KR)C1b{DHsWYfDpLz0s4I^ueEdu_G!rez0=FEt?A^xh` zDxs@6PG#y&mj;NmpEKV7+V5cEXUNzQ0}*}r?6MnZwbN=BqNjQ30_bPL-};#*hoKIn zK?`&g8ZZt0ndkxEeh!wk|5sDrl&9A9lTDO-N~9Ad ze}))Gg8nox#Giq1?TgZ$Cd{8(|5v7i|EmINUVuK{&-4NHhptj~!BFJI=G_7vmjQI# z*^Yuc(C8!oYV=!R2F1Q;9Rbc7m;}Kh9Ca%HY|LQzS+fOD^MCYF91ur90e>Yx%>8?cXjajp1*QW9Adde` z41sU|(UHGwf6B(8MGH(`zg$Fs1Nv+K|EFTafc6Oj+6NegWWf3L&(qwC-PeD*SfiJKf?Cf7Z5jo>p zXi4e2h!cxc*-d=&+GW8&Rqx7#&HUx(nov)vK+aeTwlv`yhL%RW@FJ0GN~S3}38Z;q zs4F~W`D|#g_L*d8uSQhlw&-PVUkmaM(bHaH$^H*7b!3)4BNT^7y2&po3K#fT*(1pG z(k8%0966ZfS6(PD zCzf*0^M&HpF?()g%|QHuf?VI?FLemCCxtA9%cvn#kGCS_T=7HqR`z{GjG0I}GVodGlR@6Ft=g{g~kJVUL z_c3s`IeYsZM;SG3@xp52tZK65fCjcg+bO00#2fZ`GHWe?%fXb1$oRNbS;*JWb@@?3 za#@tYxkn`qfy^dz?H4KNiuTRpLgBC5n;``5oEPce+i zZ$68dI6S!y^>QLLAsEQE> z{+GTo;CXQTk-ekJOQx%|ndMOfD80&)C1D(V^)GTr^^0nk$Xmi{h!Z;TFCe-JLfl`D zDdQkB2vFn8Kg4csy#kGGTA-{vVRp|r`Psq!yDIH=R}pw+`1Xi=#@m*0 zo093TRs6gZJT!M}WaD0Af{7mZ#qe>rIZ1QE3o-UBiEx%R4YMZS5MlSHC1#%3b?%|H zfjjxAel&ZJi<%O_2ge+-Z!He`Y<#%h==o8v4PE>w3L(&$yK44d*L9ndLx3UNa^!uS zE!1=$&$ghbvW!i3Ml#;ZNa$A6*)%ad3TJJnxgIUk8SvGdY)*H;31KFUoi}x(3P`%FGy=$p0R?K2DwI@$&5p4+gZ*^0T`g`=vaA5!cfGu2l|| zk@7EJ?1@~Y)0x9{qK$<<>>>Epu$9%O4Dk#v(H)uO7sVHSdbheTK4k82cka~wcs{aY zdy0gESc0JQn6Pq@8tI9b(Xe?`5PRP?LBK>bQhk>3wPuIn{GA99%(G1h*$f;dyTOev z#C33+XrXA>0@x5pB&OX@a0k@LY!iidUEV@Oy(dDiBUYUdxf7bKjP0QYOC#V3a=%j3 zXWQF8SP{>Eou0M$RQWD= z&N!MIydy%i)WRzTPyfb{Es}4v$5_6G20Y4^iY*#8xfPL9!*OB>Q+nH*GBVj{t#Yi~ z1OkPvQ_Wzf58cFI`8p?fA52%Zc16Ui7T0S4h)e3URXgz+o@Xy)w9u>zaFaW*rB!rp zRz=8`A_VY=-ClToRhtP?g1B+G2Zs}vVpv9MTC^!-SHcMwALumyvS8BBZsa0~IlQgE z{JK$ZNzg=$)_ZwjQRa9o!UZ=TEia`s;zux4`EU;Ijkp`5O3q41DHj zjZwIlXjnPZjMi7-^RejmeHBpeOoJl3ttL50KujLp5O*_kILlATwy5A5c9MSZj&%HG zT_4U7@FR{te#D)8!`1dNyo4tlrDjpBCHzZu|460Lif4B`&UZ$h#WH>mOKPsXnvxrQ zhjgbaD_-+FmBiScmXwcCecM-z@zhzlFSoH1f6(bj&Ee+msH%}_y9!7Md_)vgX>=0U zIIw4YTVVo%EjyrNA!aebH2Jxte+s9;S zSbwDV#f==(^nI6Q8bLv+^Iw)n&t``2_|ZZ)KfSeeisib1Y=pf!b)PkNEbGCZf*H!a zJM>lY$dAM-pKhp6>XEs2;%%P4a>tvExuBU4(j%E-t@xQ|pZ#{rI!M541NyJ9R?zeFjwOHL`qirUH`vqHekio{4cuAB6UWn2 z7sOPp3sl=!$K%H;*RN7EhZR(%{I(2CzgCxf#r|0S9o9B#5gOXZ4?m-*__Fn`iVYfx z?}w`V5RPQ*xTwq4$ahgY?5H+4}OX{kX;UMMS+F{y>;pP2KaV)^oU zQ<*dJdY4>#YR8(TG8(w`WkjFih-yjpJ&#W23+Jtr3@eN8?7Hib$A|@6w8!gnlsx)mmuzfJ;M{VoA`Q)<7wnG~+ z1&aeGo5R_$xs!tkOa!yOh6`qGh-Zs{x&>~|&tQ>lECrYW_%`^GJr0dKKmlzb0;S!U znqonZIuAckaqi@49O2BLyyqpg=J9CZt5sJ@m*OELn%y}fJ))hM7Nwex=+h>J0Ow!Q zCjEA_NnuX>ig$TFB14#44sXqz(>+*cQK8451kc7=oWReN_pL@?2V;G-2_r_KSFxx$_7!m-}rh{Hu9lU zG__q-`(pS#`SbNi*Mx|(_-%fQed8jCnNOZldeLFt_wqOG)yn(cNb2*QYnY#5UHt>R z4PSmRx76)l$RVt3Vl1BqtItmiybFTH1-R@B4v_WXr}TMud+6@>_?YVvk{Q)<8DG*F z+~GgA(Ys?!uYKEk&#!g64pwM=-9O1xeSR@`4Br_*(ACHM14ct`DOcU=?X91zS;nYd z|H3<3aXvTh%?0^uY8RM~d<6VyFxC|gnl_qr_XM{G0|@=+x7@IF4=j$Z;M>a^CfZFc zy~>fxJ6uMPxGdHEAC?QBI9PTy zs)UL>dC+TH+Ikr4%*j26C!7(>V07x)N$*2RFHX#bMNxJONx0SL=)aqwshytuK9un3 z1V(r<$2oh?Hv-@#YbbG%fNpbpOTt#gJM`o|fgw`Qq^-o6fY%>A0&T&&k1ndz@t-GsNEaxzqg!-zC+nDc65dyjXW~j>!pJgaq1WHM&*}L^vnm3 z>QghiX}>XFJ7D@2-`NoABb+RP}=fztpa~qyZ>%$Wflg1FtzP1@&CJy z4L#s8yE3sRYgc)&skw!6{%*u5dsQ*Jxp6_(sL^J8r_k)(cl+)-a~e$$*INfaS82uB z!$rgLFnx)zW-=!Y1WjEsXAHi9b-$b0Gjwx(LE)6)35Dxt8s{nK+PyoE=E%CiL zvJ8oSxM+WBb>iCVD6@y2KE131uk5a$Rni64K*58W@t!|ieW4~SbO;?7SWR1KkOBpg zM<_^XVy60hH@|PbqDPU`UA)AMk~Kw#adk!R?-q#MNlDp`In3h!`8S#>xP(1 zsPurQC)P%2r6nu9Z`Vl}nLPkq+C0!wC~7qJD}@b*s*ad5e&?=EjZ8m0MT0pj=EYBN z#7lNG=n^3w)g1_hQFYwAb3MWGPRyQfw=$12bzJanc^;q=(zgU>pw&i|C4f(c&S)oY zAUjghxBu=?n8?CpvE|VzOuDs$psEgB<fey_RgV2t-ahj5d~A)tWT0ApOP4>_@%@HFO5M_V~Kb*xnwD+ zrpJ)Bc4A8E%ZJKNGmJXjoe`>zUi3GS9T&^l&;g7IfNL)0cMK+p6Jk}@3#Le<%J6x{xHK`H;#T!yRGD7Zo<*z*ca2Bvmsn4Cw zZ;`>&H6ov1@qn2q`UN5TqiWPF`bMuEUZq!&y0ykZ9^cvM9~kaY*1GVU1;J&mzL#C_>Mf^DTY)QR^A5& znNDi;O=aSw@RCGJ;N@EVwQ4ecrLSaW-KQ}hE(jg!sqNkCLJ}x*atxmo3%j^K9PX#d ze;lq?sVdBP1>kU}3DN&?xROfFL`~<;(+H)W`B-h`*p*IU_=L|(Jk4Lbw7bQ6RCj|@ zyuOITCWZrtDvZs9D@;t@cqSLWUQmyTF;OmA6?`rM4MqJbL-ZGiE7t(y4-F&gVE!Ay zy>+Q;S+6UIpcxJsUh_Hn7bKDZdiwN!$^_|t1ww$k($)53{<5Gg6crja();v8$Jv_m$TIC%-;d#ev>|np zc*L|ed@h5x{f8u@1QXFx4S{~1c7k03MuMY?G04?{tduCmg0br)?g7U^)|98u`Jf~S zpqYmt4cnzMz zJbmHMk)cwaA}gw7Wcs7~FdKI9Hs_E+f-pf2ij6=k#UVi78>ZX)JzFQuqM~_`n#=o2 zbi>R@1E=%l9_45_RZ<2#ueOEw+sr&haHpu%y|ItPz$)A^*8W>V<9!#ta$tOYT3w$*+*?bra}MsnXrlMPl5JdyjpG-uRbQFBr>4Al4x2K~Y87+(=TwHL|! zxR^u(*6@v{w~LdD%VQ(`XFvR?uA0V`pio3wfj6ruSzqH^zhNmE(e8esu3&Q=gNw9K z&MzaZ*=Bdu+ImQlC8Y(BF3r`SNEesz6?O$jwfHjlE*C4WpctLls)$hnmJ^iv+qan7 zZu-SpsCztKmdxIm+tV50-#|Q4Di^>YqrD=x z4l*IzeEZPkrrJX1>l-;2VokXj&tlltK$;Patxk3ZtYnplGCObkpw7;2DeX(n*iL)E z{Q{=fGIuJAs(jq)(#};yulki%*cit}Q-7NtiN|nv=VA>y2&e7@qvDfR>T_nW-a-k) zi7BQjePRfe7w>d0@=V-jxpDO`{BL*pZgB#N%0*VWlV@(e`qPivoni^1UZK7}?@^|D zrp06cjGlqwiky#F0lAJ20O|2~Aa>^|##Lp?gtV(+ZS6 zYVrjQJgXoqL~h=!6RB%55279GQGDoRD;}+=RJ1;d6s)Imf9@~8wuDT4x_)N0DG%5j3GH2@&9+_Ahrx?q+OYiZxvpR0TQS{1DN{Q=NuY)u~9hFn-(7 zZ}w4={?o@0xu(d(DdfWodf**sg2r3rNF}ijCEx>Sxm5XjukMH}-TEsZ4It^OfwfN9 z=w~Hsx`j5xJ=wxT=>@o$!%Mb&Lv!xQ`8$v`JWO=mqccS7{lhWex$AoczNdrLW7F*w zCDJ8XI*1pX8W#^-=tzkEJV^f%vnO{Qdv ziSPeC{f(sq|C9bYtUOgz^D2r&?EJMD3n|!{2qhgS4~tYVVgDORj1J!Dfz7ONr`&x{ zK}n47Qa!@`kFn*~Nx`sUD3IHN{EM$zOb^x@O!_!fWl`X0t6(G|Yjg007RQmL>%I=tky`Qp zbn7djxGtnaY7>l*`vN-NaF;D}cRSQ=@ofQQ(y3S`8n&sTez!Nkhq-C)mLZHuG*3xC zD~T#kc;P^}zoU8>fGU;yLOZP|AIz>==jGTDa&cpP8w;=cK4b#9ausH2cel>((Eza| z_4OovLVLq)cwebr={M|zYop>;KLnN1s$z0KuJE~YIrUD~2AxA)+uV`3kgup1em=&@ zS>NWr-1;IF_H(dGwq8tHUe-e>rYJcyxTp^95GHtQ&rE4pv+l){A%$D8QYo8U?cGt$ zjKIPWClD>Nz5>TrM=dlK%myv<`yo>?jJdn3ZESxkJFK=vO(ejalk6!7p=dy3Mv5TG zDC2PM=lf*Tfb!K@#_PDU1tI~i_shWj4{IGx6tB}USiCs`IZtlr@CAY>Nll>^cdw64 zLxHfb%vK>04^RsQQXmr8pf62@u0^pI0XUI&R4Q_tmoh#rO1{-WIlfRnS zDuCUR8bD_LRv?fFBN{*@Q|ej_Fz;Cxc3!H$x@jTxMNN|wCbD|mQCmpj2# zPX=3kYxo7|bu2u7bq~g~wom+9X#w#%E#$C{$Ikee07PD--+zDG@@3_@kiuIoV5I;Q zV6nvU9Ju@ao!Qy8gOD_pTFibILbeVEVXuvREbS9aG48SL5sKHrNKU+eI%Fzpe|^V~ z2fQa$A5HlAL?;6{Gk&-@Yi-!HI2`_%vGmR2v77FKZ>q+ifN>id7Khee@dT~G>1G{9 z$?gU1BM*ck-Rm5Fe<4Aa_haL2*kj_sF=vy!*u2pTv&4FL`e%p-3UQ6f^N`un%#%|Q zZ>&SI3u2=B^G)WbFxqsCD`w|~Ur7s8Z{urKz5ZD57^tzGX*D&RLzPR}hTu#AG_`Z`MBz-SGKqg5echHCwnu%>WSThNUqgZF~PDTd~`Zsph)MB+eFA4NNtI^zg4!WvLCN%>W$?f z8%-rj=!%@n>#V;*0)E|)yQ226bZpTJx>2gyZ%VSWnoYx< z3nT*3g<=B$#H?j6t`}F#A;#Xhi+`S<%anUrcVzh)Nj@C0VzQ5$wl%oNOEN@wSZ)WC z`M(QhnRGCdZF=^H9US$}_cQOfPO#>ttd~Y3YB@v0>hwE{H1wejOd_!y-DMBQ6truJ z=NAkeJzIl5V${iF!1C8Bg}%@cTA^d)KJMgTDQQ=}0cj`9U(cOn^&ZH$t*>4Z6whUu zB+&+1`28uE`#N(u*m2%j6F{nA75p#g?rX88JEu! zCU{Gb9^cJ)z;om-EJWXX)6G(wPqnQ!pc08+Fm#(BBqe0;^-GrmLdcAk7u~ zKkIfPZZtxx24Sb#EL-qbO*!T_L%p3;Ru2r3u?YRWD9n{yg65sw;P7aUw%fD5hcwX<&0-g8eT07u|fx?Qj&xYD#2UL|AK} zZN;gx;U^24H-j)wa8xhAb}AdMX>OK@4k;N91szUZ&Bj^~B|YE=I8oFe(#9%jgXd;8 zwO@JVM1t+evUQM%d&xcV=F|81|K`n=6J7t}&5K9B^5$DFn8s{^NINUeP73=tm_j?s zQ6dW=Q5Ns?Mv;pXQ+PW041ve=w!zI>0!7z`7<89-dEJr^TamJ6#90EeKY+ z$2oJr{}5SSHspdfe{+k#|Fkt{wUJDsulMbCFiOi9vsLMCSjgWHnV^75vTsM?8}k?a zSFgAOYHDR7BF5k5zO$*GDjKtK@v%#-{#LcEPLvcu)>J?q9W!C-t@hf(Rml*Jwme6=pJH6f9cJ~%xzWktqRA-T&&OVm3F&P%EljR zTE!y~b!5i6AO9@f$HG+G6mC?PCLY3S8Tf?y8lQ!z6Y7TYD^;SxK*9dd4fB4LP4d@3 zvZ3o#Mp<}tS)SB0J%{aJZXK(s;f;G+;EnfRWo4#sYzNpA&xUSH05mNX-a^i9`&q8`-ML4eI#1!Xb+8PdB0Z<4>Au=a?d7fx0deSp0U?%WI<&xM+gdshDm=c zbd^{5-whFZ$B~sqX{SsvuW7m^wE-4 zOza|*v#4iUg&-?W{Kfhdv&c7%wi&X#X)*pR9YEC%a7a@Kd2<#w9sl*`yVsRjB=z}x z1EXAD%WL6MR7}7)K8+S~6j(mTTNMdwzzhj@Jxix0v5+iAVw73XDDDt14G=u-VxQu$4+Q~SoD&+zh|n0x){Cbyb%khY3m9P$EQw~nW?AT zg$fsk##|R8ejp1nhl=YC3KG&Q%}95>9|tl=MUes)1#ygrx3}Xt&qA7kZY{v8w`)1z z5lzGgaHY(27v@Suv|<$lC1!Av<}#?6!-pB!BIY<}ea=FWr@q3saheg|w~uVUkvoEV zqS5a}#BC=ICAzo4-n)%OC*4xrMIe(0WMfOsI>l{s730mZajR~O_K*i2@^D8HhG;Vx zuE}Sw75bQrZ|f?FpvRJ$1xExH6l_Hf&41TQxHwtGB)~JocI%)0=CX=5(g!=8@EvS} z`fYAv#q7|T)}!Z01}`yzp+jwIUo+oC7xE6*+Z^y1>L#YnDac8iO)*H?4BT~hF2eE? zO`U7I7vSmwk4l5du2i%0nU^}knyCb>a(XQsJJru+?7?Ilk0ST5<(9))7SH}ZP z7#y~b=}GSoK5r`dLuf$Xj?vt9!yDM6ksW$wX%`}Rz6*Z_)71$Ij*E3h}K2Ufpvx8W1H5*rnnc|D<4_okxoC=>) zpG3Li9#J0NZL`kHjiuw!SKs-M`#*dF_D<)*QpS(`{n0F9!zYK0W+W3xdu-kd7? z8s@8k(;0_v8e@}V&^tdZ^7S!9DbIL-DWR7ZRp(N%^c-5T!yCzSWr5YL2=3@i{yP`p{sq&8pxX==929p%tqBll=#sA@Tf1 zp&%H;#i|fY;4Oy)Z&rBJtGFe%_FY4i?tsGfxot5^iuYzpRV@!&Loq?$B|D9uA(Veo z0?2l6F?`1wMoHqN`K20izB8FH1;~@jpZ-J?AnlS^vu!b`tpzc?-`Y+u`BkofyyFaN z;(OZc3~Gufzh&&6Gad+0by5Aa6llpI+iU>d5zC+kcFYFCB3`3Yvo#)Fj-m+7i`_VI zFPBk9_bSk;j+h!S)2uG^NO*jYptc$+1^f<6U!7sdpthRC&#cnRuE&bEJU(e>5T|y0 zlFmcB%v-@R`*R&QBl~u>Hn&SKhvSdAr(E5WFk(w>Mph8TzOs~Z`}6H+Ymc z3x0G*9&0x?#>B}W&OiDQf!3+Q*$p7xbO;xse$Bm5=}FomGv1+(B+T^c+*NpJX-wIi zqA?^@_X#iCKk*N^Q?~oRp1@j84DOZUT6h~A?Ck+Zt4HqE-zXkzPJV5CN#yy)fPaiw z9Ziz&028U}0ZtX}%>9K^dnuCt9o`cM&(N! z&CU2*^*H`hx^R1@Yc=l!$1So>{G_n3Eh!;ayY%~84b-A#IRAJ8xTTCf)#m3)`X=FG ztinvKyo>E!VYFM|?cmx@s~c!GMEBY93F%JrPELRRmF>)IPF@YHkc=H)S9zhYf^l~K z_Hc4CeIO%t{LboSU@dBCq|TX2q7z5W>DK+!e}Uh6G`@VLr`7e{c%e?K?Vp7{3E`MG z4e>u-w7Nx)e>o`csu8*nk8SK%%M#K5<8N$CY($El9PsqB@HmS4k1O`e{8iUt(-=3y z(AFW7k9GMPKAe4w5)(ZU(9ZcseWxlhdWN}MUtL@Rw4n=OdxfY#jgH5i2ijwVILKDh z=p}^3O7v0olWu{5AKmnsn_HnhzWmUXg54VT1fJwnN!*a$AOLQ+_vXFKJYgK~{eG%B zMD)0)<9WTZw>ES;zP4L_aeRJVbaDS}=*75bjs%lc9CW*P&121%Oefa)t!eG)d*0#K zk=UU-8!g-xHwiT;YdW0=?O~Lig_nDm2kRM72r35`z$)G--LP#hs@Jj#7H+c$>!S>B zltmCW%Ho#TaFu7=>qie7tURyc|B9cOGqy6cQ))Do*rNgkn|Wf?dGt; zq29pa?>F|&Qp(KryT@+V7B(MFb~iAGNUA>Kt{F*Do_%^{zFhGRDH_Z5ele|v9| zf+z2tnq#-Q;l5WbEqqC6&QZ{vBEgaT6}J1##=(Z&c6C(6>~@(r<#`Xt#HYKNA@(!) z9;y~sxfRwlXDAE4{)b1s%(CvVMX+WJFu;~MyMOTT_;7$48POJG0tN3c2%>o;FY)Ye zpp=;`_GA(wQIb{Y4vcZesS;4|H4=J9bQn8<59{&~Y(IDcpUM%}_WO$>KzmOJqH;qk zn6t*Jr=(2GN#)jCRv-CK;I9ePqJ~S9Ej^4?PfJMed;+w$gtR=dyTr>^Fhy!#rX_~^ z++rq#Sc`C<$@{z+&Osc@owAQj#_eUM84mMF9PL?>NcG!Xa7z-4l7p)So>WH9nhbot z=QlMzmEnS>J_s_Q;mpb_^-DNKQ+Gl019W#*-WNa0dfW|iwypfxzjZfUS*l($kr1G} zK_!uwX0v;K`J*v_?jDUp66b{nboa|)5fg&aJc8I!ZdK43weTHf?N^(4Hb8d^?Y-YK z0d)5$Hzh&Y^iuF>L{1JaJkp+tIAv|lwuzWfH}{0TWw;=2 z^f@o>9v)hgd+5WW;J9I6%nK?E3}6ZNPgchcx&$6)PDn)zEb)zgs}~-(E&D=L$Y|%@ zq=BV1=exGdEnRI4VOt$k3|-CF_`|&yH%T}WRLg$Dk!o?S=gysK>t#ph_r54msYfr+ zKk>4TV)x&jfryAt)FzTnNo>%G74&SuOf~$m(1H*#tch8(1K)t{q>3h}!ID46CDj%b zWb~dT5@`tP_{JBS%;ITNor{76cy3z1uhHKGB(sy2I6GTwUXLlXCuwhJI$T(BG&agz ziS^G@&enG--(_t^5LQvd=%cvV>HDJ0YAPzE!{!ATd{wumbTO2!N1X)Z_S95<7LB=M z%Q3I5@nStYERtH_Vg0i6{@3P)?g^q(E@}3Sd*{05nk~0X364zphl|$142vju(Io$2 zs+q8&F9Yx#FO{-J&%}!3G&0GQXl$wyY{@w%(-t3TWUlLox#I9C9&>}sRV)q39okBQ z7({AZ?*SkEwvsM^}jKF!rLL`3?$bAv?ya<>C2+DMBNDVeVd15F2MdFb`itDy14Qjh%|S ze`xHTA>JoDK14`Qv57#GkVo(EF2PnqraCVDTWnrW94bsgv5_PlJ?4JD0&EKBvQbf7 zWS(w@Z+;azP?~PO$av-~I;eBdgD`=6#>@jH0qp}?lIm{M*>m6|ywIQbWKbp)2RvSN zDy#rf8pt_TAw`b~m^BgrOIHKQPcZinmM)f2UP5^im+xa3u%FW3@_kl_W7w#7%b*8d zC8-3fbQB0EM;fm9q|hhr_yolP5d5Dq?HEvZ6y|Apt<{ujlEZTY3IHPnxSKyf4S%Y+ zUrpx$3p&Y@=Y6uiqySU{v@j_k(0(%JUlib^-uazg(N8}(`vfUNfck@^6GNVaS&eW_ zoWz7zD=MhT5Gf|Fr&nE4HbMVe9;tew?U!A)ThzZ$ZCu>fe!~gcY%&u}tjG`I46(|n zleGwNnU?EjCAkl~D*R=ntK+n!e%)OV1D-WrKQwR{c`&GjRhD zV?Ur;xv@aZzlmO!9ffxq8UWb61G;1fvmW5f9^L@XO$L-UphSPN?tD;PY6?m#AfNg7ZJr(CrTvg3B{`o4z)vLp-vl@ygYyV7 z*Zcm3u95#_-9Tdm{)RN;0Cer2*Zeop4$Er>y6oSw`WF@53;i`f2r_4D+eY4t=|nO&yE5moeOZB^I)^DEZ>)N z90G`&4)C}WrJw{BQCUEHAI`ud(oZT^J5(t~0*zh;2S zz#=vb3e0!`lpb|fdnGj zK?hi60BE(uNx*^wk<$lA;KC1q~-rF3Y=9PT<_xt>et5L zMCG8SNu&Qsw1Lu}Sohxw`yYfp$q6hQP`Ks(-Npdx{ykQJg*JXQ-%kYs`XA`A zf9d}x5dLRvzasL#Px`0+?*;pd;L9ZZL9)wg0EkZxDpG4veFD|Rz&rDdY5et&)MDx5 z+4PIR|8>p5OR_66NPH^{3y9(6pVtbGpFsa<;vfjk`@Qcz+7&H6g~9*F_*=gSxX}H| zx`AOK{I8H^Unu!4%jqxj`=2HOO!HqX{7=>mTonJf%>HGXi`sS-gnu#LK+VAVCISD^ zM|nWo4;Fy_N`ROHRz3J_;e>BMNi;wl1Bdcg0>truEaUL&b|5!!ZouRPERyo;0sXcA zpQZh`V%UMJ@vp2KVDCNuIv_D%p8Yk;uk!ovdG=;k;cV=jw%_9ugMPz!7Lvs3azliq zqRogY%(_fcR(>4ZH+gSjwnnt)BCqu9F;$T9aaQ3M^4{SDg?f~KIg2m%6Zd}gEgn)2 z#@0~vgW-t5n-@*hM@+&CBFzdCG^mQ@`{YJY{qZL<grlBvwnS-aeV1g>y?0?-Fx2wPr69g zmNnP#k11bQhFQ@uVW#`a(1Mi$Wj}XdLztY+G7MS!Qhg*kBiQ56A_Lf9jMGsJ6bhjk zIXF`yGmNSjuxp>o4VRXRrp9j6O({MfmRps&6P;FrfRj&~Iz6R%ozl4o_X||^YF~~6 z3gOo2ywbw;TAg}Yk1PiX{mJUoaf_ zp`7PK64RpI*ptalLdTRnamL(wX=(OB$LEfli`Y6+*&u!R5AHpv`i^_ku>BYAP1^^)vDoi?iXbpwFC|9I8+5nq>8)H~>l+t_|&<7kMP>@MVebi6&KeR_E*3-63u zAv)UO_#6YVJ@%%%?8HL~?1w--8udvjzz2aEGcHjn{<91=6;m_StFTUUjXt zv5(a+EG;KKs<|aS$Zbsy_Sf;`lMyS{v03Ee`%|^@2cA}0X4o|H8G2cN#h)$uaty6s zBS-Ru6d8H%^l2XzE%!M5FBXO*b76DVJ>oXucJcU%s_gj11!2#$Fm?%$p^3A3p`pK5dzAQ>~sf2&+a#l28DvyEu&cXE0X-T8Ks z$HB}js7p%ok-2f+UcZq@!rK=kTrRW-DPIc!4V@6&1djdA{%&oy30EYT9={2^(JyZ< zBR!ace(dWmG!ckW8eu46wTRrAe&uFkQ86FJtqg43XllFM@^deqpr9lYM29T1xJ2a? zq?*~Ao0*|Lo+DS3y|TprQ7jT*c5huu0ckBuk@R{%w_uJtAM*4zl0bvcA&VJ_&K_wq zbkHvRT=5(9aMJRPG6bA~E{;4Xc;nLY;X$X~Kr+R6m!fXOeQiQXhvU(T6PmR+GwA3K zS*k>>fL|=sBPP+{J~Y0-r*u!mn5bI)f-=sEbD!`$!+m) zaHo#&aK1&Goe5_5vE4^y4|6CIxb~U~Q|I$@8>G$nDVb*ZDHlHUe|X`Hv47-^m?)d7 z``TtFw`Iw$RTCo1vNXXoIf12AMFni`Ts6vG=24Nvh@*vL(bA5< zz|r&CtsC@N;E!ojemS^!U*qtI4PIs0)>FeAbIhj)Q1z!97+m)-=gUK`3(0EqkbLz% zMW;R-oC9!+A!~5r4}Pk{DQXH>l19?1s;S!DDiXNxalWY5wJ*Me=GG+AICZ#X2TAxR zn>{vgFa#;XkQKBJhigxV13uW=`StC*{d6QnA(C2;oj*(vEl_ExjH2{s>;(v8&QbeM z%xUU=uaRAmBchI?^#43p9fE|qjWUscLv8x-Z5mR-3lE!LNrUmj$1AWtfx=~wi4Lm7 z3Z%pnTeE^R8frgnHff^=+A8?>lTUqjXQK!ro*d7#-#QqxwLajdiT2q`cQJK|B>Rfa zFAUHrp>{C==9OT>t>EQ`FrkkH3@80?0cpKok?wX{`zw@$%}E9HLj68WAVCO1l@9Nd zt}Zd66bh_RrC|ocD(Bjj$w&4LkTE4U1rUEQk~)q0K0u(dI2 zsPac{q7?69H_s}HnDoOdYB~R17ivEL9S2k(350uZE)IlSZ*ExrS@?D}LEx+bXCI9` z1d)=sGvdI$M$Xx8mRT`szG=SbtdE`X{ST;8(hjp|;3VX~PBaumU4CpEyMRw`B?%yQ zzWl|>)qV7dFyZpQ)lkX)78X47;lj%6u9BTWGC0fOa$zH0p4KY|VIioB$+T;C`LiCY zY7Leo(J_mAtzRb25e~vvfe|j6>IFA!A%P=X&Pc+9#CIq%NbzdlJG3|+ z-`K680^05>joj5T!r`&}X6|(`66(SuUTWF!*a4PMF0?MOQUz2$Wo5=`AN|7xCl<0T zHo$iXw`r|X;;7JUwe5y7O6`Hp;lXbnLKMkuE-7rs;6?EBm-z84x#NLYHL!KC0~m_{ zR5yLWo=KPtyBrD{J5qEpyZDCgg%1%WwSKf4t++d^SyrOom9%@m|8(|biQe9h=<%0k zO}(p5e+-VZp(EDkOz|oodSKH`+i=ac{f_-*l+4gIgZYhL6>r?>fH812VNbGCnIhZNYy2j#aPcsL0eV*aEE6 z^{#@C4Fix=is}dv@kw)KfM$;mgwVGP6_@_qm*->&C6BxtmSHPg%C>njeZ*U-4?CpS z1ybdY_u>?dV@eXCEwHO1oXQ_!$LAMc#(7Vq@IST z#q4-7t+Dyo+*CPy%ZFgiQu_t3)reoGIIo1eF z5t`qHtj@=+9yYh?KpBEUD73Ag4cGGta9_i_-xV9pOe;7D!-Q-cOfxfE5oZ+gH!>=Y zXIJ~~s2sfb8uJ+B@H7qsF$|~02XBRf1b)NL5{h$^3b&2huzsVV6c8u%Aq+3wCzm@g zVdDE4O*39P38M0+L<=KPtE|Mx)4Q9bc+%hL$%X1H*cilP3HD0pW@%>!rA7=XDuS2v zZ^-FED=!Qxxh=HmdO&7`(c%{8kF>3jCKVpg;wpb=0N=qxtSu4*U_~-c^$5UgW_3z9 zp(%%4~emt03+nHr=tSxn95*NG4zNq3DKIAs*4T-DyZwgBVehQzsdL z&1*_VC#+9StQD8r^GZN9f$Vn{=#q)|Anfgx(Y>I{o8e&cxf1=O!8|+qTb3T1rr4(SGQ#20 z^$;L}sO$ynAwv)D739c!b54)nsb5nFHk#2WS@~NTuh;zTS|uLD6w^+RJN?hX)a>l( zbjH4RF%|Yrdhyh^7a5R$WA1^xXhkCS!|c;kD8n%ue~KIEzQZ-lc2_`aTEV#AXd$u{&hYukz7B{u|1V`(XA zg@%QiQ@YwZzEj{N^%-@Em*95d%qX{HWz{ybo->?TrrQk7GE7qxzllwX=hbUU`e z*!qP>d9s0EG~QeE*N;m^t*BbQxYHbGs$bSm{6F7X_$R#4D>NtyWJ*3w0h-A(AFo98 z&={sntA!2g9x8;_y^GU@rXaOz=Xg>4Q4XJSsIw?5ri$o=e#rO=*fsFFL+!agJ-8J+ zA{rfi#gv~X3KmXc^x}COIt*1oT*q?5)N*7gx^nvFIN6E)C24=dOxUYq0(6Mdo{Mn+JG(ncn-spHfGY)K@COA6G~W$7u#^ec+yrFSzsX!$S1*P z$@bPvLaG;L|44V^W$X)C{&ArgYkTIT@MBtGI7G_NeU0EKp3q{p_TiQV`dmtN9y@q8pD3lM z(zu1;Mju(eY`^Yn(d^OPcI_6Ep}U;+>!PCHNsi*gdEZ;ZyuMe3C)XMwXd0mt%UHB$ z>Ez)p>GMbeLeV@70{!3i3}KPYIj_#1t)Z;*3#4>?CJ^`Othn049Q%4?5%Caqsj!R5Qhv=vvN5V|L|W3v0c z+z!&!;yE5ZWIZjyrn(zWB95C{GoskCzl>&oY0Vx%Ns{KTiR7zZ-kfp>(mXDl!+U~0 z_tt3|N)?UT`t!!K;vg99zB>a7v1Qx90`pj9?L<7YZe!Xuq9*RVb+kf(>!2ni{#Hwx zWIz9~?qB5u${@gF-BjLNc=r8M(a(JFI?qAp?7rzpixa`UAx7v^UyBfty<@W3_{b8+ zowUHe!`ym5lm?yLsr!nrgI9rBPDjpgzx9wb;suJ?V(<`qhiQ3+bh;uqyK1K=$xVHl za~rT>UMd9;hpCW;sM$o5$W@FY!eIc9Uj^$Vw@aL!UpS;QJO*;S;El`Ge9w_YwX`kK zZFc$CJ{7=z)EA!8z9z5$DDc$|Pfl+lg1YaJ4VvIMRof3j%gsrbHaGZOzn447*#26W zC<#3uG-sGjS%4uHvsr2lx5Z^WzM2dzJ7XzxM{St!=~{49bOp)K*--VcP(s4R6Z4UqfzubtpakKX(+SB7kYk4X@;W(3_i0KS7&ujUhQEB43KY!>> zUmqpkalFtSpvjlnH$Hm2m7TPyECkQLvJ;RQJDpgs$wD>1wl8st_GdLVID4RJ%>NZ=%#YiTpAhM<&s}|84|S?1NH0l;5cYb z#$+Teh`K{lVQ8Q?W3|?+(}jFwcfqDi&$jh0>8_)-b9r*_z>NE|qW`aY+teFL8-)8c zeRHcmy?w+53v9pjE4!O;V>b?)rWBH#CPPpAn zx|jAq2)rPzGXpUWo)X{>Qp<>S zg|U9J{<)Y*F1j+TA!`Z;-f>CjlJ#Kv?lZ$;-t^Ry^RpdcPL|JPzJgc5vBT?2)T;ug z2HYsJ+7@_!2hIzryPwG&DMg8~wV^mTHM2ZGCP7l+kQY`#Ntv|VYE2W{+f-wXpu`>4 z;5}_go9~%_01+*Z)RW-U4yf%J%+GN@pei2=vwYYEE|(m!Z>9`3?MhN1Zon;d3*g+!gicvyw)F zJ+C>MTXx8g5RY-{65s|nX~ummu@X3m&gLlY2I~g(=|@Y!>?$cY<|RfbxkzTW`G^VZ zD&u$0*OL^w7%n34O!Uy&1|jNCqPts&zNPI+T*qwWo0ehKb9N#2zUJ)ot3FuaonCE5 zw^^_kSW|2#`WKq

    cb(4Jl_Ou3GO(cdBGy*<1FqEo8}uO}GDuTYyy3+V*@YSafx zNp^$V#lc1I8)H9AiD(kd#qhdfq zfiy?l*qIo z@5RZP$%-t|!4evpAb6@QgqV|q?sFnPO}Lfv;B^T_A;%)%Ct5KxRakFbX-_1Px>z#s z%82GV)K_?lRkGZv?A5|_^uT6>3&+)qV?bN^y&>?1$>Mjo0)3Z(g<~4`XP&-X-cv0j zppU2sp9NdH<%t-#dVqGcy4{Gj_2`F~^KAtTqJCrwz4Noj`MNGl`q4d^=AaOTR=>a; z%*6ilkpIi3M|Z~5io^x^ZIon}OR7pQfk1claf#`xUNW7&ypp+ zPT;jn-zSlfn>=N(k6ap`ri3Tbd~W-vAQxnRc9oWMH3gMdJA$|i;s4;vYkloa8Sva|QXYg-!2@4DFFrN0kUEmg$S)gWOF`qT^tx@wih5#K-^&KGR-zH2z9} zd@rl=NXh0|4VC@(P&YPG^OqeLC1$!mq;7pfxllL|)djpEFm|9%!;Use(pb`Q2neGv z$0QNafaV}rr%IDx+z_6Sq2s+~u{}a9>QAc_SItG;c>$|8eoa7m;S@iUen! zsV8Yo{~z_4jo{d;0nMX446FbJKD!#1$q|cSFZ{)fPJLLB zqd~QfDmRSRhc**5DezQ*-{9CsZQUP7@lQ_T3GhIC$wI%ysJ?LWv-#EqVCV*kN~H=W zlixbRuwiPe$zd$kroVbcQ*+r##UoNPjQ`g3ojvJLh)XKK#|x)Ca|kan^Yo7?6|s&W!vK_vpsUhc<>co9$Ppu? z1+w~4cpB$F3BN4RiYuLrjdu{Zx7Dvf-trJw`;6wW3j#;?HDD_eKRMy)X&mKQ(HYup zgTlouS00%vHDYxJ0&#`&W>KCi;fl(qgL`E5F|lO0(dot)twl7|QJz3;N@>R91VNF) zgR0jEu<$!J<;7>g2+<`w=s=OmundL%R#5%vthhA#JN#p<3l=uEZeWV57i@JT=&ynz zULdq%0w0)GNkGeq4Rb+h^?;nG3Rd`mV@*`Q?P9&wF+!9-yZa}DQ28kxb96CE_^L-W zy?*w&2li#cConO(=D2w!aCM%aFo-gd;tu+xecQ9!_$=P{olC_3pg5Wq3Px| z@P&C+tE2M(oqfzzH#mM*>hTgC&TH_}4Ycyo7;sx`=zErx$uyGG>yu;OuAXpc%v=Bh zuQPs!z@;q-?-@ZP+@T4_AEPnw==uqrjKsSL^Vb+Xv#dR5t?IFd{3JRtHua~{rRxKi zcaf$kvM=uS(CYd==B?K~a(LhOwb~pdAYD=Ab?va0GWh+nz~i7NBB=(?yy{zZj+|L3 z&-|cSDQnuUQaSihe}mlcR^7o6-cA}cbi}metp{_$>D%|yG98&@o_2l|uY5l?Uyvqi z@@_$B!3sv@%`~Q~WV1GHDkqWCtVCH62R0N`My%VS0aIxKTT{=BaEJo7JC}H+*!Y5*$#`3-Cyt!_K5mx_ zfj>J+{NBlltb!){_)CX@9nLA1=O3@vqwLMar%C!TI5SQZLZcSa@4wX$nE%3yrC80o zsjB>eAVyL7lND%nvOxT>77e?sKUn+f5YszI`9ONt^v znwGDe7FV=<%V@_YF{*uHO{<5*iHe3iR%i&aWL0ay(d);}A(FIXuGi^8*ZC)C^RW#g zhXTm08GNp%0SKW00~MI1LnuvO3OYGx44Xy8!6+=-uO#VN^z2yr^daE+`{=9Q&fWQc zfJ@eJH&|NuetDw{$rV~zl>dJE*GuZ-m!uzti zWocd!jt%UcaU99RQj#uX2KOnTzp42f_LghmZ@CL>@NKZj$hwNXCQWhrW%Kc;I7$-7N(^wSuZ8t1l5IKM{Kfs_ zC7HfldBWJ$DnWj?u3YU4#(e`2hf^R6 zl{1$whT3@*-$^A96Azq6x@(-Y_2Lj0PSp7(x)VkNRHHYlDMI9$ROy7IlhIy2_p7bvz4sc%_Q<2V1Rdv36 z{oVEDc{<3BJ<77z{;5(;N!4Y0F1Dugnv>P%SR7V}M@{&z?-ZSP;wNjXkusv+uDjwW z&qUJ;pRNNd+;+TBDL-qVkB#AdvANZD0v{qP{`thB%_6>!IDNmdi>5TsZ*RD;FHlzE zO`|b2H)1mjY_+7*ixa`3L!EkE%~bFIqp~<%^g5b})M6+r~OnB=+ zVb${VO5g(hpb?94n8rXL`U!z!(Sc86#HH5UodtW|g;AaSI&o|5o)YGhyW^;Qm}dPK z*`X0zFB(*-ykO;=*-C(wE>PFwY^sJ8=i*PT2K0)YJ#U29=jRWZB7IvtqWIa1|q6v$c;kPTiAK96)5mDO4hunynwd&93cO*sg zJ*9g-g)|o7^FmVr+fAov+d^tkpTDVV9Dn)&(cTaF*-@7{*O7wYb%ObfX{S$IYpsLxORrm=|x|1cVKYW|&sx zj>k?Ci0g~+{RNbu*d&eLlJ^70IwaMV(Un*%2x-juWH*6sgo5gPvAL8)1FajD(j!-& z5`f<`uEnNrsR_TNMrPQH_r4{^KFvQ5x)GkdWNS(-z^8|f<4mJIvG9d?N()Hyh0)*T zkq`|)-~Wt_eIn4$B_Lu~`5716w~|Lh6y<3zz|4nz8Jk~ddR-W%KG)D=Q@~cK^_{_> zCm?JTcJ?}Ai4M8cG@b!y;J6~<$ zEbCHi)Qt0LEY6k3^oGfKGhY|s4QfTtZrftfZElF2Nl!dcexLPMI0N}^O(Mt<&-u!2 zvE>!r!N()T(vK;oc)bv?2f1a}JKd0Oz-GL!xARJtKFf>06=Ikj){EHuKxXc8djnO) zc@@`BZys!WWdyYFxWX$N9fnFm6Rx4v^An-fHWTXCd~z{sr}6m^CTum0=W6}O+D`VuM;e2Q&8k=)Z!ZNVgY^XgEf7xL1#+y>ikw8+2( z_3Xw4P9X=CB`ZC6-8sJG(nxgr!XKQ?qcj}MOXWE=;tBQM9WX{kt}&Sv;?|kr1>x;s ziv?CKQCQc6wa%@`2VhI2=PHc^b4q9Udf|l&Oj?7k?ZYd4$&d!Y&Eh{U==p1GuU<-W zOKh`$+0Y_orP+dU@hy!yq|{@o;f(9e;i&myD#@2;y z)A0sLVN9iv82Pazq&=aT`Nfi5*fDpF;u=|w&x~q~$bc}MEtr1cPTWYlBTlXUoMC|THSa6l!lIOwu;c$PhTXdzT=pZ$I>6Lo1^WlJvRc zMt|jA65@fdi>*C^+KuHdkcv@N<1@&F(-|tGy+B1WOj0V|`z|k_TJ_Is`i9Bn2$b0s zy5P0iXJiI%ylA2oYvwN#U-m~q67Sf@KggaE4;|sPY6UKiy^khEIe=70Or9IMK z2@HYA$F3q0e%uYFX|KloU1otl1&Q|80yoZ(qRt0{M2Hx{OTM+5vq6;FmhEL2T@N1i zSG1XFRa%X$Bu3wrE#AT?EyWT3O+3TbRAwVB+J{mh{?wH&@b0*oW#>Nmjnva){&sI! zgHE%aCR~v|gdB5u?{(b?6*371;@$cH4I!$uOFp>JJYTg>M`sk6AE1z=#D_>SRVnrR zyO=i*u9}xJzVz9eTs?~O3#8lhb$4!FHK*M@eHZ_{NKL$Z_1Ky7$dAmezeJzI!*G5s zXfuY(a2-hmjg9@ZovV3-JrwS+$vk)nz|h}Lutm9TPA;JW(EGn8J=!)?RWnC#DYr6} zqKyB^frakO73B2Sy4E?wpRugKjcVJ$aTl)T{t;zGpZaxappkAgV0xFv5L<~phnQC~ zrR$6*SAanag-s~yTKVln0c&gS(0FPXOcE@&$B+sv^jA;bS*arexWH>wn0i3g1Bq+> z1jo3sVL3DYeZdM9j6Cq#0r+doBIQ`OKSr|2=7w3?M(YGVbCa!pHm6Eg@@MzIewuV6 zpk*p8QW!;YD|MkyW{du@sL*9~``M`r{@rq;8f=^04uGI*b)i?r&VOX4fGn!o5UbsO z*=Q{%D{zvAUD{2aFeEkowANbqwNgDepHQi5u0CQiX~TZ&phe+I50^JdTYjh|36{uF z^%3mnTy^WM;U6sq0D_*=OU>j7t3Hm3_GfQlaQi|j@F>F=W%lL3-na5t6D{Cpr+JS3 z7tMBaV|E5kXGGmO96aEmh3*mJX*wf4MTYT{9!c$r&mtoNn9yk|G+3VHIE0xSqx?Fe zo{;(Y#|$%XK)*3j6Kea`LDw?N49h`xSwLQqP<-*X9yZ@kwl;=0KiVGcp%!Cy zyW=`&wFKj#pty%kRpejJJrP?9T9><%fBe|DdhWnHZgPru1r2VIs=L0PuS022Zz+ta zc5i9u?yU$=Ft0X?!v_W5+j|JVENB|vShyzW4RnJtQ|#IECXA|3{p-4#zM<_vG>2=o@m$XD-XP~oQBxl&<95Nm;F^Wr}wArXwmf;k}*YZ?5I3-9->9tP#rP^@b$ zqb$`kLJxH}?IT=Tx=$pva%W4srORKX2iZ9_1z?-heGJCCb6**5gASv#rQNDIC- zj&~*yRtvTt*Ea(E^9@#ZS&abjIv(Blem5YxU-tcsDQaHu`;7so97%sw?`Tq z>+pu6KkBQBO@qeMd49DZsn>6T7ttf#S=!#qg{gZae7ylH{tlkw=j(MZtHya$9JK~_BFkN& zJ4FjfeAg7`nWZ^O(^!_VCwhomiKm6SX&#d z`li%ir{KyMU=PPr&X!(8o(={b`Y0~=E)P6IE3sjp7Tbu|ILt1cEt)*tmtxksRZlCo zBI;o6sgduBOHq*BJ_Krrp%E^+X7C{M#2xjswi9e^#;ALir{AKCjqy%I5{M8%f}yyw zI$l1%cIu<}yRA!xkXxC2NKXHgXZ3*cbU0XH@PHB;FSC#||2r+w8*|sI7-k@(pG$zM zg7?#rIfN61nrm0bc>K$ZOwF@`3=(F+FA*C}6SXR}B)ybx^Y`NSMe&)YudvJ##%klr z{>f*WYDuNcrDv*YNtiO9)ogQv=NX2yWhcuXX)2&C)Y!QSOQmdx?LSbrfU@Q%Xr^SX zEijuyhA)*00f6~nfG3D5OeEsRU+a&}f6z^Gr}4+0)Ro1etl$_6shYnfPk+=Ci^_#A zko*}m{n12hZz)<0J@alF#X?H;dzu1S zoLDb(y>kY=%!p|lP^yQLSk}KNN9JdgGw_-!^SwcAIK<3Vvjc zI|oGRS#vyZxKgAT&R>_>P2&?UOi{UC*ODW`cNnoB*P63$%v4%+F0$!n4}9TMUC4h8 zjrm+-Rq3J7+h{HDn9Oi(CtP53HJ0a9ZpouE#J)^!)#DMm1gdQO0OR6j$d<2)q7)Zjt^1X6N9bRSuYX(@N-ZOq- ze#@!5B*t7-7a|2D%TiQj0HdrfP3CKPy z%uPD5f6t&L3P*1eB#hasf)Hs|uX7+hO3>!C_$^)r2LIB>j~TjD!T+X=F=U4Dgmk78%yj_T*#(VMY||O6 zLQfMJ^P3YuJKMSJLl%4B>81WrCGD5&3JA~v*JqBmMhhzO!^1Xz+i!^#(s|^5DX%A! zWjUKeq<<`dKD32SOn7#8{N8SNWwQ+GNoA%oGEMRlHX478XP1WTh?Aj1@zDTaXFh{u zll$?C0MjWwA^>)diA6i8h6G^e0swY?Xs;&$HPx<$1&38b0$&OL>}YkWI-8-a49_hd{;nAG%AMDj*+Nsl=a7dfb@@Od! zs8RFFUG}N{!Q@Ai&v79M0{V7>g!o$)QPNoQ*R)>4>5JjmpxV`@=Eqd{Be#kGr8M|a z;GmKQ!CmyOwVVnFu|mt6*Kq=F&K#><;p@|-7S5GG@EOvP0tYce`1R=M5*EWT!yD5^ z%mk*CZpvpK21!7|nm({XClYAxy;X%Y_z&*1PV8){AK#T-;pB-l)8Lif)rYlo0c0|{ zWWPG+{U&HPkcLR9Jah;MvmFmlKH**OI-~?ZHp%$W`sdzdP%CukiUEylpnD47@K5)V zfViw4ATEo^kkSqJ#>3za3@MQl@7-Op944$p;84H>?cibakA!vGu$qG|q&e*y3(j0p z$v3wO)TI)_PQDnAc>rj|@+K`tR8uJXg>HkjgVzinHB=#(CR6pnRS%kHdeb#Ueb(=l zK1T~})*6fKUxy4WG{AV(KD_-YEp$}}}b zn1w7?yt-Z64UK)x70wQ^f;r~nwarp6I)F-J?aV2+N?OiwaYr3#Fj+?3X(1_Cv{ zeqOaDa_q;ui1qPTtMx;AlJJtF`)LiO-tbc6DLwOwFzH1adH2W$%=ckR4Xf<~%FCq2 zv_2?`Dwl+X@|wU5z~?Y&7R;5cdUoB>s=Av!%^iLva9=lc0WiV+91~Zwv{!a$rxm7^w$}N?wn*+$Rxl>c} zKRx;ozGqh@;3k8vdc!=P8*NrrLIY+8AfhazGnOw;G^+MK1kG}Qt%YZJ4}@FA$??0k zxdwwfjN#ZJFb|UN($MIsY)5M04H_|k<3J*C@)=f2mB}xRx>ex+6Q%z(2S6_VZxf(J ze864u`I7IGqdJiWfFd{rgL^!ad214VNsHb5|A6w)fuPSoCW=D&PBQ46ovFa)BZwI3MIhG|;C2bh=5 zm7Dr`<#`mqn4G;;IB>q4vF8Us|e{2D-l8)8f|9x_$3{Ob^x5XS_ z!Dd*gR4yO*KhZrY2f6}of4>MsO9_b954Q@wf6J+gU^iNIT6_@G0TUoj%n*Fr>@2##aG` z{ZCQ@_g2l17|{Z~iMG9Hs@J zDB=Gf)kD;@0w^9*kS72m?gLavAlJN8o^jtR4kwTiF#k420Qqzu)v1&Pt^t`#1+)ni zoJ?R8N&h(tl-Ymx=e@aq-2xP+%>UDke>(iXH2S{M0qJ#MrHg`+8!-Pnyjkz*{huEE zw=n?9H#Q{yh{XZyTR)U6l4(P2TtNvsL8vegp zMwk4nAV@EiF#W$Vf<0C%Rci(&$q!yptZs=i zc}XB9|8*#p2lkiy-=DLwmH&1fum-YT;@<-MUL^kO{(rUhe`}@%NOCS9sHMPe7eJ3$ z3TZa~S;6jA-T%!*Da{5bT=xH7xOzbIQVALUk;?cAW+04fS3uZ%A=)$o5k1XX<>sTl$poh>(?XFF%N)cU3?b6}Z z78Ja9Xkbu6GSwn!QO!!LIVV4GsB0m!nU|!~V$>xoz{%E|$dsPlJA5fxN-H_t%y;7_ z?80xYt^3MdcOyyE7PdF8_WqFPBt~Al<|urXcz^|t> zfnoC^b&V>D8!JkDd4QpIm_tuMz1ItIe)s*6h(lX=3Gnpd)$sD9mZ0q`Iqu@nQm_YX zR55H&KR#bY72Suvm>@$;67cWLt;XP_Od;Y#6kgjRuy9wXHMlY8I5ET#Uc|+;Yol-h;ymTN{X8bz1oAL80*+X9bDH7t8+g15;I--*kl> zH>*4@r5%z%79GgUlF-@usoW<@1A)gJ0~M^!Wpb{Q*^$&Kd{`7@x@e~>xPo+!Z!Z! zjWpyH(WmchX(^Cy(3G4hTW&9;sc_lL3nx+q_~*)Z{+X^g%%wr_M(fVBu1ob*ClYvK zLR#+PKtqA1kuUSH+nDQug%4>7Hn?BRZ7#U*qVNqRVsE*T`7=x?}Slf zUy;&>+}cIgVDA8Q3?vPki>2Qh{*8t^t-yFkDGLBVf9gyBs9`6xf74qty+bxm>`q}@ z0(ueVdAv4@68w`_It(H~`cV`y%`(V^{E)b_?H}#%_2{y0X?!Ki3+4;Yl=eBB)4`Cr ziW6@>T!9ApxA0F=0X`Vy6tZyS-Z5v6|WY_FBS(De`@ z?j2bWYCjptvLhls5||%-XJQgxVez;Okc3dpoF&^#I7A3rp>83eCqUfOzH&o%Axaq* zjCYV%ts>dD)88YGqc%yta9FEx_8V@9`!WZzzSWieEkCavRIFoXoM_g}tH{K6uTS@Q z7nbv_gulJV!h3th-gsVChl4IFz($=_etEA@p1sp1hOY!WOV?BCiEo1P5V-<}hXo6Q zwx0Ej7M@Tik_=}Vn=OYRu2zCQ-aiE*8Hud;Cgo9Qr_%j4co1zRkA~P*&^bdL%C=Fb zUT~#VY;j8iqGCW5Tct_(QDz+iL)nMeRxU_*PKF8^f}%;8of1z*{$s`&vvvj3Kt9#P zgK(_GOulTPN^-iY20hcr>x^>AQnz-UBm)_uk*YT#8sV9raA)sG&;eZ~A_ld$VC|ZP zM}J|TbQSG4vIR_uUnmU}E(h1H6yM8^NU4~ox3BvN#}md1+Y$*Qa2C#G!sjV=p_W`U zRBd$(7(QQ)>J0}*cC5Bnhgca1?m;9ZL}N|2jG4DY3=gs0$7bIzdhV@tI@7LjnLFGD zubJ6ug0tBP;jrzWUogdx5Tcb(=6#GN)Om7ebm$Nze=hSeeG5yw=v{r%~V_b zeqETaWG>ggt6`48DyHXA#+Q$e1{)C86K8F~#h|^_uGbp0e6Kp$Rcd)kg7ZU53edV{ z(BEp8ZM8eog_m0@QtO;^d<}w5-Ux!-YwBbwOLmkC?0(z8vx2$06#cu2-_=P1?(-KH z!TfyDmM8ch1iSsalhn_45i<(Y%N@kjhR^#PrPizIFGMfA;2Rw~py+#7{I%a-(YtY^ zmg}tT27bz#3Ay`ibegL_3uQIfP$~p;LdOtURlFUV$ETSjMHn%E)QWDRs zNeiPXtte>_GF{vL(iv5Dy70QYLy`q8iG&NE$|l>_e(gwWGYgTg|ugm5Kt6~$JYY*I-B!5Dc?q8~ZoN1EbNm7SR3Y*CPhf)PO?B_5h0G$~WDK>wgLMFdVb{&iAn0-q=k zgOY?0@Rqx8yu9(Z_iCd5mpo?EQ&w5ft^@~Rw3L(dK$UimF)jYO+t<2_Fax>1Q-gAB z19!YVtdY0b$OxMnniHAu3fH^2E-Mc}yoRkJkHc$oOb6?H&B6M!WZ0+a+x-6>0}=g6fT*ZDM&%CsC26D2U`E4al|j^@nF};HJTQZE!vfyKiljs6#t1RWKG*FZA>~e1op5;77bR zn5D~4QpZ00X90q8H}sj$kGsCRFM9WtDtqm0dI@a?#a<+n_i>AxP!SY|;4<^wxNvz! z$@uy-9eUT%d~Lz%^e++>YhJT73*LKV5!be`Q$yg)zPFB5V}dM+m$kR|2TyVX$P#&A zkK=|8D{H~MQmF&kS#cxIfqi9rqrW37o9h?Kte*Qcx^&%=jOoIAiVm~w1WyICa*Wp% ztGm^_W@E}MgrYA@_JSGwP>=0lL{uSs>7fxMBXs#?=W01Ak}tb|+uVQuHQb4;wz#}w zG3dEr+upk&$A-M97kKZxtE3NCHY+ih-w-0%zZ8v{r%G0f=&&T5> zW%|85QSG5`)0cu8tPwsAdhp_&ZQYXVjnDHE;f|Wz2GOH zD1@XJo;noceh;1X+Q*sJ21v0OX<_}QQ}|{hQ5Rr-ZPCn(&yJqkH=9% z!Yo?*m`ug^23J_0Oi8qw@z>fErQQ;H%~P(K>{WtAB>t|XxnkkHy}p{GDW#$G`r-S8 zvBMR!q}Pu0?3s!7<8JOHiR{#wO3eJ8f07skFK^O&h(L7k)+Sf5xx4>YvSL-4p@8` zogozQk9?3yOnpLv+ovJWEl{F3r}l}^9xG@VqBuAm{bo+@`Jnn>_rzRpjAcoU#QDP( zyD9j8pb%MvffI3t#YKVi+x9Nbdo$M>Ufj1*gVnjY=I)iz4V&B#nZ2)J2C8t`OG9tj%jBVeWw@zlvxY3J*<~ zt_=yO(%5V0unYRnqBGWEUFxdWCwDA*P5iL-=k=TYEK+`Aq&Wo41#;Icd=%^-Yp)GS z>ocN5c|wo&c+zG0A>kMq=naYa?k2Z=QVNP&d{l3z?<|Jv(>+D2(gTz8hihN3t>{TF zI1(y~Z&k40P94u~%~br$kbdrp%%)FgwHV|Rc9A``bFcoy{J>X=!|&7R2Hfe`Nn0R&^i;G24c{lq9elrE%Q$ZY!Yu4uk>5kz5w< z9Q^>nyvVEo5{gl;*497kP7PIdhjJAEQdcSNscZfPYY2^LX(%i|S?_TUo}(ZE#fQq| zacHuAxQ*8LOlI(mCz+I(HT08|*V(dK{;@~=uw_B~_9fgW`lR_Om(He?(Czz?Ph~3B zl6v0#-4}4f&kEu6sHYN9DGR5#UT|{l#srI*Z9>K>s!^3~_#&=nrO#_6WTwf&Y+8*t z$S`*O6GO>@d-T3ki3X_|KjqUD&3eg-_|K5PCn-w2DJAXHlxx1q#46o0MRLf(uX+of zrgvVlIQ-ILB4Q%pkM^7-SAlcfC}J+pnF&pF=k zn+WywV^jQ_j|Snc6TwC+`HUi+Iad$;h0EH*76$G|24@CslGI++)U9T+-!qumQ>``j z^n=z?7Iy?mr>394O!57Ha%lLZKeo}HP1gFw>rma&q3<8!V|Ggc&jQ=ZUCdnGOiEp| zR(QeldpF+9B-37(aUVYRtMS~O=!WQZa$P1HQWmJCXn(9Z;vYf`em4U@M}C%byRYr5 zck>JR?)uDR0pf*7UJCLJIv5xjELeV#j4BpV1>y4>FfctNFfe%FQ#(g?JqsHPCpz4s;(~pWcaKgz^PcA+4sxSeGf35_3uhQt4*R@|+m#DqO2RS&xb1=Nn!Z@vb^0 zi#`?G=h3?;?}`HZM^4H_m^ze%bg zkQbe*ZCttBRStm8iRlaiGf{}^CGF$SI#|AZzriTjna~}XSB1{Ay>}1?mYJk|MUrAl zBS~dOiBp3ehN5k*Qat=PJX2JB6)S7R6#PCcNrHUF^-D|MCx%;nUq4?E5nRL`IustF zvnE*@qlB6CDhN*ge`>4#dN#H^b$EKQk_r=YA(GP`2Q_i!fgk+S6K z#Mlo3L!C`?H+|EqI?hEWKX#@lI6_HovEFhlDf(_AL~!QTiJ zLRE_E3Kb~bjqaGrf1-J|%x%Unt2*5E8E(w6>wOSe|6PCex$w*|aXtd+rbd%s?#4SO z+J;@H09msq|n!QIY`h31b7aw|(q9Wtj=R=#EDX${} zo;Gw2=dA@%)1he;`NYt;RCv5ZK2bg3qp3o$r^ROtqAw zimHN%mLH%7>JzWC5GYgJQk8&}44r*zLD|)_FAyyB*I6UNB}OL&<1I^p7#`dybM`P= z>6V{ofAYhsx-M}>S|+KnEP6a?8s22YG4)r_Ne$m1w9YJllw8~=s$u(HzAk9{Alv|Z zLN`yaqM6@*lLPZqE^t9xRfo6(SNu7Hbp2zSPCTX5xx)x)FZ(dfdOU-|NUWsS#?QK? z>qC3HMZ6_--erUtBmJeDK;5CoUbj76XT(S4D$K7>lbg=3H_S1zteknWe>^*^Op`EBU z+xFFD2Z_5#^#WR9b;*r|pRh>Y9bQd^%e(T9ltC0CiBSD3gZ(TUq>WEnU*!qZ)^G$f zaig)fDr^1Z0)MkghP|!AfZ@8HaZfB;QT*)5NA#%XLwWmOvt(iu)RcWE7#K4lEEq6R z{%e-hGqbazGdgUwjQ`M>M0Vfm1I2bT^tGB<<#==`oSE09(_flqb4Fk~cc`NA9e8Xw z2F@q&udy@MPpg&nTgN~0%0uHj3e1p_R53W{EG#T7B{V&rF8QPG@78^%)pMQMyuBhhEWRDQB zZuVJe9bt>`oqpEzE#@831*P?RH7;8xMeDglEI6p8wGR7g+JZ9YF19c9P>?;Zw@upS zr(H5J>y`~K+_kj$FX&Hfh(ITp^bsRgD$OtFKQ#GfDw5?Ql85}3@}WGSYn=8HE6d#=GLp%tg_ctMvNqRSBkjfY6SUKmb0S_teSEQv=x`@5ij|g z*}asMn>Kro6P+!cFmqPY>bXs4&Q{V0XR1fiMA#0^lwAKP^8Q8lt-b6SNues)vOTik zIPOoXx{>J5gk$--uSE?& z7#mwBUSOHwxjbG}K||m`9$O3ETvOe{u^X2pVMX)i!c+I{vklX2wQ3p-*et|{D)rm1 zSg5rdUe#%|YFbGrxNq*hBpxJXYmHcDn(ASdd1Yb_RlZ#;yY5NvFFaH|NRCFqFph6+ zVc+5h4ec%rdEDGABpE#FWx6!am1g>QczQmZZ4M<9&80>2mw&=v%>04&oaJ$PCa8Toyq@n+Wk`N<*w=dl^*mW197$24t$cFe008vAcZLzZsem=-t)1HZe-E}_wo5< z<~jeGh<|#1w=feFPvuxsx?uB^%71s(|G2)zg)>JUxaZ{bV510hx9fYlyBHtr$38=N zpCjZzpS?NXyX2PrMcw?wdZQyE@GIwtgpzjncW?ixLH zc$9_D`C-^|E$)ZhSO^}iGq+ZUh@T%;r3^xH7bmt_IgK>hPAV&VKW=t5PZ)DyC$Ii$ zpCwp5Rny2*x`VoAAwVYQnUg!0BRdE(IQ4uesb)udAl;@(J?y4IH@`M8fFxt+5I=Um zbpH66q2)6fwlh6;H<-TyvNHCPM%*Hm+?u>W=-Y5;llkCKhqcxz z0lNWv_5CjU{WTw&`gXJG>90Cu^r$aP6mCCGTnhsis*3GdBU#B{4z zi*N8A(`yRoaTw5o7NkB`<4VrJU6pl-v0@;Xr%LincX@uLj*w50^r}u7G!0HyBaiQN z8~ho{m~bsCN()&eBZ~%QvL9^bfw>--64nae{*%0`>me2P1C4Y~o4T~|h_7kxbH}~v zFG>IF(r(Ex62MH86u<2*Gj=8og<|3+JAoO1naGl9o`T6IHhNJfNeZa*%Uh;PH18AA zhTvQ26Y3i3Yie(9TUn%zwK8FhX5Rej-xrwHoC)*TTLuEze%RW&q)JRj$@D`uBu_}M zI&I@4i;Z6{-JH;f) zC-9kxZ?Zw)lE*}ov&%ouEFGS*)57?oTNN4g6*j54vKSG1o0)1JvoQ%{W={GPSdB+Y zi!=x{f{2HRKD$^B62mzK==b@Tze$M>Z(UX!t zH%i5?y@`y!(hvOn41E0D(INiMEYA)$5e{^-+KZ(dt}IH;1 zZnj>DS|vPTpej8nk6+1TsBL=p7X&H6+~3@?R;Pl|Rt%&z1bC6CkmbnlMR`4LyYx}n zL<;AsXM~-%azR(v^~6p+ELL~Iv@Ii*B*$~({F@ez?Xqs<2dR2kpDYdw&CnT|m>+eI z`xl$afwkK=zrT0E9Q7}nDq20=-j+SxicZ0c9Q3oN+R(W1w@v(Mujrs(_~}d0wk)|u zGWkJK#R=*s{h_POiKv7OiE(4Xl22~$-T{=Fk5?IM;ht)!LXn-XDee~T0`^wF9t8aSUN_PD+I)tX=A3@VXTq+# zOWs4a7MKFJO-|ENDMe6?m)Rcb>UFNyI3a_ez*Ot#iYH^)YIB}_S^8b5a2a$X*`7!P zyx5MceB9r4h&&+LRNE;y3fI9_bs(?P$GAsWTy@wnYMc7Sx?R;GvukZ`;?kC;;4$>& z5vCq<-=favelxQ)8(k}nDd~ccK4R02)t@+v=5JD0RQY~DqQ3z z_GBfin+A^0HPyfSyq5jV=Vz`>+SHs_k~KG&m-H`8<^II>(JmdPZ61wKRnDzE!*k8=1WK(K{- z3x)#8=i{5)SfncbgJ9dTzp+rIY|Tm2CYqH>Y!6TVX6`55JIAAOgjKxw5lm{Cx-nJJ zHKLqwbjqm=nu%0*!hO&(Vy3Kgl%)KlXncQ0;lT;dh#>~1<2Pw)31Lj%w5K$%!;{(1fpXeMRB5Cix@7sz&`iS3UT{9O&jr7(}kOKcuExGdda?Hp7(uN zZ>^&Z!;^9^%xa)~k$tM&iH#v$p$LL!@P;XQ@HfO9E%Um^m%4=Y+1*1X$)C(!qf{p- zoLQt+RIRyT7ZTDwt771rFH+})HccHwtgu{Yf1`Ey1?M{=vz&z z43(f?^Rq$_!VsYIpL_FDYT3lEtHf_#?J5wg7yG@%Vc&Br-jZ^?{J~&b*c@0nK3xA3y1rvneP8GK>Ep`_8K|)Xr3LfYC>ZmLeY=aoKZ zY*yd{{9AuSLh3Xs`02J-m;!0ec*Z>k%@DZi_~o>mQ|g*X1$$|YIlyFt_HpHJnj+>L z?%@JY^aM8)`wT(lNeR>Ttkx%!$T(A(Ge`h_%t2jnn2qn|5U(t{we*rlQc`sn?#t{X zNkV)Y+-(p?>ODb)_#hF(^0w9_eAP*vkJOhxb($Rb)>rXRw~{s6e7uqry3*UR^t`}d z=YzuOq&{t_Sj9}cyFVh+X_;?K2&^gb#+0||tbF?!YjiW&`o2E> zgwMUBij2Mbwv`19^VmnDtis;27!@7a6kIUXxr;F8dK?NY$_yCe^$VR8LQ+CO9 zcXb>SRdI}i2VF*xc(JDmoy`7^$i~N?Pk%7B*Wl5^jDeT<1Jkxa=qrg)0}2dL*`5$Y zEt9%c8{LitcueES`N4o zN!8tbnIBbet*E9&jrGl%BrO}UGYJub) zw9m(}1WV+NVqgfBR>z$*FQn<~6LIwFZtppTDG@yCy;V0a% zZhWCgm?hUB3<}7J(7<3qObQ zuh#x0Z}?fuva*~LOJwq7i$7%bShYb=cfC?+Dgc$%$tikHCo%(QX)TTw0iZ12O4Oo4 z{y$z?bHw%la$#(b2Mm;)OF`V{P+#U5ofS0v^G+dESG+HRxi~jh-o5!v%}cb39P4-6 zd-O=n76W=Yv-<6cWFfd^P;~OvI}?i`6iO@bS-A?O<=?S7!k{bbA!lYyd=`h@nUWL) zD9II&vHyT+S(^ZuCe;piHmIx2ut)X}FfG8+?!zmX=FBFi2Y_iusVRfSG}ETstmp#j zYc)4pN3qL7b_*#y(VO)s4bkvni~Vn5n&r)dFxbew)CIJ+G+UV-^ph z`Y;i$pSLc5SK}p;Dx|=|n>t(y2-u7)QAjL5O!~b?_phVuwPSlz`^e)RX3;*db$cMz zcW;QNyKI>SHL)a*MkDnwD2MINK5S7tsNLID?i+EAW16X?OzcBxB# zsFNxg8*BFp6JW7pNgLkQWxQ49{ZXQ3#T`LsjFUjj@M3C?+tV3;WI&`D62y+Ez#X=z zpqJT3>1p|0%2jIi%gfJ*j;~_gI_2<+Lk8EHy%yS{oDpAs-+K6QjjYNmd znhOM0+)P6xPjq|=hxvA!wf&8li@yYlZqwi02AM};Q?jB7l+N`&h6~!Kj?}0zI_HP} zg3f6=WV{PR6>cRGb+Q|;Kw|m#hl82^!mDoI8FA-Ncf{=&@2qbjf-7rhCPy3)w{G=V zZ3xs4k%0$VtJCG%+-}&ZjxYm&)Bl?mudn5k4Zj@JE_JP}b%*yWrR_&C={*q%_)7hU z(32}Ncc94AChorLsia*@e^lKdaD=(h_dkJCB=x9V7vdH50xMC#AfmK}rK~4MesKFu{ z?JQNl?=`K+=1^GyG35YNxh^^jnf&F@!5CV!p?WG-hOO^XG40Di%TU3>kIoC@?~Ho2 zy~*O7%yYM`6>hc6mcKm1vadQ&V|kyd#oL1;Gu<5wENyyw=W}@qV6`TRfrnG<%rl`Q zgH^2CV4#(_;h8?tr7V{=sfgi|6@hn~-fRhZ-G9e4^3t-lcrUh4Isr-Ih z`p+ZE!RLF+lO>)mr|HBDTr0$@Oe;u2H~PJ zNK&QzplJ@e@6W&e?X|6mw9&69uEAXv?gJqYPA_Sc3hjV(>>0S1DO?zaRS-0uzaeR+ z<(h?K>QoXJzPwc_z6jO*`Ki=YtY8e2E7k+b2GBD)aK*|vo zU-P%NE>s7L(4|la>W9O^Q(k8?t}Q0blL;zy*VssFHFwJU6M=L8VvyFj&}9-DHF%Kc>HkROM2F9cfFXV+7gRL8qxEIp58k@1uESG{H{TXPpiU$2q8CI?4o|D}#;z-8!K?H+ zL|8cOWFG#={jMdXe5Nfz94x(_S5O8_1gqNUhYdbKHB=c~GSlJh8rXsxTn8 znMD1~HcXwqzoU7T zxe(Ut&bwxq{Mm{PSKaUC^a zY#_XKCP1(n(Oc0rt#;qr&B2m4^p%n;DUR6Xd!oF}D$mFL0Y=6pOD4~jb}-loVu7T5 z>8r6SmODsvj1@;y7@2Ximp5lFhEb(e@dGUgT99bpC^~>kimB{XFo^SJF2yG7k-rLI zdS*mea-~%XQ4j44tN+s%zw@3wr{L#eV*$x@FpwRk{qbf$z966Oes)>nO{G z*-+44wIjK2=xf_edcdo`Kevp9K^~1ogkl_KX2PI`Yr{W8s7GF75e%?bAAJYlyd^N| zM$c{vGjJAe&}dah{w%rw$v-w&={wv z;ntpLP*(j$oIr0Ftrz&dNF)&T;3xCjKzOx;-T{h4XjVFJ2ut;*jfp)}i9m8F$*K;8 z%P&sKyt(o+@*H^|RZ}0W;}^R{Z!$*KKJhp1d`4urD^6rfg|(-Os$lJ=VmDl({F8^Z zB(CwOI)8sP3@~L)=-3W;1}E28f^S@(bC8H+}2%jiREmxrLxN17TU!GO!}7-2M$@7_;Rmr>v7hmFHWj5MCv z7VP_11eA&$8dVVXT6}pq)+Sx#oud=DCaMOW-uH64TK4rRhxq{uA$pajIN_^nMljZ4 zgRjav*jD7pffRPKs0`k#xrUnM`@$R??>CifMb?ObjgO>+^Yu5{$Dcj3?7$7>!YflX z0n7PVe;T?Oy`v6t#9uL)`FZa@CbbRu-?0l@@129EnM>9HcZr`j1S)CsBQXfpy(w<@ zs;$?9=xlqWX2|#IS}6rPs7)qOQf`{{Rg2#g&s0MM07(0X1}@o8cc@Ho3Z+WF4s#Ic z(+CXL?-WP)^k{TT@eh|~DhCv@_wG=M=mX-;I*MU~J2PnwDFZQvlvyv)gu979gmiVo z@2uzr5hj@shlwz=AM_!J2oY}aE;7w+Ds7tN3RmB6AvxNTGGw8ad}39Otx*<_#_?zE z5vTVo>VW8i+*v%5sh_u+9knp?E6{<>>Z=eQ!j^4FA#_8wwq>_9H(Nla^^!5)BwQeT zKXonAyy)qq=k)xlnaSw5J!V4^SuN{6*69cH49OYQZcec! zaGqu34I-I?Jhjs>`!RQ9tmC{DB#M6SUPo_#v`TO>Ezg!w;b87t6)L2@tcYbbdf;Al zv*K*-!ZPX$(yaL!fr>6-_72=*VIWc$RR9dXa#s$yYz;L)&%P@&->BO!7|{e*;3zHY z=fW+EpL=6nBn>yp#B8ncIClS_RL&BwlsU169R}XQZk@gM*^=@p-9uy9rbZB z$Hq=p<ToA64V8@GZIdfrw0P%4&;Y>QkG) z$JZ_W3Q|{glAyactmIh5pb%d(n*&CSdM&w#tHreLyT5+@Wa%uF2 zPwDvx%t1%WFtoup%`MZQeWq8ljGir%K69$>_p4bJa!<|(m}T03%(A;*kWth{rHr_1 zSpiL$^M+dt{Ecb-JL_XSTI0M+6-jatPInMel?1xzAs&uf2O^Z*CH{{3hVqSGXC>Bt z`*|b2QPg_$+Th6^fz`Nma9FP!j()OffA}J0a(NQAY@x3Li0Qc=+Fg4$nMq^ZH|y9f zuy~>A)^mMG+hPz>MYr%iyZhd{K39+~yjeP4EOrX-Ufy{8qU$MP8LA3Q*3A;QFofA(@Gh3x;Jhd&_jP8WY5Ot^zS!nh}UR+%)O2;{99H{q<5Nb&tG=1C&6Ijq{m$;Md5NB-~T{H=7 z1i3yzls;G#c~~dKj0}Ht2gjvRN$7B1{^;IG67w>A# z9Ee{>Z#TdU2^aSwk!#PfKwkD$=!s{JRJRFzq1aB&*vp8-q{@xO|i1*PD^49ZE$Mm+ILnEQ>G2F$`2w%9pmC!TINTX06bXd32~$R z917wqK!zx3=QKCo_fB)qPy=wwNU;ua4a0=Daet#wR5kT2LOXw%j~ghM&FZ0+q=_J( z8;8gpZ_&SAk611^@sEr*tq=#nD+Cv^&_lmw%(H%n z7Wt?{6R~UerIwWv<_EMzpdvn*i{{*#7{5*);EzpH{L>$!MDi^G{IQ?Y4Z%BjV>{)! z#Q68Q(y55c++yq9V|kNI#Zao9w0b-`fkfmEes`Upba%vJ?l?t)>GHpW`@~H%1;E z;}(aZxcwyz-tfZMN-`@-p$Tr}&J*g|V@B{z`4S0CY?q+g!pi|b#(Lz-{i=Chk+G5x zRR9^|WMLb~?!QKoL7suf9@^As*(?h%S2=mF^2sRv1L!QOKkDmMFPG3JNU7Lophc0tuG4SPVHG zas!5=6j9imlO#6YzlK_dUk3rx>V(T3y(xLrH zq{|l*!fOq!K@Ydzz#X%}z_e=B0}76CUT(K8FHB;;081$V2}>8jKK)3IlJZ@Sto;pQus9u(dF15pg1Nj4y|v& z(<={TTnJ2-9ln9ki-gUvQMnz|S_-#ik<)VrZR*9%h?41vOuX1O`^Bx55yRGnElDud zdv8oG?9XaS-<)1vF+o!D++0}QTo$8tOzCofu2#LmRxzLB9_YO|<6cVQ;hPW)8@ZET z$dixT2l5|mh4$O;w)zJi*_8`(3t;< zXxQpLc=dv~I7f3>>Vj;Q!D(tLyQl#KY`^^~0V@^QUZBeUd13+jFNiz>LA=F14U z4Oa8z)Ik9%6PsN{ktMXy`Kb_Ka)DGC?_6q9MJAbV>iJa0THrf|Dl{lgz7lEI_5@Is zq^i)QaH))Z7Vmr8HXE8dPuFA$-T}a5V5dx$nD28-H8w7PtR=8U7_)2wg4l#KhF`Ky ztt?+E=MU3x3v?j5bnfj8jSm7uW~(c0|L3Or^($&78m&`7IU{9AEW4cuL}?)pT3-ld z3cc7~1@9G>lxQ11(+0X<#KG%=5t$*Y-qC^yIxCchmQ56?pIfXkYo7?tM`_4|94$7w zKD{)u#P)7WHDM%^@SZt?uL>cxS&SMZtIiI%E6Z(uZf>L%Ew4nB{|c zU6j*-jLdZx!G9~$Bg|akaPUkI2`yetWwP56_9>oJ%{WG`6>oCurJjzjlJ#6U^VHW! zv2?@o4+#J0IZXSZ_LV5AzP;W7Q>z9}EkT@bLZ#9{kO_`x`lPOd4D~Vf`5_bHYc%^Q zv=#`dwZ%V84-!+g$%vl%cz$z-zKn>8X|jy}t4se>>B7_UmGjYY{j8km<4$g9_@m~_ zu}jCfq4w&#OMNu;Cu*KGS;F7B<{CT5)*8?~8d1b&=_c+Rtnu9wN9N}%8AHR^$PII@ z1EHGj{A?WEE>A6iy=0@7p97fjheqG2G+wZCbaUA#nCbhE|HnNDqIpLF8^}3GtSZ9x zs+r?V7c!n_N1Cw(rM%vuh}Y*zomv zkNVqn%@)f;i!Y%ZK+}|TPX73)>i@VAQ9%1eX;aj{7X~~~ba=H@mgjP7^)xAq+48GgH~AlWE!2$4F}Zm~TgzRX;qH+I>cc79qQ@96|cO zgz`h6;^>-AP`(b3CrR&Cc0?bJ?G<_Q-ZvaOIk~2_C$v{~}X4AvEaB}j@Tv>f$8n669qft3G z?g^_16%uXQ(lO2(BP4V`wR)VrXez^3a|I*Irn6NG z#D%?@7pSGSKl?=?WSZAS#2?)2&~_QxM0~{vdAjI^LHZ$AqQR9{-1hih7Jq+~f(YN- z7J@2>n!|9hyn+L1-hHdf{)VB|H)ZEozAaBng8yv-f!ZYEGKU`~G#Fu$&c7EK$(TZbqz=jR~ z`=jVDCeA)bjPdwr$oTH}$2?XQXq#g)puBHL?ZAqet#cL?4bsgiF*iH6p zr3i_Jw06=JFzv=W3?9kza380>Otmi9fu)87^0RE%xw)TvDy!X~G}@hJQAf%1^w_ne z=`QkS_?zp9B>rf~XeA9C7shs@-}rq)IX z0=tKYNzTrw?y93<_zpkkurBZs|Hg?K$snq##Y7oAXXc0e!euy^pr!UT3gkwKJ=g{W z2tQCzakB@*UGfW_%f?B$Jp)gxA8!9m>G&K+wf!{&NP80%_+aIy46zeI$C@QM1|r+;Mj2O4lS(L(q1MW$Pgyb)u-;rNV} z^j4YhEzEic{at6JtVot~jS6Hiw>_oLxd6h>QK=h-FG&xj7~B9uKJwm*3>4wcC(S+X&+^niOeYs5y8h zAS_!W7ax`^2qS9eOe|g=3yz1hdZof=my)xsg)@jvkJg>iW)^Al#U4lWib@e(a5I%* z`k95CLC8ZQ+Xyb+2xK2ms*x~d3%Kr;7Rn_ot?^|y47VRrE5$QR)7}BBYN_Hqs}AbVz&r6f%&q zei{w)2MbS@VlvW=d0fw50&<&v3p&xS?iZ4mUbfSkc@QK%79NU`zaypY_7vw<47U$| zDsqCA4{u|0M%2lre?rvm7S@1?GcFReewEE}C5)1H7gi^RYP+axI+Qx%T!M3E`~fmw znEIxCqch4}y^84N^ZhK0!V`7L5}&|YAPU^bfPawzhNk?duCFB|xFnl`Zxk-5Ysv}) z-ode#gun)&sjvFKbw`m0mWF{mV|BoOLw@$Hy_&pXfFYmEKEMNFGi$H;D%Q+@OVkd6~sYq?o{6tBX z%ZbAJ$TBs~#g(O!#B~x;t6?(6>G!dc?%c9O1G4&J&`LLDXnG4BrlaQ|g{H`x$!Wbx z1k74N`YjtwRXstL4pcEUlo{hIK^d*7tR)D762Y_3{1|Wh$&=f?kL_VI0c*;sXfJ3K zO)mDQX#6Bq@0;Yc+P3-?DYWc#s}ibV@o=RY5f~V%5?DlCYSGIaDGaI94RmKLqIwjo zD$+voW$Tj`1M_d0Kp&DoF}3I}^@WSTEq%q_4-Sd>2_wEfG|n~on>I4=B~saB2i@HNan- zQ+^p573l+j%z4GM$ddvh^uqtAr)B*QPfKN~^dBJ8nup#W_Umu%)*tpOi;e ztQhMnA{19(Sp0`1`&ac71e3WU^HTwICLR!FCifI&fP^IgO$zSSpQBC+_->&Ayqm5{ z`2vt^{xb+*Hw^&T(%+FDfV;{iaDG*`o>AjqsPg`QK_*2y`Ew({8FJ8yZ4cVY{_xtn z|CHc=CI2c-!AjKuGSZ*)LqRk%0OO?zlsy6{d+eSf?LYCRzsBPX)4n21^{bRt{!>rr zTt4=-vtt4c{TdChdLsVT6969yFv9*L#B0KU#PfFmiL2xv(f`U7C@(EQgZ-UT+JCPz zm=IA9J^ef z>gt2${r|?eI_=c~YpKNnzz=~sEC6*#`|mn{G}Q-F5P%GJ!Q&ivI!6?NPLO!X_!@7i z4ecMDjqNMl4Ef){HWPrk+Ly}smoN4@dR`+Q0MjkdVB|n%f5(qrkwNd`6kvt{?4o~e zq?14YcfauhB)H+=e>H_E&~d2&=ExA(0Ers@-7oqly!N{H|1%KaWA$nO{`Zgo8seYf znSez9yINK>CN)ODGd2JfM^Ee?BgCaqB3vlt3>;@9pkl;R`CNZ0hVkz)YV?Qv;s%az zsBH57_?{vGFeZcxq@4dQtN{+*zjpqWAkeJDf6L!l8HoAs+yGLL3pi$>e>-Nch#3`@ z&cBY>fa3D2*Y)o?A4|$vu2PD1SfZ4MjIoRun8h|EX=cb?Gb&PtpDZu|M8Zx*op?G7 zA_q(JWT4D|6IVkj)Az^zdu8AL2Vc0)@Y;i#03DD=pqBkB2@UV z4bc8VuX!m{qvy#C0bpi8ejJbzTn1etaH#*e`AV0F@;7o282A6V9|#=-g#JGT`e*#V zQu|-Y%m7Z|Jy51hpnkwV8*iZUa{pDJdq9)>&mce($Q4Lk{TW;TGC}Y572}_O(~0{w zj(Iiw>S0Em3tUZOQkYpBwG!ADXWNQ_5S$!C33|o8!rrM$F`3NyXY&O$D8JQt9v@4f z(J_z=gRdcx{IWG{%Rf1lx|16km9yrG%=j*N8-y59b zZJo@ylrDE8cEaA?$WtS@%^8Hg$3CZ4i60U|Y-|WLhDo7Ci1yGuhH@GG8pLsJ)KuyH(3_~4`7{NO&Kz4S^s&kXwuXiI1;#8d4uS{}&JB?(h7m0u6MnjR(k80{2oe8p0$qmVPKp74x6Y2*H52k7I&u zNODZe2EZVFj|W4Z2$-Ps&riidIxvC~5$}|8&&OzB3B*HT6oASU&x2gO)jqQb2A$iG*h>s0ZZ4;Mq|aC6A`9h>TO|2 zPX@JIogFoy%CRy^u<=0NSZrP9+f(7X+OE$e_8Vddx`-CtM3~k&VI>`7IWc1RQx7Y* zfdXbfg|Yzc>o#1?l5ESE>q`7p`|1I-FX1SSebC+bkoJNc@8eFwBJ_<z%cC1T-`&n9`xqIGOZ`#ef0d$&A_RShcCNq{G!Fe z+A`D#!}zu}jKF$EsW@BYGPeLZR%0>227!B%eu}s9!%9vkgAdMF^E$hPH5bHLO_Eb( zeCWZkQ%`p|N?quKkE`af<4NF(i|s>;-nYjj?T?jP>Q*Pl6Xvb=igt$$+UK}mVBjKd zj(0-x{b3qfbCHDOB=jLl5JhQD2(fg&saJC2OgC9sai$~;RiS@WRI&i}BX% zhDS2I3Ap$s@YT04MB!Tczk{Q!>)AzG3{v-3bJD zNU-4U?(XjH!QI{63GQyeU4pxZU?I3eaPn)iyZ5!b*K@z;dCqzN>NzvjRn^s1)jc!) z`BtYYRVhda(q+_q?bLA)WMHhSB8ngtCCntDp+eH-&YrlRoC27%Zf@^RI!6jAWPTG6 z)XVHOs80Ld6d7mU!_MSgFOnz|n9U1h{dG3uPMKXc3S4wdEb;qnfO&)l_;5o2XEG&Rq!J{BVNlDltTR6Y2@(i~H{tBKwR(A%L6b3L-AQ1E zyNui-A5B7K)bhBcdVQBcgR#a&1LmSFMbpb>+avDJ{A0`~7Tz}8kCOMEw2i6VT%Z#m zFSPrk$nVjvrQkAfndH;0q@2OiLiXw}o%Gw9VQSQ5+aT!G}rZ`qM8a9C4(hJ7aa zk!@Q)6g+2zvOecP5{kh7v?5qNcf?FX&fbVUU5R_ih*odHGp%VAb#XVWzHKzTyte2J z;|9<0RO4iqT9S0<@SU^ne2TWr&?GqI!kn!7+i1{!FQY})ek1x>y1%@#V{8rZ`iJS;^d~Qz;xt4`v?m+#H2nAmB~G;KfP|b1yuX$M9<|FbrhR9|Wg=MmpPYhRl?+oZ|{l zVU0X7ymDrcJBrizil-2GyOd9L_1tf52*(umrXB=@XwLTIrJ zP;O-;DSD5IZO|DHD#|tzAVJ(PGT;3}7Pc%OV{k(AVR@$MYsy%Waq%N4&iT=`MN%BN z14P+l_%gmAffS2Se}E7#2gQ=5=nm?8FY6d|Qc=4-ORmegFb&aVu6a25_8pEc=Zm@D zxeZ8$ngO{gtnk4d_+|*!H-6aG35RkX6;7PkjDj-;#{z-dv@&87=I6|6=&g{-K>288 zu*ueiUbk}_EbZV0cJj?6E&Qm^Ij1C@FamjgiBg2Yek0jNGNw>NxsIwzIZKtEo#UK|V0^J{@nt8VPHD$Nutmqk}Lf)CDHU zfyZ+i6`4BfeE!GtIDDZE?$prGJ1X)6M3jVSwM!@Kv*Q9-nVO`0hOUNK3dT;wh@rbl z-i)?`WJTs7*HLqd!0!g!@4qpNntC=|<7618!ejwXzc}Hlg((7_* zOm!&2Tn@U)8xg(z}NX|vub~ZaF5%2DB(VFw_wo9_jPU6eGm7Q zV|K^my}5gY{o&k1WdjjgjuI^a^1`RH($(FCS+o4y%+wMpZn zpuBG~sm-zJ$42{Q?-Y?~1LMOwQJtybShJEssQ_pzWZejs$@;wqkhWUi6rO)_H<0+F zQy0oU%5&C%g(~hbZBQi-YL)+&Jw+w?|<7OMS$fS)S1km&n`*DvaNEv4724{>zz0P#+Wt$p94OnpSk2 zM)|GQN!J)m?251_kb4f`hivb8zT+Zo^aoD1(`viiefb6rgPomQIfBA zvGo~$3R}>PjC>iMU+VH>AeM=9!iSqv8^U)eD6nT%Bw_Y^CLK)nOeV?%cFsVSUq*D`URb^7EP52sKyT|#`^6%%p5*?dc^^3 z%I{`<0w*u+cL5)EX#Nkpwr|nC^+#D22w^k|0x7+FtP2z=uK$XHIVn9KR!#?5bWh(G zRx*rGs1#^ogYOLQMMCvy$hech*RsfHVvuMMd(~;;+d{RTxb$C{Ex-F>h`uG1Jvdf~ zK1v|LH`74Dh?G!$ZlGTT3DL6~-}Z=;_Jj0Yv4 zV}4sIiQ$3(_bpS~Pd!|y2pG;?fQLoSEx+EnaXg3@m&x^7Z>fF59MQEi07ZEH1xjdp zu`awJQDtL9)zNYbK2T!$O}6eZRAk(4d~ErG(Q=3vVo?OGZ)x!7d*>v=k3_RSe6r7_ z7g@SLgv~C?O}z(^^%M1_yWO!_S7q0|&y=#HTaU6NFEZuLjtIcjVID8+c}Q&de0;eZzbflW z^XYci&us{QlPRqU|IkcWqxG*|?`Oy71rNoH$+YjD^9Dj<~cDV+@gXC)J>QpLUbUL0Hko1Te_xe>j z#m{Pf#a;Ll)Xtxm54X5whAoMNwlT6xI-1od+77v^GtZ?b=Wbkco=pS+JXNMFoF`tS zJGm2gF++2n+DN0GHLUK_rhBI3({d$F?41Q2GgIP7;M2Z$pIw4QUN%`k&8s2j&3RhS z;0*Tce1F?fV&~O6{quc_IR~dNh1U7)=G)A-f~@vx(+cXHy-|Jr#6HZQML7{BXt^O= z63yP*%*MLxnPYe>iZy(m?GCb8-6vevzl>(!Sn6y+@N_&t}OG1gCNA1 z_44|Kdhg1IEI__Hq+&m^9mG;;iSuaU>f6VO9og##|menoTvbN;oJv(fod;H$P zm*{+mx`h5tqZ>a)!rLEze6dAbY}-6v!yuR zSFDYh(joqInLRYq(h_k`}KOot4m%R>HRqrq)v+q`WW3@lVXaiGt zUv4?*c|RmDY@;$ z#KvgoTla=zV5+&B?0k2W@Bt@vp6b8Z}N+Jr_#ht=sfjo;nFt=iNf5m5A!Qs4!mDPHracwTE1v4FoKvPE(m=! z0hy*p-U5dsZMK|*7kg`20R8z2Zet-g+^4^zr zlPHpX$QjfxWk!>^kRJ*Rgus5(a+jq~2)GYx;UGAx5DGCYgoc|Q5JfbF_k*E#qgewO zS74Rtn(+2F#zj{KE4r<+2@?V^Zftb~a;9Ldhag2uxUASIZ1j6uszWV~Pj;F6&J8FW zN~}au9D%z_^>n44vGHCPxAJ=O;Hk$sQYzL_S^tG`U4H!s<4OitQ_}Hog5l(vR=V@I zE{-?zs|0+)QI(%=lU$%se2YPpJK%u{sT|Z=1V>ddiWEB=!jhr2pF3?J1AgM3%+K>o zto_xNY*~*E`E8ac8nw?G?v*k_DguDgxei9JoS;Rr;RK2@ogQ%=NjbZ=Y86(j*j`*- zzYSe){7$D}RlBiDC4{&L_O_JuYTu?mknI~}vO)zsmWrlO# z!3fBUi4vT=kMS7c=PT@%j?n0$Da7ivD86hNmI&W&LdkTVc@Q+AHd~mVZ4tFMeIT~s zIS-5(`nqVg%5A01M%Yk1KKmkPy@Hl?x> zQ|#Vei6no{#4Uz^9WfEh9z#G8TXRj_2#l$NotsD04C{lbc+H4(LFP;y4ev_EWdxgm z#x)xYN27xVeZUp~bnbxZ{)z4LApUEu|L8_Y@`Dp&L47^H`4?u9KU zr!5%(rJO%o*rae^o>yx?7n<8S(2%{)1 zAWfPzdW2>xS#jWsZYnkGJ0w}7$Y{V5yG(=WjT(vR=d4VI(WYF7M@*R_i;6k;A3$|SI{&1)7z9y~Z*dt&&Ow}WFbIeWOqd+F8KjW8!K%v2;imYUD+?6V{=Fb=08baMuf3?@hmK@SRU9S z$nsi^b*HDPeM#D#i3kf+(Ima%rPDL5xVCBjilHN;wM1lkqgJeAHcaG+xWGBzW3no< zBzFatII-^)(_B8`euzPR5z`vzX*~Ryp6ZHH*Qnhi>JCJ?fQnaswO{?xA4b~d+JA7b z^2!9)_+e(f3?7wQ z^(uQp%dJHXRvpn{DW$+N0!O`HmYl{`MHhx za)XActGPGbwW(hW!gC=jzgxe`C|Dh*&X2%gP>IG8!+20h$-jO<5cZvgR=`prH~}G< znnC(yTHY-pM~O#KRKQP!Y4kj?Bzaks5NkM7Thy){da?!WoO+=u`kVizl>q$rr|K*J z#leoNf41icee2wX+O};h7XlBuxQHhR{HczsbwbdEQhb z8W%i-b?h(y+mYmB-)@6#EspJkbc$2Ubx@0mQYB!ikC)>3G&4YA zdA<`2fkjob(63*nSMr|n-ZIXVuf!i%L1uknM0oweikIfg6qm=Ipomk8G`K%pz*lEL z8c@k)kX~%JAE-KI;gN-~(8Eq+;L1gljPRE=2ngNR7I8oz z(K>yohS0|$_8=C5t%F4Fj0;bh@Rv3cCNzFe3PvwyobS*;I!8GJjx8CEm-dcvhNlrV zHttzYJRFz@-B4D10sYH#(Q|A70{-RZD~GhzK(`q5&)(H?A$@-gdBaCixd{?+md&2N zQE1zql2hl)6bLFBtx+T@-u>$;6b<1i7C7qnc2W#zl`WP5-N7;S7b?oFcy%F&3_iR? zcGtk~xe9r>-tj#gRB^Us$|*&2e&uDhm(FzANctnV0TFxy3K!teuZXztI1oOnXbTP5 zSv%NF1S5=C9@$0FNK`-AOQjVK9=@`NilYNuRY%9ScqpnTK&ueRPo+k`DrHr&l;NoM z5<_{x;9jdj$$b*%2bH%0fDMNtE9_SYDg*^f-zk89k{omUad3r)DfU29W}YJ;@Wrhd zhpK6+Qq-D1_-FdReQ}DXI)%rUx*d>!HHMwJaSBf>kB9Ell6?-cH2*lkIyDDqRx_#m ze<5S7@i{N_RQzO@q%b-3NCI-h47@q(=4JX+&y^xM>OIbP{BEmCppHRayJU~Q=4>0l zlIVD+8|Oe5mKn_V5B$_O@mA;HRDVpWQZra>gG+Of$^*R?Qw{Q`L$g+8SM_Wv;KOd1 zq;t>7Xa(KT(G9*za&T_f(#?3UDT@|I(#sl`!Z`MXAUbgL*kd8=bZ}UF)`&Lb%b$R? zqum=PRTs0qhhc_oZ|^i6$fO^6_nDekCC9tA2**PoykmvU&Mk_v;!`WOpJ~xfAO}A> zZyMJm11Ggglzb5mO9*_CBu(uC&m{-n?tIa7bCK5dsbq9XQNg$QcTZkz2j>FWf{5CF zqmwYJf%PlepH7sbO+j`ymfmX}&Ux%=Q?3Y`KFk9wxzzK}UquQdH^W6fgKF>F69xZ4 zDb@NJeAyoQY=R?eFMQPGJ?CSKn`YJL$sDC4Z84HQ2BK+g8eNynT@tQ~F_N67&0Ic< zO3bz*rWXrj6n*C#(QPm+K0KrpqgJ*bjk&J6oegi4HF}6GrJHAt#;9?bX`UX)5x$Nr zIlLKop^$B;?LWY)4+(^qP}$!AZmkTF21I+? z)iWqWi^idYiy-XT0gdowLXoLx5up5DGIqQajy(PwBSU}lda!EOqVLw>obt71Au51I zSn4BgYfy$qxHHWZgViRx9BJS^bM604-J`mnUAlV4XyRf&$o40Cv*>6cH6m8 zA+&ay-Hls`4L#Fz3t*|5p8Sm?DXXifWjYG9s&CL%F>IFG@~6g}QoE`yO&;P!_RKH9 zN0S=3z6wHj<+DWG_rvk};mJb{{|G|td`I;W65R4X23bv%s#y~TpMQkB@p;=r^d8z7 zmbMl)ms_! zgk}rJ&VtH{m8~)%2o^|iZl|zZ_b}LR+k@!Ytm@~1p{=1dH1O2hpVK$ZF4RB@5#K!F zvGSv=6rVwoIJ}7mpGhx1xv%!Gatsy0ZBNr!r^qAit9cMSv)J4~NN$V1uqs%96Ux>r z%IY+YoTMFAY&0wd#PVsAc-v|XQs(B5y zMtvC;_6WWS2vSuyR?2}mu%JfKNFw1cR8dzs?M2DMz|5T8-H=`Y*J;&?U4||rSTP_Q zn~Ibn`iaxyvP}2Lgh%Tg`{9!;r}5pO|H#S!nAEx8o1CJz%ezN37{m6rV4!&X3KxT% zyjl!S4e@CMiW)Q?4ButUeWrmZ=xoPMQ_hlLkFn|+rWS+k4+k(l(d_fe5K)@mQY`0J zoJYT)U3TcFXi__5nc0bas)OO)FM_3lJU@P-)Xq=nGHzeh?%7oC9sM#eEi6FMyrmUy z!&jw|Jd($9{6+txSUK$~2{~Yy3H!>3sGGM&0L!dov$bQYp!O$aepjV96mjvzhvxEn zxmn&Z^|lDOu?Hw~n#LcL+11y;w($?jyu$k@Wj-|elQL7QuyPIbT@__`cd2)%wxX9* zY|xhr&Rvo7>Ozq3`0q5r1@dVzTR>5#lv(bVNQ4RrCx(P#jO!qX8Kjgmi?PfvaA3*6 z8i*5E@d1{3PSg0k>Zh*;r_m5l%7S?1A(A#>H)*KqLQ&WCp>Q-r-1=SX-;5(COi#4A zL8lwr=jWH5&9VCrFz3L}@=i{EAf8B@HNfbNv1YZAtMV6T&urVC%`jC~fAth`MQ zitrN6xtif&cRE0s-SYw-uOhYwHGdqw#E^}5SZ&LbG2oz`0BCdVbyvo`b11fW_gDi~ zCAyrBhK{~(T??}m#0pcJU)(LLuLK`jhwIs+MA7Hy$KMjf;ntfy= zxYE|y=#WNrTd}0aY23(d1Nc3GdpI@+gGm0EO~<^iqFE<=7+aV_|RaC(`xs z(?)#do!Sg^j|DskW!7{%=ml=$8NBNOYJbf>741I=wB6SgfIv4b4%xy8y%Oke6nkA1 zrw2FSKLhguiJ9#MGv4a9NMf-J!ws z+UhrOs&rLV5nW(Z?@*h}B|i6e%F=$1|L(2CaBaly_CD6>Y#TeL?1%W6`w7id(cuxu zSqDMMVJ~xUL(Z7%P9CZPOKh5N)MnEtcl4Ygj|o7+Eu8eR0;85jVDGdIMHdUFaef^F z{J;i1Jp9PVq7RWVgWeJ)g*(2p<}cs)EZ#&e2OWN5E+4W2xsk&WArX~-UMg02nV7D? zaP7!$Q>&1BDUT{QsdcN#5)j%1Ke!uE>VlqQ7=O|xz&~o>du_sZg*!v!vkYJ7)Y1(% z9VIz!wMp==9QEm26Q`?=G)@YYxEBZSxL&x0~pNq$xza;{8nhOyW z$GRv1u+vJGf(R9t)O4xjQv8ugyDNyVFu*%0)B}O zezf70#@1w=^E?;-!ajp_N9=as#1EWp3OE9-5f(7pXQQ@|p~ycObe7i^cf`aL3xtVM zE0p9)?~IO+kxi9T9ZgO@%Qn0V;!Li5E7WQ(gqSO$4PIXIhm=9b7SWG@whm!euJ%WA z0IRU-u#sO1qfNKAM3k(|AE-C~h)7EhH!;SNVP+*yX02Ndy1cJlU|}h5=*V`BvNVnJ z=FjXW7jyA8aS9P79hNV{b%d59xqgssI$NrnRkiwj* zvY~Kr!KuZ0@IAjf6>dv(9L*SwJ?5gyjXArJ-rBsQ+q(cOHr5)7H_KG=HL?n%VsYVt zx+=!%`Vi@AkFZ}>)f7}d5+YHN20nh?!g=He89R+{B;`7BZxxAr0`&E{`K!L>^l|y% zNG{Y{boKk!x9>_GH=E_UGc^&2uo(QbdM;i&k;wVyz&oF|pLmdkfnV(T7DsF&F$upB z!n?~fkF(UtmN@OD-p{7jf5wV&$SI5WUacf;qcTl|h{w)VG3ZMLmlByh?CP(het zrxCY}Uk`vQ#fo>#!ST-JZb8(P=@V92bU7%4m$}UVSjAnJHSY&?!d$qXxur3L-1Dzf z4eN6yk{~-mqKwb;SCW|+}=a~0B$Q*I4)u@h`0N?mPB~+>+V81A-RLEz0%v(XFv@@wthn&_|V1RV& zTS9`+)oOy$v{_SVjsybTEzmf*k#paP z1Mb>w7jV~GD!<+JBx^^xc0(;{3JymI%})B!8FOdV& ziw+HIK6enVdr3uy>@7oZrZZh?HqeEUw}~H>Kd~XIy0a2CJVu-zM1($ z`lr4^ZI;-LA1Q6@il;fjLJwr~E?!2nnW=}m>S)-xmd>=Wx$ZQ?Z{sZ@@oK#L#AyS- zzQx=RXNK10%dZQU{=n*08fHUf-OB5hx~|WW)o}?o#o7ubflW>GmNL_Gv2vLF{+T`u z2k(id*%FEEF&b~_hLyh**&WOCEgvK!q1`4AY+3ftODJ0(M0J=WZ)$Zu zJH*y|_@mIMDCQ%%;`NK`au;7$Z=Lq`s+&aAZl*f}lJ3RscKq57tl-65=tqkqwJp%k zD}s9xV~oD$V~j+T9}&X$XvX@>(*Jn+_f*?-$gQQbONw{?;km9CyZLAjzq0hB?m6y0 zu3U$7-$tO`n^8sZGcM$#&x592KAr{>jRkce@@9wZJ>@OKbZgf(92>0)G)TSNo_kug%$L1T`BVOt$G+qP-}|& z!`;%6HFZk*noLm*oJxVHLtceod=Fan%3L)Vy$w$(4jUW|FANs5;mfJ>HUq=2kk4<9 zcca+uZGR~)(JmqnPf5%V#9+HqoI!7^B^d;lFd0?p87PAu3N+7*Y@f z@$3B4ue+^KI=Z#p;ncy7X3cJ|%1+z0N~Ub*4E7ySi*qilBfd+B`h=BXJ*w&v=RSVq z;<=fVc1CN3(Sy)lJN=(}zyr&A56*g=$LK=4R2aw|TFvxcjr9W11eRYq@kedpC4Ln3 z35gdaXw4JH;bRM>+t#=Nhr?cJhKjb^> zm3%w=Osq@2saj)29PvC}!Mh;{vG8R+_*o5oFrl*%F0@{D5D0!ENE9p&8S1P@5d;2{ zw9Wo2kMtQ~aVyvS#6hTkJ#xb-)N~(6Pru@q$IzprP)}rEr!0{m(l7=HN%5C=t4~60 zIV^1+`Fv1H9Ga$}l=+AVisnbupcE8z96r;egz2nM(;XN?1b?)IUlt^dUcmasGNb3QIMbeF1uf1uF~@Q`Sqoa_s7Wvt z5Ro@hG{r!Hyoaf>n4MXT4um=3=FEtncEUdy4|2i8pAa{1i*ZpEoO6EN%Sn){CISH7 zQs(nGI3PsC%!wf`M0wd_LJhA)s$IU%qhwi)ou16k(@<1{op|S*G(CUpDUHDFj5zVm zJ!v|rZy07GWG5@hv|m8Va-Q=w50=Cj%=hTv&lmf90v=Oa!E(jgehDNFnrSUSe1;np zI!p2Rj@mqOXB)^|E_bi{Pl{oQN4<0!KcYX7HBXLaZC~fHW(}2)PZ5@naB;KW^ORS3 zMr)5;ZZ6HQI!jqoE(#L*zkPE3L8lF;OU4cuTA^%S?ushPHCaH z*)7On)-Xq_^RQ8WTvpY26K;4;EjxwWx$3Y{d!#@ml&dDC!|H|2ZyqOwWrMD zM@W3RDY>WmW^)9(uKHwxYOaQ}ZKRW^`4wCY2J7JxN3zn&u6Ops1*cEk1PF68HVpR6 zrr(X>q1gjQdK4n)9d+HOv4X(6ze9I(icMA}%H%jg_!R76j%%tpP`rqS)rFxY7+|fp z&R<|=MVN5NAj=VS)`+gmQzd)?T({bb08i<0=&}urr8sDBJ6@moy8g)!=vs3Y`@_x% z^N9*bzDKfN$149hu~%&DJrHGHfw3Iw#oa6O8&4ROe&~#Hsd)4V2x;GO z6+Wvzle>>IGcr~RE28KRnLyLbJ=}6YdtVw-KIYgWH>uCl^g`D`>(W?m{+b=kUkWl* z%8y;Z$5uT#O*i;@YPs1<8+J(WejfkCQkde+evHdaVaTW9+XE-=Ss3|HhuH?Z9@uAn zb+b$w`mgA+=`5FR`k@BdE{y%>Y3`$y4xlQRm~FPNuG=emo#54VcYynVm;d3qv&_jY zrSvoX8DCxZBH+63Fag)SwCk6l^&i)*Pw3<9i&#g@h{+zht-_lvB%8PM7WRQ3RcX=U zqbnEw#zDac{Hbs|?I7<9go%mg8<2DfvCW``8jUw**Y3UP_1|1SKKDYy>^zPJ(VZe( zLteh3ZgBv0OW&ikz@g;PbNDe=3c|w)vq!MSF)#`W`!Uy$jFp4G3A0C~Bg#$fIYc&A z57M{L5m8C!YuA{ChW}-HhS9evjzc)8fX~O)>s2qXsML+U&hVk#lkN1|*Dq$IwOtZz zXSK;b@6!vS@xsY=p?Rt5dZAA~ND|isY6~&Gt8zi_Ob~qx`#77&Wnr~6oz&Q_=Z4>! zXuI4N7*Z(Ys(0RYD%Ikp)qAWv-Aj!K;S^ ze1MTgI}Rv{5?P*BAJy^m_b)1pugomc-(^FU>McJimvtlq)?}Gv2Eg{s#H*#oM6Xj0 z%qps#qgrqN<%saio(WbJ)rRF+s(;nI-g^U&B161Y>Fv=e5bG&`(MsV=GWhYR;g ze|6#dD}W2v+?uOTBH!SYYITgMPr{i^EV@fT1xuk)m6W2v!21I5Z?;X-vY?ov&8)!k z-@Z}5NLZzW15K)T(&yE6+xj4L8fv+spm|W25PwXoK z$T8s(DG`9N3I9utMU3so_P?6HSJ4NkO$?yMsOcXtegoDLQ_93rPzx)X-4qu2lx<`w zVxHFuN7(C()|Jnhi~VJA1>g>@wFRq4I0ID;>e!q1&@3<%Bq~6lS3RrirB-Xai{_|E zIIBqV|JaZK8^J2DuTcPQuiEaQ5h+v=Zc*Jb*OO`eyXk&q+v%zb@8+rgK^C30E7+5Y z_WxtLodDAgbUp#nz! zcgKE}v;QFBU(_SCQ^6p}XiTPykc?m5^WTu}|Ao|!EBY@t{#v5ctTK%=l+Nf6Q)3#D zYAH~l(HQp?L+k!mu>GH|ZAqZ=ANCEPYXI|70E(6DAGFgMFuaWge=%yJV5f%HBP*Qy z!;J$CgZ2+938?E)NJ*bpcxp?1nHtBfZ2ZdACH}YUO#p9eP?qvn{_@fPW4eJ3{6D(- zZ(dXLw-W{^{AY}NDRBa-`q%0JnpG1xPya2peTGIsq~JLD&UAWU=e5*;u2iylrw?6 z5)Tw@{taMR4;2yNrLa%jfbM9{4|IY|I(DR2-1ku@s&oTL~0PIx-_r>rY7lsXx`CMDg1%g1AG1Se@pa==KtZ=|CYX3YVe<|H>xcu zx=7mP7#OI3MWcB4Kc@Td%DTYtf5xcuD_K8u|GVi1WH!Kxk^W2Z;sdAuZ*2R2kT|wf z{1G6AgNguF{FfkqEe)t@sC4S#zr?V3D&uZ`#b0NPU8CIdbq;SFRn(Ozpdo*EV)%-x z%R)FTl8eYfSb$kfSv$O_?cW;RYPM)w$QJPgxIF#g!bj8(ffyh0MNT@0+BE+RJTO`) zg+KJ#(6_&%fH0=K2KjiMXE@*fYkFin0Op6+LBaE97?9VA<+V>u4l4e$sioWI1!(>^ zu>H3|=>eE!51{D3vu(gE|7!#RW*!(`e`njkY(x6b*#yXaaw3fHR5q&yWK^t^fA&}S)8e9TEdA9|h=kvB&8ke*OP4Jd5^ zmmtb^ZrlvY{shXk;wWZjB^SJvO}f0|BtbZcV9LxoY=6_y2Z7>BH71iE$qAIia4Co* zNx!4`y_CB!wNcjmF=}pEJ_Mh@r{`7MCeIdP zEYM#Bk|v;MoX02-Lb^qkA2mveZ(ZW7dlJU2D3JY4amQ3%)_(swQbK>{%>0ZSN%?Dw z@7F~?vYu}9SS($ohI*AA@1pMKlWXTXjV>QeYtsswHZP6S*?Vg?sRAHO-sLYscfoX% z+k>QWo>tkRrV)KklVAqQ=O=q=jSfD92a3qyh{3J(ewykKX3Y-yZa0|u?cykt`_tRu zrUQMitGPcS)4@6&&1Sa0fWQ}aL!`4XD|SM`^qxe>yg38yp=-7UC8`b*Iw5o0T(Rm1kCdid0s_h=yxhAjeWstK+u!`m6v?zFR74(?|aZ7PUGLy-vX1 zwNyG`xaq20&{w*N7F8aL`a4}cSf31LC?ZPXo@n6Q2N*ifqWNH)LTDg3)!ITo zxizT@$`&id4yf2(iR10Da(quK^4XJYcP2;1^q#eCnagk$!6Y_3LNX zvqU_u)a~9uH^~xi`^?Yr<@-&Q-Succh&EUyNbn@WqxCPje&wdpLfECJKaX#o*J@&t z(hCa<#Af|0ePC>kB6c~&quk95PEfAczvvt9x5)c@idHm)^OyY zh+-_6Y6u15>o~3q9EFvVi_W?C%6s0hD!K(Rh`e9+65jRI$?G>t;jt876m-7rW;)+l z!SvkcQ;EKz$JrJ`&od0G!aFVM@9mBX<+;B7oVoDCn;u9IbEUEdUER@!B>4fFnJCE| z;^*`zOq`u%5HqDI#7{_;fcm&H)DUkw_Pac$OQ_FeSW!83J^d|@6xc|j5?)*qR8F;I z*icYU&V-z`6-RMwQQx@q7l|)-&}TMh6Iz&&u;A*-IH8cx?R?{e1hx9X5tjzr12x0WYXh?C%)tK)kPIyu z0sGg)DZ+W&E-?^y5ctBokZ9bRX-XUkQy$cl@#YE>F;3DlB(nDXVkS)?gM*h%F*GK4 zVQJJiNAHDqMzK@FqKs+$szsNQp>W=gEpvWc)Y^~9HUegq_kxn{d9x2!&e`i2j&Ue>4pZoHy6t$^32TO%gYSUanzC@8c&w)x$ zBq}cDTUku0=m2PL9-(1*I^x&@YjqMWX|s?rOU=m2>aa-tE^37a;@BdqZ3Zp2r-#2Q z)6dmxpR0E?L}!@HSlR2<oV?@YgqXll+W+-pCKPi<=YAFq@CV>hJA7tM+5l=pB7g z93l^4`Zz>RLW-@0Y*rg}LSn|CGB?zBwme0-KS{e_QuwK1xqM@8zmtB*XTp%$N0xN1 z>}u^>obLTYGeD1ykr!1__AhQ%>1n4l);B6 zo50L<-gKKqzBZ=UTB|%G3tCAnUf{XM<(Wnmf#^e1QTM(%hHFIf! z=p1U75!E~N&A5kU@Wk-*vXA-!&6i zZW~~b!f3t~MR8XFF**WKt_f6p+H7c}2g}_(`^N8`R%Ks3C&vL3sY*-;#uUhp>>tiR z8TM0VF5vxC^9Xsres7}L+ChRrt$i5v7ELZBSlY}gN$q(E(@E%fMiK8-TP?>FiDS3b zBwhp|xp9WUhnMu`eb9huB>xtrDLBwJB{@NqWnz@uBMoBy+an1WFD{6;>o7^XRIsA% zX#4g!5d~NjW{1XaH^};fLGZy56Lt&W9mOf+At}iU5P%oTf4xuyUId0xLh$>_UCAGx z{?cda4W# zP1wWur}WNwJ~(R8wvn>La}Of{Z>yqIX7WxvLa7vmhb+TQ5So(2(2@<;(6n2rK#jd3 z(C(@w`I#0|h^$alKfH^OMY%Se?mBWEBCw8)++ek{jCuFLTC81itSHrnjrmAuiK0(6Lm0Dj-xC*|I11g{|;Dh(`uUpWnGdmc&sR zIMtOwTA%NcDw&1b9h6?q^(#k0oVsj^F6*4yLgPsat4WBw*HJf9uFqf|B5P$D_SX{Y z>9USmu@Plxd!K$&6dRN!wcKR5IuGapG1~*%*wv*s)yKSb>ew_s+7k_~tUA=;2H(p6FXw zEM#3(;Y7Xtm9*38;#x2Bq9-w|$}^IKt%Q$Ezx}tm7Hqh0R&ryEaVi|a&MwEJ~5)j*0+yeToM&|8s) zP(?3(Ohi!w4r3LEs%1EAErK_3Cdfs1ewAdEtIl8OO=18FVqN4 zc)zDoN6`sL1{x2%(!gw9N|M-0J2V4V@y!=Sz3up2VE1ePfOx@CanMd4M9tez%Ws{= z^mtL^Wozpd_&p0@Y$8rf+`jxp6EH&SHDDK z1BVw}PfF6MQOgQ~$QvwtlN}JBb{-d7>6k#&ZCpbSNm>@P?XLIJb>NNkhME5*jZE(V z*d~;`bT1JkN7p1&>zfI=UUR`PL_FEvP0m$P4_Zt`MhwsQgP$2yGB(FD14c@IoX9wR zchj&T@%fmC&to;_dr6sQO+J7MoFQ_u7YEf@&V*jDW+nRB$mEQGaOzjP56y(xhD77S zq8B-&DAy~P?H&cmxA#Vx;@!Zz*Oi3H-_dkc$z{91LA{_QW2KHxR0Iv@PQZsF=Z;2g z?c#oo7gou&UT6RO#wnutY5*?#`W#AVHl?mkD@0^N!c|i8!ZFZc86sPE2rAR{K0US+ z(BExN1^HpLK)sjlozw8c%-of_V=RbCM`|4Nm1E|V;QZPXW;P;s+}3L`KIC_fOGen@ z$!(yx)H!$+l?RhV?@({!&;>ve4y%>FHr`eIF($tco?cl}-hy*bZNWMkd`?Uk*m??51k1W`1ddZ(^B=#2+406~qJOT~rm^ zCNv|jBE_cB=ZZN)ltkPatSSr>>w#{-Xv<4#4~}`hXjVktq2@fo8uOks=opuIZ9xX~ zQ5khFtyIn}dS3WYWUqR?vKbXz1;qxVHMH)RVN)q5x_RrS^ykaib@_lQ705BS*hLZU zmh31f99L!O=ZGqfBrcek>rGOOPf!7RPWa}W!G>&yZ_X@G>QhxgTGz0rpDvpC+}`iW z$+37Vc5p*qrkbUMu%T`_O13=4LED%5ruPZ{04JloOudP4ejiBhQd`=$Z>>_Qu8zsL z^b;y#ob~}U`##?gITzPMBMq5@$ARNYWmEIw@<&DHgqkw_8#>#7uSJVX^ro?&yPz_7 zth{mN#;T_Dy*h5{Amz1g4aC&ck1EVg(fP4s>j;!5!I_bXeNl$mieNQ9dM4)jYA$FLkkT_mugjI9ZZAR*C0wS_O zs-AC(^;Bjp(BDhPNf%_eSxrG*92WWs0}B$0?^YFd zpGbm^oc2*)F2NfONJ8D(hJE&1X<_3LCK5D6CKnG&Mu@wv!B^xDSVklJ85fH{CqrdJ zao@}eFJ1O=$S7gA@eR7+yG}Oj>bic0A|WOMbe#K%TDCZ1>~S)kGcyB<>yYkiV#3y6 zZ~J757$j~9H1+diNDUbI+VditFjzLR4rKncw~VIRt4F#^+_ zy&SgRGzpx~!+o(AsnbB;pba%vylv^KWB1{1J#Xn!8L|AC*)mk-%E!0@{W79pds@8x z%gggZi2gz)2=bRs!_JGG2d)@ll>BEBn)d^jn-A_Y30p_{xmK<(o($~xNAi@cJNvJU zUPTr+`O&@fQ1jzAJl1@4&398H&h={NZAk(1<=)uxCVe#@B2=c|?&yBCW?k>7_oCF? zqA9BM3EAGE5g*rH8sOJq3K&6-=9J63ZdcfzOmrc(!j8sE_RMneQKo(w(34|!BczuRuUAL?S3KK zlg~?XnB(Bq+a93RjJ)Ic-qd?)VM8+b#2~et`8ZY@rZfIhmanvL(YS*`hhm!+%<-hB zje){BBGPI6OF!PK^jtTs=VTp28y)G&q{&i`Pk~ZiSyJt==eksG%qn%0{!vZP0pPLvG(J2{hJAQ6&YT__At)_DNDN@Ta#?qQ=+Al+ji z+Z`tVn}Yi#yr9Y_Qxt=JCMJ!1F`^9~+T}6cx_o%H)6I^w&ZuaW-S|~1zeuGYo}aDe z$6OiRKYsSO&_+)8QDh{?eN$McVK5~IfkH`Vra$N?wZ8RfBfDsoHQD&?!~oTs(_j z?*JX&mrhxg$e)H>l`MG`5z!M-bp6<>54AywMjdxBvO)@k#;DtXO@D+?2;I$M*AspgjWmyVSl4O0_<-Ra^w{Oqd)9#jC`}~pfc2~ z#GuBg+xfM8N4{~9U9R4V*3prAXOLN{g3z>ckUV`nA#zkntM6GD)pSWFh$hFz-PD4H z2QHqE;x%-Kn**U$pM%r2p;-?hs@6I|v7?X4wO`Q|TMRh)Z3ap&1CpgV{3es(nsx8G337Nv$3+J6y9q?; zR(TW4M{zhC++|=d&N6I0SgG~CiZQjuX8oq+I32hrZb-yKp!nEXTnXY2EACegKL#FA zWzr5_Zt$u!7Z9+WY{{12S_T3-^w97jPiT@>MBZGH%`J(gDt=Q4Dp=N%>SVM6#Nq+g z(Y`Bw*Nc~5n*lrg@(KAzQA>XR^j^eK&)nl%nd_Sl&Dqnra2}lcITSQ7fp;`)>1px1(}c# zR-gNjKT+6;eME$NRdRb6BQFs-senoGcE1aI7~U0d`Y0=oPqoV$#u+#Kn{*z_75ot@28a3fA_9tNP3DEvC1yq(yD?N8>FF@U ztW$6ZHU;-X$#9WaI9*f@~iST{eDvGY(!+yy9LTh2rDjv&xQMbqSq&R*SAu* zqGG1oB>j>S82&%+uhuaLrGV-6tu%elKGSDzdH6A6lf#L3W)r6 zR;q`dfvy*kj~M0rwq$bW#4ocF1Q!=@{_QXV){%-^{64c_#>jQPMB7CAWirkw<7X{x zjn$EeW@VyX?nSDR&z*QzznZA~MArueDt+wALj=VBp-9?HWHrC`Nd&~Wx%p&{jC2zS zyntmTmEh9c51-Ax?8ECpOY4!q!iH}w3<*)q=4~t#kBYF=RvY`5+Am(+gKSL`iqP%* zTXUkj^+#L3?6wq$T{nT&Q$lwlas9B%4r8+WZGPZB-pC^b`8S6xx`014Fl|}dXOJ0$k z#Vqb&VxihzFAhq$34zfe-X(F$D#vghE4z9wrHON@%ZPaUlPkl_#R;;gKJSo)4F)R` zzMqNGFf@!QCM+LPKv^J8ILo4_&kR@Li@0KCm@H$YsEr5_Lzxm19D6-Zo0(A}v6vGkLcBC{t<%*E*u@O|kSG zS`aA>UgE?*MoNE1N}RxW$Mx8la%m>`)D}BPpE9uuaBcuV@dW|3p6^h113wB zs~Y-?W*jC~sBxCB(qSrGBqg<8KD>BD)PO-D3olLCTbRT_>+A!u*s%SQwOyMTKm2FC zV{3knTI!5k(dOVtG-7*0zhJuwbbScDQ{m5g{$3l@0hM&s2N(h8qNJ-iCFYDK0hujRLOdw9}gc_uEKlIS7oe9g;7q_*5fLD*I&~-FTc-VtyEs`FW6Da#!%jy zXI5zoLK@PC)RmNSH+k?u$RxIIR#KwRBPilgL`dc^LI0$ZCp0pta2Qx+GByI4w@#Pv z%YfB*gO>%i%dV;g5a1TW!R9itG0W$r!Dq9}MWhjszMkR+nBPuB@{=GUD}Ht;T$~Oe zSMDtYCw#O=5-wpd&9>=VVH;*Ac%y?4kg~VNDk-YP7 z*sA(DScA*7ur{Kk26FZ%zA2U9mXc8HkZFK^)UAt#vv^~)yyOH9S zcs+Y|+d-Bm0B$hlQ6SN-eZxYe6DHEjtH)sBa145*oKQ@qH`Av+L@cfTH9M2fOofS0 z4P0q2u;~DQaNhkuwA}VxX5z5So0D2W;<{X(5YcgJO6GGZn5GvAa{xZm+zZm zSiGbBDXt*2JXhvKg?GUmYTm^Nwun^MMr9N?X~n2yZW z7;pBDO}#YPb8=mQAd!RYD961g-|cE~C%hO+p$hMA14(-(p%9i0<^y$R_;jSY9%Um;uOY9qyK*Kdpj;UVJ)|~pppM` zsIL)*v67Q<;&3rqX2P!s`!dwF*$wal>-Hs;SaF;P$+CjD*?cn*c2sXQvX{dHs*MtS z3#SxYZH%= zRWlFT{d0N81Kuhb9%c&Wmub~uV4otwzZ~sCQt-$`n$7c)3)L9eAcG*}g*{<2@oBTN zEa-$=BAZh=u%Zq_IB7ky9~^x@Dwd5(c&}A-s~bwcf;5ZOX>sP|AConfC} z!;Ww>X)rZ0;l)AVF{}!)2yCN4-Y!=l=#u1?PZ4}SF|_KJu`r1)5J@dOX&805ex5gC zGDG8KLTYbaCZb)H9BscBVggn7A@Pru?kUrN#TBk?PH0X68DIJFT~i(wa-!{5??l5( zyXdSLn*anYOJ=JwhRDaVIG^ZF5ln+cDO|^Cxqkw-INPcACkA5+{cER3L^9{3}Ep0{P93jv-V6OUtXbUbEnA zjMaYB2DRN)W1)5g=&U50QZanc4>a=Gyvd{1k~)je*RYlhZDU8llCSf3;8ZdYqbZH* zJu@gu{Ln}@y*FX*b z^QkD%N7U;?u!p#P9UV8#0V4+5{#k@1zcVYpm~AHjmLi7GdptBafRgCg&!vYZclS%z z+%lTPG_yuVh|qT)_sU`TEy3s}&-f4i&L&uL=U}0!l@1YDsB))ZRw|v@%(|ws)#>0Z zMUi^eY%TrJJ)#OxG`j{3KVOBuP9epCz)}T-kjL!H8#!wYC|+M5#TP%;oDJ_nV4p@m zT@oBIax~(iXb*-=BQ)ytK?PDW8(||P$#1)Tu0db0c4*15Zr&KOLiE&5c=+a?=(N9D z?J2CoL=%uKHO{9pARNN*8^>!uNo7(f7%_W3BHo#`uM1+$E`=E{O0-ewtuHg^aLw|w zl*^IgDhQOk^S(rBcBA-5+iM#dfu&exb~c(+V#}#){A^>G{OL{CmhbS}e0S2~s?87j zI>%w0)em38QM$q+08ZxbO*N!lzR?A_JTVl8x^d6h-s>&i!$I>;r z=3KhH#M!L8@|qoyMoZ_vD3(bYe;2^X2!)2_Fx|Q=V04JKpu}VIE2H@^r2r-se+f!ZhD!KH})iz+J%Yr>M|~dqbn&)5+G&r zPpgGN8;1Zym)=ZZN*!{pd?g;NII5tPIjg@zsL(=#HZ_4N^O}HzMh!{OIbK(sB=XlBRd`(09_ZmmE>z zrV|@c=ho@p5PY17o;&;DFlt!zJZe)VcEpRYrsPe?EfBcyfYVyyR>1`obM+0aFSxd$ zA?ju>Q(B#>l*tDI`nyia&0ZJyRn$!Nb7@)j%u{XEX)t!~R_pQj(^|q3XEb6>f=~W% z>B~ko7XOC$*Z!x|tLZI^XZ^1fMoP*U^+b$vM$YBh`o5G*Fwxy-y@yzK@4zVBlx;31=xQhLoXH3)VEfwZ?fJ2zp})fUv`UoQTxE(+2sGKk`&0BpEMaH_=pV z$+D~U3;788lX^P7pvf`j#q`5`WE7}NGfs4+b5tX@zUdK6j3AA#!bo1_8wzgVw&yP* zTw<3qOmkBQn~`sd(>{L+M(dOqA{imz7UsB+n!3VqaeIZw2-cW*#K(NKKf^pNYKk)K z<%qb{+s8F5p)O`&4Hroh$MRl!QjCZ)Y;cT@oR&e@z33b`JuIru$QnFDK4ILRi!&it zfHXAj402_mB?*y4i%PyB+P447+F0qzku3a~it~PPoA5OM zFP$(~EhQw{b6i=pxe!U@CASfa2KV;dX&=Vq3rW6CBB6nCNPMT3Moi8D#~!9FWmtK- zdJ&IyITty{TVJ_Y^ft?HhTI z8hS5_Vi4LDd~{7W!e#nQ)8-vjN0vQFpRqu+@OI&$C2yPTO7-evfJSekpIKjW@Vw1V#`yct}Nh`o{RRWmm!i3+8qy6dx1v{t*brtu?wim)9hM?AC8BJtNCnPdQvuZ*zd%Ic4wpKUw z&Shpam_D?Hn4EzS+QP^QCNsBalT^R97fnW((%JJK8L7DG+{!jAm|q}mbPQJL%C2dk zqJL8QfZPzuK|_!nd-}aYR4CsxHwc64^G8T9!N7R=xljwG(-emDNLNap zQ|A(uAJ~{Y&+>?fB^q|u)vP?H#@=i{W>bIGg>vvb+mJuU3|vm%OOnG#d3eUAF+oLk z8Ho7>i}1CZ8n=u5%Fp}>TL*la`&7^_G8_H*mK!uL=*Kq6Gj9S^lZg#(``4yL_!<b@njDKlw^wipuBo-+$>-5wrsB7An8M z4%;%63FvsoX~C(tf-}$rAL}#GK)mLrU_iQiO(1JGSt|&1+jun_P*$wI|H}$YWx@Vm*_8t zxSG-pqGU}pjP`Kq1L#=5L4^9reT4guaE+A2)8wX~+A=lcAYN;<=LQQE^R%#;`r+Y* zqu9-(z=`LCkf~a!m3n?6R!Y^+y^JZ0t$L8%NE@JRwQ)0zz)`hvU8dlhV>1nTB8}yF zM}|={=u^Gs@(`JNu_ij(49cgGI999pIotA-;OT}%+Q@F*h%04A>s7eSTTA~hMrw7t zhFz{n{q7o8i7%(msYV@ct8^~cG=ACMD+aLC*DBlq@p+9sQ9+iXeim-0MMMa9zIu&lidm%)U>1p&u%K%x;sec4V7dh@^glBJ`m| zaST5#HG1ycsr4j7ymrcEV;Kr+nYZVgL*3a9Mg2p0mWqcZc_RF^Q3IDA%|06su_CAG z4$j&GK@+$0SlQ&W{8{1dcp32nmc%l?Tt?wo6FbiR%l7WFNekE_~Wn4W) zuu2c)v3cS7ZrBP#|E>fTllM1jCIVS0xO7t*se|y~iw7IegO($OlHt~lOT_)_P8ZK2 zyAa^(B}DG>DBF_z?}6khWcho$829*wu36J=pbi8;LxjRuJ4^v ze00a23vK{a>*TF9URVoe`Hi`(J>)w>WYL}D<+r{--PA7Z@T`ILX?`2^l{=2$LO72W zBJ0aAX7sNszoQ^4gw!n4HM^zp^dvfjhKjywom9({FojxjZKQ&bT|%QRi2Ad}fI(%a zb$MpH%S!j`@j`ygx+UYi)WvLPJ)F2o8r*uxj`T>fT=570u0Sm$BWR(5` zJ!X}1JT#P6M{ukWvo0gmu7S|+#M}@DjRh0@vk;K-3(Mh)v017%;O^unVvtKvIW&;F z(`gA)r$i?knKnyA2P%gaj-j;}F_q;NybUEITYHm+mG*P8%k9>+GuMPn!HqCso-*@5 za9kmRWO=C22Q7f;JWZTo2X{p_&>?Yz5YP4Ai!rS)Y68Lv2f{-$h_n6k#Z?&Amt_;+ zIh*Ny2ui!pHG4$-g+5p&^oSU|E54Mlc$k`?j=Jwu1T_#e&&ESqhNW{-3}#29z}(p; z75_3OUUe%Z4v(6jDqw*&Qlw%pV}T}C_&hJJjnW$m^Ol(A-fX(jx)i^c* zyHsF3LE`|WsD!dx+=6XLOoCQEF{2)tl|-SzOqio=X|kw9)LueTvCvM+?EZ=*HOQpX z3sY>i7wH4zDZg@%ik1)!iiS3auZ4tJou*Kv_9u;tq*;TOAoQLOLXo<_Eti;&(K^g$ z3A0hD0M!{A6O54Ttu$h`9=D{Fu<^{ev2ov`Caz1|42QO?UhHFZhuvVpY&pi zLduUa%X4&+X7w>9b0M;_W~s_^ixitE8J6(yARL4&$ssNzfQImb5j{$V@&iTwN80rm zKri3i0psHonQPMQ;JzjeoRTs86q#qzY|!|~2bs`=grt&zy_7|*KMj8@D|2GeRl_uk z_1JMuAPmNsR4N7`4L)cjU`y?*nds0NOr!BM5tg}{M-Xs)czWQ^M;UpWMl|0`rW=fz zzRfbY&*$14CO4MDk68Q6!||IlYOq1H*TO~CIcOfrzL!~Wts=+fA+LlTr`U3_rZsR|a{YiAxns}HAagA{U6fuc zlnLdkN#dpUlIJ0zI;3yP_TxSZKa6e8zSk!#DZ3QdzFL=!)+zP+)jXiHPT81!rF<~j z489=jY8{GqYq#vOdaCMbUAkX;sg%`>>mgVb*c`YeAIC zFz2x5h8MFAm35_ApMETqWk20I`Xpv7INfaTM}+AL*YttxRbNQ--8 zpHoDS-Ltx{+!@QXfDkN7Bq$9+*j7(r#L|vB<%o@!$MfEswLf1arK<@!K%QsIiVZv~ zJ;DA1<3`~PiFq;zQMLywxL|B&1mnRq7peRS;&whorR>(6Z#e~-?r4qUicJvfFE|?y zyAn=3SJ6)jYX{RohywWT8G(8}6?8TCk*00HO`D{UK;58#i1;4-EwVsvkbKT1DSahK zJS0Vh-VcnPQsi&WWHZ|v(!@}~z%{hz!JPG@HS>}fE^!rFk)6a#LX}80k|% z4LUsFvS!f29gBtj`Z|{qRq;)byl|HpvDhI)^>P-`7_%g{`kO46va4H+9-fOe6ZrKH zr{`kE1PX_6VS8MZ%Nkx=x3MS^TLlet1p2O}C+AQhbYhL0-~0vrL%k05!`JkaIWUG4;7{W#up z5T_ky3TY}Nx?}&&{h1)>TIv&@r+zMNT+5s0XM#CrwTxRr2P^{VZAK8FE&>AT2S-#( z0wV__@FEXfi`8PHV#}rRDzjK;W8l$O@q%f)G)#y>$kXf2guDV=? z73)nns+V#CG-pvmb{gmAsUdV4k;k8024xYBDgD(EEE~V?)TwrsXzG*ft|tFjDqEXW zxLuk#g1MI)PzZU+R#wjqDAvROx0P-EKUTK-0W0ihIjO}g-&54bwH%U)2h&mj!rvc$V)TE=oDpzaWD%K|vYg743-J7e8XVXE} zK)4Jk{4od+1vwUq!9v?nThp0S9R3hc$!VMww5d3H=!(ZQj3_HAzozUru+{%BhO+=Z zUGGOJO6M{|7owo!m0}k44ui5;z-0SEv5;xI(#ap*mm@$}ZP82tgP>Cb>W#dbtDOP; zBC|B5`3^9qw@wxEnYF2${!k9HGmDi9pbly4lGK+4)Fb$41{;ki#oCp^&J{wmvn9F5 z+mqHJSdbK;=t|}saV^mHARA$#hqOJbiK~cc%+PiPpl8rzB{qK6Ts20_0;Q|l7pR0> zHAGIND?R|yyC&0WFbh<46ACen5lAakaBmgmsPWuYL=L6OUjU6!K!X!tM2BiXwx(03 z1axlIqY~KlDIixX<4h?0Tc8aP08AcASA^mG%j9^Q3h0Nd+C_<`h!ZP~;Pm1{UKW$P zU#0q#uAXKEch~u46%FX>uG;|kdhG~fS<$gsk+Go`?8Q1K657QrgVC_1#Zg<>Mt zcBMn0B=2;M6s5Z4axvYI0>Ym<&Oo64@Q!8GB#Wh-oeU|JDXD-^D=DkRJ5xGBKEtF? zwcxky14QZ8g<>jT*vBEAD6=!eX^i(wDWrnEjzs^bFKEGZXn0NdZ4N%#lIp?rbjH;J z?<{}D;qSVfhLpzu*WIpP0Y>{wJS72W2aAB)5Nnc#^jzUz(*l6b_%CNlndNG=GqCog z>8Y%`Bu8x+Bo2MbU^-_KschX;1(p0tsdVaDet0RMcYl2T3m&j13S8`t|A_!<`=ULK zvU91FG5`f-AOuUpQp&i0IJDJjFt;v1o!4GSDP_6xzsmqB*?`JFkeftT+*k;- zTO|%oXuNBXp$?$^Kjr~QF8zB_{0F;~dytYYe>!GDJue`RCHV*F3!?FxO{s@oXl_Eq;f?R8)=VQiC}-A6qfiiRhKqT6^ivNg<)s))cSFt7(L&4 zRI$>wVyZJ`!}SwPO1YhSrds(G&MQb;YgP?J=LQBP$`1+8aJ>6=sl0GA9X0N9@F zKFAFz27=%W49V6%hor1yi4-mlk%+N4S;_2g&NzmWPL2mfbYlu6+-r&s{+ z#|FX>0u09 zSpP8;U)z)FQGveEfg7391g8J#)?WtyS7{(F^L0t%F{*$Wju0EyNA zEy)ZR{(FqGm4G%%|1N0?xbSzZb4jKuBo|NubDl}SWta(5z1$s09EnY%3czYlGh}LQ zPh4@2qcXd05l9}SQe*9l z#cKa>t<0(H;18yjc>XLv>sWuKl6n9E+7ZQn4}6kjDp$;(X#am1EmSK95}gGQ8x0_W zDF8}7 zlX=S$&lKwZO8{7hfyrXPYUAhfz(VwXOeLrEbxRFy6qgbTKantO zgEBxsAD~2|^q1S0SYb1K(f&YcU^XA>QbO{JNl{2a9>-*yj5fq*JWp@Dy_^7TEJ-!Q zU{>H8Wm_7Ypv}02aI^rEu~QOdp+kvuR{}FBiC_fqJ3t#9m(e>qp6p%z>^Sh-Q5o#) zT^sB}1+srmlUDEtcig+eS1g8i(0qbN#$2;=^St<%Eq|ihd=Tp8ht|>-Pz%KM>XFJ! z8d(X(ywii8h9a4$G@i#atE*Em?g8%RofZlsWaE1#u84Gpfpl#&M?J$}<@ncz({oZkh z=Jft$^^S^qC!rcnKc1;QW6At}+p~ya9=a+T4XtYj?=4yO+!TA)vNpT<<1j;|lnvA+ z0=fhOM6j}xLKV!1zMl!&sJH+fx?LZXfG$`VheQq76ajSTD$H;c@oM$&af~Usu1fc? zs*0q4=+IIO<&_5NyH8eyN0Q?b(Hg<#53mdt$~jJ&yH8q$DtF;K=Fu<>0jYXQ?lF4) z2My5~k0DTnCSSB;!ryy7lj4l?kQtWP+CVp|-a!f1A|-_IDP=6;{;FX=>pYDP{~mc{ z-Q>BWShz?s;cP}pWM`wZ{S6DKa-9fAJ`7a3o?vyQ%1}B|ii0p6Yn6##GKG2a=TIYD zLjHVHh(4?tror{9DPnD)Vc4s~5cR3HQ z7<&3n^Kc?)7*G@CTuk1`YT9cRXHLnOl4qukiXk`}6;EFp8HNr2>n~l^lOJiuvDgVs z@>_4$aIbF7LwL_}%7(mAAy0E(zF`_rhkBmc{h&Y4M|^v`G-2(LJIV_^@LGECr>?0E zOqc+L|3HfE&)diZc9@AxC=-F@?=2XeM`L6Wq`&hSI9iM9?4$h%RcK1{gW;-MA|&uD z%8qOT3@(jCh(D*;K1?K*-=I&cPpCnJ^BF zdLXB;*S`eQ%io!>q3x!1CJlo;h#09AyBDI?bxT zRVLx7ZGqppT@d8rD!Exycv>&F+Y$oocT#{sQGv$t z;a3*33<^|ILewSc*CPJkeV!YhcPT>#{UGSc!}@)FSBQ6^&@^iK1zu?!H|O?SY;~W| z;rSF~1mUVn2)Mk%NWW6VW)p+*2||B$_lJl@KT?W0Y}k%)B+*c6AjVZp4EwbC%U09uz3}8&c*)2Lrl#vSwELu6Zf_TrCMalHeU78Y^taP zL!wiKLX@@+yg1~ft_PZzzkdGoolEA{%xz3UE%FS}hk^B554**estR&Z<#7}a4b;Ul zB?+^vaaCmEqGH!_;&Nnr5VMoeGz*gfho)$17~ZHAKVX)Fzt>~&RD0%G|gv^EFSbxb-E3! z5xEPaPG_&p>?DfMeCc(Pq|$-uCNAnGC3Xs|>d%cp;b-KfLTaom6EjkXX`%9})L@Fz zGUGZv!;M{&7CDp5p98ly_?eLE@Dwm9?0gCn^1N@;kJ;VqJ{#u=9+cR6n^>e>8~XE+ z5~K`*hxA{LeeP`Y@og zI}1Fh9WU<~IqFYd;RfBUzI2qbgN1!=aIP$!?h9D%H@nRno{sDV3NSjy(oK2g6A(2V zx2ej~TGqq%q1@8i-*ShQ3pWZBM;m?WcSWcTm7UBww(}!U- zmIT4dEr95*K$(qdA|1sJN}dQW_yo~~)p-4!T?f5!u-`JZu_3G5r$Acx-Qe6#oEZLE zTw>H09J`de?S^Z|)kfVFInmaQO8qD|Q930=hMP``q2{-HTTWHZG3<4u+=O!drq|n5 zr0P45E)UHLtSv|NLN_ZG!t)@DU6FR!y+lC-MLpjH#uw-$t}9wx>h-l5k=-`PMKXkzy+y|Jd=kA zb<~7zf7H;p{Q;*oqMtu%*XA37coTAE&e&y;J1BqZ_t<7~ebiuc1{=+^4ddUAcu{0L-tVz*{dSjky6en(#GTAea({um(fWNaA z)V+9!Kj;m8{9V5xYawoIGnZfVLLZy)6DK>FZ6VLVx7l}&q}4}v>LsfXul`1 zJ^^GBZ8s6R^t6E}-s(4^dtCDE`@8{Of!7`U?Dm37+ctk^$<-q`E#|$``|atB?{CEC z_if**uJ?7Hy|?h9Tk@3U)J41+aUK&yvwrktal-8OLlDD{za8A}Z*T`a-sHR>F&fC` z@H$sW)_aJhXP_tF_GbDBp_i5FXKrJCd0vx#$BDx9BC?W|!sn=OCQ2hfez&6g%t9#R zdNuu2Zy7lyd2E|RdLK+Kfu0~9Es4j30f7%eC5b@?$?YX#3V)hGcF&>fQIiH5WGClI zQIGVb$)<*+aerjqoK8>CW`r-~+Hid70_xMcec3X@y#C4ejTPOu-Fx#5XYqGO8kmG$ zmxSWOwv6kxjj&bA?`SBp)7qfknXaFAo^BMwK0dy3ADr(%7;|<$k#Ii&_sTcX2yqjB zQLBPH6OQrFE!$Z~J>GYEugCqilz5Jmn}lg)XRzfg5}9AM-li9Svr4tILS19xab49jOCriVKy0@9w;#NrYMd0ZZt(ZEZB!x0b&2G`*Nf7c@b9+xB z?+q(LVt$K*AhU`}FwD0<@ii;2X_$PUx@!wbQNiL^^?6}V4|%0_vWCu;J?DK-cM?us zeB2cl1+D4o0i#hU=t)>?xZmBte;2PG59|+pUeVRB1|NI-8QbTJ?*PXBe$aFL@pX=|j0pQ0ynz*MI(Do$+=$(i6~)ew`c@DkQ+8wS&CSyp8ba_iZ|saC#Q{pRnP^5vsF2g%Wb1?kXX4yEC=O6D59 zg4SLc6B}azYN}^RRJaalD&dHaA?5eN`u?2ymDANory`?m@pip5Jn|h^QNz_G(GaPP zW7cF)op8gzEtC>{8daawNL-1vzxJtqX`xLY7m5l6z`%yJ(0Ys35*|Pi7}) zq_9>?50#gAzn*5l4Gx>BfMiA~RAnGBeSl6GOXneUg(QfNbOU?6%e38{Shz66jzmBn z=Y-Z{bAl zj@Rb@(*B%PYz)LxxP7N>b%<^ux5=MAsUVTu{#G6b=h5>~-6_&=w>~5E;#t0$3 z4gsxf2Da+P!Cfc>8f(t;ZOFIE->@_3M_1HMO_y)F@1^feY1Dx^ow<+!LRrewS!PY= zl}YBbrOCq51=bh(gw;D6iT1RSr6Zs5rEZM9nDPqwCVuij6*yT?j25TJZp~RzZU;0p|CsHQyRR^Q*2C>$Pz2N zGJoAL#eDe%-&M$dElZYy?#+1GW>(HOFkKIe8mP^l;DhSX7)ghFM;AE;gKoRc&wGtw zB?~)Y89RX(>8!Cg(e#+ZF=r#VY1U0#9EcpCZ=(qjFRO?Mo+bfDbl~*U{&{1%u$UaQ z)RX>+%;@X_41J(0^m2dYc*x@+^D)Cqra*45lpeABxm_a1SuDH9OC<6A$oUDaQrLGa z#K0l=rm279cf)2J*4IiqbCj6~`stsD&bjaMR`|Lmv_IZK<)y$OP(eUIK7bT|lTmq7 zR+Qj?0s-kj0s%n)-nDaN*EP2>chWVrv!XMrQnj|-7e)H5?PHRYot>I(fAAx;8r#R8^cZ%C zd;#uk85DC$<<7LwoMrD8R<6|zO6Pd<)MApdvD$>gkWc2G~(YK%~2IHq#>1{k$* zoL}-mh758{B4Tf&KxYV0?S-k*#?oRj1_NgtkeMOZk_3krX&^b5@ohYWTlE9V82knK zB;6pi@fhQoKG<7&B*?165l;zYg*8zz`jZ=ZvM3<)!k zec*e6=*{5yXlL49y>@p^FVB%F`DKlm`rDILj-Ao4VVS%UY-0|ljrGcN7}Zhog7d2< z54aOfkEth~(=%Nf1B3QXU5NHVaNjKMJ?{%C>VJy2klc73 zUHUfXF*CyWSs3Zd9f{m&>2OY+G(=~^b{~J!qqLrXp{fg85(BpDWksnMeNBgvX)Nlsw2);DdZGNPrN;Sw2^?mcMt1sA$N`T*$ zhaIjf57NcRw*RFv=bq51%pz%Y|3hVuQ_+jB7)EkMdGyzbEFI=Ow95NB!UcT{;*bS` zZh*?l@Yza56XbSVj4ei99prY#cCM8FgRI@`waeE#BXT!u*C|iG1(=I9*S=nESgRFy zaX1ZBpIXRb$}lgseogcSE~P}T;V&r)A4&8x{C5kHRXz;+3>oimb@Q>8{C+4G_MTu( zO|=7q{z1>Orwy~jEX#kh4$4OqNr)CgtufZ25-P9y3U}YQ>Pw_bOSkW zoy-_3EWic51QF6zM182d$g1Y6Me^1l>R^Pc`8An6@^N-^!ZcfH%p1FSgu3R#OVS+k$^^Iqh z9p_N+@l+4X;+^@eD5}^nqB14E5j@`_+clPORJPuavyJ|Tq;TdT%;3%SrI*@X$IB%t zu^pHd+Hh_e1{H|7LRE;ie<4?C^ za-iCkADDMCCR(#A)8w{?d0=lO#fImoFTlN>kzP(C-tJ{C+&1=|{I&$X96D|al}3bu zTLkszMpDvli6foU{jd|Nf9~3Cxb#5yZ7q1GyxF^P%GwDZvfXmBBf*istUT$;5{F*( z8DB&Zop-kH{;90SIo$*_gX`#1XJ>7$SZ~fR$7b_-msBy%wQ~-34{98np0gKZ-rD8Q z;#G^x&;xk~>$xD)d?(I6Dh5eZkS^=X=NCo&G^XKA8C45+4KCla<+k;Lv8KLL30^N# z{nQa~nR&>hp5@r`Z+<94=&DFQ3dLQOw1vH^&i)NM%_@=={1~u=)e>bNbsILEuG5pW zy5%gPu6K+tIr*sSG0~u!l(M$bveC-~?b&sSn5FF2(l@<3O!L%hXw)F^|Fy=@nK@ZoU37Um9pRFcj-+c1C7|oG(X=zq!{IbSF91bH9eVMg>{o94TH!~>ZW5%r-o(X+j zkxlK|7KqOl2sZz_@8#X{58lL zv2SeKc4OPN?dSIW`To{={<&+`%&fTwud`o!?{ntNX?NT^MuD08qR3-aN&NHvgq@9b z-$4V%*(Yo5JFd%GdC%>YPtwb7QP}!r+iv;+;HCTts&g`!&(UUZoZx8edRO;j!*o%Y3c&obP&aN~cy7}A% zzXlSDtp)Bo4Ul!P8lpez%I8G(%0fE%kf1XKEW$JS>_p@SHfx+wf6VRQR#{~=IFH1n z=|%%^R`1W3P6B#}>=D6*!@6->y{^3~RMM4ur?3O1Yk$b@#=mosD2#OzwDg4(R(mZH zR7QYpxRcs?y2SiYtR(xJY`q_nkzgJy1Iu5FB6UV!&at0gcLJ0l2W-|s9u|ecXhU(U zIBae3yk`m9_0ns$Jd><=C#-N5X2c&6 zAMMO?l`;~n2_dYG>X~Z$6Rz2`=`#5BbINP1WOt(;k-kw|L_Fg2cfS_*0RfGRrC|{Q+D_MK4WS1y2=usvww+i z??{-z-4{BJm}g()*B=8@hG{Ep#JCcSR!&WeHHCa=_o#){b7x-G?d-1t0f{E!tACdh zC?*lEqn&1Wy;#LD=idtzdq};>y(DW2S{;nQ(te@_m?vUi*CF@NXAoR>n8W%Sb%u<~ zOgSieg1Vbc*n)Kd7aX6QcnX(TGLKC-*l5~@#X*?)$Cyl7>49N=qX~}kC6)MMDi_cDoGY-QC?|O-5$Iqd6=OAT9+|+0Lzgmk zFwGl#6H2WL z--Nl?4-Iw~zCf6t)d}tjH$Ekgzr}>^gC@KbZ3Z}P(u7Z2sUSX*m+2p8eT3RNQ7IEk zbi^_0fGBpNFO!}nnSz@^P4qu8^kj=p^m^$4w-(2c^ z))9+!T^V_+TZcg#o3k2~2lsVfpV?Mn%hd+BxO=C196H`DNTBc=q~ImFt+8^izNu3C zD|cUCPuod$9-p-l5vkbR`frd$eIwaIB<>n%=nY*l_&f zuzV1ON`Q#}c6+s*AKjm>d!`@v{aY`7D4S=x%Vj^V*+S5ARgJnwyan3lHjbx*v;78? z{2G|8^wq)nLB%D)M#r=F_cJH)%0;Ik>!tJ6oOLV5KQ?hi^cFWecL{&&nei|zYT54G zvs%PF?hIp1R?m?ZDG_*r(%O9))Bm7e#qhK^d3s>cTD&4b8(mtXZu~YW-UuVSdw3!? zd9AVy_RG5sdSUj=;iq9G1p1j-!#r4-ID~hKVo0#G|D(d(IJ`za z3A$nUmLq+2?>U{7<5_FJ_(+{+raU}2U2oy*d-yW9+bNHRB@l#LH1;7YU1+X6{siy(K#hb2r`COkYTxK3rjYbHs<3)9*(g zwvCnmKqK!Z(dxoKiVs`OLFEyD#f=UJ?nn>hYd%n>dUwRfCgP7n#$@8(42u&7kVhtf z$3tVgChsEE9t@uSV^V3;$<8GESwYfN?iZ=Io&GXA`E_A7-YxzFKVD?EHX@zkHG&K z^>%51HX=?C*nIjFhZP&b+@DWLybo&iE}MCchF!y_=d0w#+ktZ~0UP{W_R1CWq<7ZQ zY5I@DuIAg9cyYUm7NW{14bjUhv~;4>koVGo4>KCO%`;u=fWHD_Bt3b7u27#|J^s!~e&+~Y>Pj6 zy+DCrq^MN^o8>M+%;Md;q&X_OyAEj`;-z?I#}Xio1APOeFDHx|1NpT&>(=%>5rh2`fT zzL|rB&shFBAu*&dKLTmCPTxKIFP72`U~e5WG@hMaUgs_%Mk7$|5EQqq_%plw!!%E! zg&w&H-zDX3)lVt}LfmzOAs^Sf1$*}0Ym;kfdQcwhuk;7{vOFk6jqLyb`^^ zZFgW8$RBUx>E+9Gq0Tj+QC5sK`_*#?5;}l3*9!H=fKmBEAv2Su(+W&qV?`QvSLaKG*6y#f9THsx?{}5X3|f=(rtRmwyNzJxf^osGK! z_or+jH`^EaD)Ay{p@dYKwhr5r=!f~^Iif)3>5?x0Tkl^}_1516QcE1~3*T#%EWYuk zmO9Rx{C6n$?~ojH*qV<8r`&4c;H^%rtpFP|J6kIKY+N!&)trsn0Y_*a0@@3rp<=){>Mr4~YjvL?T7PEwlO~?i%M?+0^55^yrtkOx5+g=c z{l%N3;!g@n8fn6axs)tHtvdW8$+_}T@fMQ&1vCN%_f0IOd(X(d_`6mpN~0$&k^=bi zfXC>^zxkMr$ifE4v}g}@vxRD(-D$yMcvAOOy&tYW558y54Gn}Y*(0U@npJbAz3bTi z=D3F#NGSU`t+EAcdYQKCv>h$Mw(B|Hi;o;41Aonh=nX?sV>YbPS&g$D`Q&u#s@%3p5GDaNoIvPdJ z)pWU#k&VZm^pKH|yYXhttENjQZt#TK5+q)yf-ZONVU*ZIbF@afUV}fAg*01`6P>Y( zcWt4}l|nw#(-t9-mG}7`5G9Lt4xj&QkjCgG7O()v0oC6mSs#FZpPN$;6mC+5?YT*&NzpMvTNT3ahLypOiB(V9 z67Q`6_P!89ZBy5$_|4$p%XpPo6g(3gte)L#JErTPOE0_E8Sqd9x*$Rc-;D|$szYU? zah2&>6r3RB=S`Eghuuof(NAGnjAS@@e`p7^#mHto6AQL;b%OSls2@V??cVcFJbjpwOcwdffB_e}#+$sk|eT(2Ezu*iN8;^}d5!3PE z_Ix4pb$|JJ^;b=^?fLJ_N}AVF{J^DPL^hpe^ErYQ6m}?5B;a`I}^)sqc<3)4KH&z0wi@~?G^W@nZMz^^+LzRj^w+jTr?08Y(GCxS0v z-{F1=WdM%@%;zw_M=PMoE{x6+r z;12LxbvQORrlyU0{1sp&N+ON;QQ=q|0Tzr*1**&q}C+{FLM_4~?nC>R#zN9xiy zB1tO$W2d7&EWuyjY{{=v{Pr1{-oIjF7Q$Ix_!LFls5%oC{Zva3P;CCs|=@|KLtU$eyURJ zoChI|bgcr_ZVTT9o00(s&lNAK&b7-b+8%Sq#=(QNrk-fR!-ww2ai6NW!`TQGVI9=b z>U1rCwlV9z;aL{Zg3N6Su|Y<7y>W4IK>t=pXzBzP@#f*#@sqelcH&l2y9!)5$0w8a zemW$tY-I+j@r1|ttLJhs41@N@4O+X!jY7vBdK{)|e^!s*DEg8+wBKk#Q>VcVduLL+ zMthGIc=`Jamt3FBix*(`55ewgqChnd8MaKrRO#Wc8N>E-U>A&R#6cb<|!_h0Nn_$n5QcO?T4ET}ErJ>$K*N5AD}m*DT)2tuKhxsY-Oh zx4_e3uAB>Fn<-}Fdmv*D+}zG_&}GmKK>pe;QleFA0FvZvXMe3?S9kLpeX^69JQ(^bt$bLl$ZU7t4H>Mkw=f;jr zUhVNhLB=BwI9l0LY>&=0Xg#PAz(%stcJSPnr1U1IKYHr~F^tyHD65uMD)GIlB$je< zQ7a2{m70Tdc3`~)7Hk#lbW}B=d6sI!0v^@0-W1O3^vauFUTHTpXQ=3-D=TIA-`u|r z)?S?^bgE zM`$c|@v8!Z(cTxPO<{_^6-#Fl-_un|LHQ-RKr*BDjfanmA^}GdQG7Nk%1zlsY~1wP z`RtI+e9v$Z`@x~rJsk0L@d$h7M4Ab>EM(H_n&9`SDpNSB>EcU)?K%;utN=9jXmz}~ zuo3^93-75>=aKH<;Z`wnd_kg&=@Vov~)RUUpN%YKVU(O7b2^4VWFc)Z zBIYW-FeOB22EoXWv%7f@4AgyEoIPgPo^1-Ofyq+ zdm|l)nG{e!a5oSGdUi79`MXgLpHq+d|B9ICmV?j8)0L&K0&p{3Rqs@QQ4q>hvf7eu z(D}Iytl5$cDEFWw85(a(47THNadvWc0P`4BY{{bKsX62JX;){bM|s4PHLy7|I||hg z46Wz?=E>&$j9EckyP>2WI(8!|R~3Ve!IqqeUjuL;ZLX zZhgS=Di6i?Yk${?oC?2E<3$*=VMlgTI(J8c;qfU-W}p=H)Mrk9uZZvrmTO2LpPkNE zdPk+S@oJvwgcwq4N=sUvTE{|Ywo5U@UUIh=EA$)Z+p-h+`TOZHIy%+ABpO}bK$;ce zs);>m5XT#uQgl9cYqF<-XqD`6#FScGn+Fn^(c?;wlsj3j0}q&ywm=FTmzkGB9pr5D z6I_iHl^ug+t;Tf=?k>l;p~asxIE%(S4=5wG^IWpZdaHqzn57Qnii2*1`(1}uhFmb* zi6g{0=*sr{a(&HKUElnHkD4|E)K2r$aT@Z29sFAbNBAsKTCPmAUQu} z7Ul4|*LQ$H(UA45JxLX9t$j~2xlfsbv7`gO5pn3W z+n$G>hJ0N}No2ziq2-F$>c@v1yfV)ZSRP1i35H}4SzZcoK~c@9bGp7>%y`eZFSbPB z_3+>2`@Pt@CV!QxO8RBeeI~Gk4Jb1zpD@X&XAsScp}@0=TU*Mh^vz z;I(9?p#+-)9WKqtxyZDL+8F?sq!994IpjYQ6HL56U2Um1!Zc7n%jl;yF%20aD-Ui{7?9h1|XYIbkL4tikxa5 zN(?Ra=4C3P<3+j%b30QPhc-<+8}K3 zCQTYG3n+_j-4!dAe$MLwW-=(CeVk0jikTDXw0463rIpapz?D=$AWL2k|f1h%Wh@Mw5cRi_^( z=Pfg`{9M#z3X@qh^U}NK8a#v3P{d@%-CS6WRVAO>(~Sc5s$xhO|7-iB^aG+0eSjXc zJ{c5l)Hkty6=H-W!vYjB1KlVhJj1!iB+af4VXW52ttIL}CW>DpBgq*H`?0C7 zE(WP=hIvMviap`^SxfAa;7H{D5thdJMW##RXJE}|wsGT*@}@No#-B!v$YI*(%(PhZ zX;jXPc%+M_OXcZ63m$wnYzxrLp@eC-E36Akkn~JX0^m= z)awh&pN^Cfm-KsWKA61Db11lN*DYK9;j3XkjBP9X5Oo~sr z6toJ>_hWEfoF_n{IF5y9?>cLCr&5qy`kwSlb{w|h3Z;DE*Sa%)iV?rdcgyK zDc^^}zHB(I9ytw)sJxwue?(*o`&iv~Fnyc=-k3TwYltklQ7B^tDXz-CG;NZw7;?pY z+Rl-_VhQ!|vfo#9DiVEBny|b*H*kFTqK^9XrkTa$)0~_pKzY z5?ZzRZwYP;O9SJSiV+qfEZo_JS*U2t&vw4<@7Vc7a9jgozYpp8RHz(RvV{7|#5R7nAF zzGJmaq*hRZOOM515}-k;D$e0!J}-@BA%?-nb~w-J@i(wfvc&qv>EQnl65=#T$_}ld zL6-C1Ae#sBj}9Uj%mXJn|A7YAsPla?XAz5)188SbF3^rSjs}1AV{#o@bz)`??n(_( zlj_o@+3bx%T1pL;f#hY+T0`A!G!(O=sgrrj{mllc^J7dD`A6egK=bri(M|TlrD?RA zQktY=D|%8w%P~7C$5MM#!ZlQ=>OBZY{nReZ=C8tidsD9LXTUIM z7&ZvCQT>*f%3>JAVa>bmdWU0VyhGScl~HvIUB~Cnn=wl#y}36NbcZN6Tm3K(Cd=yZ zvXz44ZXs4IDoa^-{Swc{4|#o92FAn~VBUwdvs+^P6e3U7mrr5x^CULwl&~810v7{Z z;Rkstjv&P$vpX|2cmks`3K$4xQ3U@FX0v_O^#O37b(iwnpR}gS0D#U%FC18^GSB~b z4KKt+pf>2CEzIc87?SrVB^#)O~tqhzZxRM&6>lB#CX!@i4r~AyGE3O zDgQMDg!G{NFFM_5XB2~Y?Xe2}OLTnr>u&`Yn5>#+COC&{n&Tw%-aXikx>WxJp_^%fRM_?n3$V|Jn z0CMk9-YURBc_tpOg=)x-{mr#$EgycHo)MUL?(`1qU5%=|iq_c}MO=c!dQ=9p(3FdzIN1F~Av-s`7j4tPxxKDVD3tzL7gu zT}zr|WW>i@x(WZEX5Z{06Qk*-@#ls#K^>=Y!VWRc|K(tF>qh#T16g$E$!o^Ci+`iu z(D?9}`mB=t_^Wih>90UEJ^P&mOkRmc0sgSm8+89uvuYL-26K>BD!tB@#J&yR{ zT+@%W{x!_^^wV;^~5wp&aRKOWGB8BREH#m;ilbpoRdby7*ltybN@pBc%y%> zi8-lwQBdA|&ZjsGq|SAp@{@ykZuwi<-08!|UFO6?6=m8*S$I1*a{8wFcpx$NlY%-i z#1wbC??>?x0rbucwlFf~I#Qj9YZ`jvebrdWJ(Ok-Hm{0mdGn5}Pgnb21g>QUxYA5@ zQv=6m2<6XLG(B2MgO-sl%Pe4#Q`WPV)IHD3`$)EJ@ zo*?D{|4uV#z+jp;nDS#PzFv$>))xovm%KggEC!6Vr@iN<%sk%N{58M+LH({&(oQ~6 zM7;1v4Wj<%kIRLM3+2OIl&b;(j9HIA`$H)U1L6fwNEpuFO`A*66OhP}=>ao~6rRbT zay;HAinGF)hQRFfUat>V?5_6hM{$)n(WG*@3UBC@5PaU>Ky%ePDjNVAwoWJxKpL6p z|1@&xs&mqCcWTAw?|)L*0?IYXCI@v-#nPEIY`iQsVAms)*Rlb++yfa$#aBFcCplKk?}AYp(}9kDOs#}z*-DYQwg>E5=+p;CD%%4i#GE_J`+ z+BmW;fyP}YCspZ%#5##+d3$24SXK8LV4t@|YZw#&!uEllI*f(T-WvW%u^PCqryBu= zWieMkGAbG$MTsX^6B{3dfJhDepdOY6OlIMs(Z0d|IPh|4Z7+q@zR3(LPyt4X=OlCG zUTwb_5gn6DbZbUTsWjWp*&gsB;O~RE=nY42G<1)}WoO7X8_r~3d&fWWA58&ech{1w zgUtb~Qp&*6Z*zHgWl`CgU$T?hhT0(H{v+LBZ2w62CabRkEL>H${UBpcmmX2WAJFU! zM<4Tls3>!4Z;-@A6O@0Ts1WiutO<|A|vSW>M z;=ip%iAZ>H1{ZVO%DuDZ8Iig{+NX_k2g%No=AkL1oonW_`V#_Rb**KwoTCm34| z)sjV1#aGKvCQN->yC>6(X<8XG8AR!NqZJ|X~2oqDL1S%>p`S-_ke!eEuDH5lkYIt1HY%*mt= zc9tEa9M9Xs8#866H;pJ`G|WTUhfI=i$-oNKwiM!s4Kmh|PNA>Ae-VR=pxV9v8cB)~ zUrM?A6^!$Kkbz~a`hG5wmmO62{lgU~?KMFv+e|-MJKtU*lEPRL@ZWu*Lb79_hKqMm z4&c8xX4EZhnH8~VTx{dE%luJ6gD@Z-8}bj?Hs@}p8Rzn`sW+el&d6?LG_A-mSI5=_IdlTiJo*dQw`|6R@E+f%g#Ly~ z^mfyrnna$~+Qi^NtiT`LDPGoMeFs;)QO%k+R;MxhqI&K}1cK2o2#CR`R52Yb!EC~h zW?v#3`Niem#Htwq3$fYm#A&@mEJ0ch;$N{lsek|L`QIr_)neZPEGLd7>tt|YNT*OI8HzN zAkEMXOhAso7|1cm=n%Hw{1P`?7G_wQt;J7Cu}3_eDr{GPBZK@8P`IE*##De(Z;+j> z@AZiv;pq%eGIc~GVn=w4dKy%|Q-8o_#{UN&<60d|QM0$YXZ^iSN=EiJiq_ScCS}?G zbiW+mpZ}?4!ekFGRj4_qf1M)eB@?Hh#W#r-muvbh1p7Y@=5U6lF(i4icXqz}!%4d4 z;dlW%;_MuwL({`^_sgll+1Iwk0K0hWsp=4sOBsWZ+lA!=O{qj1j#Fv)+1<7$aXZL@ z!j^i!o##wk-4yo7Lyrz&uK!1+;y7AGV=@j*>A#NgO`1NHhGp)nEr)pzcH{iwoG7NC zf2{p$QMlLvGo&(p=Ma})zQ)gU)N8v^@%b!GXWI9tNRoGYzSv$&-FrMVIyr=GrbYSZ z;eFwzf*?`?|%_6 zQSoHz{5<+FjHiXR!~rSx2bc$|J<9 zyDu{L*@320?iO79bvkKUtYhVV%uy+qVps_79Xbc0+j+bo8=9nSv+Ta{9{KMPe+As! zYtU|6yyj3-$jBEubALDE$&6MXAA2hL%`6{YtB5{QJ6HEBVt#L%cmI&-YJ5S zE?z6ARtdxEWa5L82PTkf(H2c?tQCcZmweLIkhZL*cCHWd_E!30KmvbqdZ4Wf|6P&h z%aGCeUaE}(0_4+BsJ@NMrN;mK`HS~qm-%PNG!uRvz;M6*w2@>W`AB25irLH$OiQ9qkQkx2aT+S`W8Myk0 zOyY;}nLyOv`bc!B9Ar(a85q%z5j4*y6Q?f^PYz8S&ETDPL;j^EVgh0=407|?kkjD! z*{v`a;|c7i$tTN~4BXl&alWGO%5w825u~6yu3mN?OIVz8ErnAx_@f%iKd6h1$v3-; z&!H@y9aA+v(5TcuMjPa53pmt)iQvuG;*T)$rYr|4+BiYtP zP@CpIj3q;{b=`<~4YjRWxb+>I(aI63ZST69;5TZ)-?eW8!MEBBUQ7Wr_HbT)FFq>k zuN&*Yi|sc5R^4Y5UFE)<9+T~x`N_8Wm`CI_$Kw?7wLA4aH+xW(;C1Us zM1#m>NVYhN89h4vOKzaon+ucE<;iB$>?XWY(+Z=YX;X5J(b(jW52n)1h+$en97}Iv zfsxeE|4ty!Q~gLz3y4OGSbluE^#85%Jk3?Gr=WNdYv7{rdxNTQuVZm<*tBz;Y~e@%FK<_CwVK)LplUgyt*R&`j4C zcwLw4Q3ET-qHXIXU37|%+3VIFFnBl725J0rT^L2Jn8n95o6bWQPbS!@v@^7Wr#I35 z)H=^OKQoyUkg74A&sfAi~90Z%2v5QZRfcJ z&Yc0?=b40rx&+!Cu?__vLk417zx!A;y!^z#tYC*8`E>7s0q4n9VGC|WA~*tkpH3TS zV^vUAH8=Pq#_*Gm`@d>y5pS*`^Bj%8KRgm+CNQIGp`^k z_e6vms@~RU7V{Nh2;x1lb*_I!%=Ap1bLBn+2HcLa_l-<8R`nv3`CRNerRd)u`d1l2 z1H+F6VfpT(fa&oJaA~{B2r|V`Za(YOs|NS7bnPUX?cw?-iAy`mTT4|2@LikdpXkNh z)XNOv%Lex@D|vKgl7C(wN2}PQlWme!nRGgY+uFlxPSIEPmA5vktdn_s2I+?}2hM75 zsRx9Y%50nv%s-_vM49Gl!g4N&SaTxj;WmYKfab2`eoy(ilan zGTCeM7xV;ui9Tp`z0ohK2XikF6^tIu1#2w(`I@}J zG@q2kdx?bZ2MJmysW)L>yN=?{zQ&U~UGOEXoi9yPTD}lpsI#RIS0AlicG?IcRT6m9 zT=`XSX1uiJE@=eP2;baD=o9D-IEKKr*6Y5MQn`UGns;gCm3vBD!9~@+sB*N6<(0qH zUnfTGJT{2Q>teEwoMtGR*?Io3x^XW`NNgBB$s%wKVt4C69jUcs2I_U_(snCBHqI3p zV5q(4vepv)b_~;RNoM7MeyY5433l7h z4mB9&`;zQhRd1p!(3#XWZ>N3B-ukDJWst{CCp)N9=Hqee0lzK?^yF;e=HldgUhJ74 zeuk+|`QekNx#&mqLcR}OQi)dPPIqFy8Qt#Pv^qeuaWE!aL!|2-4t1#WPx(?D8MM6xip-h3=klu7od)bx3Vm2s5c|Ta2-P8CI1209b<*baB%j;SMn{RBJ z-oDR+=U;7q3w^Xx@w?{Cq9qgcWt>BvR`7NDnH)hRDDhl3o-iD-_+5dP{MosjMw${H zLH8!=&ajl+B-YUbUo%<0Qia$eA`@=)$*X}@DtXXWZf6jRJ^Wi^Xy*Fc;wU-RK;l_V z%clO+sQqyoqr5P6HzlgbeP|mb=NzmHzfs`?Z|KOiC>vJ}t)EL+M*^AbjtYJ^tw7$v zF&;O}-imEuTl*ZD@gaJuu9JmqP(NxV{m~O1S)9$5ywec1vtms%5j(|}KaCn32F;#I zMaH0Rs4EN%x8j(!$!~Udsz6$4w%rvuZRT4a``C>%i<1?+9Qlixf}N+AcsH42nBZE& zfE*uvkmGZ~bK`WZLxN?_F%WdQ{`6q>C7uQ`!GIaKqjxMQ(npNsu#`MFJIw|d=cG5q zks~$u32#VzSI6(n*|wMtC=@xXSVW4+T?M@0b)6S0$VND_J3I+E0vM z>`{wyxN$5ka+Fb#gQ*uigvbGYZ#o218(VD{maUEpwVBP6Og^O@vK@eC!-`nl2HCV) zgtA`a(X=!8SQtOY!_^~887VtcDK6VxM84A_r4Mh9|5Ph*Uh)iY#zDfBOCi#CrRXc$ z;WsVODOgRl(Z+H0tzbq_hH*)65!X@R=SQf=m9@102)kyd@|l-o^m`G_$Ge6<$esrnym9Wd2Hj@c$8?SU(Wg9+9^43+ zouYH=`_!Lrm!%~??O)s#W5T_gvy;$Sl4yR|`3TbYTjiraRb6(=3LUE<#DLM)Y70nN z(!+PN>RWLjx>#B|)KCm{%dtQlmvDXZif{4u{Bp(Hd0KRVm?Apzb}KeCia)i<+x=X8|=i!|{liyA6QKtPTO*$il; zeA6b6f(xw%AjH-NkAGw`Ydye7H~)b2V8h>0^1Tg+n1#$H+r$mSk+E86?M_9OQxSk4 zCqXzNNf9lEw8p)&1}{Lw$ICFY_~qYA@g!Cj{7GEVZ$9~Xt41Afo~^$>3|oLz4*q7? zpF?4?Hw>wxum`0YTX~U}WM5ZY~DenukvKmWA(Hg&t)0^iRo+5(># zGK14W9*l!Si?baJTN-)`>jo~83?2-e)uxR?F z7Du+?zYY?(ez%iIuOtc8=h(@v9Zjq zBkq?D7Z!YMb_|x0t?0^`0P~p&UtsP2Vo4NA^)6zCIwao2z};NCkWk&$8PMFufRmI> zgEjOZhqnU$_Le7w4|RuS$vmGBQSvLBpv5q(XIuQ|Ii+M_Dy8`k54r*wzhsPc_JLtR za#vp0msYV2PRKnz^LQJ$g+f0G|1<1p{S`*B2ai$F2Nk+Wunc90)^5}O$1w5n(`3KD-8|Yp1jXGDg%b3DZ?bA%{>O+Y2rLReBx&S=tMezj8$=nozso>j=PJ?JzUH z?eL>G1lqJ}n=wp&0r@z^*mfYy>+=a+j6D9%(x4C-&x-)HQ&mE`{X9MwoXYOF=YQEC zBB>BN*q`>JWq{}BTeE{;?njes%AvZ$^5Z&DJ$MTaZmBgJ9kdclnhgT<>lkcr&C&d1 zSp5)NR-aD3K}N^i1Vu@KcYQT7*4bb{HEpd1THOGX#&cuqPy?0^_XSeMH6lk4Gvd5U zn$uu=EhZa+{c*3)5ASC8A5(=GvM%TW9b!&=wv z|C}qUY5uq7py7~gS}33m&b){T$Q>3-)FRum?Y!*l2B+5t3GdEl%WV=rju(KfVK^zm zYmJFojG=jIOw88dm-U?wn@}QVI(`EhFFIA~&E#>&iWgVFD;HH*Hawes;Mz@G3(sjw z*A#|OLwx70?^qyfN>WimQ8*CG%3+qj@BL<~vB4_5K>$5urFprE$1m0~@OL@3-Uapq zoF}NU;5!ec%436equNO8MkBEIn{$$htK^#hH-`cWI7mpayOa|oghQE3Dl(RL+*nN$ zHajf)iIzSYNy|`{^5wVQO&8J=w;k{pNGA%2M}ba-v^W@-2gmI&@9I(nxRZZg>~AB~+}8`VP< zY_8``Gwl~<+;QZEeLnJb5Y^Uq6vYDkZl!1KO)Q=Hiv9w)qJ? zcaY`wdPr-33Rf2@{H{Cid0kmW0X3|9x%Z%qJDV4Tzs<$KHsYGzxoqr9^avN z8wD5y9F2G%4~>iP-$8m8-KEJonmY1KO+N67{c;#>-)lgd3JPcnCi7i{QKyI15Km+( zXBIDBaQd4;TW43iAx6q{V6&j~*0aB$stva(f<8KcxSTpzk4xtlf0luu3nw-*Ck8$W zVS?TlA2KXCHiO{E-kl7^Oy8L;c>;ZIYrV9ut5+7E_)qer&nL1zRryq0>IhFcb0dM!&PGRU7bG$i7OWRk_ z(Jk%5tO2Gh%Gj7@{e?TyuKBj80{|mPX}y{P7=^?*aSWNWwkzBPN>X2f2KsMmiQ4Wz zN&>On2dkfl3iTUTnH((1FAVbabLl7KkzuhW6W&O&pSRy2M6w^I_ot8LPpO65-^@>yxc)Ck=82gbcxCU8(UBq(hHd&i;*0p$c~$mTMF=H2mp!2u|ZHH>#MPC!nI>g6|dJn+_Fd9$Y92#&YmML z!Wg4VSC@fPwo>L%sMPlwbnoBzl9soG4s+F!mSRBWp1VM{-Q~m6Ng->5%7C;W5)E*l z6%@9 zZeauaHve)i(Jt_O|GseiTvVLkRJz3WqfoJ=N_s@S$o9}!>HIq%I4-H7_23iB?JHfb zB;l+9CkGK57Vf9la%w6;IBwRsocgcea3-4BNV{MQ!FklAw7eDPMwf@z7dv8`H0pTS zsW0=MX{9=x(#lmcO0+{XzZ98niTiLLf0<-)uvpm3V~Xe$l>9dnWL^pa;TV5~@7js< z)8YMWHG7um@%nm!Albn0jn3dd5-Bx_8)arUqNuyY_PrOEl-F##3G?!kYLo`?j9|;3 z?alJ>62Zbvc_IY=V28(N##V!nj!PKaJ9JP@F1lcbuDB8?N@pi`y$= zW=hfMm{tMIGg`MnhNE00J z();s7UZ-a_Bb^lJQI%`yT-^^F4O2JN)FO1k0wXjt9^I= zx4>B!h16~CK(8$Xd1Q&txo66S-iOQNicPVHjwRvdkEGhaAYF3P>%xA9g03=n;Ij$g ze(kd!QyX*zePTfBUcgyms_UVP2YyjeIU4&lCvW!uW9^;dOr(_p&`#rorxVCVJ{rQCnIy{2RHcd0BKB1 zUzMF>5!dP)tX$u;&(V#ZeG6UiV;5fMoE3UrV!ca!#0$CC`Hw$#^Dw8slgk|8sk9>; zZRQO^diTw`91oh%tU6~J6?LCi}8v~Xqj7#?`h5xM! zyS_F`F~^5eLRR2B0zGEZQK`3Wv;4?K07zW?ity7QpN3gs$J@}CJ~8dhy+W4xs$Qnn zcJPaRd>}Ch|MCD}X}F`@BsTM`mJJOS4E1sUY2E!J9HV>J%dpNLZS2h_ttM6#`IRD* zvV4?q{=0*8r!6}xuS($B7p%#-Fb{}hLZh;!5wj7MY5jHg zU1Bg=edkMMxN*{4a0F5Fq69%ix@B_qj~{@K5;~Cvtz*wb7jtG^S(YO$i^sUHNkA}` zRc((!?-keUEs5PSS5n);!PxI=ry~31b|teMtym4<=S!tRInI(oXDcVTfp9gmoJJrY z!3&P!;fupS%kE_thLe93F^5i{c>{H}Qy85v)EXV^ZjLAfC?tp*br?oC+Wad<5gcorPaMiLSWoa zEUiWPnYNcjzA1B$)8U%j1b)O3O9z`NeN;^w3b1ShJ-GGaPTlB6gIF^^=f;k1P(xhU zqhWZ=O2BD4!YDq7G2AImD|>A&TBsVH8q^498!P*xHFeV*K_P3eS?Amx8gR^H+Z8wt z$57%)^J7=xSG}dqpV|7L__LwvsB^3ELy>qeFE!DU_5q#JbHeO+j92@{DoLOv(~MfgWG)6?;Fy?b197fo~$}^oO~op=b5R zSF51`MHZ6Nigv`?v35;?ClnNfQKf5ybot~Wr453mR}Y$dr!$`{ zk{$8=f$QDyH`K6mwp3)b?q`2M(X4vut8Ws|LZ7>Tb_&Ag2p+A2!cO+FNK;VRR`EDm zZE==Pb?N35!Rqjp1l57d9M>kA22)SrwsM8lE1q5CKt%L%h@{ge9wJCXIn>}x zzKHbH!a^%9kWP6;+ICq;=JD-GTv_r~Bt6{}k=nYO&-DIutHKYH#*d=hAf{?+-|ANM zQBzkG&)sjFZt1ae)Fr2Cv4TGoO<~)VY}g+LoL;rurTtBe%drc9aUQ#hMs3ybuZP#m zzWPBbBJ^~gL*yR+6WAI+%^d3<8xB3;6st*>cq7NjK8jo{gw7mW=BvJ~U+vaPREk>+ zc@P*YwwZ5?dFKtzv}?2Ypkr4e8x9l&W0ymo>1w)B^dvRo!4gi)-$1}R##|m{Qxs`V zlkXz*3g$w>UYZ7DCEDt%H53BVqU?G$Eijy#rW+`x6XHVXQz-Ne`Gp=GV5*z_Iv(ju zt?`JOZjWb>J3TuAXf|YS$O*4l6x_ zt(T=I>aTE8Ax$Hn91eg8(dgVvmAe4{I)b1ko#!Lyd{Ncb7dB7a8vZ zj-81VF?HA}_2K8ntK9^-rDdtAJ8ks3E|L0dmlKndr^-%=AVrfL)Xu#Lr6>9dL17%& z%JDC-{uxZ%TW&Q=_@iChrUPyxvCBPM?09^@^Z^j9e8Hat!a0ehzWFCN+f^O~nhom) zz|E%Ac(a{acjBa{`Je?}muHDK#b{{|ZBk>$F-_u9-FeK|7PfCxj-BwZ7($zrO(YZT z1SwR~9JT(cW{h{w$f#~C(GLlk!8?j^*!Qb=L(czcASURe_c^oqvpTAU5FQPY_PeRNQfg&CO5N@}(5509K_GvRP% zQZX+oENN~X3#?$R+BoFnh~LXEj}02TF8{+HQ+ak1CfhL%4*p9Fl}&RJ&*`YX?fao2 z(+sNG4B;{S#Qx8AJ5=JLDI$6fz5T23i@Pskdp0!(lFDIBZ0_faqv-Vc3P%ZY4vfC( zDx%rJLnUtQc-L+2w;)oFK_fZ7g3J{#?S+)vsUwZ0oY>Es1eg2ab{r=KLX7aa4Pig7 zve*!QhD|l4g~efjj5e%cA$FBKR6Q`_97Q#$=$W=^aX_*$RH=}egY@w3C6yPpVacabl?TfjilVn#xF5S?r_tGa*GkN zqCt=VPNiL5?dUWRvBfJSU(tmGj5*iY_9ZOIOK`}Vj4C?L3WGwki>=vu2Q%-VPp&y5 zNYFuWIus(T7ls-o^>Pb%=4FNujix&A+aoCsvf-v}A3tGkVsdBSf9c-1Cc>NF$;+~g zv>UEfZ%@|mXtSbMV^Y{5YC7$BIUr({fmBE=;Moso9r|m1oA3XXg+?wy zF~n+*x4+{L!U$qazM)(81hzMA$)sg)DG%@2D(@$)g!scN+}O?1CGwfl9o(O|65ziv zE-^P`%Kb$UIhYE`L2k7T?bJz~0D^NFh*>dVsIv~WYV5{LW`7G_)_7wnT4(l7L-Z-K z_2aZ_CiW$3wfB{@OA|V#oSW5X@<=SyYOYT`Q>o-D{T4hv$E6gxQ53_DlBfJW@7PTo z96v%ETaQ!9VaWcJQ2{I?9N?_7n2tWrY!5)ro!dobV;3D2mgn>T9sHW|QdHO{Q;Wn6 z|AA_s2-Fp`XPm|g^6P?``v)xp$CyXLhwuM{J+u$K+Gd_tFb?pLV~B-_1;}0#DKx4v z0nznqOoHG4ftfZ4GY0Rc{72-Pzj&a7ocskvg82iZ3zlvc<_%t(4E>Pw+BK0#;?d$K zO19%o$C#K0hET@l1y}bzMTxdE?6S)P?M+^_P)hB(g#N_`IW0#=A6#BwK zp-HK|$9g0}kp6jT(VXJuStqG+h_&tVLy|*tP9M|#F^%$Y64k`vtDi{bUX%+?o;Z0c zp>vUmgG$m!i&t}8w`i^)IBJKGX<3buLD0<2$skdEWzD=d6-%U}zhze!Xz46{)zHf< z)8VVDB_KXO>f4_Qh2u}q)A@2A;nq6DI#qr+a!D}m9Q~&pZ-{Jj8Va9lJVk<64I;etKSBe zob91nmaA7cOgq%Ht;?#f7sra_x=NWEn~L5?Uo!(j z6VYksZ~v$<+t#jWJi~`-5CLx-DT0L|Ke+0La7ob2)7y1lZk)|^oS`m7vzu{p=@THU z4_%vr3bLA#3XO^*-o+$mE>yW%RJ zlPb)%+#3A|sNFO2&jhs}i)Yz31J)TF*JRdIxN|Kkp}_%&8jv)uLPjj z<4=tO(Ls`g^-z=s@9Wmo9OFW1=Spf^aKa6?B0PVRm!>HNld+4s-|Ze$hW0Mo7&}uP zG&g_7Z|fW+^)ZhSZrrXX=1jq#NY8@lt8X*K^vq7Ty(H`#wRkf!8>KC`8uZOcyOfT_ z9KDZVtXt~y*1*U&)bxx(CrQk4vRrH2h~>1jnEYb(3^Uy0Z1W&}s;X+2ICNCHn`xLy zo*mond?eT2x4+O-lgcZ!*fjeJwg2B5VLLV$tt^Kp_$IBVD9-j?{pfrHU)tZ`%~&!# zQK)qdo0=Z;UB#aV*4F9awJf*=s;^9z^uCbpEodt^Y7F6$ty&+?KkR6 zcc(3W95Fvo0n}|~TJ)}tPhc~V&UA}&5o>0qIeu-GIwU&Q`R@B^u__F&L- z+oTr}A|bgea#xASz%_%tOE}_@iIJSFKT@!W+TLF0E8+*Q)S6OQ{UMA2d*&dVFHk1j zde2>>wMG_VY0Y7iV93$O0=(`6t@hPBo$0&kcz1{ttd;1v1rqqc)&x^sC98LqQLKEZ z@_M~l1(|eo`D0%X5ZO@>^e!;&I2Lt=kGfWWOUi$Rt1KgMvt6!l(~cf*!DPXVL>`}% zv7T-oO-#`k6jQK_3gkIKYK60`SMHf$z*w3Oa(PFLrgj1kJ%$}0N|9Lxbqi!uO`4UC zqEp!R>@OTFOxbV$^2k_$UFB~MWC4Z6?Lu?=9Ncf(bXVEO(7KU{`E7(Ji78BTy^t+6 ztC(#b&QfyN&nm;Ij}%npCK}j7LupQ5Mj>u7EugW9f-kdU*draXO^3OHY+uiQn5uCi ztxGotSPs^EHL(iIaIzo~lO}XKg88QWlA(Ab^5*t^31QA$BpAq`*ozs(4+hPZ{pJ;F zLlH_t;hEJqaDvM)BSzaD^@sJGq_cKiEL|$b%Jg)_AcH#sn61?hWHMPxtu9*pCUHBb zL?V!|vaZA9Br>rD=0`P*J2Xzjo%{W=+U6kUDLbSM)t0Mg;XZWJrZgFEVT47ueE7f9 zy%nxpV|VUhPV_NL4=}qRchf~sJ~@f~3p>XAuGX+1N1XLZZVJtwmU@o;BxAn-833YD zM_BS+i;T0VIbEvNATS5%;$i5WH~06xwb$PFP-wF#lUdU7!J!mc znGva6vg@?X^#z3i-O954P21)pTejN6Y%0P!uia>*8+BO1)cq7v@3Ao)E6%HO0~`$0 z+B-fV>-HrVIEO!K!nmRZm~Ck}HV2#jk#4;=Aa-c|Nehjj>@e7xf68D?6=s#L?#@kX zh||Y$V>UVtHPs)ee*FhZ)^BmMO*_`((Z0@fso7j|p&!voXHU&F1x5$JQ=m!L+MM}~ zC}u>Q&rIBI46_<_B2KSG_(vmzl@X5QTJ0TPtmU+WFswf|8}V|*+70f}TZA&V%^9-P z?}Z6GIr8X)UC5@L{zTV)v1<}^mE`R;`wiA(Csp9givgC%n8k)d`n~Os8XIKXQ-=^w3kaYZLE4~3)0F_F;-vK#d17q7P-!YI9NT8-KHB%b*{c+B3B*aZN`AR`d7gG_&`oOO;m! zKb~73_`+-;?9Pq$L~B?W#_}3?fjqxbF$K+6nD}0vRCX}dbcy9-f_6iQbm+SnYnb2S zVIYkNmI#v%vsGvLuLKi7CmXu}gWvcxNbrN80w2N@Up2gl@1|vD2j_9X?OtbPCjPTIyTdG zT;z4+O?T%&Cy9US8hSr41k?L!Y8u0e=eEHyE$G%v10>B_Yls3Dv0vU``pzB0Ir5jJ zC?H!6m@my0k7My#Ns7tHPxulzn-^4nbn`2Ympe=ECCfvUYtmQd0jUw$bQ~A=f&4i5 z*Aj<*W!Onv|CASu|8VU&i9%m_+^b}_4ORucPgGz<(TNVjf(n>YobI>0K}}->e3Rwf zGrNQW{e@3!EjxqyJO^C3bn#px_`v$S(=3J^%j`U*J*Ta~rxgqQ>W?X#$a_cg2G~hw z+{S5-nR;qK(~M-WZ;@TE>ZsKTo`v0(L#~IEwLZYY2@h(DF@|>% zJTLt%dx8%65>Vg;1|~OtA$?6h9WLqP*eTjOJ%WKpR((@&bm98W5+BYr>0v?Pv)2MUyk$IHoSEI%8m zQL-&W?4I{Q2~lj}NAr-vYuC}{#b>!AOO5ZW02QljR-@#6Ov=VJV;dW>p;&ZMXIrP+ zA@;Nv2TCoyOnG5wHu?u0)xNNFR79S82oIw1IRWAd%-8--V}ZO-3llqZL{g*HEyys)zh|R+{sX2WMmz0f!f17LOIad2-^ZvD za{@UI#J@>wY=-tSBRtRLV*zQoJX0i@)I|UI1ds<#iKeCZoJ16#&mAYfwG-ONQ#&6c z{}P%NrrUo*E0}$PZnnfJAd?9g!L3-L+gm98r1uy^`DbN6tgRp4y03DAtRHjeH}6VQ z;%v-Mv%J%nu^pZ=mbo7FjiwGIBn8FwK9N(~`hO#V*WWrjBlNn1C-gih>GJI2n}25% zEbGI&#+C5wxGphMI8ko}f@GZ{KW{K2LAoRMRW2~_ALB7o#BEgTNpFSIzCb7GewD2p z^N)GTiD0>cHs&r+WNZo(-kL81ut6ZrE>e!449$c}&RuSTY1wgJ@)$FEueSNdclC4Y zbIuPAA#bv;;`)wIZQ%O_7^-s`F|=C-ccENk^>><+*ab3lfTPv9BPPCZv<;0AAW6a!r6lf&gH8saBk0S~SByH*8$A86@*J)d2k|+d-7=LuRx{ z>3j?f7L~34!NYzIof8_s5`~`(YGIY(5_b*r7^luvPDSRASRQRyZe~)rtzZ3ZW->33 zJGYA3FJ0_-mQC$J$}(0=_T!{JDfymF|6mAV{}YP#me3`|RE{5umWU6Wc7qH)DgkxN zlewQ1x~_>;S`nw_fQ#|$kGo7sSCCdt#6JbMxx5J-DW7%xK|-D6<{>-s9*H#0&MZLb z1G}`#12p~A=^(>k4a=5v&)wUU21h>AZ+(6}v##6zLvAbccn9x3y#2a$+|13w0{|A=?Si|9N=_Lz;&gQo)2Gv-kl4!?vUtI;4fE;moaC)WLXQR&@hbI{6*4f7O zQn@j9`KbyL+ThSVsIKo4#U;l!7jQ0cd66?R;x2#v8EOv9Q}g7>|OH z?y@4HR2LVF@e~TgBUBH^q6uebt*<*zb`yPsARPQb`-t;DZis~tBSLpaHsA za?UVR*I2i+1+*yp4L5NBXSDgefzYYD3#nWgW3u#Sr%~|U_Hfc?mj`8dKg^(;JwDDJ zgnK?37GV|wyDqh?-|V>@=&Qhv1dQEH7!OBRN#}G?s~+ZxiY}+?Ed(ETK7t*|3We2G zn2<4dX%+;2@5Tpxg0Rr1S7|0}2%h3+c-n42p5@DnYKB_@JYdbD8K1G)RX8bzJqy2< z!U5a5RBZpTxIdqL)!>XD(A}M>HkraB#k8ADXzM6+Is5+bn|NIPLD}KBi)~emB7LfZ zuWq5aA4g?Mg^sEoNbo35{ztc_xymy)@oNqo>XB#;O#Vyna9~fdLh2I64a9XS^NTgb z{trKd=fggUZ9^=drL+aFBxfx{Dio6otrAnYEUH5vL2V^ShEp2wC8>jh3LpG;hU_3^ zXN=#sFQ=P(R_KW$wotfV2n(}uFa#qZkb}h!M3UGkVy`_lgDp9ysw>l9Bs{-Kup*ML z24SzKLq!9nCXOlLc!8wLaPS~qPajx;W3>qqxD7B-t+}h892dBKkw8Ky9Z(oy7~?-e z=txd{`&2YGKaKxi#yBI8G0x-lh4BDm0Sx|Qa7s{p>- zA*8jKXi<3`e8a)q)=`h1jOdGSxLMUbyhCDN6bJ8)`69zAu00>ijVJvsxAgNYcf9d0 z(t&U(A)amQU%w6Q@PeN-YZQrDokj}I7Y4q930M}tzmWxUu1yIX37Rl=w>yA&bB}*Z zI@R1q;S|V;M5q_xLU?3TBP+MvWBA?4n+w_y=LG^EfdDyz?y9rMAxYzp$014H&Lu(s zU2btN_=xBQD#PgBFMzMQ@Kgg9~6)M*N@U6qEU<1Owz}3(Oec3Id;k z52<(}#@sNVhZ%m4UVH>5i}a)}lA*b>qgEGRVDoa33EtuAhd*%|+RrB2?oOhm)l8M+`+v(f0*y+o9k4X&hx+wCIYVcyZ7yIzpk0 zOTV$Vb6#&~LiKA;sSI1uj!ukNQSDn7@3a+OjV8k$j7(9Bnrs)r&HZKjdwiiHe~J-V z&uaq4am~E<;yC_TO8=AYc;?3rpDiQP_xhuyDEzplgxhC{@p2(MaMH-r_ikQb7YE)M z){(~2{XXm(7M%W-rHy#$4SRKvXrVfis0)?|!GlOZc48zBUt&3P6q*=HD+o!{x~vZp z$3m}<<%a8bz#gJ5XvyU=IM%pbQSD71e`(5FZW72FbUS*Y^t{BwRT9ng`5#NpTPq`i zp(nktQxDm1opLOnt0vhg#I0Ck1Ck4~tpKjYF!z-p&qqs(KeL_SV<(;pq~`r1LO8MhLEeM2Vykb;d(1fxflPSok@;}ZCvu)#xQxO4{q^3IIs0xrXY|B z3Lv1M*90<(URli;a0}&83GhrZ(v@{fhY;`N9 zPyLMib+v?K|5y2k>q`iMzw0uwtA9C&98UZ&Wn4i^wr)|7A|H~phUsVNGhdi_ z5K((Cn1a?U|Jv>>!t9)<>kdSg-DGn*j(Ep{6ydXUmRL#`lw+ zYl|?;eBI=nVGOD8a@yf(cMad9yWiZoyx&^fX7ccy>uLvLt0Q+e!J=yUfIirSwf#Mi zRiTLDQQ#slmbRdc-|JLLX86!RKs;>1H#K(TrtzyEYSm`*WJz0 z31oU$70(RKfU=3cS1w6vgo``gqDPAEXFhhmkK?cR#lpLU>tOVi2x-(0e>=8%AC5k& z{`NHJ>zkj0JPazJUyHMMC`lAtA8*`=zi{s%8h5mkA$!bF+`fl8%`gm$q+A5t>Gb>YI1lVK7}=6KdcA%{;Or;Tf?=| z;a6ai^v#2JX50M{M#9;yo*X0^k-mttlrH@~Lrruf;b%b6vs7$Af%yS2sQRF1^Wt;E z5XUc9$3?W~vD8-cB}~})^X%s9{lrys>vs7C8B9`eH^`S_E8RNjlg))F8qdSvfSU~E z4|4MZcQuv#CMYKB*VFw2YywY9KWT0CQnQy2QIqPi(i)c=b>~? za-WzbbLQQ$#dCklrKJ~vVWGNS90X+x#UIgNAs|u2OsObSxwH@E@FuVz%9o7NW z1gaW=Wc}S0_o?J^>3Ue4es=RNh(+=%lztQIu?-~y0?zs!$|x{YrLI9Yqkp81o)WYc zvKPIV&7E3IDE$cD3YAr_L?}r^EjvcEr}}C{I&}jC^6f>!&uzpxqpTUb!b@KKisS>8 zHPw6z>l1_cJ__(@i?>(FHfgV0Y*Cjk1D(R>;nNzQ7!)QEQmyxAUZzWmRNW{ygw1KefUH6~sALHOkuEUeyr zh_xg22MjK1uHuJjkGzyv>69^JfnibJjtX81{lYZmpo-0-dW}*)%1!u57t#wJqvs!- zchl@BD{itgKJ2quSYA%Ny4VQvKbn9r9je!UxkpFRx0lM@&2_pI_z?Xxq8 zKag}GObu&Pyou*s);}ZFt&5LCEXs0PaAb@*iiZ6`cpqR}mWPC6NHHb~mdk(-%nTsZ zx3^o;>&YcJlZ6^^ILqL}THu34*3~$N9IL%KlfUJ}??rkMG}7f^e^%Ou168!}CV;v( z$0%6&tqK(HHBpe*1rhXuC0E^Q`)5^5F?3wqd#?42^Na`Cy%P7XI8GK0 zSJ5@q4l9Le(^vBpb_pq60-{{Bp7lpEJ;60zxDWQ&ZJZITZBR{bo-0y2s;wqCit>JFyR`rtWhP}g2m}ZUAKFj z5_=$C!~dhA7`*uepmd3Fy1<-DFhSzPylS17o7nZB(V+^>zd`_&Tg@X8L+sfHt&DIG zAyFg3)8t@*X-%UdGOnczwKiW+CNH>b}R%9{}ZYw+XH*w=<*rtPQ1pUk4vIFgSXuyDUJ;XlBQ z{+qA44A>yLO9x*gRjKeFVA3yK0C?(`H*)|nemPAOL)&T?#eY2bm*LXIn}sUx*bkG~ zpg}U`761ZbDwZ=#b1fNaI?=J<;D>$-Teg7>yO7# z0`9E^w@P$@>YK@_A#++{wu}Qe59l_)b+63kn3{ke8J#7 z@bV$ExKq-kQ*mND{~LJEYt;FaF5D*}4C>w*F0orn9T|GBqGtyAbl#hiaGtX?3K(Vy z>ufdSrsPs%J~;5gpo+>{7~>)uYUnc_gAIbhH!Y2B@#DJputzM+{c&~PaLV_>aGOYU zM>&s02^+ndiV}?`rbjuS^FuBR&uY(1zX?@{wVFJwaHSajqn_$#U>&p&sXtDJo^Nw^ zG!PkNVy^8+T-&k~Vw4#~$LBJ=bGn&yar0*cY7;am6|>;C~;=l2U2+?kcJnTuud_aSKiBedGU)Iky@^!|{*n z=r3Y{2~B!-O01ichN9|7LX<&*cM+#>+FBzvsqP%kiqS(%p!c8TDPu6Xy|vj)%cnh_ z@aw*)T7#UYNJ{BM*}D@GcvFjvJJftZ%lq{O-A#zR77*hSUC9X_hv_`4#v< zCI*hiQD?Y+r(zpUeToB*@EweGmzyzZXh^zEkGCKN@mNsw#3xw~)3cw6_okjU4g-uk zEUgacU?FD3%W-tO~$X!S5{4DbhsngWjQ-Y{b7sVhW}#w`2`lg@ml~wi;v2A>lklZ{-^~D z@1b>3BY`7PdcvMVE6isX@~3;ElO;1~rxdwAtO&3RSU_a};H+miajAo(2=NXca#%_7 z;7wbEF0~z>ubV{h$n~mHAV8s!B#;POHeq{NrDGmO@L4rPe_%I2|7GY;o2Uk$lUAHv zZTne4?%`-|CT=fx!pxSnR9ATsEHymz`r7G{OK|9@LLOiD9?*qv?kwLAmQT^!(z%W@ zqD`K~&H3i~z32Wyt6qa+7rVr_J;hd0S~+nYp8^jmR+ff)>)$`^A9rINFQWJ-&teNG zkyjnw&e-oP-=I@&;pN&=FX`+xe3mHMO%7`j&P;43bluHZOWV<;tE%v`kuM4YRoP7| zI0o~U&-V$@WmZ_GW(7ZR$>X3$~*;b#?kA|33Cl zA1({q`8$?O9(=t@d!pD{uJD-~%&6Kl9AohBM9dof_z*nX-q0n>MPOl`{>IPGn&d;B&nQ%WI+Kx=9ASD19hVxRY?sxHlPoCkT% zm##6k{bEkf6)*FCe4xmbcOdPFXQhX%!wsbHPh46v8uSp$9e``SWDV~{cDEpz^zUOq zEKpGR==H)e&1|kGthO+Bv%sj5m*WMB>*@=tt;9Y_X|g7vEu;aGVazkH(l;)%5^|PY zy(2_S@$yZ=7YTb`CTOyL^*h;sjbjERkE$Z@_X-9R2m2^Nb&+%~o1FSYPDwatF$XR) z^;|;%g!IKJ8`vJxBkI!e!r$}Z|Kx|*r&m@~c!6|rnox$f|4SFgTIv77c=*L4m!mnWh-q)1TbArZWcFylpx2A-(G&JV`%GPF5#guc*#R0DoQN?(@pqYTl)lWY&q z{*@^={dssOl;eftT2=@heqUbiXZ!F0eJC#J>f<BIR3JebM5~a7-Ac}*!}-5s;n7sb%Gm@0_88v^gRTie zcXcQe85fTSkHn4gkDw(q%>@2b&!5NaJH2$n`U!i_t0_@4DwIn36jQEumZx|&hV0=4 z>$W8n#UsW;vER;9@;~x)7_>2{u86K5>`BT*mMtxbhTSZBfevli!*U40YOSo5V$ZEPyoghJEH{!jpG;qLZQq zMKJ{>RMg{{A56j-L+OrW92Z?ct)No^uB7IdR8QDFmc@UUjoFOZ-!CBIdG2ajhj?#! zUkbO=<6B{TQfj|%9+3r+)F)f25Y@-~eW~9nooFm@)71Nh2%iYy`(BBXA$cp-$`5_! z*lnxcE)alxA+@fRGU+mF@moAPWK$0%!&<(!x_cT*qYSE;MrSGIVKrg%*)TyEd~Eja zAlxYk5Phuu3{PoqLsPp8*V^>V)~zcq8=<3wytSZrYsj~ZG{WbhA}7SsD)AX49Yt&_ zpy8zKjoS2n#hjTkaSgEQUH=@V)qHARs%BACakl7OmC;pLZo@l8J709^tt(Y=Az%6U ziTdTK4cw}{tF&dg}W@GzO1C z`-stsv&igI-Mm)(+D|{V#s^>tEZ+mFwafB_@SR8gqFn*DKiotwKOX)NmtZ}#^0NnB zafUsoy#H2O2AAfqdAPhEqki+(1Q5MSL4lex=j(9>3HpQ{co-QXSmPZccqW;w_Zpb8 z7c!|BnEQRpVXBGyMiCF^A1S$tHax+gkaeZXF7+6mT{d@m`BEK&r?a{8_jjw8A@2 zBcXL%puS;VwK^TKA7DVM{96Jqo=?Jizx*1$JCnZ$_iHDeC&$s^r-bt{+l1i$d$^iw zs>VfnhiBs<#yOoEBhiSqWZBOB4Tc5b>ZYy1ijDJ>?5qjyg9bIMTw)k0EHo^rWq~~k zfpM2GcNb$_IQQ9@p|xDatZaLx2vfw+UE>Aj@$u&Uc~$57`Sa#_R9@%G^_C0$72Ls5 z+t=}>f)T*c*|}#H6FeI#!jh9BLlCTjqnkT^Vy6Y043hU6`RqIAm0YPxZ<&JfrE+As zgvf0-dFPuu%4QS=d6$r<3 za+m!bO5&*SVZ{UJ+QQaLGp>Kg%DHw{WTJ#O_q&x#fgJ$4dW0`ZH*S z*h){m@nK9s;{DpvckGT=REf>hgaQ2RqlF6Wip z*BeT`_zK!Hd8N{vAE|eC|J1}nd}dB|1h6Z#AVv0ZIvHsv7)@^QuH}vn7{fic-B%G< zCD@t$3HmOgVqix#yDq&slEulS-pgH(S0)iWvSzwDGMU6-T6BL6*u{M`dYDpRu?J~p zee&thFTvF9z=4X}YQ1?K7h%{K0nI77c{bq#Va}Qv7xxiwRgPmHJ+Hd$_2_PQ`jmb9 zo`MhEPw&Uj)dhWhI!-vFzo2E1!KDx~v~BZ=%SrZuz}AN2>E7E`J4cgm^?hEUI1|qE zkWbGc#`V6_Gf7~@c{Vm{TRvw^%kA(M1BK1w1e?O@I~IXMouaLL1^(HF)f)aphvBiG zvsk}@jAO?dws>K}T)%s#(#-61!$>Yf5GB_AQ#TsvO17j~n~ z%1bP#TKa`3i2CDS;q}874S?3g#Ef%tHX=j-W2m=-gu1n(I}hySabDw8AYe7X@D;9)PYno$86xdp~i1RZ4DWR~Vt zZP6D-k##_zdo2Mg+5aKHKF-X%X&{NmiWt3H66M0*$Yb*K?&;$*(ymp@V3xh1j7gDY z`2u!{F3(=IDKW9$K))S*lXf#y{1#LV6G?LzD0Ctc5ST<~b&GU-O+DK2+Wc zFOeVYH#nYqIQ+!i*0N7Y+B~rEjzl;R#z7okZQiXH+ZY~1442Rg=B9J_v}@n#Oi6)${B-C zB48@dS801?LwmCQR+ag&`XlE_rnVeKOaHAj}qS2dL4RjtPKIt%o3Cxh0HwJDL7#3`kv98(; z48N<2lQ#h5Nj+@wn-q1ye@FmrEBNi*zLCJa)`10LsU$GTp34E$^bioW@ae1%D*K%%w7@@-cju&l!Lht;o`2CcT_K=Vk8 zMxy)xPKGbhyL3XQ7t@3H(%xdlK1;)l?cFbjc6w?Ph@oQgm(t0kB_TLGS@We{X-wc1 z!y@qvle5LNzi7J<$ITlv&7eKAE0Hy_V?z0QdGOqpNQSjTv@2ZmNaFvkh>1s~P1s`9 zQ}J-Hh_kc7u5G=ZPS+m{*)t!Sy-nhTGg5ZSSWpbVZo9XFeCiwf7JD-@Z9-%I&>GpF8D#Q{w%R{PxA#Tdxyb`MKlr7A;3EJGZUWa*SJ z`i#tYIyWDid_soW?AK%p^E9BKl6IJU?Nr{b$C~dPduZ}=dTS|qI6500 zLFBs-zyA3&vO5D&TPYuP61Ri|)l$B<_4w zAqqnbw;o}9QPsof?!{bIl^M79tlNQ)JVCOL*ROUb0O6l4Le<^#peB4j#(doN%3gD7 zs1J8}8uF}e>C3VYfpC=av#@UQ;>~h&pUsV1LpeJCWVqa6tRB(`4dG3fpSAo$+#PNw zIb8Pr5Ac(DWl{|H9AU} z!H2l6l1HFxka7<4EqS+fvEwVwz9+GwaQ-q6dj=v0nc|KRGh;t|K;Q~71U1mA=fek} zfRRB|{?RsoQLS#OX9y8YIh6YQg;bwV9Aw~I)XIN9U>zYC0EgK`1Yup`jq&$6kloL{ z5ihue5US&ePo-`T6R=kUUI81RT^}stA1wG7A_yBmJ((n&Z(I`NLj_Sus{jZ5rREEk zMSo;UV#S2SzxP^TA=J9Ffym`4cUmyX$mQrfiKq4|U~1phkij5pMPO9b8!rSgfj=h= zqx#a^gIum@WnuvLU%SDAbZ=kSi2lA+ObWbTLg4RX`YgXoGAavx$Lps*mv;>7q zQA0xk`U0tF^Z1DKS}R|=XTM2kQoue}_nc^m+jV={Hp!c4 z+(&eU(_k9ddCq0i{o9rsun^eSZU#>8UHd;ggY}JA3%(9ZhVM6)ANkLjJgD#0lNxLT z=CwhD`qAQcfd-jg3JJq=jmUAi`bf#`@_#({b2%bql}04qrcS$C&)mik*9PP#eEbgh z%DnUCR?-N)ireUiXw|@_ze@HE&g1K$|8q;M z?>or4O{V)IwN8^lkVG0L8J}gMT=t$PB$-HlifxsK>~dm>F`28o7*dwx?!bvZ^8u=l zj^utAy)K9XXk#uK{S9}q{kU~1{>4QkWys{6G($)f8hz-UAkHdqjtiy?h{2_8(&!2@ zLue-qn2{|c4v@_z4}{cz%b-a0N@s$s7%@TLK!g1MsU*=)b)@a0tPQGzGdxxtIo@M%4O-m?Cp0!lTmB z^+yuvk-GV&VEe{x6yEM&s%*<%R^bIos_Dm>nv2nEP#Rs82>TT~x&QPThP;E%Zeo35 z;egpAhh}eq`BS;QR*YZJfSFubszEzxhKg=`{&$$B2HTXVapMNnc2a`0c``&xDn0dw z3Bb|+Ixh%)gAnpQH~H@{IR7^cnUp1y6WRY?srJf)=a8&2b*j5tffulPAcT}nV`(xrkkKu8ytpA@I!>80!{J)K9 zQ|WnUHHgtjjf1hdcACQe=N^HhZD2q;*eF5v+L2}MF0k#6Zu=|&n3NJ)2h2q;|w(nvSbbx4u!?(R5r$K8nU_kMSb`|JK; zjLqI>ues)&>zT3UTsygN3HORm#dqQ6q_hb+YdU5TA1yUMRk}w+CAVoP{^V_eT5dfC zYSTEe3YJy}=0iQrMR2jofu0XGQ5Ia5uOz_0Qm2Ab?!r?gJ*M7&31i3qY0{(lIGa*&djr=?P1v-Y5l9L=qKmmdVU!DFB6Fg!ctepfgM$a#BMDNeLeM^*Q1wV7{-mkIG}rn)@kS!KdAbJ^OgFVojFzP0N^Ec`i*2IJ3-?*Ra zLCc$E)ArVRs^`SrmAMp^LVS1;Sru!s^J`x-YmmoDMPYd(X0qgoXJIh+4rF0yK&K47 zrYbRDILw=0jqXroLmA)1+Kp%gmZ;Z|urZ4~axT?-C zvH+wmdqGU4uR{+~q;CVd+&U>v+W!O~an`($aa8)+vKuM<4sfxuPI}W{zb))-c>PxC zYr-^ux>GR#HBl;RdlIB@#{@%PUcWtUPRGdLiV59&UO!TrV$$-m0Di$RI!YAZ`6et)qIfDr55c{f^kw6e9VYhy@AL zFn>P<`U!q4Q<@vMM48QkGUa|HP)-~+1L;(HDRlgJ7L`cVh%fLIzZiiL-3{H)RWK3C z2Sg)b*Vk`d-pB96W)zg=8mwQ{#HaA6K*Bv!g2M={=bYWpy`bpde}qz`1wocvce2C- zTj9r=weN3xeG4EPCrd9cx6G|K#t3vc20sREElNH7HoR7za#KhgeJgs#(h(Jx$vI-g zjRU)2^3zL3TzM=cvwLkDT&#@sJFw(!{k=mE_Zzlh3oQIOP>3}NDv&o(^e_=+2|HHe zJ`=nvPRm#0%W9B43&C5h&-_V3O7#8*Pg;;J6$ZkB$p(-7f`!wPhd#XccSG*(+zo*n z`=9J)QbUcMYDBr=L>Kw_-NMSm!6Xk_xWy6otA^J_{;URH(4zB8u|Zg^1FJUYTm8T( zUONrlm40368o_6DBm8EB$H(dM!?Tw@oRJ7Xew&lZgO64@ND=*&#c;~;T7SM;avja< zpUWu<4SVSVHUnd!kt2y*sXIGYWB7waLG~lcAJP-0uwyzbPWNQ~K(I`6@L{NWRy+TBq9{;b?j z<%fre#oFn?^z#qLL5cZIZi6hFLb5?D->(oziG2_svF#*F45+cZm5tq}yf=|J)M~*9|sn5DGaI zKcHNQH8ypmj~N^!wYWfpXH!+#rTNWzhg=fx#g(i!Dv6f$k4UAk0=&z9WgpzuL(i6X;2?84n#D|AsW%DsfZUk@m^&XE9oV#XG?G zvH`YZ0LeuD53_2jw+i(ukm#Dh`t2YlRuy_gg+I;(Gf1A_>Av4qcdlU%$8pnm&HdUi zM<~*3UTM}cF_R(HbCbdC!)fS>cmPhnbn|W4TbG^NMg>LOGH&k!RB1V}_pDqj?Nq6zMEI~V2l^r8!~6}u;q11v zYSu}65KM7XK+ul$>hk-hxyt6-xZ`8%-t3a5OTM~m+d?!Y;-OM_?*@HRM>U33%h4pe z96sJqtD%kx4TX<8=>BhvcLV}yHTbA>^R{qvz(+baP7Zm^S3LADC?B+}NJ3M`vdfx8 z63<3eAvP=JI`gGDeoi;la$JSi)~h~&XE*rQdD@%jL^tzM1?_(z`tU`H=4_X=Ko89B z345J-SlQN#_DMNbnKAFXH=fv~XD311hDTRIs3EN;$CbVp%FedkH{$)5*zEP65Gqj? z+xUNKP0>iwXZ=QjkNLQnI2KMF#>qpW&zusP{NnnvRc-NHEM37x~MMU7kBd##lmfC?k`mYUCXqqsuwneo@iRsO-Gizgt^i9yg|1998jR zaXocq(`iD^L@skxw_i)-9&14Z@E(rda-;Foo?)9PE8S90ZA*O##J)L{SFvDJtD@;7 z9I}vYG~T)J7=KUxM@SKC9eH7n3mvCay8b1nLY<4v+S#bX@naxbu=M=>@z(il?-J!A z;+y!BKc-D~4sYdZwEnbrb{HtxSlX4p$K)vpE(=Z>_2baN^ZKO@AH!7k=Us0ejoYh6 zaR~9P5fKmGp2aI}SnN=;+@txoxdLyU=58`)iGQXu-_1p9jS~qNAt_BdH zN$1w0JqY;&6dPh#rw+Iam&9Qdx+;sFp19#(n@~GXmi+qV&N??H{JSk=+#a6anpUQx29*a^7js$83bQ%F^^}rHrxm{&Gt?`X7u8< z)0;#J7(@sA(T5=ePA;Wu8y5{6G~V9Foh+Vb%jzd?knWGrLj|l4G_A@4mz7jkvLEp0 zF-I?qT~INmAjNpdt%Scg7WcywJO}Ax?%Thd`uAa*;85IQ2^4Lhxltlq8WU~|?p+(Z z7;VsJEqrb+3>+f{Nq85Ll@Xim(e24QG8lkHkP&qu2nfUpy^sy4AULmhe}0`C7sH$T$=Pl`{R^jb@`k9 zVfUT;v|8UEUSnd?De__=owl)<&t^3@PA5jxR{~Q@MR-9Ft=<19(?47ui4pe|??#ampyDxZtpF_#{Gt4= zA|G_JEa0CO;qJe8zn$8c6}AZTBI{L&3xPp*&v~8EjfA@@ydaN38;+)*>U6 z3$~epFJ;>6P(OOsmqTQkzua_=GE@abD?PedJoEIfYOTv$67dqqkT8WsFqdCb5(V)w%hP3ZRl{}G=g zqR4u5qKvO6yq>FGL`G!SZl~~H#@c*OypG4wQ$He&{1A6br*k_cowzEJ8P|f5U{dhN zeb4!jbaBb5WQEIFWlib0ncb8)Q&?8~>2_il2R+Og3f?tW@(WWK^8EfX|HIph7*{qeic^WRa!MjdLIXY5_g2}iGt{dDG`PGpA+pugYS0v21F#y)_!AwdW~E zskOd!7`E&H*T|n3v;lQtJ2f6)nfUVi(%=Ho&ULL|Z?_lV+q zW?Q~>y#;d*t}D3$Tn}+EUEA6(ZWN+HpNa0#qOq1!rm+U(bNNp`f#&mir`cm!$3Q{P zcjvzndVDIs5d|G5zcKsR_@9JMYCkR@$o-WNLwpZ@J(|XEX)lE(k08My~n zm0a;TUjnZKl#0fBi`x*eN(2zdcMgelK&MwnQxj|+o*Z{wLw8A89UwHZmfV);)eMX$xJ(Lb~j=)r$8a60NIEz z=v1dhr3eQRzUgx$ZzRIT;Yi-30N8U+yK?_7LF!V;+&1~-=NT5OBJU<40e19e0O0Xc zQ!S!qp7HiMu=Mo(?8~h#Q8C+W5^WMD9)cKYg#myMoIOnaGP^lLEmZQc{#vdZO zExmk@+wi4(ZxCZ*o}p0CBq@s9qmbmWPnT4u$+najk6qu1{kRq~~#3JyZVgyG9b@eAt+pYYRR!tV!P4gyG>)Ybc zM>x#_g0HopeOPy};-b#^Hb1?i-iYlC=Cf2Hh^@e0jq#jym|OiSdv|Ls+Kcwe@_EzDRpOsz>dAmyUW-+rfkE=r6a4Y?|)z zQsX1yerCx{+Tu?%yV%m83n9b;@O9c^UYZ^aq$GxYmyDgu{9X5t*4i0PF50YC6nOW! z`tGT=It^nXBh~M^bIl9d&E8OLU9SBT>0Enfr;A^i$F%WH((9H5!@avTI^?6MhRBB2 zwDr;LLO^xia)O+3kEArq_5$>bii65VY(={xo=M(fu*Lg=I#P7$m`t7WCO z!h(-Yc91MG_3O;?GS}Brm4c^~28*QcVjzWDePQ|QW=1neI99w^K7q)LbBD)KaEved ze2X(3-TCVVpRux7=Y6+uMpckjV(`uGq*1yGk-reHOUpl>aSiIH_e%lSMc=aA0r#+%L2*{5EFv;_`|tvN~-+^a$F&)XcvQr*6 z8pRy#shNHw!$%%V+Oiv7z1vjyO>WBB*Gpjng~l^ApNU8If7iG-DfIREHSk^!UuF{% z4ERw(GI^XT>gv-c!yk$_1wiQa3x&kQLlH5*7I@vBH9g#Jg^9G44Owkjw_w-ey8ooy zyoo7YElK;fFo!*dy;w(O6WpIm^5t()Mg<0iLg!YY^VV_ZK@WP(q2fR`!^GfnP{|AE zPyqwv!aYVD>y5)jVi+q{18}VV>*B%)CyRyF9sS0GJN=3A8P!mTKH_B)vP;c9;5OX1^wq96pr(YsK zQ>(F@aDn~`U@I;d@9LhtRvV%w)L-d<$;;m%A|E?2Y9bV4WG9RmmVLBxl)7P@7|(+G zg+>2e;f65Vz^SKw>7*7fgBYtO^bVHriaE{A-xu$bSsR2BjGrp_s;{wLg$>tKN^Jy^ z{_-JdQLAr!iuTNwH7PQXqrTnk8V9!SNoK_gTXccl;JKzqGwQmP~LUwZrs5Ju!^johR3fEAU=jv?AP8lAdg|d^nkyk~wz= zcPBAHR4^uOmeq6mCZs{y^$EZ8DZqVEC;J;s^5CthO-4*4w-`ibEM2Gi9Le z*JFaZCRKL^6U*d;^9S;~@y0yA;1w?S1SOj(`2HX01+T^j!!@bn7Vl_Oi?1Kb){m1? z6`Wti(q+M9`3g0jBHYRQUxt9UdqaKm#@m=9sZ=rGE2I20VC=P~lgMgf;eTpVQbm;$ zCf)Im+fFkk*wIq$wXa9U!D$i)R`TZ2nR2^2m{nHRIrz-77-`&Dm|?G{i%1z$k1KxS z+2zZl3rj_B&i%-w^V$jnpE{PvV9*2;X7Bxw;IjL3tEwazxl3)tc`1deIoC>9z446R zn%4u~bw~$POGyuvDm6Swg;f&|+Di+Yz@r*966w*u0^lWH(M>+7&t6benW0?t|+kc^2;P<>wzjH*Cr% zH3Jl;^K}H6q!#(VNke>7+rZM6p*VVuH49*t`(7k z1GVO;LOhKY8}dOcd{G@-@QKNS_yP6^{s&e4I4|5d$SuoGVE6})Sa}Zk(b{$T@RB*| ztGw@MZ;meHVNHaG;?+4pU)fNyV15lyUROs3nj%NmrwdaH7O5RH;^ufiTwAAHY}U-{ zSqCdg-<>hWB9*9j)?lxLb{;P2OHFoY6L380H#(veKY?3lGTy{!FL{h8>=_qG<-z26 z5@6!djUFwZ=d+yYvhCfI-{pSaU1Y!76>Xy1x}KG9xQ6{P|!D=xyOLfYND zWwqJEji$ga>0arZYWqn~Ek*I#>2Mo*9ymIImWqbqm)3*#;7LN;`6gw^@OG2uzDIrf z1B6f6d#i~n*IQ+XZNH+SVhnfKThmE4dvr8yjLou2is#@H`#0+0vwX#jhe`)N&PIew zyCCh-<4(F@y55WUf_wR^)ceYlJ5ukAt{*%rH;dc@N*myxtD{2l-kRKA#PM);weIUq=8(P*3;n@n~jFH)S&JT_1dPe!UY) zxZ7}U?X9Vn|2+Uoa~5EvwtpX7QC-OGt*T33EZe)Nem-%)sBG>=t6th)!*DOO@7Zjr8YdlE8mt zZ?4DwKAfhyZO);?Q6J}M;Ay>KUNh1*EQ=FfVzjKjnDl(MxYEvH^n0ec1{eD!t;oWx z@npe0LV3hVK*MR`pH}^yZy^?)#>{V@FukyExE?JYA^*S8fjUg`M+@ zP(q%Dk>g?6_=pmttJ)j)dIR810`=S1!&ODZ&ff7(dwWtS5*#{$^>LuJ188q}ijFBr zLtZV?u@~9yfPK?_GrVZ2JM0rHgxE*04BN~7co&km8Wc@I(-LZt zsJ+O?F4h}+V!(K0IzsGpv=TN0EXND%e@BceA;AYm>|W@b4g&}jtM{`|SB<2+VR?N2 zf8I8o#`Q?uzh|kvjk?@t|IX*%t+&08LjGkqrJ7oBn4GfLlob zw@fvJQuq6l=Zh-+EOKbOa*RN()g1Ot6~J&mN=T9b(xw5@`T^360n#*8BdxFgBX=Qo zfcvB6ejW`1_K(bD0VW49v*sT$|IeHD_m6r%{l5vi`25IPUKzE>AYimBV6-5B+@Njb z;~{{Ni%DEJWh2PPOgchD!049${r$fuETH|#p6ZgIY17I2G^_f}eXGqCh*ICJ<@#~V zy!SxOs49OcSDIDwNj1xfxL4^|W*LvAbN43jtys^dlTRg{2dbO)ZrcjiAkm4!8G+kOGeC(&dA`yo!&jPE3Vhsd$Fo-P3OXowozF28gF7Y?z zx>}Vpk)1`bfD3+$4Yqg2J+rP%C(CBqy@S#~(wcIG?j=~AH`A8_xfy4Ij^9ET)f^jN znn7Kbd^m|NUYEh!^S-qXa%tm~DRrBcncSXj(6k*3W$Tu3A#%IamtM7aS4^>u1cVO` z?`E4rNhO#GAXv?dACF%ia7QMtkO+r`lK))NF;w*p(cjrm0@2KA6gC5TEN&yNe24XKj_ zAs~M4ijQB-?U<`W2hWb8Y}xhZk88>u_8T(UfYHtbKKDc{d@Zkp8ORsHpb3pF>8ZFr zji&f1p{q;C$yT#|TY{~>xsXIHIWDw=4C@yX}cV7Kki$%ScA}MfE+3i8r1!Gd)b~<8Z5|1N==NY zjN`e0#yjT>F8Ek>uiTyy%j9B9p<-To`YaoCR=5ssY9_5yb3+bRRppzHl&QzbJm2Dr zZ*5p%T!gr*NImE@-CdTS+ z+iiyl!^huamM~o7z~W`LgmAF(sgNaDLM`F4}rW!Vdd;2(HbuMjRoRUc=>`p(k8YPI(~toCgEd} zWLZ{wsUKWtHzBD4_Nf%Q{(Gj?E@M}BumR?pBlw2y?lPHl-)9E1s6)GtMdalpzwcdnT(xPzK+-cE*)xYzH`8A&q)s=*%a&iLx8wJ?rN zAp*xo)28D_^y!c1_~^P2!g&FuP(k%Ry0FcEfF%a!1uuYfS^QcO`4a2UT>k}Q*c{yw zM=|}9T1)BUGukpJm;GJ-v8W0Dn&MG(OEr&Ky>lR|M_c{uw*L7gh>PCD0NMhbt!SQP zyM$ORLYxM8=4(n*9%WHpIW6NyCeIan}bqUy0Nl}dTG)Kjm64+B( z5=4JHl*X{M;M|pYykYg=EcYn)RMggugY^)UY%A5sHQ7*Rq|Jogfu57mg>>&XB9Z#6 zxahuk33*@6+jcQ#9`l`J0q6H5l{hlYE!ad+q`JuasJA4QHA*k2E7eR&fBa>Ju>0tY zuzSEc@;=r~Z%5_O!v8R1XyL!iK$wwcqRD|EG5NArhn*jDxxSpa(dyKwrwCMl9W$@^ z6+iauOgPL_5TfS>7knhKX7Hw8$k5>ebwtr14r8b z!hxk2`UC#CAV#Y^`u5QN*DHr%Z$F&&)uYd4Q$?{D-M@moJXIvwmn=;!uVWz!dk zpPe25GYx)jfZpyD#|l}I?tq?fQ&qw`d^Hm2JG86tS*Wb`0mDMz+(4&x%=GCTWavul zdT3^VZutB!cEAl4j)pxu^?Qz2`O7FB=hOmr$elm&^xme#k+R5*E8@K1;qLC|tgH8t zWb><1&I=tgK_sTJDMz@*k&5SFOXM}!eaUzrl;c0?dXfX~$kPUuZr;v=J8$aM8|x|Q zYjE*+4>C+KO* z`PnuYw~BKE#mK*M8!iwfk*VA7vMHU6L` z@eK!oqK*reQS_%+bEmB&fx576KCo*md}82e1Ur+^K-VB5gYpEp<~6sK9bd=UY;t| z#MR6g)L<9FWLfDL0CyJq>pFg_?o4>NXIT|bl>+xyX3iW7dxB%?u|&yD_QmtGc(AZa z;t<8?YDlta$EGqz#_w^zk(CV+%UCEi0MnUa1Ew=3y|1|t{5T!t$Qj2lW~Bx%j!o){51EiAp8HVJVDi zs|>~#LiI;eAfAU-0tzDjBp{c7}GNs23 z)#4>>J?1_KK5&m7A1v=rd%i|#Lf~k{s>je2U_eg5<*?Ap;aP5IQ>k?BzT+Ro-_p(Z zb2Zj@fMfhbNUQE=mGy3-4liG};k>nZV*l5;SFpApvP4=B4%1@%aC_(_GJq{oz}Xm9 z@RE(Sx?P!HcT}`a#pWF^Kzl{{4&B%YXmKaJV$le<0zY`Uf1sqw_r4c>cn94%nK_Mp zwk zJq2m?NkJs2FIKW2v=M8pd7S5Ks)?*BwafhAg2ugh(bFE>KJ6|T4=2I*-#IbD!-`Br zwg|vr2(kn$FWP1=m0CrAGKQpw1lF{=Zg0Y#X*t?pZ`FD8?K&`6L6c`g1_CrI#t?Zo zc$zCaJTh|h`15|9BrqQ6|H00}4;wMy?;EBgPe2C;=`{h!Fia#D6$+Bb)NDb_dQ3?N zZ&lQ>97Eou{JFhiNqNDWBa%mXExM6$JS*V&nJJOCe{1S9cYxP<5yh0aI|oazD`)=i zUamwcfVg=31tEz<9H2u^cC&bGZF0$FMx~jdbY&k!qjS=vhkIa(boa76v1m01nbSB* zwmh87bcnq?;Jet%JILhGX{0R4gUZFV0doW~cH^Y-=Dgo;Aw*aM!PTzKMUayRbT1E0 z8{s!_>_F%@Z;qabcj(c)NV8F)bKn0euq*t_KGA4IU~8S13RoeP)>=f*{!K`L8NI&t zXKR~g$j3RqhJ@gL(sWBbltuPqmaCFXPn-ivE*tJ)9!Ma3C%!;oHqT)>xFe-z;S&9B zg=wTw8cgSu&Or=8JEs{2Z`gQ`_72#v?#cccD1I>FRQ8j*OFxH}n#5N~J;PQmmZ>>^ z_=PLC4KZB~>H5hL@_i&bf9yQR-Pygn9*KIg0vbKIU!q@g*8&3q;)p!^UU>`GG%(ir z_CeG3x%<^=j?MGxc4+M#Snhj$HESt&SgvI^sX<@OW)4oC74G5ml2&Zx$!WLV*-_!z z=2tIABXAq0QG8mFX`A zkIcFm{Ofc}LloMuwreYH50)h5Y3S}vUnyZJN3MM-QD7P|+Scz8=wx>6m zHCsR4jW6_X&OdI}M8z!L=-x&Fr~K13aS?j2U2LpPEhz*01IahDZM!@vNz!MM&`+0Z zeU(e*o0`OGO5vmPZE}nA4SS{+3_K7bF20_zUR!HOnR^n*y0)R?0RM;tSiT{F}i7n=od}XQD)wOF#aFp z9uzfm8N*a_&Yd8r&`qOv)Kk6k?hV6MRxR|S{H;gk{Oxh76XrM=;>56Rn3C2Op3p~p zyIr&LBDR6{JPO~$4>_R5%^GnS_5M4Bz6nXV7%_Bz|BChruTT;%_%G1`Kjj3 zSt~J*157XtZt`-U>%+}e&~CWlaN3NI3XyRZiz!9B+rJ#k!efD&q=9cG zsZ+2Le}mtTD7M#3{owR!y@z9=V#?j(n*0LP3F5$-3Or?S91#RGc{e5Yen-LODm+ANcQ)*dn;8xofwK znepgTlb@re=9K~|+?|oBL%p)uh4{Wto^@_KUVYLIM0g)8%fv(%Qst9>u0 zEjV+j`|yJhp^zV;;)4UdCQk0!c^W(XCOh9#yZsI_!jW(KnsSwj=!9@zGJa8qt5it9 zVW$ZQC>fTCJM*y@@ozm}B6Qx`)a0rfG_<>Bpy~eB|@Q}*6<}Gb|IPptxh`lVp8lS5M7p2HnG>ae?1?4sN z*RbX6$(zZqAns3^>vic1K zag)RtGwZG#4w78=cckC6QiI@gV^^1mUze}fajwUq-u98c=MXX^34*7$Abz_lu0izH z9=LYI7gfa(MPPfOR!T2s=<)h(6)**9>t|7|yBMNzk5d3eJ%6k989-n=D@9SU3%4LQ zWyN|a`c9~DcO2F9{Mhc*K))fk^UT8BXsQ5pddGOCjGK7Ga0CYJgR4MdYcO3u%x2{;m4FPyQUF-Kb(UlZzBkKGr_X+-Jh=|yF}CSd%k3@Iej?|l9eUWLo#)9zPX zYgwX~JPTjGrc7b{!X(vyqUbGx-RpGhFbFqsqY2Hcw+N*oU)6!qA3>bA6rvU>fD>m| z^73Vfb2LQx!w8=&YI#PVgd1eiQc$BpI~RpY3uN@tNW<8m#u6>8+ltxZ1tX-%9R`mF z)}%;`&&kUv8)0<5rqHF^xEc2!i0fw6JOh2nknenMshP8Yme+Xeh zF&#SsqOX$R!ww{VX8v;1haJ{(_t7ZYhxoE{7@`s1c6Og?*d+Zpbz7WWs&2PSVW_pl zsww7gcCEZMG>&Tz7_?@O&o->kY+`Oay(W4ldhnXB`G>Gw&0-t$YgciuRgLI;r3E!1 z`4BzC4#h!Q8Xs#2)OZ6g$PwvC>aTE8O@w`5OlP^fvQs;2+BPpJg`_$4{$K;IAOD35 z&pb?H9UID_7}Npd5P=ndvVD*>g*8xJg*m)L8@GVu0xXE7zYD^e+y(xrBE@lGMw{Iw zW`FaFf^orgI1m^&Av2h) z>8x?3tJqSBu#SB^igx_v7?XBWbuITwJ4Sv-COWS>A_ZA~IM5>I82bpHHRarJPnqip z*AV;Z@hA&v^$L1l0p1#d=H9qx{`Al7l;oOD-Ey_|B-E$PTMmG~H6%Q*jvuYS1<6#@ zQhlA)D>GX8=QxOow4@e(AACU+ z>@sUwXW`mPb8J;)cd$PMUKOZ{VUEe;^Z4#ii1@(a(DAGEMstWKsf$zBZ$7VQ3@VlMtYv4B4!f^}jYp_tj$b{4^)NNf6o&XXgAV@*$Y)S} zW};&pw#n_qC5Ao>{T}L4p*7qk9=lH|sSmmtE`zSti^~?)XJaeFYDMRmEr_KeFpo92 zf;cUdKGsibj(o`+X^ABU484H!VeE=Z4!6r!d(Zl6q$cpRgXbD8-WE0FE)F4ZZ;OTb z5exj0ZrEOw>25@3knhA-WI#oN{JlPHGVa?B*fd97bVT&)#QCqu4{*MZ6!VRa=R~@E z)ZjxfvT@elt16>a~6b6dq$7#{X5JSC8j#09yua+}5_(ho4CRg93AZzXDW24RmTqmPX(- z)dWI267p3U-n^==={bKj68*u&8mD42;ovr5_AK1h6zKEv@Vp?gnd}2Ov!Ts($geP1 z=7+TEY%1R{oREtj#Ie)mcF)ViG-&9RCh-oSBoMx#?qg8H>yTJTWb9)AV8b1N4WY+|= zokD6__&BSsy_NU9jcY#g2#uUGX36K4v&8jl?b=k*N$LIao`WG2*TL@h&?{z+T|khJ z5PpLJ<>^`Xtp2>4eQqq4Q2IxzGZfttMuu~7p78FN5*m`W;{Ea{X7sEtOEG=T=*5lP zEi%Q6bVn^H@{v}Y*yC)zrv04_nU^^8kw_mf8_VCNV8E|qI0B5~CE+YavjM3WfZq%Ms`6KgS z0A+z?V|w#^3&8C3$GZD;lr2o)I~I>l%v`^qZuejW@)iq>r#Qf1!8Fn>^EDrS=d*RB z@;b&zT(Fzx1L=r!wDk2J+KPds?$j=AO6tsf{LRLTpI&U0&GG}QEYV^a(eZ3ZXVTIr zXa4GFG=M)q@>i*^pOkvXIa)!0sof9zJn%ZjLikS3GH)?oLEuR<&fr6+6+*;`U6P4p z#DwnvW}ZDU^X|*_6EmGzc5tj+X*!RD?_T6B+Sc*o?0lBETcONHJU@jQbBQDwyZ9_4=g zmsG#oXIK9rbq&Yb3n10+HZD^43to?H=@6etJ&pit*w#YNt_oQ#rTcZ+qrJX|wkhjc}yhkx}p5(2qm7|7Qg^@?8fR5iT zU3yVUI2J-2DW+h(UR?NcEQZj1>Pg~xn|OkJ8$vn_WLIrq-R;w{A0Cq_z3bMb12I8% zs9B2YYew+GCnF=mCnQ$>$c?N(>#Yt>8Dy~tRBB-~Kr6L_%#E8?-y8!+h=L%jX~80?!YSl-6X9|tQ5x%N^;xWB7e z>r4-TzBz_mDw_PhNTg*FXWw7P17-mg_{F=zy9$C-Ech&UONufrINFXR@5S?SUt3UrvNj z+t z^q8{8o}B;|ukWwL1D!nI_!r6XZH#(|DCmZtx-}PjI#JR>@vh| z{Eti7Q9^mHTIeWKPfoC2=^KB(FW7=8?(pY{Nj?w}{4!@My?@Tcxga;nUuR+ivkY)1 zTEKsui84w(z?txv?W)7~g=`sK+08L%Tcb{*D80+g)ZY2t7y4!IO*CIkod3CD4bk5a zSQcrY5HFo?BWiAr>_WKgBBR|GVp6*CzDoKRi=LA=-^2KYMm2W_#)i^j6yg7!mx{Qi=~CA7QQE)o%?IOfK?T@h%^U?-sVa4bC|XN zP&8}_?9t`H<%Lrpv<<%Xv3ilvb5s|}r(C|d5y>}Q8T9CRI%B?d7q2rMJSc+<1MST3f97-kC-?QmyLG5i>hR65b4 zjsi{5;q1O{o$Lxw^>m^qx$h8G7?V7@1&EJsfda6y1R;+ri$Os?eS!P0b+ya@w=wk4 zN(b!xP=F-h#ID+BxaE9g^vZvp?pCh*7Z0EmqG#c#c|;dfRtMW|c)Qyk?Bk=f+UQO6 z&fj*k+dy`FuCFIWA7NCVL=QkHJ@n}Rg-~TrFxs+U3wI8q`3R#^JPXhEQl@+$n6U0o zhO-Ru6&4V?H5vG~#wz_U(JxAsAqnSHycUjRnm26UV(V3uT2iT}%r|`armO#H44iu|f?k9xF2_Xz zAJJ~HH&#g^duyQ$e0scRwVK?d$OO>M!hd`WyXB>7N&{zv}7%7u9np>u z+Mc&*5J~A05Tv`ir3IwBySp0+r9lbl?(XjH?(Rmqc{gy*|NK6^AN0D!=h=IhHF3{9 zYt7oi+b-pr%lt=TZI@70nt=*V`Xt^% z8~|p1z<>Oonftz(Io7n<S8!^;m|Xm+Cl$JFwGlxJIu@x59?& zu2t|kT zhVTVxs;UNk6ta}@i4}%Qd#P-N-U=sVZdO89Z*p(+>hRsaE%6@F)Hfvd2G zE7;7bSQF-QmD73(!gZ-m{Rth6+vRwg58MBXCJzA@ASD+f*#AhG{3fNdCefOUJ4XFm(*D{K^TnYc6|jqtb}nhgG(7kPNmC3UQ0=jhl^E2OtHSMG+f$<+MMh( zBcj-le9PsuvozGyvk11#{~pP5>}nQ2>72gEUG;|p}Cb*g>0$XV{=CIWW-Rx4Yd1Tll>0oY;k6+0XQ>s|X# zwS4?P5v=w#f|peEFZcN;xk21Y*%GEKeREBcK57_@#oh9=YSKt| z&s$3NKIt=Y6CNiMK05~Jmhq4_n`E}u3~BRerL5`NzN{pm2wO2T^85q zyA9!1lj7XGmN}LJ<|mWhM>dE%+sTzVYstf=a~W3x_0U>g4MNwl_uPa_(MI-PGrz@c zW$E`d@q`Z8E84W&1cfxB;p_a>$2nm9 zKqKY--w&(pT1fF_U)ok6LbM`$_@4-&{b~>W-WnC?;GEy#_};5QA4UkS>mhC%m=zSiWb{Ex7W;{wYYjzH6 zc5nEN2b#nUAg`NsZ$nSn0gu~xwcAtnHM=*vg}+(UN-XGGyk$e-2?YFWCUL~!7sh}A zfBQCU1^b*(U?_dxnGy#?S)D6QLIvkYn1S7zUoj@R zqr-dLCcJ(-S+WLUqRpwFMyEcj<|~9Z!eIsx;}-vn`wJ^Z*@#qMS&76E^gnupd1J+h z>_fkgf(pL`TLB<*jWS!nXvo35EqB}~ngn~s*mX>}CKJ}XG+@2IzpZx~ioieX4fF4M zYuX85q)66OhUWnJznC)QKwl1zrJHyISnKZxf9h(BC!_ZSG@(}z8afZoR`3aX#^S{? zc6-&f{KtVN&p3a`f65d1M|oLh-My#ZGDTfHE-cn{Z| zsS}k(@9rw6=9IhhYsv?Ho6*Y)reo$^YFpcvN<-p#ijnXSe@V?0# zusv@M(eeL$nD5Q@z#V$t<$~veRF<-)9y_DRIO&4#OF>M&xd%U^tH2>KjmE5F8SA993)dN|p9lI9 z|9OTKyfxnWrrB|uJz?Sf=$f|1%_gP$9%a=>%z7$Nl_ai5Q-V+dVyiq1c|c5gXqEpF zGyhG@++!ww2dINhp7i<&c$p=gA+RaDX^5$}s_7fv|5Qyfc#R1B4zJl!CMmW4Ej#+| zdw0A{cW}K{O|2*5cX-J&E#&#pNe=(4Ge|yX;Z{0FgWx_#%DhuNExRJL*3G^l@MpXE zR6!~qV6Et*YNp>80Hj5MAKibXh5ytmX~CfAq%5KQYKr&m`;(uVKnv_Fl#?h6-+X0o z|CI^^4^IK|w=y81&YOhFNu~ct*#4h{rS*C`|43L6ZSk*!NCkHA%6QkP=Eq_V*wcGd zzq#{iG96B*N+c?Q*1*9gx$;|UplKB_#8r;oiT@1I`k&T-gQf2Q2;B=AP@K`BQDmdB z1T`}SIrC9L5q6>By*cYPrS`q3I`L6@CGQTB0k?>T~K)3br+XL+`inADNerppGe(Q+H|L_k1 z+bjMFT-~Sl6-0XR5}4xVcfMw`1hoMKY;Shx3qAqti4egTl?3b%2Czed+E+)0kwRL0 zb7X$&f9(*mjs9h?vul$V>lf>CY6Kj;sOb`W7y)Z|aEKnR_CId(xbtWjAJ~McL)U6c z2!o>ol>ideev^93cO3vd>jaelfgXOFx3*Rn^9NL;QlVp_pJvLbwNee!kMelfrIUX+Dqj3F4Z#!P0qp%bo%qI*foo8^DDdhWKW!miTOJdMk3GxZj= zmqdf{&(~YA3Bq(a7n{%aND40ye3Rqy{4*8o4EZlbf(K+`?P#0+R-9)}W4(?+_`gK*x$+VDssWq8X|v%d!i ztKx&3B@Cy@V*W5w*)clB+Ez@iM{XKw^Miz%Ygh{788LLnL^E=CheR`8mzVNfI}vX-AV)s|21lNx8T$BW7a zWC*i^{d){t|DYGjCvG{0YoTqw@;S@e-QInK5+phm4E98NVr_Bex_(!MU=f{@rbaCU?;EYr)kHhoe?_{Ng@k=hS(I4l1?6RMZE|dEB`pA-Y-(QB`>T)Er zKVRfTgWnT~mDG;uV`kx5`+~!xN^uT?b+hczy^r|}&BhO0f1Q-mopP>uIh*grXh*Cs zBwev_99<%O=Er*}Tybp8mFRT8ym-L!a#;FczNE#gnI9#>QE1JbXqqa*s*@vScR>I< z`&M}07j_G$OtbFXI?nj%pe0MV{_UK!?aMjon0~>ZN6Hj&z<8tAGtwX1Dbh^-;Je^o znyX}QEF3KW!#9?$=9c2IJ)fhVCi*X}5`Nb|U7^s1g_PSgo%v)W@~NRfb&L#aGr$l3 zR@Z!#uy0CmXfoS#wa)%cWoGt5dqg@1PPFZno1VF^xQ@$dSF5jBn5#_8oPtEMk45^nDs9)a5? z`{f(*71QK#ByN$dW=aI((9g}2E zL4Ow=e@}U&w+KoiUMl6MZ<YxS~8o=*44 zi$zazlViWea5D-7k{1L-Xr=L`2I>Yz$C`OD!ye=9PKE-w_fdd;1UIKON3;m9cfMzO z*2&dXW0@WPscy^3B5%+9-NKr3fw3sgGlzy?#iT=qhs(VW%vuY?GuiwIQ|j=31Fu_E z-~^po){jM(JbXL%gV5*PCPyB1%@&G@E&O4Q7SoSoMGh-YJmgbZ(uEwL8uVxT=#F4Z zA7Qn2RrZvscxaB1>kY;=#}jk7 znEt4BbfMalcm+-MAeWj6sOAf~pR8vFkWmRc4!o&8R+4GMy_odb)GB>h_lQ_x77-QeKP%gFuo)sUXyJ9V? zi#zr$h2T8Ft*DFd^w)dL+&k|UU4Cy>k#E*J()fWJtJ~@O6jL>ixv}=gIqp2kE*u!~ zds40!_RrrvR-80lgKsy#F^`@LPdbbY`>`H*DX{NQ?i_$~hn}t$JVe`$0>}FD&Qwnj z?|ev^X=PcsUXJzc63bg{V;3Oc=UO2ouAb5*rDYE$-aUSiHt3PYZpkZ6p#FII-I@eP-;>-TSpg;(Wx!0hi6v zesGT8;@LANWJv*L48|GO97n#l(0%9at=N-n;@Nc?KF$~n#8q=&yIF3_C~xT}X9FLA zX-W?sSAQft2Z6(4(GSjDQS!7Bo>aGGn>|tZCuW|9B)9ay%|kf%@%VlsUA8Ejt74_? z?-=sLeBqcKdH50TV(B5sJyW2;KJ#w_7k`NPHolxA{>&c(q4GgrEaIAhKl_qXDq`#p z-27|{1Qz#*RTSRBs-A50A*Sh}prg9ETx4>kr>v??^RQrr#5VcVgz4xC-2x z>&J4%z-fr6p}L$`cpWzoKOaS1;$Y6;pUn|l24>=sGEq&e@cQ!n*O%8^q>(xA(=)sS zMm)waR@wOySDki8rzPekd0nmAZjXJ#+LTtBxtlZJxg#O_;tSCUk5FCTbaPvtv5$7F zLjE+{2BreL;+;ta3^ymoGJ1&U7n!kGb`f{i?7Pb7b}ueX zwGA9rcD-#JdgA)%?7)#kH~-lNJBC<9Nva_ zqfuWtw8vws-}#71mt*;ii5=3Bvmsj6pnruPH;sY;hMatbD1RKl^hIqMak-BIvwoQb z1*!ZJZju@jYHGSH>lK=mz(v7d_GL`sZN+MHb`v3cRmDhqoFFz`g_DM{Vva6BSFMi7 z+E!q-?VL_JQR7?ko+kFJIp5SeXVL;AqxQI+3;Po<%T+8FH z$e1H^O>qtXD1T}6lcbdcjC52^yvz{qa%IU`q{_v)7Mb>L`0!HFKC59-#ZOSv;7cOe zJm(Sgx4GI7jeCn!P?f91OMZLDIZr`u?%NmW6M4MJ;mJv)Rn_@kV=)*}E>5?{96=D5 zB8$@@+1{HZ<9^p)AY-MkQ*{UKY`8L6?cwvzO-4CrZ;d^_I8_=C!27GQBij}TWX@9N zgsF0E@N+M3aw7i#_O}CPoxp?)2jjD^VG@I9aUDsQaQJJg*lANth4 z>R!-1)5nIm5>J{({xkM+$;y^=l>2-RP#kR&L|;Z4s%(YZEY`k_8Z$e)tnTREBApn% z92@7@Vu_2XrH|-*JaG8YbtDUCwR+|2mzKPw6nD_$D;O9HoanLGaY@2@CwAeLo>Z!% zU!ecjf$cVMpx5}!Wme({SqqzhBR~nNH-J-W-0!xQY$doQt-^QC~{iCb-naG-yFhML}`2O0WSY#4a2eUTREpJ?F-ynp8fdk449c_ zJ562J(6mt#xnx7a&dyOOG`AS@1)hBF=;7`Q8sE=f)_o9P>!=ZThPm~`6tv6oLDb1m zVfV(U%A$2iltq4s=~+$gpdO%-*N~BCQC{dm+ zC4`vk!(?c>Ia#FU#B>(mPOmRldFheD#Com}iQ0oV;i*fpE+ID%lS{7;bF!G0E7ls3 zID?{j!h#g`;DC9dUT;H$sTJM82}gPC`|fjN!HGEi>|RgsK!x3g1W^q4fU^2Xp_~vx zt`D7|seZ}C-cnWKQYJauC)zcIU(5@}k>25-T;0RG5jpa!u%NZUZ8ENcx$nrK4*Kh* z#=+EP=jO$j#h{9Fcq<%;XdAB?uDwuM4sQ8-axsNk^sv&6XD?Ogyg+sMP?4}M)!Wzm zGU7zd`9xK)Da_1D(<7-C z#KDo+fBYws(t)XYJoN8MtP~(9nn~~1rlXRBg$Fk8GwFX3 z_m}OPtj~b5_e?lmIvkt0nPq=Q<5gmzcj)*5u?F5>kZy2SzT!0uXYHscMNN#d$g3v2 zgZVzCBE+)L7Awg}KUqsS1?fY7LxAJcU&*>~EEjMXj z3|rRa?dEhA(GG|E3Sy)2#RTy(o_1Nb&JFWOS z)1|g{B%80*+;kzZu(?v~q``vudO*eDZzYAtIH3OX`H0-?|CM{?^e8>`jQA-wsBhTd-*bF{uw zB%RW*W0Yiha8cf15o@LXJX*NGpMJ+6A|&aJ4P%fkEH(T$+8O-^KSGzx!*Wp~9Y>;A ze)-QWxU*H1ph!O7D2!Usm2LaRF4B>_?akvW)~_eKR_nAs6DZ(8H;psRMplubPF1C! zZmAXQpIBK#x1VmAz|!=zejKfz&Q#&tHf8D?J=j%#rt#$zHl^4Rw6l?vCA~gyoBO;U zTDLJuQf9rBwz>#CR0@c{Vm0ewVkRo(bH@0rW;*98%<3Eb}??#5# zJj%o-Z_G**f^2}^dmbtwT;w|Y@G-NXWdm?Bv##% zZpmZjDA7hTxWm9UJAH`@U9f3@`!?=7RkHZEM|V$qVYLFiKMXK#%aDYT2xQm(@;ZE< zTplU>%O+RzHYA++AQo>MDZ3(88h#24su%xO4>S^BdKWcV|-_7H9`WOMvRp*O;&vRZ0|wyqylkdl)% z1kGrxCgDfG`qukwi#r#N@I2PU6)K{(kq|HVdnZMrF(ZO8SLGsdQbNBMn37uUX6$@t zf@$kLsTj>Zsr$A$rekD7x+G-1D83#z7TS)2O=|Ls5E)g6@Tv11*G98MVc4Cfr(kF= z?Rc$tS6{M_!Z1xnzM2!;EHO;gXAXDi0E!VRQ(o>J%^)T+DwYq$&Cck)1frjWQhF#S zNl1@2qxNr^P;r=b2WyQf16b!VdgH4VwRJvW1ui$?OA;OF#@8?JA$`;^Xmga0AhXQF zH~y8#lsljHYaA0-A}x7MlpKbQwWM1c(?M}^kP@PUYj@MOq>@8_WXG@EsQ>Ft_P&dH zBVpKWJGN15BN?=~6y+`P`v8|-sZr}clkq)63vNTgcoD-@^%KUHCpn@c&6>$xO{jr6 za0uGke-BS5DT;e9(B=bh&4R0|bl^V_gy|z&#I9@Um;(y!9=44+-q_J#{;2Be+MH*J zAh?yVZ@c=57%g3dr+9}|VV6)GEm#{DcctQLu~*kdFl$@?V~F854!Ty5ZTD%{Z`x4< z@_X0P38tVSo8I^Vb6#SZ$2W)hu#?nlg{gl0VRNnJugiFy*9DD9Nr?oyk^zRSGW^@Q zp(#Vjr=CKl=9k5#56381M2}=r4^cjWMmj4esklhivSS276Es*SElOs>+G>t2Fef-i z0Ql<`W{JOn8rQ~_a6YgHx+PvU_iC(6MB&uEPIm`HqD^csPX~IC35_f8Rd`ySkZR!3&HP5niq>zsdM>4w1|0 z2PJoe-GQ;XS~e~ob8e4nQrx6CtRWE;`#197US5J)2#t;&p-Fi z{0MsRHz-o?TT@Qe$4V4&T|m9|{R=_7+LdS^#t)i!pZ#enPCU7@d2bmC&s98!K(L4s~*~c!%Vu*|*nEI_gxT!)CNzb+X+p}z) z@)g%$h;hLsyGoQ{GxTl}5#0!cW$RmGdpn!P&i&KzCLB(SEM1ppQZilUJGU_${FYsY zB9WbqQ0z!61Kw2>nr5zuor+y%7{p>KD(o)Tu^lTRx&+lzfg8YVtnALa=uiAmo2#&& zWwcHE&5-^Mxh*19og7J5T|sp<+CSm<9M(2+jh*2lLAR$<+tA?-dx%(!(v4=(^yE}r z_Jq4F;NV_tpw}Jk8Lv+qfvRHw_iJPX64TL`DDa4m{`-}tMSbe5X&2r zRswG)!ZuEqkstcmCJEQsw}WFxq5M74xQGLvc|!(SVUwNbVP~zZ_Qv*N@2pf01b;5e z)bb+IuwWG$2u3%NRVDmLoi_}~!LVL&%iv`SH+uY0Oi#6JzZjD)t~2B~@O0f6I?p&z z>3)Ek4(Rp?n{F;qeCnz3831K!CTEqI`u>I3VHbgj9>$N8;ysxcTML=eijfxW(PdM! zQ`P+Lz3*jG-oTx^huL$rThC>a#gy<$!G%?WllsvTwf75J_QtzWxTmevo40&6{}z=nWuS;4JJZlTL%UttQaRAMpRp;!j^Q;G1q^UR1*zECbrWg8Gvg2?zgldh8Sc(JxBU)bd;ZqKd`e>CV+s1NaZ zUWLAGzaVE5ld|;!{Y@%MbwMWi2pBIXC>{y@AYK0EpkUJ%den{CAA&HzqbtGzphiF2 zQ}v|4eoLt3YP3C%6_3se%wbGfrwb(4htF_dDRt$l&*$-O*yaxcrm=VR)pO~5mDU1# zRkofdQD)H*Z=vH+;4srIe7ar-&ETB^iq9;aNCh&fM7`U9_R)+;LTjoYJA> zwtupBc;EVd<6`wZnENkM{YF{OOdNi-*O-!vaHO=_*-wcl`xF02{E+HS8|#hh&IqTd zOa9x72~@#oQ{Kv^uL{%x5hK!_4YW@~MVP}kS#(lzxMbL$?;AE&`J;tUoYt|1-7)L~ zT?w6(EubRjT1C+rFQboTq#FbuzbvIaxh}PlZz2?YwPwJZj@IR&|PPt9FoRgZ7oS9LX>p{dug`MoWbnhXVbW@0`&lso;T^JA; za{Lzq+jda85qR)EvvQCID&Lyb56)gRfj5`&TH#Q(d>@FgZ06j1}!;~6ElOhZkBlZ7G3 zOC(yZ0I%BHs4R~UcTbFwZu(iqA!WiQv4CnhR#9nFU>_7CJ!vR?DN98xHz1W#s$it< zwTQKF_)d+k)dva|^b;i%BRvvnO2r_#_TTRoVFJ_=1=SZ#2PXNN5@&z6{zAahJ)}=N ze_E?-MR_-Z_GsD_i6Nb-*$XR8?7kINQDLhEjVDI){78BbC325{#p^LR7W{MLXDpeE zkcTkth3mM2(4l#Wa2q}aB$0{uH|wMDj8)TBt;&fz#0RZJuSyOh42<=1yNla%9g)gm zDPBB}r+M~TE)LGGkVL4;8Tr^n5`s*`8VY`Qa>sFgnVv4BdFk-y?h;AFHM(+ou<=u; z?n2KD&Z$2cUn7G}0Hm0#Vl_PdrW$=V=2_sVoMaQ8lGG;W>H{8<1v$!@ZI$z6X&TxE zcM>vTag*BhGNQoPb@y^E{+LwXEq}w3iPyuTbuO5PoOyP0B+s*Dufy0u3U9O3PjDW= zlA5o_9!iPlPd_v9npRfldcy68is9F+T-0##uys&7V1Pjh-Uzz8?V5c=-wOhc&5yfd zYT@h$ebYY{CHW~HSR08fe$Dvdo}~gpgcm9h{t;F?*xcVe+k%a z1UwSDDA0*ES+e`!v(wu28qKMLE1x^8)k84B0l$2{(dj z*kx)_*|rAQWrfpY>ehzOcJSImGd?RMjS?C^_$(c5r=MKioe2@77Sb=bRxd72*{a6e zY^^2ptBgx_O7pYebX z)bQGruD5qASCgiB`15?X)kZSJ|4h)O<~Q_x0?eF*OX;EjO+>Ra-j$HDH2(BACz=w5 zV>E6 z4X){WzNSY)+3?Xs%B@WhT?tMx%bW(%T=R@%PQrAIo z6nm1sE9Sg?mk}iQUCsgPMB(a;Z?d_DcWNHzp<#Uj4ey;{uS4JEw^Y{0ak&42$ws*BR@g^0!g6P7s>xf2G zf|MrcnQxB{ae=obXeM4v%%D{~B@X{a;T*L^wJ^~)z!``kjD4>{q!3b1#Sl?&r486hRN z(wMWiy7?+Vz7}?Ov9qdLYO!mb##@)P2wTT+DxiwhODp`i%CGL`$CrM+JEmYn^R6=1 zuTl=hEu?ZyAO26N@I1WlydxE$z|mHVO)Q8C)!vGDuJH1fUCSbme` z*wUWys3Ne52))NPriB>-7+uM$oWbQ#s6p7T9oM;|_AwRaN~EmMoqieoFrAx+3+X}J zW=P*y4+zlXc zK`2{_235ET&n7MYLw72uz`1s3BdIiZi6tUQRw;Vgi7)nxK06=o16zm?(v16R!hv`< zTx><~!D<}Dd?^$>`&V^T#!aSDEXFwgYcAEBn*=uA+FF8aSW0j{+{2V+zydMmYn)lqDW$OK^Bfr*aGe4p`2+3# z;3AIyxxGASE4$%b(x-gh33cAE5)APb1B1SKnx6{ zHlS72TLdxp=^g6i!yI)q3F5~-Dzzi8l~IDkqUbG^EJM@pEmephqy=|WCZ0I(g>$uM z0)T+2OLjyKsTZdyL2x{_%cZ%I?~1FAh;NSLA6>A^D%CsA{RTB#KK6q1Sewu*N@G9Gr^u`$6NW_K@>@w;*R?wYz$#7x3m#mz zH|{NPU+N1hJPb>LxtW_P5K!a`>w;C<@hP4nw=@K}*GHdTmZ+pS)t6r-H*^L9ZP51@ z6q>3Qf?5mRK-X5=meK_1=ke^jF))h3IEqvd_Gxso%px-+@UqWKWd?@e8@iAvt8Vgi zgaazo89fz09{GVi@1i=H02ZYJNbuResO>JnzewmpF>yz;1>6b0cS7!utcy#1RjnA) zXVLLP2CF>%Lt<_>Vceb!F@uH33P)@!aEzOr_;@aJ1e;e0+QFqky${c&z1@_qRm3*! zSX_*L`JD5o=$uhI@C!pz^4y=rhpKEi0Aq&$T6E$vP{IP2uF*k6JA7RZy9pRdWt!ui z)V4yF3^b;oISOOocfiITJTyaspzrpus>+(DG}eAWWBfoBBCFWETSoV;TJ*DB+U*?J1Gnddhh`Hg36>-Tc*b*=R= zQJG)$G~=l3zDxPk@v(~0y_RhdukoCP{Zvgt%vNmDXF=LcdO7g;7;ezLM2Az4`v#hh zL=fF8>*DB+HY$HVi3!(@LOI&Z%Ot}k_aWkOZI2&PNa0D-vD`ZG(>N;!w1tW6=)!Qs{PAU*wg?3bdgR3vJfQ5; zEIg6)CHx4TvGO!!ex(Y|V9g?E$-My0ySKSjQaFgY3&)2^hy1BT6ZoPn`ViM*BF+kA zSz+UFT+!#jq8-LA#{H1rdfqc?#)Eka3d_+KyU5ZD>s7z86Kcaf`>MKSEA9)YF)_#a zP^O(-r>eR$hYnl<+6%GQHJTWLLk(zKDnuryVpbT!E(0gO)I2DTAJ)il*Zr)I2NGx*f;dqiI=RZLYm9)$m z7dC0Yi27;O%!e!_V*V1hKTT=){)4~;7bGYXsq}qco31#$A@;DKxL%Nx({TpzRba>9 z%-=`B8GgDoAzg8D&yl&l$>g%4_2JVDdZ<#IPpl~5I(!RRX~CrVq4KBgt>CTgFTnp> zTd)fYU6|r2pk_$g@fJqh^|F@li9UCRRc6vx>FD;>n|;;HuAeV$?$NoXs+HT-_io9jOL1;u*bk( z>n&kTjkLfTzmGtK3HX?QW&ngFPRz|-gj|K&a>%cWy=|S|OK5!;t`UM<3Cgjwc7NEn zzoRxK1^ZR|P;FO7>h;L=CeUaZD!xl+K>=48{F?Euq4UgOiem-P@$!p~^(=PwO_QFz z^5-~s-$HGCQQwf3*$1#xsP?$LNGBzBm>*VIO6|M^2-+f+B)|_7glpRwkm#U^V1IE) zR4CAa*%mT~IBVuHj$XGqtF*xY#AHaXZE^b)&KL2DLdPBu8Q{&6y=Aw*wMsGHbC<}} zrB#I$G#dM)bq4RbXE+qGgysbG6!Mdyc!J1s&|r}oxt%#fwPo!kXw*kE zf1a$Q%3x0I7!$=0$^&470JWO{edtU|(O>qU7G)WjR=Cjs=FXgrku&^M(N=vDs85%( zz@?qaP}kH4@A7niSJpLzl5 zT7;C=%b@D}A#BdYU?>pgP2Z`E`sut2lAHR_Zw-=!p7*&De*Xb1jhNfDbE5hNeDcGe zug4X#0;xnk=!KCN{SxmiPA1PozGG2$@&ktl-gVViz0b|5rC@?*pZ@q213qVl?*wAQ z05WIIP2QRV$N@Rg2`&8$0%0n&GQ^17Ah*{zG(^9!n++Qdv_-+bDuV|kqSJ(6oXyR^ zV4V3c#$X`lYqtaJ-o-1s2TMXVAqR_2PrqrehNsKDLZtKtLghdW1DmH)9awGWmv4zsl3Q@kdk{{e1RD^jw=D4m4WtEdhdAb#|+g_kw5J`y+oRt10d2JyzLi^qh~v&7bcU4Q}6 zQM0ip=lO`#tD(!Flp*+QLGsP$o28Z(tv#@pR@`A)KhK>p%)d6 z-1e^02DV`N^GOa%CA$!H@saKpVqQ637Z1Vl5%+p8-v2}(9iQ?h3&LC<17|8+N z*SeN)ExMoR3c+f+vW3EvzXAW#3>OMTS_grh*BSL#Nx|k$ZJp2eyA0w`yA2>O{gKJ{!-*AQ^In#$jQv>3HoMj%LWRb>)~vgjR+t;u>K`Ij9y3&qZiVn1zY>+mNsvh zdQLXwNl35(3bdDH@+|l6IX)Ug3?F)0eSZZhhO=h?s6`A z1oEBsDHS|+`X$4@Q>44*`5lheNqTtkaOF90l7||#kY%5D&mTNgc-fJerlZU(`5nv~ znR;se9htbVzWp5eNvmwRscj$C>*1iw#W14J^P9}2_BqV%8Cw3+OddqBEOLRu)0g{Q zs-pYB9o_sD`WDjhElPQAa-AyEXV=j>$pY^4y43kLTkze#X!%LMN>!^;Y7mAeOh?>l zvagn^Qq;uW70BJ@oR2`qyD;B>q0c&rUqLeY%S`d8T+m1|oQ)zrqz)QK{P|=$>DXZB zAZ=3uC`hlT=fmlX&P!DP;^o7BmLg+9a}librjR>_-U-}WzQ%4hC zW{O6Dvfqq1X;ndUw%ji~$(!+(-4~pQ^tC)nOuBBwe*976;dPi@V*6{Znig}752eI> zfiIcO4+ueTnCmau?%>hZKE20HHLM*i6fh zAn30F%V$b?-4|e(7WD!QE$6hVs^=LGUny{5nx@hT8Wts&u|M_4@5$cNvBM9zQS7=h zQ$hjbu3TgeM7!!M%X}Se#5TxDkD(t_V!6Y7$?@Q1rXzTloQY`dN%uwSDFzWgOFvL+ zeCPY_ck`jlsI}0jkPSk^ zfqSia_^_ph!1KbIpJPV4l4Yvno_x`~;-0c=pX9s=Im=0B--S-6qM03T#x9R0{Kut0@v z<+Fyaf(4s_LV)^6r&?a@Xr%B)Fj4YUpfCS9U$Vz22g4$1a|n$`QIg8k9?V7pFmSeS za}}DP=)n3QIM2iLTUlu~pEeYeZd3NE^Wn!)%2j$4@E@7TSJWG2x8ZedTU`(2)r$wg zRC-md-neEBt#LJ_{HUFG3_Vx{XaO%gNmaXY1hK&u?<6b{dq#q)PGQ%bZjY_USZM{) z8}t}Wg-(-#Q4F#zH44y8X=xiM7bF_SDucF(>M&-5f+c#TLG>r5@Vc0SCB{g zD_psPaSyKCcMiEy7NneIa05)24h7uCk*Y2Ks}2Z^($4VXj&K21Gi;$iSQTW!TTdlg z0D_%E$yKJHl)^O}w!n~m;L5>YVJO+hc^ae8Rv}uFj0;?*Mlnd{clyx!r;j=Bc765_ z1CU2q04(RI`Gu1$&T(MU+~j@LGqjoEhh z7}#g4TdG>N_=2$CZZ=VC1?Z#zF^)m{kMPOH>~rx(o%PR7Ch}T#-CA)o+P>ozHWH&pg?b&}eT#9ePH_poHy` zWkBf-6{l9bz~jmD2BG7}>H3h}ry;5vhoqGK#R4!`v)xS%v4r{mkOVMEbz#*EXU zLQ&hswh3YBfgLey)$zP86qg;TckYBwi_Yu=%AkfoDDrk$Zio7YWVVP*jhLzsgw-tK zANR74$jyKA2}yLgkfc+dzs_AoDpxSwu4_%4IT7mvVRkG#B&;DNF^Xp^Vogd}y_U^+ zR;vlR5HSoMDEO#2=y%O%f~Bw?NjT!D>A@+S2{!KMEh(hp=ubvYtXohACe^U{z*aZ^ zeU*D`2>uWoFZCldO*9$SCTQIP?>k@OtXkJ(a^f$DNP&3F5kLzFm(zcGFP($gEzthk zQqacI!jS7k8s;_4<2UtzygG`aE&Xv}KM3Ov*Krmz$ZtSopxVwJleBQaBS^Q;(WDvutQrp)aE#bxHI58=@yEk2u%!DTDp(O{Fao zL%ba;*MC+`QB(UpDr}M1Uwzq*^2uN0Dc$1&F4oEP>p;~00>})Zt6B+bO<3hf4$K%? zi)Yq*^gGWoLR}F$x%En5=*B*p!Yi?Ca1U`6T200@C zff_Fp=-6=gFuxOKJkE=DwH8HOZ){QhY|ZRbjH}ZO*8}#C%`5hU!5=btu-k^j`Eeal z$Sm>6HB48tn$&sD*fpQh_T1_0K+wkNEEQqbOXWB$z2e8UW+(P!78uo=G%LQUueB`# z%|3V`)iaPxClB-cF0^MjrxMN~j?wp{>rw6>JKy@DSsY$EM$hh21{Sadjmw2<-PlJ8 z2moWnVpq?G-^3Wr?H`*|o zt{(7>zPsQJ#T*GH^g6hA(!YBEdWa>Q&_LY}HAv!mMRmxMs?Zh_pt#uKfRf}fQN8hg zV9iRH5GlGM+NfEK9&VFY5zei_ZN?Ca;DbKjv4_J!Xs6(=G}o9DDUI}HF|X_nvh()s zHg^<9PBIKs`jrOH+6L5fer>l7-CtLI7#k6G`-+WgwRLSa)U=O(h{mp=og|HCxYP-=$Ks{%8Z1Ki?4!Rv2QLEN1sGT81&9O2LOEJ^qu7Ix$He zgw-)g_GsKMmUeGv{Ntt1T)h(=DAN;qzC;n7g_xaXn66gERCuvX=^Q2gI~dQm4vhW^ zJ#y<<=uhiuO<*7hvO9_CcJ&U%8B6{Askmft57zD-Qjx-qh*u7#{M6f%UQzYNocwvz zxsa@qU^3^ArrNXxF-D`>e%7zFpt-f?=69yB6*_Vyo0Lxx*oe&1mP%eb?qS(zelfeJ{`22 z9i*lICgiPmo_^xord7*e(WR$&ZY>Z#W6eim*rsJqYtf}7d!DkfZk_iqNv_qVwWBxt z>Lyg()8@!`CtPfiZTzF^tDi!YD4L}uYra!%fec;i=Np`)JY zJ>9dsZlN!`A1y1HQHaSU_hMZF5)YoxHC16}9D`EkYF<4#p>rlZIFAJVKX1xwp{+h` zf8P;EAsFR?JqkEK_qbf1!AIL-h`G-um+TJIiXP{YEo=9CI(6^A z6G0jJZ~5IQyziUPp$i@HgubJD;yN>zLn+pQdW<@Z0q-?wpMCLSMY9@ZUl>cin7p(n zdVU&;Pu2qa=k@Ho&ys9a%RkI7Cs^m_2w*BcZDF64AuGcbW9$h!x;p&a_jf$|T!@9> z05gxnC~MH4b!k+yXc>YnwX>+l`hJP(tsTx1zCv0^%5*{e4)a0M9S$RjmM0Mk61mgk zjjC@zQ7*A+WswFr?_=HYqhs)<&Hy~AXGkJgZU?75c5B06H8pFE0ouyvvJN3ypbFg0 z{Z(|GQspLz6cG|AV@8#Gue{qy`qwIMaT^BA*w+e=q2?-l(w7}Jjj&RYng61Z8AFZv z-vU8}iZneN1OZJ-0bpzgJh}6+&{=w{ICRr^=&C5GQ$=>n+kPx@fHRm;g(siZ7EsdI zrLDMOKUR!lYfeqUtFckd5VkeFS312nlzMeEH)dEWK00u1%LId)rjJp6&!%Odgl2mF zRsUumc`@vdzIeY57VrN>?E%(s|Iz-lZYyeoFv}%Y{1&9X+%7DbM#hiMBBF`lK;gZt zg;@KZ&wdk6;MYf3JiOhMuZrTawZME!G4>#*$92EoH6t=0W@h73{=+xDJ$3zZ**if5 zxVaYyrfNe}pP<=%vD!aJ3AU<;6Gk(NJtAHU^CDOLD33vkE_D^`$5rk8cU4f;GvuA7 z_)%4F*JI}|6(msolCddO##r(2o3*z7uMRTGo!M$o$ORT>Usb@-cdSchvwj<*hVaCmJVPG@V|9hKwn!6X;=A%Nv;w95OGbYwF&m&1D9SQ5A4BU zk@miHgu^oBPFVhN)fLykmK0GC!IPc>O$S6#_iuM^jpmq3awD;h5;egjCu$cd9Tn1J z$W65Z7jYl@sV-;9{4o~qGSl!*P+w-MLYS9iJLU}m{1+7ir~c}1i{BkdU0NDO}g1`KzZMb-O zXdYEM!ryBZ%bc{gl02d9K}0btMGa74>m(i}6IX@Ap-qmVs=7}KNhhts%{Agm;E15V z-BcFQ985ot{)o4!h^s%b+D`ha%wpSvF8%!@{&FY23V8I7EsK-mwJ++X0!Drbya_Jv zk{&$PVsM$?-yX-MMXIn(R+R4D6|=Rvk-G-nZgily}6%n(SD0zJen+}O|S{GQZBUC zp&X&HOjHt2?5qj>#+CShcZTFV0nGZL+;8o28iay;Z@{TXG4o`n*m$;tGI?GEDNryM zqqUd!he4-u$CpYEAWyg-2|@?{pDD@z&vWv`w!eQi)l0VBh3h=HxSy^zz80pT@u%ry zl|P_q8GbU#wy}Nt+2UfO^`WFVW-ahcOWC%F{muAk_xS3ksggu z62#PM_2bHYB%fe(F0xSSfG`X3nbl8U@y=Qxhv5BOGRxYOG)7*ewHrm|ti)v3QdxjV z@!$!3s{S!5nAeO7!#875fpPKKm#LxZD+I@LQknicTY2uEvYWRcGtIYCl3300p?s`| zFyFgPWPklxT6=f9y~{f_1v;%a7!{d!U!ls*t#VVdWVC5o;0gK)&zi}v6^mb+ofQ-D0k?PkiXUOFid%Vnr=P3o^>53U zO1kC z_8CSS8V`>A|FKYJoNxq_hmw?hS)lo|0qt#VWuudfuf*N*cs<3k?_*D)A6YRuMsJ+% zYmu5=RH2D&mw6Oee_Dvs>FqxH2G5Tl?oiFw{N#D6FV2-1(_98D5~z6YNWH5q-KY=S zu}r>5+5RUzT=~vsK0oDPLLda`>C#sn^)`@o#~j%JB0gD*;8v9ox7$RJe)A<)Hj`P& z^@*sGlDCXKtoR%Vs_3-ubcO&<>k|zSId=S#?xJ^4=BdEn?ov46$n{ioB(d-}73;U# z3vt$9^$ilOD5N^NDRLu38L{~z!?f*LzXS!4yI&J>$C4X5;r4t1o(E7Ph&4w8koOMA z%h};MJjg4z*#v;i_#Nl4`aP=3e0}k7q9bFeuKAkOn{5hhhYYtEV~(5*JV+qQCT>@P zM1>W)qvz13Zd+5jb*V@uJDu)O*m!}hb!VTsXSz+;Oo%!P!u;X2fY2>~*T4rppT4v*AL&5MY1m7i2ew%uzvvPZYqupy8hJfwRgS_QoG zNjp&Nh~sUR$@(~6rmN~MY6iv%kpXttO75wfez_7ZGnZSDnT%;MDu6>Ve-cCC6gLt- zP(D}koGdDxz8aFA3k7el&xFRzI^3H?(}CO4@Ek7^36clUxs>PqozXChWO1vYe29*| zJa6nblB2_|P5Hyg{aCO3WAR&|g$RP3&UcQCFqP>0uC(wX&mShvnS3vrai0=h5_{rG zvv-z}3C#&z^qwU6N0Q7n2PHXl9RxCsSg`EpM%LCc7scKA9X~N%C-2@!wp@U!T&wp% zOf-LVh6DB#9}C!tL3E%gG;5k{Aa9=IB3Z4GEOUz2Lw_8vfQv-@1h_gGZhkjO_C^Pe zOf9i{`sR2nvNvyn##pj2ppN6d01ioNLAocUD>x%j{v?Ft%s=!m1S`n6x_F;OBF;8) z>L!Bj!orR&v_w136IY2o-6tL=iP>L? z)@PDThZ&s8_it{u-<%GQ6M^SXk~%8*lYMBYbuJs{OF4Yr*vJynn}}Kx|9R3~Pm0vk zPY=nu_dtuqrF{)#heLsT%0(h2QSDk0HCCBgI4H{T@(RO#yrYc7y3&zC%xk~dpalzV zGjQTN*4fb@%!_`^?*h@Vqj`8Q)8GF94M7>W<9s-tLH>zmg{!q9+5!k5{v*vr3^SCs z=+)G#=i~l6Z3lJ?XL@fach>phS-u-bZ+Zyj@Q(kH&e-W>4St0&y&o2dysXxAYsvJT z`6~nY93G4*h+ucktdTr^P9zt%XcV@w4paAKDkC=%v&8^&=& zpo1UbT1s-QiLAoCCen{IN23eVEn3SR2d9HQM~NVTHsA=Nv#=pTwZv{-kc1Iieta}U z&Ym`55?!u|oihN(%S3#Vs(;&9Cd8;hN`bP{}PG9sWPEe6*3BLQ5VY0GHRtHex7f1rUsGw>8$gQ=a=o|?394m z0P(YqsdhZQT}w;3t#L0SrwelO(#K#5a`O-rl?$`JRUFsaqr_-4;i<)^4A+hiwj5r) z%EA{gM<Igu~T&J}yoTb^N%9;+7Xy2qNYfH|lvfdAkD3F!5NJ?T`$v zvPG`+JJ|}|*DzMjEwyIs1-nGeBT-j#RamQ%?wzU)Jl_2@7gKFhZS02TWYZ($d#qHt z63~iM#8ui7*kyveXd|X0ow>k%L(|d}3f?%iUs`O<^D2D>F^0ciCOjo{19NyftGFsg znSrj#Q70p%&lf7x_JV0V)|0=d_9uHzrq#j(@7Fbt@kTs@8(0q~S+=}a z2$W;SSlUgYJ*}!3MRp86AupCsI_j*h>85Dj3SU5e_$B81sdY_rcO0x@ds@dpdjh+- zV%rgxaLj}`MaR{RiV`86|EWHQU4#)(_^>OWo?wmPgFyHzY((;kljBy8Db$#x%c;|r zBEhv@9G|8Ox>K&%>%)TwQdD+A)c~I=w8eZ_2Yj2}?i6)?@tYw;OJ5Pfsy@MH%5w77 z9Iqf@tDGA(bW5$xT(ePGFFVkx@&`|QnGn<{qGQVn7_azqqpnS!mQnRe$l@e~-}KqoD`%A! zU%G98$AwA11YK_P&HJm=Q8T|acoP|aw(H=Fp~UC$;clZV<+OaPzqdGp9FZJ25^`g7 ziEr=6>uhs_ZB$cjq=+rI)jZxr{C!N)&xYPj=Pa~mpgIQAjUj6j2Yy4og=FFts00t! z70@ZX_a7Dwtsgh|9fEWgtZC@mu{^N(&GMlg&*O%M1;XWYB~?nsJ_MDmAepNnD=m-M zUJ?u%gzPlbVR7-0VdO5M2nXi+qpq9EoEE~4sicqqf zW;$0~HcNAIvzJ40x0>9jUT;{43%IhfnvqTP<{Jo7YoSCN1kTp1C57d1Yx`!Czw^PI z5)ss^>B!%qZ+N^Jvkys*5E)OpLABMZhVq*LTG;B1PglovrSmp_U6=J6{mTR68;A3! z*6ytslv>2?V?K=PuG&_b;($Bc-t=ms0F3~%sue_PzOBe1S=jIEH2}b28u(vUqG>4< z7e-3vEw=<`xII)o5zZxSP^Zp#wqILGsV)+T+n^-$8Q|YMn?f1?i4e<(zzy_gOynm) zn3*Obz%56LG+69n6vxbo5ROpdDjS6823r^}v(!`ntiXK&vVf%$N?Ncq7m9&>XsPbG z^4a6vS@+Z2X$k4C{cjkUMUxvlxc z)~C~zmj<_LqST-FZ(>!-v)^+>5QVe?GgbjUm@ za#lgozWntSjl2~$?mMYHN+CKBCywVq0cvX@UuLeW6oG6upR-Mrmm;Ffg-vHzS2 z$9VPjderRFf=w+nIBS76AuzzlB50>Ftw+n$-0_ciR0!|eU`7PGV!73v@L+74F&L}1;fSU*U)@2<6`Fs5o$8!VJ8R{;5D*^!t%ekIEaa* zn}nsFi`7k$%uLGOM5e+WK{K;ghvUD;H&VI#?rY%0*VW0M$Ir{5wIkU|W9^{Tso)bR zQq1}pe~X7T5^}dDPQTD-Oq}i;;(58kZJULWHg>QY+pJGMIxMcJq)DyhtFm{&flxzK zwAR4xeX=r=rkNw@qM-VE0+@FUH* zpa_tXcj04pg1a~0_&~8Z*iUHb2y0SU5v%p#hf)h?^!@nxJ0cmBrF5J615Z^?tfP#V zsW!{0iJoy!a}f>SZay;#A59Xg_EzO#o&Q)e zuwUBP+}PNDoc7z{r9XsIG2Mp>6=Q=}S%L{GKT}JC2JTr#v@`?|`*{kX91cvjxeAy# z4MXaGG9k5W6Y!?1>>ycCIY1^JuZThuqaOGJ3}~&2_IYPs`>uwRuIJ!BlBp8-8DtFr zCkcY2dwqPLu&%^+0I9qn6dxDKJbj-^DK^MW9(YT!>^w9c7 z1af)|x`#GdiwyA=^A4i0D+-NN)JF5viNX5?fytm(N0(?wMzkf3m@@OQK;MKoWn}US^1o`wC%18w++mQHqHDZYUuBY?MQ^?~E_j2dK7XdvTV~WC zFToZi1JcD{QO@!0E=-a`KdIhmyUuCM1Ab*k?a1i&HPa#L8}NB!~FP_Uv);zC}8oAXKxSZIp+8bx5LIPM06teKSqpkLJsPpsqtaB zwk3JdWfKE9t`bvbD@fMrt`UkHj<3a4R*<#97S=lb{2%VswrRdBASqM^~= zR!s$snzAT4ixU4?rbfw5Oe7eJIo_^cl_JtVddsEJBEgQK4l7 z#9?N0yZKW=o~h}GDOl$?%)iD?jDzLTt4XL=ez{PPDb`qBV>?}m=kODqSxHMjY(QuwtZ8T<-dvO8 zLDszH^GyN!Uet+8NwhWdl>i&cZXJ<9-&#R=CcGgqW6aq<1LwLl=(8PxlDN=JPK1>X z>x3Z*4|CF2?0^$oa^0|Yp%rdl97pMdtg4gx*{6N=&vI^bir)x)92pMa$#9N**@}j6 z1$laCDvrAyII!)db=|J5pL3att|GtSdHM^g-`OO~xB;sTCHbjeMi)bAb6?K`8H->-_53oW<+Q|{Y6?v6!;L9Iv z{VOM(h!N$I)7_t)F!~XXn^|aCOHnEyMa;&OtbZFXT~5wXbSp;H{mkr94kgBMi!TZq z#)?Wzp9|p|lW_fmzXR6qsMNmD&%&E)K}HAX2Y!HPKZ0O(7X4D8Ml8pnwH!QaX%CIY zoO@qWZngV8DZ?dAzzs&39GR(B9k8rTNXMqqq)v86b|tP}K1biuE++21;W(roZN9oYWCyFUgwl!n`1#2O6*#&Q=9_lPBMCwq_Li2(EE2Tsf>ctEcZ#Z z<|Hk;>!y?hReA=Gj77|#h~!H)P9g!U#Gh6T^5aE*47H`PKwYnqLrQONwx?GTDx=Kb zV)^oleR(K;s##c8>@O4WDu-V{(ky1}a-ukYQ;Lti7O!4ogo(XxxJLys0$miOWMP{x z!F@ZNpa{-Y752jL-fc^?9JSbUU>DAa7T;P*?uWyJd+e^sTS4?Z!7s0XE={_c=U;vT-^7R^triLt{)5-+n*mpy(t2aF=nu zf$jnz6iJ=t4@%}c#gxsKljY(c!-q7C@dS)%lH{(dd$$8D?oRlxEgg}?_^Z`DTor`8 zpqVDzOmP5IM|>*8LvXbpQf2JH4^UvKB-^MM4ofiye;*3{u7Mdfb33Zvvp8T>;W;jO zM@{1iBFfy)A4)~qTlGT5JoSaeU{q0*&D5mhRQ%L@c-Ne=is6*=HWT$G?1i-#wySKt zpw?;{=ei`=;8dc&->X&&e(tN2u_Nf@Qk&jJS>gzfMhoMxal7+-X3 zD3j=*hv&S>S5zx~l?jZkM1j5_&)Fg>tNt#aw>uOA07sb*H?1CM>?LCA*-LvPD&yT< zHIOMc**AXcjM`TQ!%=RklPL?fX~bhuj^}GSV)jPOO>hVs*bPJor$lR$W&&9e$cTA| zii%r$!1xMvsmPfw4Lv*{VOPoZPKcXF`1o?nT}2ep!(mWda27B6a7PVLhCIg)V$85f z@G^?^)AyS5JSY=S40Dtftm;S!F%??V_`g&w)-1d@vC)c_`Iw;kvm?QNNc{4SidbIb zr(*BP>`EoeuD}ef=6zvFDO0jD1>kt?567}CrJ_XKqucDd7 zG#>j$1k5FiCy#J+V~X6&cI<<`G5jfPuy2MdfLs*BW?`#;(+PhjHU2sO>*9Aqc95n; z8@b`8R4KU?{KpCsynhW$m;g>c#0)Dm+`uq~$mGLii7ss_b&Hn)TbRc;HpDSm-BIQS zmQj|2*`&*h`5TU|K-qXNE(s-xd@1cI-o=8TVC>&AK@`AeNa(8cT1}X)%N1LhJiI7(iUfJ* zH$Dbxyp0Nykx}cyolkpvXz}aVuDk$Jy7I5}7*+d;15Fj&=vTj3B0DDm`B+$C16osr zg-s57>}`f@YX*c|VY3Q7GPus-`^tMp?lBAjS=ab2vn}++&Kh|(mf(As;SZCw3x^D* z0A?wh0xg{_6|E#csx4BYhXDE}gBFhxkx;i*5x~LE|N8_qLq{mNt1pdFT#Zm}41`$Z z>rYCG*uWJqgnenXSZ76tJ@WI-ArG#McvMVxP$>g6BtVvRtN4J-@?TZpIV3`L8 z;9b@5H(;lfCUs*BVyvuBH=e1vS%{d&Q5L@6i_e^VI)qt!HxGapoaUt$@aU-Xni-KQ z#RNSrt;P$xVE-hqHg_shR0?dZbp%Q?=s4lETk{d#aA}Fi;FH7?Oe$W!!^1gJ_>_X1!PEcXcCAT5Tm zKNfV`|8ot;G{$+J{Dl6D{-qvj*UF+VW)Y^Nlxh&6wV$9P8^`)E-ru9AutViv5w2?#?&cS=x?6U z+x_;$EIAItf&eq-w-~?0Kpu&`Un`B_1@ih_HN z(3ca~PpeR&MhOcfLHmJ@EpKn;j-9omifa5|-9q{Az(AqV9=ejpN%AlBm5J3-Mwqal zF|mn}#7^H1%4~3D5>tM(CXAV~bBWK3_2b137~m?ik6tq|v^pa*jW>0hTYh2$xw+l2 zzgd5$^AVi>5phNG7%2G;3^fDv;QEp&fEq1}XI9zwIRaBzMJ zO-j{%2P4PSquGSoDeTV%Zrm+CA^eJ;*-axHx04i>&xT@f?MVMH(|7GslFCI3R|&bp zuUPAYn_)X28`+stZW@Ox{@2(MXU|@&UL@ybE0-+cEt|ZnzWk{@TcRFzpB{$8l~6#o z?u~rvqSy72hEvdb5vkZXhc5$ssE9A@RZf<)t+x7 zSzJHiw@k4hME);K@AE-wrL7=3-eO!LFwv-XTKsjflof8ty4d)*uHIwWJCy9NMl)3} zpZ5CSlZP42b?*9=TK4Lp_=cz#vJ`sTrNJJC6OZv3pP!~ma}%j8?VXw}AC;G9Zo`^% zc0?my40a3T?4v;*iFTG8S8CSU&-hF0>_Asp3x#v%AQE3K4=n!S{1Ctl+rK{kp?Yo5 ze4bv!9d+&jG>H)FRY-D(|NcjBsmY7Wp^5lV2Nhq)!HMKGr|Cm}z7%oe5B zOsP>%mI`lWN7#WF~ql_Rsty#FKan;&Cto&#gW|o)dt-xUsX)32gkOw!4 zH9cj6%AE{upT&b#JVk3^e|YY%x(riSip7zXP`pz{B=zQ~5>n^wRvD_cd?zv!alcg~ z^5sFyrTgRHO=!c4p_Sff(lehpj9aF82)@m+TCYSc{ovNPp{iequ91*?e353vD zFcT^s_NR80jcqpwRabGajL08dhGdiqkk+$X(>K zg>#uT!}klrVU1?@u-0l}bb>!TM_zyXP8_*KqH@$J)e`~|h%! zXi^v1r*b4mc%hJTiM9Cvp}h~jKJudaAy1dVY8M0R(&ly zeKjOtFs7O)CGd*r$#g`xmY5y30u#=&{TDFs(h9e)8KfjS01u$Gw%S0IPYdIbs|((f zr&2TvnFfDM5yYW^CkOdwqxV|cZqm(hzr^ga-fnYSS!oMs2w+#o4+YkFxGWD9Th^tl zPy1=V`g+jCYfbB_F|@0zXJMu$uos63C<~efJuR~J69|-9dv`+_7ta<`o{g!x*)gn- z^kJP!!D{wd(z%O@u??;_KUA?rrDnP3_NNY%@^ZFmv79H z#NTZfai-eap7L_WeAoUDcMni|vWT+#sWnp@EWr&E+j#o&z;^QTZl(6b(DKIfHzyc7 z-+Q2!8_D%A*^SDmaR~%7op=AZM8Nx2T_aK+2)?Gi$6*4J0n#W(1<@`7_xIJ}GB(@| ztMBc>8Qzp8%qn2{Df~u9!GfRombl-$V^#Fg@rCe}i!#?hp0(f=< zqeCFI;6OIc|D@Coe|uy4Rw6nINrr`Fag4^QN=sr?EQJK7ra3~3KK}dXg~U(;asO_< zgZi(->Uv_}78#2)Ai*gT+LYR91lv+m|Lzk@O+)-|i!d0-p5E4;r@@Ac{pV^PSvYZ| z@9<42r(#PGLj0S^JPpeK7BIK=KE1O^GQRexo$tR&C#0UWYQWBgY__uLQI2oKPuXxn zgiQPS6T=fi+;?8$Om`yrY+MD^25)H7D?JA}!s`P21$P(;Fv|27ujVrc^Nj7THs_JLAaqbuZh9ueuEppK=e6Z6W8;9L|6bRSm?w);h+2EBZo;u50wAf=-6Ng5Nd+#Pv*Mngbxy3E~DqoV??hcHAQ%yRP9!{yi?_HX^(; zUZR(8IGVQHF&NS8{|DtV=}?rBls1bs&VYca!t!f0*>FUq^N9--Ll15vJYaP9qGUPxBCl z|NfehYaIbyLIe`lpfZ2ed=q9ZMA)V ze41_Z5pE!QO*+2m=hJiYH3&4ilFoBC8k4O5QKqmF>b?CPzR4ybcWK>-RXi0 z>rI%?3_8jjUjVP0zPEDY?1Bi(hdjgGF8^@w@kRYX^;7voE9W5-jOk=Q(Q68QDBr8D znyi>E{a^XCW`LM1s+_Q^IT1i5-eh64%X8XR2|}Xy^>zr?wKSrjtry_c90NTIj`)LJ zzrMDjJa=Lk!O}}c&cmb($o3v-jRFu(r;~-**BiD1^7{s>#72SMf8@PKndXG4aAARB z@i;mW4fZEP-4MQoh@+Kw8gM*F1gA|y&C#Hv7g1)lm8gImujDog~0znDMp8pNdF&&!caXWPPDVxv{kjHjhrXK3pB3+(*r$S(H*A| zrrLEE%j&*{@40$Vih>s!dm&a>T)yAkIW4&)}=!&s! zN5+Ob_=^9z-=iHwpreA2g07fDM7L=Q6UAfigi|(Jg55hmZz1H_svH8-dKU}Eg+9o0 zbSSJJ!|xx_;&*ht7kfw`;M|(kjTI&o>t^>(XD{Q41IhIYrayf;@MgGz^TGQ@eGy!1 zS2TS1bav`h8G^40kkZN1Wt zDy@cs`}8%*Q?(-cw8UAjNWPz_OB&)sU@fx29!Gx1Pi;6Fps1FeEhn3rnY+UunW7rr z>g;XU`?RnS$MhzRGO{&;$1mBM*WQhZ4D@?>Svq1^0 z434|VB(<|wNcsOa=D|oWTvt|l8j4&B;S<0-g?htA-tdWRus+UX(v}w4G3LqSM1vNZ z>HU?2z;q0hop?lw+n1{hK~o7b$Hm96p1Qipuoz0Ok$Z~2v{?)#? zP>w5|eDxvqd;cp(_A~15o)~O3qi`%T;UTvWzao@u>=Zq_Pq)@--b$wQ$(JO-(QT-o z$2CRE{&G)S^p2Z|jslf&UulBEVL*)!N)ywxa}O?QNfH)&`%S;oTZb?-_y-^)(g)2+ z@Qy?;3{uZ=d!UXTpp22#GULT#UGtq4!Lcei(tR%=eCng^pAgd_XVWcgBxM_2oTiHvtC1sQm^pes&tgi|K0 zDe_;B{#b%X29_3(RKR0N?t)E4KfaUU0K5Vc9#^b;4-eb-d?9UbPqTE^!!f3wqER|9 zGjXfK3u;Kx?OTf}Wjl>>lP7NwG9I4h4T9!30<$S0Pr-8mtpz{Ug=Qte#X*@tKVZ)3 zC@`;-m!MIhF-|lvQG~aA(Mf!|OOTjCmo8OhCEaQ{ASP3er0EQ>UF1Sb$DJd;KZX68 zsptwwsQ~?h%U$lq=<{1-P&I%ZU68R=9U;4k>rq%BZ$M?h&@6FwT43H&>ZXxDcs`FK z5TYu-v0;6Yw$$vZ=7+G#VklbPvPzV62x9vDI_Kn07hI?>Ojed@RWFch)BeM2Zx~D& z&UPBQ%WcURp#J}ud_kF1Z#@HHQn zV7eF*ve05bW-)~(kj0+$Mr0d`?1Tcx^2C3B1Lr)<0lRWt z9)eJP@qhCw+MebFWre3T^N1yJmAf8Y#7Sm|cRFuKKQ9m{1D$}!$kEIAt0h^$cE@KN z5{n^(e?OWUUb}9#<;Wflttb5$o z-gEf%`Qtke)|!EoEfi&iL&O)eb22AIP6&r z0?yMDcYz#1x=BFe>#xCS%(?IebLY;Qgg#JgE_E7=c%O7-Ex1@1jkSNt;6N7T6N09^ zxuO8KvTs->HpF&yJf2{ak*=U4f>gT6-TImbDC1JOt=Wm>tl@{husz$k=%wXJIZGlU77S;@C>;UAdFu;r`rpd}D(+WrtW~ zERu!EkNb+mr8N`XX>sn`hQ2T$>CSzna@*ru0_Z*}z_-mM2BM)wKs0ni7lMN$tAvh6 zG>ce)%d5gGANt48flV3HYsX2~c+T-1pR}zDn)y77ad2WhU^9Z=vk+?O8!$OmV!gmX z5Fu~U))8s8GamNo<~Q&Jt0}!Ml%lh^nqqO@>322@TPA%q(wP1}%W{T%OhWApGtj@noP$pkVxJ>NzQ9;kSG0#ESELA6BO;*aXYFe04<4Aw9P@R@Iyg;7^(QPzQoXgpq2V)9o~-XB}3kQ-d=Z5U_C2<2tf;yOWN)RoFYQ|A!k*J?WwiA9xD0r&Qy=J;g~_Y4l5%GH z_>4O?Dpzq{?Vm58V&4R5Q6ztDNW_q1r1yAirzyP9x$vEGG*&TvlKaYSC~tm$HNk%Y zL+h-$*}H{_Er5Yo7M{}UsKAbXrcN~>skoGB)u>Sl4|n!Bfo|eS&H9UlZ}hG90m}oN zh03BAyL0(2T1afpS{}d%whBwlDBDZ^ZG-Zg0S;O~2(C4P!4wo$IL)b>8__m&FA$sg zW&_Lv6Hq8&b^ZC-H{GP}lViUDF9Y-!>?WN`p#{xzCB;?LRU1+qO9rSD3A`+p($Mu=q891ITcn>lMYOHYZf)n z*9szF8|s*@d!`{Fb}nalIgqcu=;EMnN7F*@)_QT2+;x}Cvu!MFnN(UMO17tet#VSO zuTFiY0^c8#Q`-wh?n=UuHO-{ZOaIJwVW3@!F9XQ7BMfxR(#N-U8++e22yK7Ai1tv_ z#Ux$i_vvThJ4;mX?6}lt@Jspn!a#cUsaiPS859FiNu8Z#Frm^SIhWnzX_~2gs_-Zk z_uM`_Y+YD3mfAP##6pxp@C~hov(6v3p-U2}p3#IkrGERT)e$QB`fq?3%f%ciLX2VW zW?6DI>KXw5=)!myqG8J3-POaa!)c%U0bW_Af`i!hm z{WC~KJ9mc=p^#wJguH%=Q{rb=sn;Xu_-d$XeqMJ)^PC3qvk%gFq7Ww84s z*=$|ky-nsc)ayMvQ9-A75Qj0p9WQ-&rXo#7P)6n+V{K2Ft8RUoUy)IUt_=i;Q&PXA zQ_u2_+XpBWLr~k8gc0rq>CgD!S6w+pGMPIhwbK(k^e`dvZQf{lYNg+$^;spMK2Z44 zv%D+>@t)puQ!8K#u7Xjj8zgUehka#h?u)n&Z~tgGX)yJEUSeH9?t%d`#NITbUb44% z51O%VaALIhBc9!%2|u%;Z-B(S#5*Awh{I5}-HcsiIidhCtMSJC-yNqdjj*H3w>W+Y z-G*tzC+=TY=V&eMnigG_kji@`ti8`CDF#wS=~&hy?FP!RLX&dr_wIczs+GLotiH_e zdMtA=nIyrMkI@M8lZV9_=h#hI{=2z>!+cu$uwp1IFL$A5OnE-`p?5%_1Y?{7N+%-UO3mORSZXvi^aCd^cySs$o?(Po3A-KB} zU>AqQ?OX2qdB5{MRp(TlKX$ifXRhgx+TS?QVWSFQ-NQk}CBJ`*GOw|m-aD?8(l)U&pUSJo1c9%cnr+*Rp%glkR&6OFp` z;V}?x(HYd6F2-}G9KZ-buF?bFVsXQZOm zxVyYH${KSWUFhEYp4sS|pi{y82s}-3G(Z{`m0` zOaN9P2#@{G1eC6!Q>;Nl{`ph}w5 zEL7mRVh2N0ub&{$lTS(!eGpd|dQqe+<@~SR`5A94e${^XNr=NdJysS=Fs&?k_XZUB zLpJ~qUd0B?xx}b+F$NZTM>In2!F%-N-C)Oq7acsYnNRkwOy8AgC`Q0TtOK>fyx z>*w>+3GWkRM}s89_fUVhN(xB&SZH?O6)8oS93I);Rj8>fFUs_z4BJ>1%#}_BS}0pv5nzH-$GcoE8L^U*x|b zK8sCCKr~9 zwVB-y;crj6TcV^Ja66RU#v)r|jA2Gu*(t7;sE-VAT@u=x1hHQ7`ht#}1joj+H>p!-PKnv*uG$ zwRiC)6-I?lLE099r86_c5+8(TV@D9oDm-WeiAL3$3K1gFc8|MCu&UhEZgbGQM78JX5`$kqhsvC(o6Z8k(tyih9d_Tzv{%yjt5p2 zif&&oxO}vVo?ujpJY~TsF+XhRZ+W~xMa>%C-B@>*A@I%ll_Me9%_|W*oea#%Y*Nef z%35fFlBpnHTby^4g8Q^RVp~sdBtusGLl~{lF*0`)=lhdU?`q{=T=u*5)uf-u4GUb~ zp&(uZE6&xbd#EZ)7jCW1;J;eiTPEyR2JI|ACRLoD!QLeo;H{6`{0M+;%S*9}LE~BU zjj?5K5n-H{pEVch#Ei~Zs3-20XtJ3Cdn|siC$>mNYTET4VFQ?Ki&x{*49;|HHfTSC zBYa%2ne@7)G8#n&d9`7KoztKt=OduW8MXjHB0q>`8y_NaDa8_UO)F z^TC{uTC!^mh;oJVIpB;}#>dM)IZ5!}0GLcTR1~2y zptI3S6QC2ThR>8sgMxQ-Nya3jdoL-o)g8ne3=kK&tT0lobBBEsMmpRi{fz!}a>${o zx_yvRkk0yyEL$`=@a_RnWw}v3I)-#{+lnT<&M$_v8BwE##(M+tZ0M81z4 zOEYT{jmqtOsxKRt98yzv4pTbn+&RoZ4Uli{7Xu@b8176!64v$Kzx$0adtqU{e{FbK zHWx<2SGwx23#30qvq9|X-I^r7WCD&Ku^*t*1&b05C*pp5%~Zh&UBna6}dGyWvn zu92yOW1$bro8M?JO$u4#7DiK&HjX@K-Zh7R?p#WpbyJgPs)szj;XjW)+n+yzAn!Bke54j^~eyGz14Pq`Jm zME+o=)Bu#v?ui+_R<*5o$dBj$K90+I^_z?`uKi)%x_;KFZBNJOY*1{}ZF^Ac+FabM zCT590NfNs&IDGS!HzH62bX&Im0D7=S?LF9%!^%-l&9BvPh)o2D2Q4+%e0j9A-567F z?!HZRxGWMEqFQMnXpCr8c2i!FKkXneO8TyqokW(@l0ZQpl>$SE!cU-z2X)Dmtoe+Isk1}Inm~Rp_B<+=ucTxjhgo#251qj#T>?{0Sf3nXkd2>?* zytxDE!KA1S)sTks#XJH7K1AM^{<)`GA!ZFN=l_v%7GC~Hi1x`Uy)rLuwO64jXIF)M zp{1?&xS>i`s?bz^+>hMwiQ<1}=DEFmb`7dGzK)Kc{(pi@DK` zP5+k@3*JZqzXkF4ewl(-AL5w|@9~BqPzAl}kDSir>pU*yh6dk_sfvQ*>m|?4l7fLU z)^QSiKN8A?9;8Fv`C^Ta)yyeQ32DzWgiWEuEeS{47?syB*`aHb{+-%rp;{7kGqCPj zS#WU;hz$5>ui@WR==}S0Z2R3nJse1b4})?@28sK8Tgbc;(rOzrlPHX_u|ckPZ)Ikd zZnn9;Cdt)e3y6Bp>XW|bIRrA@6c6g{PRYEGFI5U11x*m6SZ}mz!OyX?eNJ7qU@y?C zXd?9K5__dCPwZ9&0K!JhMYP_IIK|uyGG|E=NoX&3%XtQjU^Y(m3OhdZ#sc>6u4_g! zv7L+)h?#q*lwg_~vfP$ix~5IVl>PRb?|%7Hu{?qg7Y~O>3NaB*k^DmN9#GS+lT&v# zL)u&O>%d~p{hJTFdq=M7-w#G9KZY#ygFILmPM#Z7glY6Ul~V2p`!($&gU!JTw2QTs_oT2OsNS`i65i#d6Y*HQo zi2K6|pGDIppXS1GL`gJ5*x7z{xsZ9-YG=JN) z;uCAjp!{+3(2UTm3#uhfLW=D%iu&4V@P+3!vvbtX@}1**QpLyP(8JIG*$zSaFqu@DR3-T1i+1`Pv96A;rAD^y^GVKpfI4MG5Wy60 zMbM7fiRh`x-RIKZzqe^Di96Axjw91k?z|h8-d4*{bUIb42 zPO_&28&SFh@;NXz+$#zWCvxg!XROR9*!+RC6LaJ30{J{{eh>Hc|6> zY#{gf7PV61+}O{oPm#+S*Aw<86CIH*=NKp)BU7@(MWfMMv3mDy#0KZ?2+Cp7!NtYV z*~xMJ(cW{8_w702hRVutiiHE_X+MFR^t%Z-ta`gheWOvSC5fp=@+FnG-4**$Y*?Hp zqTD+1(dA>Ign4}zRU7y6WpyZ@0B@PW8K7pq#>(I=w_akQ;1&of6Ab!^*HuRm^l{cT z6r|Nt;|V{|vI!Ci(;17KpDx2SGNBnS0xDHXcvM*(bl;_*`QgD}trl?-!SJ1@2PE8Q zq^1b?AEEb%C+*V(`g-MZnMN0woT3X5ObfBcg6c84Eck3XCq5Y8RERx#ton0JQy+8c zo%T=>2EC!UZkD6Z5xYz*L(b2VMIL#kfDIiWr@M`xLUj&5NM+ewf+pqJM_~&hq>9+2 zK#*L&tVCM@wD5InEz8pW>1)Mu3h^j!gsY-4g1w&I<``^Cp2=LhcIsHsQ_GB^|O)XR}{(|1U75|=b zmF%);*ktPR-DL%V2)@A^Cgw-3(xLZ2e$aEPvk9l-i=kwR?P1%t$!az@m`8q51R@XU z@!(~m$xptIgB*Y`@4g5?AhjN%otN}%@!fyoC$OW!3RogflLXVURoKWH(O1UM*R5M5 zJGDQ=m>?`xyl+jN$w96%+iB3%-b;p#YZ7M(qpppcZ62 ztE;^}y==$okGE~fNg2oWHdqt-xdMkaPF=`S9@>9COeXu4g){Qvnf=-qv_|7d(suxUvyw7%OV1+Ih$Rl?n=QO}XP$kG;3f9tW41$`tzMJ;XqLD` ziMk5cd@&2Yv2({h?S1)KaQm9vLs0rvCVQXyNu(Qf*iRM|WE@lRZExqT02=Rzr?kB& zP~%X{ibgPsyb!%wA@-`*U&td;dD3mV42zf3=)Mzu${-=%TRT&0pU+F`M`CpF? z(i5r*J=}gJ8{&r;(;9a3`j5HgQtYqg-8CUi{oD0bZkhM8S2Y<_h{3w)}a;cooiY&p`gUgLho?mfk_o9R`5ltA`KI(l~;V-12gb^%5W||~ zOFg`0Bh2KsFTXmUOG2_oWOvOz$gU|4XVvVfd$VSW(eamjMr4_HZ$`Wn4ae7xw{=7g zC2xi89ig&h0nfQn;6?S$HN75G{k*ALvAnOm5IWImIHEmHXjb#LD1f1p9k{xBnk?Wt z+*R{PT7qkJb@o+2x;l~VL82=_ubXo^ElaP9dtoI@uS#Mx?+?Yj{h&a&+a{4)0Gl$5@Z%jymeLqxKgiI~!Sl?3iL*LLY?f zknYW&9lxv|XAztDc+T(&zPLMXwhO-W&^&aAYLMBLMv=k6Ip3jeeCy*AjF%*mgf?~u za5yK%ktXRWZ;F*V&A+;2iK(F!SmZAKrEZ!A3}*PtGsNNIDa_s}PeYEe^B$!t4P=q& z9+c`+A8n0Ao7mc}$~9f%!kR@`&AKRI}~!t%H!5&b7GP-bg1l%yGT)Pj0P{J74y7D z;7MF#A9pE- zj}vr^^tR0K%oi)czW9Ja?m&hby;HPA@LJJ04aUnfQjDxcJ|Yk z5l&b-R-%sDj%+_gv6T_DK%=N35vC`}MO^-d;TofFp4TIQVzrggw2iY-0^gKNxDi)C z+nr{?AXiVK!Nf9cj);AxeIs?-JS-G;9{84PCDXIVtk+TzX8*(T0yt)EMXSxt+KD`Q zqs_J&BwwiD)oO+Q`U_)s!D(<`P6xjDQ^2>mJ79kIGeC!_IM0-8)Qw%3a;ux*+5G2SiAPJdOF)0Dc3`RA`>4jMxq zV>nG#i@r3L^Qsr!A5u(z>D3W3{T>Jf)D^392e$_hl-DauPz$naSh`yvrt@(9(O`we zVi+K%y-CGAR~V3P69Yx`AlN(6Ag9GA%DvhlEFh<$aw{Z!pmN!YQhYu`w9_dd`QK8- zL*;sSU?@ON6XJTkmtYY10-*)rTu%A^E!*b^fqL}OV)rlPQT$~Wtber^{vwR ze+Gp$Y7c~kJmgmuh(?H`zjVR`zXoIqa*_QH*kOc`{cq0-`ru3T5lAnp27=KkV-QJ8 zS5y1o%dZMAAh)2D?je}acRza@>=`k63*Y+}g@vFakV>Wmqj&NP{$^CHFh`!B-bYJ! z_duQpMxQf$Eam6~e@p@h=9dFut#W-~!QugOvW-A-xD(e4SCwkIDBwacyf^ozQ~|=d zxUrrI+=RbUkkj2T$`I^eVi8uVWN3w8-2kN3&jgXK0x^RPe!#O0DISjca+dZ8DwhZK zz2#Mpw8*)HJpOPSXzZ6)5Y9oD0x;9_Y+gZ|jYWi2JiE}HIc9PAw zwYa!;Iw}d6RZIuvg7Ofiy=-aSN!p~m4+ncUCDPFGb22p;!SG?R&xi6U(Y6FXq9_M2 zYDinrcwFo5+jKRFqE(G;m#5g6n3IFdGTCZ4N_2mU{2FURNi7H-1IU8%opdL~bLNtR zk*#c``UY_kB)Pg|2)#)qDAFi(E_f+-=&aN?)~I&s)Ay-%9?x-8?Ei*A=I0TyUmJa3 zEMbF)nsniTx0hG>z*t&Gg@`K|;&1Dk8kmO|ZIWo;dmJBJ0hYO4YVep97>~ulAf=AHmsaGY%gPcfcqzu6Urr20{t^e0kmRJA42!;ynaX2c@P801l z<*pL#U+$u$TdxLnENI~;I)4R^d7v(}t^r?-XMyYB)d!1F?45_pO04RC*K^O*e6>~s z%A{aqy)a6hcY%BHZqW$%&f59K@E<(6l<1(=_CWrE9#GQgnN=CnKnl$U!;c19bJZJ| zL^)Z1qZTX~?lxM9&v{8UVNY}CNXySQJb1{1@XZ;Ewq^=HRfX+h zo`!DtCqaO`mM>cD8ZP1AHED`d^I(Pxt?A<9;;9! zq}opS0g-bD$61Kk-=Fjd#LqyCYfJUZK{rE4a-W5Bhkjy{8B9aBubd(+Bj7z0LVz`X*msS8 zb8<3L*?)ZMR@q+?(&#gKVSoTwyDC-oXC@#+Q}+KJhWwH2VOB4B#@|d&4|2D2i0iKY zm_T1l1qlP(E{3C)Yp15WBUY$`AP~BszwYc9<0%KWo6+M zL8RrJ7C|IH4JiKy{ZT4{Fk}}dDuk#*!~G(BRYgi$06Edw2{qt>KGNa<{F`nJX=EV{ z3B{4^0;!C^VvIa1XSYOr@%uxxx3d55<9MjT_W`0{K3F(xX9Zc0o(_Ki;V{2&h#b$| z@dSw@`6@P51f!{6l4KO9AdohRcd-C-yvVVD6$O4x{8naBz=%P48zqHgn5M_Tz7ezf zKqyn%+%!3QS{u0gw!lwrZMxz+on;hm4adc3Vk&etr)m*za#rRQoo&~*J6g8_5+>77H6Gh^rR25Q;Z(@#vgg1ru0;D8rr zQgoU)(Z%j>60%s{4o!)Hhi+f4#g;G&jKb;%>r9Hq`RH6MSc3B8FD*mOfx;j-K@XRs z^voa1R%R)x<}=^NdzNEHLxo(N{Hg>CvfmJI^OY!E)R5Xx-*z^L3C0rsvy@m3f4k)I zJN^;~u|a8tNvY?ZdYZtUwqu3iliN*=LcCx~6(ZWC=izyi7}PbFD0D+N(!CIRdx zRvIUmxl-l)_+Q);3g>5pdoXK%sZCMMtzVcW$nx2dhBr~Bg%W7T%LbJp9+}?Jx(CAz z@k$l%xJa_e5hRZ{@g%2+H(4c;b+tQ8T%rn{D3lmxtpvA~r13KzAq7I@sJS ze7%%dM~-Az3*$LI&;I*OR;Ik_2&A=`;(@pR^ zmh1a~IhPV3zkxwHSp`OTU-JJ^6DDM;%C^_yvEyDg1$35C-@wc-hk8PpJPNaPNc0+i z1vgUwvPKLT@!rg=9HgS`@0q(r+3}uzlO%csHv(leh1vcAy4nH>=cK}INEUlV3s~|Q z@F?&dCnU@Z;5>pgMTPrQ(q;G(g@FJ6tRchx4{NJJBE*I*07a<*BxNz-7;|m0!hiR^ zh&_J0S+ciE-9Xfcm51dY@bdD=dB5z~J6H4#5CkRbx)F6yA?E%tL8g!4z0-7T>t#=u zRg3eHz}M--KbOnBYO}QyeXE`yZ1J(r0ACxM217J1WD`%wU^|WCd=^3QwfvE5V!*8d zU_%6(LsL;G9L={jw`el2_J+UFFhu_Hn3qxT8wH}!LxLP^ZtkluFby|A;sio(*ah9H zQhn;Tle*-^7gr^nEDn$tAoaXMr=w6-lX?=&KkLesp`xu>)36k&_Tne3(5A#g8IC*c zo+TJ?VLR#SH^O|B6mIE1Vuj zQXi7~txhn43r>Y$nXvT4Hkbcx2lV(2=OKu8g=U?^IcQRB{y~h&?`6lQ2FvbYl43TB z%j3=Q@tWy8@Yq6{BJ0w{>%%-$3@$Yt*<;Ii4qohAaw7>AO8Oxpo1)OH<9r`VN15bBK85|Qjw+%*FdHZxbgdzf!yjVSOy$$(d>AYNs#V58TR06fFB&WZBQ6?!7 zMsJ^=w=dqoyU9KBn$;#P7~Z*;a+?jrY)^`&;P_lhLd1Vd9d~MZNUm5%7`rshW|3?p z5Y_00?&j`+VG5e%`d8UzKf_KSN%?Gm-RnCa5wTq=P*e(|q83%u;)cc*#r4v$-9>CXO1*{= zlyx`dQ1=EApwX1KhIe?QxaFT`S+K{1EtCqVYgC9ZyF6@?y_SK#5SYHo#)JV|MANO4 zP)cWCiMD*Ih9O6r$jD`0~RdRq8v1uIb2NR0 z!y4y8gDYcvf0p^!Nd`wzVvMX*qx!2usTj%v6JzvbOtzHj3F1O|uO!TS;F7tThW9p? z!dXjP*Uh*drTxoZFq%463&C5c>}BcasJvaaU%5iFApqBFu2&Q-{hX+?K;_Uog;9!# zqci!9@^XiTes+Usrc_^UeD#Sfm6lVn4nN$1IP^`Jg3AkQg}DA7RUcf=N4-r;d|4>4-e}7(C)A=}056$z8;9IFiQ_n+(LgO4T*o=8rG_}+aKzo4m*zazSClNPFsTxObEY0pYB=g65%gqhMK!5AcDTEoRM$o$wdJ z6b2}PF`{Usfy+y^EIN&wtx#WVS63-gH7`RT{?@Z#4B-mb?lW2MFDdpjquA~6PTFFU1L=XY=_3te^_Bo~~0{cv~${(cD0Uq89C@n38zBO@TE0 zJlpNdB`kwf#R*cna{p$kI8-1HrRXVgu^pE~J=(tQ?(nrzPUR)leGHC8T6!Q+$ge|h zo45R^wO}T_KGb18LUl}4f5_(3#NO)MHf>s`{O5*N6)Fa`0!)_cCx@p?C70~hS~-<) zjZ1~>!4>-pPK$0dX8{@X0r;-r72`>U);%@#BR-JHP{}zFx8O&+ueLs@D1E;PGQJq= zcG1AEW53)pJ#`n%9MI{~!0l;HSw7ch&z;WAB~6l6*`gOE>Tx@iAnzuyrS}7e%IhD0Hb9sGi@*t<2eI#cB z3b8U^RZCbTW(Z9Kpij>M!$9Pm3@YL64gpC~Ah->^VV%Q-tLk5ogU7F`3W_1|-F!zZ z+yW#ujdK{!%5y2civylS92lJFV$9V3jKXR?Nl>LW0V1^?^X7>xf^KP$9~y=5VGEuY&F981$8K4!J!}-^`2|D@vMWJd*E{UI?5#&PbGg^dBxs>* zIOjBKVr32t07%a^h$=%sOqp`5VFge(X{B|ygpeR?=czg^%;wMG4}yFIQ&?f}(Gj z8)7vcDrhyGUaG5n?OjqbD;pg@VrXoUxBI&Kr+*-34uRwegbBWbQ8W?VhTgpYAae90Z zLl!pYEt^om(@Mgp;cDa*j@U#q53=p#)@&L#D;`y-*dh_%+l+T4yHe;|ocl|qDWq{H zPm@nI{QwK(fC7qwmY?GVPle=3z@Z9#uhsva7g#XQXymM0pURtaFGgLciW^e81K}ka zKFxoB5d039srMZiwf2wQSSi&e_pN=t4HNi&8@JAXvNdWbG-4CbOnTxryB!iBu%m0f z1+|rI_}bS^6sqx24`ZV{P7C<+u|EK0&I|RFH`EaF^35KfK3?7Ndck`80NOb1!q=U+ z@97=MbV}z~-CO&4cFu0s=H}T^)~{IWC*SD|C-Ht3s6zkP<(Gg{i*|d;rvqK~Izk-9 zE1m~=kII6V+hvlbSB1sjU+qHYl_mOLPaNV8U@n2RpSzTJlUfUjYdx_D8NQ|CqFkGr zugn%U*3Yh(@+;54wQL%QR%BfVE6eGyY5klgggGBB7g;s;xE5Zkb|hX6skj*`zcjgq zYnrAGF(I`0*=r?J8b�*%Z<-(c+n;V#KYBcnaC+^QjWgkGqA7{g&2)d;?A>!p)D$ z+Dn42g5<8a%Wp_1M?C1{b&kP9im(R?kNHEGO{szt4Yzj?+=;FK!}=%??m{ld-AfTz z$hZCMGZlSrHZ=dbX-#D~tAJcqTft+ZP}yyw3`Q``l*y)}#Y;m@nw={?Q&oUBg*DZ{ zu#I4jsoI|2>R)73rXL0yG^U~+2Iz?r8_%q5JA1mARzq<)s=Bk2Z@nGdqRA=P4b>p~ zfbPv6X`T@uo#`nf|9k0c0gmO^-Kxq%j^K z*6m8942W;7#TEE|C1keVx;yTr_u*(-lG5(_B|_JfLqb3*)IGCQ2tycQaNka*EF*3k zHn-fV1*g-$Es|q^%V%{(eeE6AyfFA-)oL}q5Zz_eW{NmXPu-P6%Ps^vx=laPq_$}9 z%AV&Zr9su?$IZtRjOE1=s=r66cT`izk?eACQm#P8F69=Uwk zEmsIuz{NX3tU1TzEQ~^>1YJ?9pzTsmzc|vK2lt0x|iaBc}L)rYepG1N=KYutH zp>{Crsj2ep!GD~T1qk?jNv`y=|4r}tud{V^w!++lTvNB`9b36o^TjAWbgP$$@mX|U zs3T`#FEX^(t>HBSYvtvOs#Q2FRX(A<3=ng zhcFOGC3{BkP68wR?}l|Z$wx53zM+VbPkNqdVjrdiW5os*eCR=Fy-M;M406n!prnRjM%%+=)fW z-jOPgBwV|Fi-#qI~@>u0JyUO55rK$#mPu9bacZWtC?u1`NLw5V=X!o|aVyqq25XIy9r!Af}V@u}d)b;G{w79|vL zRXt9|K?t|;Tb#hEZmsJ8!356V6mE(h!N`@GPf$BvWBg{FOBCU>ViJ%L3{h@@A^yw^4b!G)9JN%L^Hu1wk zstA=M`$v&30+TWPtjzi7ovl;k{L%$)VK*aqM`g~^QNyQeZdR8BB$lh)kR~-w^jnIc zF~-KQNNKB@7;bo2<3?DH5ZHrCx2HP#%!q&<)FAT`^SFOq*asv1X&0;LyqrRa1z91P6OB})J5@@-j*4&N`y)f2Fz8lCF z4Yi$!i(sh6+_sAV>ECeumY#a??PHYqkTiy7TL5SY&xY_J zH2XZYFDIkjSs-{zhBRN12trC<1w_lO&& zHPLxgSiE4=5|LQ8NtmhYP4Hp^7gd!t58R0myWWAzDH_mbE=L-$WGm~n_FCe&Lz{7} zHcfOKe?!VMEcKrQKm}VM5{mTlo+hukTpx+O&vHv{U6&>VL@%ECss5da#U+O&TsLmL zhXFvvumIr2esS*gJV4@H`3r{+!42=J@0(N&BcP0ha~ZK4ey%`Yje6QnsEYZolgP1) zr3*q@Wg?4b{Sz@NRc=uebi(uuNi7oo;8~+g+{9;pkL^a9*`%(dR*r^N4xrh#`e<*f zzpR?k2`BGTzt}#-_H1Y*Bpw*0_7fvZa#g&hMGE07(?e$?imE z{45$|$y~U1;05hsE}Ps!10uSwb`v6`IUYB<%2?Mlbz9cx61H*2J*mWy<1Coe7%spk zX5YzF;#$m9I1hH|#`<17AHw*D653n(v>sw}Ix(35{9dI`Tb5sf*7!pXM99v#Eo7vB z%uG=g+4|Wvna>$klqjR8C@k50^uR|wT^T12?VNZv3~yl|x&MMI;q#*M^hx*6>JoloUn-d~SJF@k`ma;PbGp;#V7=l{R~;{WxAOzt=vqv?%n38HO4|nHyt& z9`A;Y6eNF`$*$NP{-r$VR_W;V+|JS;>hJO94sTsQrx5q+E-SyL@2 z!6ns_F2)(-HnBr)PwW=~Uk~VK5izS2S-srQda8v#Q)gbyyTlEbp&r(SS5A_(?fuZu zqo0{m3r7}G>wp({1?Q}>`m|TL{mspsXYDeb5CI-<{Dmm|=M>cD`Civc zV{A5~fNy7!)rC^($B$GB+Hn1s1$0Yc6kSAK-0ryZXwU**<=9=MnwM`DAY?0A*ZjUB z=b)Rb7_m!T4=Y%816-gMK0|Nh08qQt8>vu-Xa>&`gg&E0HoB{aT)m|LsTZfTH`8Ec3Y{lQM;=INYS_>lWPC1M+; zD8T{KjmvD7epG#$#mXBR*aGDcrFocrT!-YRLw?uIuypu|_7n9B?Bl{ZKZgp~>72`a*oG!eT2J!H+I%c1bq^lZIT4w-XgY$);EM6S z$W6g(+9*{X98QJ62K8L)(9%!UH0eVIFa$BnVLrQ*G+oXMP!Rc+@3CxANLVClGSQM} zbyg)P9{MbF#6N?{-!HF_!*o$qa@Kwl38Izw3Ajes-BNGKX+Ao=IQt>ses`u@Ywlg2 z^GD4~D7Is3=u$NQ={Edyt~8?7!J@8cn27iM_Mrprv;QdeGBkli%YG_54gTkzZ^m6G zChH`!tHdvzR;)!{Va-hfv8pwHVnY<$hE;ajhBFNEMJpa%919bG!870+Dn3k{ZW36z zn`_+e6@-h!jIf>s>-qQeKAs7Jf#GN0|3J=BP=XvJKu-Svo^xrk_jI#sx;4KIyA{&^ zFf5VwAU8(&w$C%r{OPaZ9kzD!`!lKisRnekPIt3Vc%>7K7LM8aiU6xgpr&Fs+R#RXmV#JY*9tyC2H%mUr*IZAa=e|5evn zrkMkW-(nX6S$HaH&br^@&0AO@1NggW{?xY*&VQK@@k$<7E-z?5ExgXHXJ19}l_|^B z#IBy^LP^dxoN~s5K*6{8{h%q@x+xCvB}dpOXb>Wn{o&@+K?Bq!k zMdERnlES49NNiedSGf7HqXiw8`lTunycnuz6rO6U$(Hj|MSi1pTKrIx$YGm2)P0Ly z!(yCHq4|?NcLuR>CzJjAz!H~XEkX_Xk2(;<*&&|XtyWx@34R0h;f?y~)?1(N^PUp~ z0Varw_YfkjSPU&5;GJie#ctySu@{)>=r3Ed8o)C8_WB}JJr!H6b-9aOWcGYxmyF2x zeYoW(H5~Bmo}mPg3gskokLZ2UJyMTRUL3|@-pvr zqwlizlJQWIdMw2LaQwB~+4*GwSC0t)@17@}X);zRRQvJZVIU0`i(9%1RW*84HM)Q< zIyKSu*x_H#gY}pcUBBnogRYt5o1E-w{bO(dZpW9pbhjY;l3zbnk30*Oj)lPGCkr6E zy}wm!;2S0|s{egbQJW>~E)jb1?&;U3bv$6Ze6d^V)nU}j+nbPA@bl#LB@FX)1c$8u z6-nfmO!@O5Cp&g)DBx96$f5g}oJ0eFptI)n?k;KZW@QvNYXgr<_!4<4+-Bn5ZzHZd zjc3YJOhko|5b3dx3A^LjguuHXGl*!x0W?yc%g(8;{W| z;gqD!gmZ$psKUo%guzR-dhj8tD)M?G^9=yXck%GtEXNEPdAo3YAZZoc??-iRyArlv zA%tmiLAgxxLge4~bANnXq4`->)8F*iZu{7N1~@j);Vtf-luy!(sv#_{AwmJmz**gZV;>>?AeDxMYtH4RC-6T3fMe)?3j5T`>xY?b;CU{_+*IL%8TlBSr^y|f z9b)Wb4R>N+m11n69-C+WcX_)8#ltQst7~zVg(YWjxw>!0{TMoZ^{#80tn6{$$6^>jIUTTkcu^UqX>)*ANDBnI^Aj=4^LN;icLLU zJ}|{hW_B$?v9cqNOgH#@zeeS;nb$N0R%YOsY%~OVzgFa^m@h49i7ZYa)t_mK2)^M= zr8WHTwA$oZG5+eU16pl2{ngpYvC|8~Us%*LVQX2Snhcu4hz>hY*kNREEiLnlL8 z;KG_Boc#17FQ@qbyEeP2UtNp;Q})WghjqV8&h_^HDIWA+#Yt@btGI#J&`Fbeyj(+| zji-A2`2)S!=9+;y*E_Rd@c}eNy0_9npR`mUTZS3#UlwZ#IP2H6T!@VOu5ixvHDX9yc zfZyXIcjk55WlPCajt|$8Ao|jwlc!tU0}1JQzmxT`z>hQiyN@|+w-CA>;vXwi!Z)w| z#21+i*FRS)*xJfZ`5kQj)N;rDc{8SrT1C2rxUXAw?OBxdd$n#bffD)MJRcjHZBqBR zDpx(@jZg2SbLss+@yCJ2?#1(pYZ0Z8^DUchQzA5QgT4hE-&(h7j27Yexj$N|{; zKZLz?RF&%!HcWSlbc-Mz(nxnmcY`9`-Q6Xjpn!CDcQ?}A-5}iv_&%HM@0|0k^{)5( zm$ljZekQKDX6~7J92*6(8odR~n>a)DfACD6JRv`YruOGlh3aK${q}ySaDEW?Aw7&b zXA@~V1YXLsI=$kB+kA2pVE0zIXf&&7MKDO`E3dn>`R91?%j9K~0JAdEF?rh9>z217 zk3U_xntaCE5^|h10}9=)PMkTt8;b6iFOjc4?^_m^ZlsO7Y77%DM2$1MEz^>$3u29w zY1bSwwc6;^9MU;3YP@F{M}D=dzu;|mNmI{rclo6B^+6zyTk;#plWttf>%8nYClS>n za_`xtw{G~!|QGHW!Rdas}%>+9vcnhi5?ZdK@0@Q%%+zG}l87wF;D zDzTn~415{27leF*Zhgjo#;i=yg{(h=Z|oV7=XItco7WZp%h{g~zJ&M|pd~RLwi_wMJXIzUU66z% zPZV%DNweK|piBU<*+he~5OBOf#;KyO_99|%)Wjr>>BmP*l3;7ZQ+`|AIQWTnpc^UZ z)%D$Lyy5%Dd1?h0;SKNY?GENg4L9z)*`HO79gFWfW8X?hG6)j#4~U_&y0tA8(Fy9YT0b;4R!1rQG z1=Pke6tjf~V2Fy#B4m~XaK?}|E;9gcX4Dr7?I8qgulF>HLLXTKMh`c5?**Y@XeY+x zS;!4(oD1>t?Tn&hAUV$fkShXBb;1>pD2lAnDdhe_@YNNDD0ZWnFf=BiebwsT-hTuF z_#s3tHG=Y|1IdM>tPDa8e4)bUTk2<^NrK4jXZ@xE$r&|1h-%_xGK&JUXyUcy6Vzy( z82Idlp|xl@!PF>riUjywoY9^PD44Fgc$qSmf#gUc@B2tsd?Z(#95=Nk#xaBcBNb-R zkHoLmaMGiWj6x3zJB2g4%hAzZrFuVTT=<4&Q(<75^Lm8h^(C^v(ByJ%qA5T_e-#9j z1BLml9KTQ~%vd(Ouf7bt8A5g#q5b)YqSa32f}(z*5flA*t#(@$exdD$P?)+OC@>Vs zKJYx9K8c){W)ZIPghvaCzHuXaZe672fPD30v!CqM25=DBfKX5GT_{YSCbXT>Fi28g zvU_@w*X-n>3Lgm(Ug4$sesF$s?u8$vB#g1{gdju@lwzlY$dH6YCk#}eYEMN-{?!ra z&pKcJYDNgqj6a|mkm>w?HAD8VX2@Y!^n*j|VNE~MA%55_SGZwb3m^}bxMZ|+@ds2w zCLFaZhY^4KHkhpEmz-nrQxI9_A%?#OaCuOKEcDVpG}~?T6{wT|PaYbXgdwU8Z$l;o zGtrKxN6?@Skr{Lm1Hzk{Q;{{t^$@^fy{R9V)dU04|Fu}}e{}imSj=!k*S(v0$|@XzC8wv(6hxma6HFY%iZb}|D%T`uMI7-qe%r$n8r z{8{1K1*t+Y^+L#ifyV70dNq$5#PBSUF{4|F(j6?R=0)Jal_*G zxd@izNiShoy+Zv5(+RzfoHB(&G{@_rHI=(6&MlUJEi27UF??#QbtN97bWUX?nal3h z^*(rwcDXHR1e~$K+F=mMOfIL{q+ZCq-9j^yPBk{bCtB?A8nN|V*woL}KdUUI5N?p# zI@#3d-s~o`&d|QrU*#))cfA;gPx^Q7#DhDQZ0?s43k`*=g{u^j$;*HUMYd=~5n1fY z!cx=%=jn|!l}GKcrZR-v@*Q9cC;#+v?|MC}O-vtCUl-6Rp?I^xvX1Yg&N!3nAZ4$Y zfAD#xI3+Jb=HwA}!Sfy#%GNqHZm>g!JxbHSe~`4wWH z%!!_b=w8ReKOg%RTQB5G0ch;JguR@S;HSYhyYjFQsbX*``uXX_d698R&`ikhB(OXlvA~W2Djsi&RD_V0N@)c(Bba z6@MJ~l(#c#WTK1H(Wn3&#Ti;t#m%!az+uh9_>}T9?Xb)wGaBmW_D;}rHB6;R*64qKV!6mk|Y-g}r8xO-0XG&b;DP%C1|(#QfA^-Qu=;DMQ1 zn8UM<`qz{+&1f`IpnLl3)iOE$TDj35pC4RX^Oke+yvDx5xA+kV!_zV~eun#khuSyo zc6Hxvb!y5(qJw+R2OoB!Ck&d)%Zqq}a1gNnHjgULl}L$JI&UWS@DI_{%F$El?n#wQ zj+%N~#?RSP-A9*cVFhFwi{aNd&L0#h=OkfWstxid7vGJ zbhQyQv%L+rA%f*>F_de4b0clPJ61uzdS&N-zm(r_LIdaJrDRl3xKzl(bzAz1w5~>_ z`nsife%{omKiG%Ctd>km7ya~IlF4c;M^JP*q9nA1>;9)7f*uKIt8VWI#~UPQ;fbT) z1bHi9XhxQdqb5iuwHOFFmSTDKMX9aAPcfzF)r7R|^{l@Fdo`1D{*5-Nf zdz$-4U-r}8oBLe@t{jn{mxiDAP3}*wMXzF-R?3CbR#S9V%bh9MdC(%-l(zcNPEo+& zxN+&QhG-~uDsoa%XJZw^R1h$(+zu`8PfRhRPcOgnwOFRAw}DR;R= z9W;DocBE^k-nLZ&u1LxB8k;|Fx$JDLrKJ53Pb(scO|eY$RFZ;-E-SUsBK4#g<3bTa zf+o^h?M8U8;PtsY3@ckqE=4y@Vp=*v`7X<>C}#wD4>`<*HQ!P*G1n+-)t)|wewML4 zfE6MJkE>{Tn|L!j`$nC!V|w5!ENOHao;O`~2MJv;*%T=~h+vdt%=mdj(Y|hDpNj)q zBw{)+tm<0}L~a}TV98#n>{3K6Ez`Tg|6HjwnURL71)2qphLNfQu((n~g zY{AEM$;6kA2@hLRsO5CLrtIE4G$tAju_MtGQ$^}8a1BsQi5ik= zeTf{>lnWHs9*cC4Q-Lpq+Gu8GhO5?%!%*ZGZK=wVS4{00WWafRm-d1*nLKzr~US|6ecjL91gl2zLu2<7hLSeQ6soAl?tcdfQp2SqEMGnVgsgj zE6xu6k(c6MNqN7%>u}z>IeH$DI<8#Aj1-A`0A^6O@<7kKTD=7ip2W@i6ErY7z`aag zTq8;8sME2_5e&RjnZa|hf7EcS33(wPFP*db(JXV7dv-*RF^{*@IGD4;_Px?&Ef277 zO|6X}JON*20C&~0Z7RrG{#}PGwB>qEY?m2kpJVX^r2R?wfN_Rq3tRv@ z>^|=*=dS}*hC|y-z46W@f5+6b2*(0CHRY=zCsB1$>3y!*J?;|rmilJ9D$f&)U*WLc z`={#R-F|GK{U&GovGz`&34wwP;IZ-0hs2AaNQ?85bj&N1v)Uatw=lU3C(~#Mwr0N zug)zfWf+z^+}n8AIp{?FJY^ALKqab|(NjUVC0U5H=`yRn@pJNGl5o3UKGEb2r*)4Z zA8)l#CG4urmp4x1E=ktkl*MlM#cUTzmzF(=O58FdlG`1~v8ZO09oReRFtZ(L99do1T6-+%i1x2?Q9SQSXXs6O!7_3U1cDw#*XCm*lTYjv?WSwhr_3?}JgCt?YK27MRI0Vm0Z;5dv zywa0>EO^yX|JPl`Db&o9EN>5tH0ukDDD`irxT(5Nw|#ZhBR(ZEk2f8@`nG5O6icKV z!9I7{FMr%w+t<@VYW zDd}!xth26$RT%7$e@#RhDBk=omg{-ibvq;cV_c9l?Aor((Y87aO2ERQ0hcQFLiR?} zhWkrwZLPwJliPA87#boF=n??Tj>oR-+@kXLeYOWFth)IJRn`O3sS~Hm*Y`){1Tc<{ z;e{|yL@AHnm-`z$OFr=rMXe%(?i)Uw1n$=@$LMXamo6BJ0S7pDl62*j^0bJmA22*R zBqf$htR?nDqsO6uxtG4H>f_gXjyTdJtoEHvw>aFtA9r>lqqlQ>dKEL3$0piTvds-| z#ZgTz1q`E}-e6g=?GaUXttB3ADE6(Kg~@+0C_^uJ@O4lT^YVV#&$XCO*qrE@u}0%^+J4Gfr%I5#~#1dTU{*L zw9GFqnLJoO5WbJ5`HT{uw|(Vu-Gm@DC7kQ5i%L0!yEUh}&hMRvx`jD41U4nu|IvbM zC6mg7VxNa8q{@Z*4(nqmcO#tP(T}Is$Sdc293*@rT>^ktQKD?>0^#&fGE+L}wtOV{Ybyq$-1E`dDq zT@r;p=ce-;B*u_UGux%q+L|(C*7&wE*Z_tP^R8{gj*9N6GPx*%7SCclq`T= zq=QdYc`;1NTK$PJOyv3kp`Psa=dgt~W1R^xWxcdpMf)PHNy4q^!P`?c9b3p#Jc0}@ zH$?h)AJwbmc0d*g~U4W4XCe6Jn%7W4f=ax=TZ5XAm3{Rw^rBfCVJ)Y z=_Pn;;&sU+!XrYI=R%bK{q^{K2xevA{h$!ckOl$>zU-_J!Qr;RuS1mY&_Y=D!TTN| zKm-sZD9^${GsmDo)%;pDR3N_5FhINqe!83#rrp^d0S3>Lz50NI>1T1WdWlGfY{gxV$~n8gb}0}rSUu;4K)KeIy@e7Yf-^G6AOWuMk7qnqL zkAC}>c|q!f?eY{h?qzzyiicC{MP`O%J1(&LKp$vRc-QF51gZZCSh3UJpteS*{dlFQ zDpkkE*6n28j8jaIhm2O$VHjj_>QcK_{(>l1zB#SSP`!@|H9klGSvqXK!ABQt#o`@2 z?mnf*X@ub^FVZ3xKij<6=j_<3n9P*ds(X|=RFewqaLo5tXVpKFs(5&KIuNh3*OA%_ z%>Q0hiNUVCP{`$cT8hC=XQqFHq*#@BeRXypy5KE7rJ#xq$TqXK4N39cDY-ek@Dy0K zqNwk)pOt&SKyH4@6PW)jSmCL_d_cJ}6uXU>HO!DGX_=tWDh_omsl=w0kRoh^@V2U; zqOZ0!LyJupjtuiU^Ixuv|5{n#k#CNSxQEZpiIr z#mHIZmK?4=qB_|i{7%LG=IRy??NZS)N(@l>z zvzf2Vb}13h%ly7~wVGDc7%ZY-?)JywEzBa=D-Zu$v0V=WLAJV4llY`M^)66fpuEL1>`T|FV6- zoR^^pfnE*s<+-_!{@^R9WHA`o@=ybH983+c>(jqN5HZFUVpvRe&=OGM+0<(y?JE^u zZ+J*cz7c@u?2}Gjkjivo^YpYtZ#-ZPPbcZ&|DiX@bUKK!Ct-vSl_0*Z!y%7s3iwU6 z&x!ld8dh!8UEZy#!JIas(C$IHYb_c0EjqPhs=87__)R>F%vpPil0Oj}H*B(V1DSS`$+4qakx(Ke6&vUIt2ZKoA{ zdtGp`Z52Sy8PQ+(+o0mK_UvvAb<_p1Tc?#G|6&L;)M&SPyq=~0J^upYP2TYrsjNB1 zUkkA-h*Czn5MRLD~ZHY=4#~A>ta)z6sP;m)+;LfG-jz;GTtQf8^#Ol?xb+ z4`1PBoGJ-y{B)Uj%KFrbGgTY9U|*}WWkG5jpNHF6ZuL14uGhDBu*-iJF5jcE0?Pa4{u>K7EFqU0E>O!CFoPj?u?9QU96EHwyvT<3`xVurue7Jemeri-xx z)&-s%8v0pYPqgyuks4X-#Gs;7qz6R>SYrB+(g#@%tCB57qZ=(^_5(n_3orspGD2AM z`DJ)#$AAt=GD2Wih$RTu?!|>U#yBd2zJebnW*B%FbuvO*JmB7f(WMODsA$iT*UvH{ zhCzEY!AON=YN~&@osr3oc(E;}=BT`Qcu6d&qSli;=p! z_;P^dZ@TztSkQcbd3MW#i69cD8ib^LgWc{lBfG+S3;xOx(3F_8C<5MdM+h{B<)8*MF|FxYQ#S5U( z8^(m`=y3CjynY#_gB$@uYmN;@z3i-RUJ0hI3CVx)Lde#`e+>ZQhnfzAkt07V=bHvq zGyk{#$YmTlisRf%aT74Z|pCl~ffIUE8QD~e#eTFQ|53+;yq16uqCZF- zbzX3-3<9T7IW|%lX4-bGaM5nbP_gw|wMcT&9#skAn0g!$$iV={bqUG+i*f$zV2nel zOZ&(Lg78|nuA?&lbu>@rB|n3|-WUvBMWZly%wG;qgd*<04#+VWEXOXyV6Yrr*iqDP z8GJ&JgR9zYgL0Mu??W*OTTeph8V`Fg#nfrGt4NYW3>oBFf*f2=Ac9j5UXM&n8ZoSA zUiC~G=knGi!Y30%lgUzGN*;yn|2_e=MaB|<1XSY?K+Xnf4|cYgcl~}uf>7x}C6M;; zbPx^h!_fWH7EoKys%{XB&K&&aH#N~@1E25LA?Zs5FbMl+1_8khX%8?6D~jDxxGf}_ zw6-qT{$a?5FO({qdWNSTs+1437rhAAar{vXnREvu*N&;FXM08eBl_~v98Y2 z&uzOsL0vnTYiVemTg}Xg(31|u6a|jB-@wq@yL3dIO-7Sa&Z zxdgVwp{QTL_4H97LKCz_AU2h-*!6;v18**wZ@+1lg;sVrZ{0a?PHV%NbVmF0#t_XLsjuv}5?Jz;9W2XR5B8sA+)429RU+ps`g4AV&kv{{P6a94yC>jzHi!M$u2<+ns4j8x|f`dGLoNTZ90a7Mfs4`0Hh6#eG@fVUC?Yw;X4+$ zVHz^)${Y}cI?e|&bOR8&0T=rp2(|mm{s8}-3v)57TVr%+E9zp-VB`_3b&~LRA0p z=_RmFZ_NzF5YpZYA!`RLB^8m?5tDA!QuKq*7`Y?}g)~*!G+IK9wFOru5~KZ`1NO_t zXoGV=I`XkO?96==jfJXwpqK-JBg@JpF zLC7Ypw4o%YH~D?nhW1Ny$_H7F?|@|jB%n2@?fXRMDjC_ombq>NwoISJfjdIU7r+_2 zR-M(>ZJPKWtkiD_r^-{>IKH(VRT`7k{5p1!u?=hkr1%7uq7T*+Sc=Ee4<&`epP|;6 zeFr&`aJ+k0XN8w73kZb>q8kUoIZZ)ABof;<(&4b3qiEhO|Vg8Y2 zL!ND8->u!i7JgPapuGp+_a*AafAISrjNjvR%PFmXDUg7JHQ zk;DSDx|zRx88AiRRlpRzo=q{R718UjDJHhAOD*(Ug6jGQ6RtbbaqRMuj?EI zo}xdQ!Hq(^E0$C9_U}{lFY=45B#>SugwO?8*WAUg?BEQUtvEY~9C?vrz0w(W%+Q#-87@$ZgvvwjI`#b0wT=Z&guAgqMp8w6PR8 zHBbH?JAV;UW;ucAyjP^|&gFaIIHO0RS>z%Tp~`k3r;ORlxldTN7@W#lp@gCz6#Np! z;W9uhwtM)Q#Zp+qbK7mQa!z&bU~+mN=u0o5sgYSnCBfTS0G|JBBMxDNVu>t3rtOlZ z?N8B-suzM$2hOp=2>%vMTP*EyHjK%mQkn?t=yYn@x`OHrH=IkFHKGz>Yv(&_i6It^ z!U)-b;Pe^I*D8ttdNCpGsCS~)NS~(V6@~tGZ?mFbyLOcJF4dc+uQFK(Ov%+jjX*G1 zCd2vHZOs6Hpepn1xg3tXl_` zRkg2J1GK~mpe0k!v}9HC01kX}GBZeJl3|SlB;`elb)8PP?{xABbFFvBZ^G-N6*#pI zYLWAk>FokQg{yI)DF&m0#W;%PpXteG1e4r*3C)t^!PficoJfU4hsF$1{>_#vIH!O~ zxCR*gYZ9={V3Sy580sLTeiQ;~ZY#HJ1~jh7>X0^0q^D}Qr(lK+XJb$e50KS58#`8f z^F4LndS6aZ*OzY{tV|@e&1+X^D++B5v#F9q*%7D}`s`Q-b!eNQFQcpLP%F%?@wiD^ zl8NsYvD%IxAE+W$(m{!sBZha;n_C8*N1eLBHhiYHKQ?V{KOxx{gTUgbQc61?0E;Qq z5B~v+129-9*13x>D=dSk^?`A$m;DqFyPPa;73zW&{>CmR=q?NpnQFbs?2ya{h(HFI z2q3X} z6Xn#fYfu5fDPyU;j7G9014Fzxq%MalvIT2SP>m4Yzfqy{Z#FwK)2~UGR+)iQ8(hO~ zyU?0a!|tV_t*r4Eb8EoqImlFt0aGoneXho7B$wB|1^O7abOdIcDVZ2`C!8DF_$0O0 z{U5y;vWF9@i6JJakeB|-&dlO1@=`+Df%BaJ=ZO!Rb+kO{3=TnGBV;XAUoBvt7>vnD zK_x&)m?3-c|A*xnT7W}>w#AO+b4pcWXfdohw-Al4y@**0R<*GO*(?kwnYy+HlBqcY zfJRw7)2MQGLyN!CvpnM3Q)@0!L`a4;EHZ5>#o& zO6|^y5SGX`H0=ET{j#;uK)m|Km|Owd@O{F6i45ys=Me%s52^j)KrA6OIHo$Q30XJs z_gksQfMti*@Eor$kKdKoe@9^#0i{o$HT5!gnsC_7}g{dKa)DpGQYKO5pgNLXZK(qn~RQjN?S%)P+pg8(F z{w1Q!e+ksQGwV<=k{96Nh8*5M^~2|#)jKRb_`g}nGygqm)ltQBXx+4+WWz%=20Z-R zUk@LG`?m@MTcs&UvCG(FIbE;9MX+OvUq$~~0bqRJjFBhz(ml~~2P)aYr-hlk*7#Pt zg-{!qu7I2@G3)v}aiXS0b#I{+U3U?;5o`gu7G%nhAPbmk zH+by`Sm;>IvxV*@jnzC`=u(bjly0~9Z}Fm)L28H*sCH~M)8D_fAW|57vsf>I`I z&j@@MO(2%e5{-R9X&PdV3Z{@UpS*vqetJ64be zYXLv{HJs4G4(So!WAj|O51boVJ zPQ$;aRQttHB3@*7lIzE@VhCKQ_q%)*ITLsCS-qiTkij5^yVJ8%~{YHst?`$`PA>&-{yK(6 zq{54YDFXOmF_<5!VHE@X5Fj#i8mL?-K)p4wX%-ULz#yGlm?4~>^iI`7@o>653M#T< z;1qYmFJG%)sfIGI=1jrri8#xg?OjVNvz=CBizA!Flu^7XAm(3{h?=2EGz_AsubBQ# z?=!)O4^(pBnBz4`LhvVu#=mE zjQ~gVXtd+bmcTO=L9uIM`?%(f`Rvb#X;)2yB-Z!wl;&f2$y?s!BnY|F_}|pH+@jvO zMg^G-w2mf8O;*;V4*W(7EtsySG`By{YG6Y;uDsLm1&%3*`r<#wOa~tmvc?^4svQGa zYmOjYO&>O&-P2b~#FyZiXyfJk86xC^YO*eZRZSi^t|)=*P0e+$-H5bT?CxL4hx`lq8Wvjys9ykGmq1!XskUoP!WXl{7K0gfN0N5$w-ql^ zaBbBBI9oBewmJh-46dyrX+Wci0Fe_AAH2og+hlW32G?QyvH^E?(@5FyHVpK@*(4M_ zI+6mlRvjy}QhXbP9|0D(46yboAgTST#Mg`gq$Y{__CHd~21|{+#yEINK@kY&1lcn> zumwlAWHrP>=HO~-Hk^_IsG3UF022^P2CO6YpL(vR3Yq&)f$OQT1&|@YB;mgOjXPP5 zu+RBT4H>&hHWl4WItvHQlQ1ua(xPE((x{s`q6(|tqnRb7)fWi%`3Fs^sLn=9ew=iG z5-9|9BmcwrVe`S1NYLsHyg5$%A_r8>4^`iVQgnqy>~t{lz?nA{12^?e&y~~vnzf(~c9V1}i>d#eNn!Dmuh#ne8c*c>3hASBAM2GrL`y_z1dHB2s8tA-2z z8!+%Xq$PCOfq!$Mj z38;5K$??RsnvmIVerhXyg}?rgn^dcOk#6>mJ;MwfSdzejWqx@#VGThR;1+D) zqGl2m8&K2)T0YcG3I3^b%hC}&?4MX&gA_)90c%{$$4f+em${fv-;6Cac%PO zw2VaRtShJZIIE}l!i`iW`2dr|1FnjKN`XVpl0E(BkYHFL)Lkstc6_FiRv8xN3A%oz zLHv#kFaKc@)?Idh5Upknm|rvkHIO~6=NgEk?4H(l;B650rDN=C%s@u0d#s1vsK$jj z1(X+NQ}&aJRRJAm-vT;zWJt-g;4sNItH;Sp!R28j(q+}V+83NPdIN+FP*p*55AY60 z)Q$fjOC#7j#%q}KEYe#+NxNbbRS)$b%|`@f6N&%>mlnWKA?`dC_tc#2j2#j(vBEu9&zcZiVSa>`z^Di8W{SRQU!+W1!T4DdERC?S<6BH_nfKZWXikgu5 zJ(-_1yw*`uOL)9G1#x@>olGR&EA`U^b@5=XfuSi-Vr4^U_?L9yB|YD6^^Fm5i&TAE zs*TNH=fzvNvMagTu5@yIj~EUuPPd0B1!S*Pb33us4G^peWW!q=OE#y=cu~^-;LGZ) zJd>l1%hAC*4%U$QK877s<>qn;s{(dGqN^jL{r<$kY;g}VTT+^I_~b% zokiDcGr zn6Vq@rX!vh28M)3hla-DhfvIUH;0Nb40>N=e_swy7lhhOHZlelxU&ML@XwPRjtoJV z!OQ>~rt9MSFh?m_k-d5|N#nk=FDX?8n^@!U=PeC=<2_$Od5@4D8#OpgZOd^p=V_mN z!g9Dp|1bzz8_=;Yd%FHOUPfDjw6Dzi>D{|V^Vmq4#)JdOLOAwRo5BS6=M4fbpGx44 zrP=1Bl7dS`CP0Arn9}HaI2+$qAx@Sv#xBuR<$nBu`q$C%@;Orb>wMqFn?zv4vM1q9 zuHsk@CH#+dgN0+%jXr&Mic!*WtOf@h*siAZYu(4r5YGEW4GT6Bx#_7aD9rpjawPY7 zGJ-Lz%HyUruQt-i_zbrfj-b&hF>Ok8wqls0GabT%rg?*f!=gVq`f5J4Ctn#3`g*(O z9|N8g`N+KZXD>7ss_)5x0jorm6n<*x38pE5+^UMkZ$7|#c;5Yq{xH(G@B1y6#5M*R zl`D_L`A0A3S@|Ke0~$i>Ub*g0hJf;!)}@VMN??j9+q^~8D<@6?(M@Nci33#kNgStM zwHDRiH*H_MA2%J)2m-4qQXHb+Pm=HUJGPG1$r03Yhu8_paZBW?A8Dk#PX6;m+WVt) zDzfbEG=DL2kc%n(3U0kScrk<$L#IlUHl+Db@x}w(fg* zy$gQcnZPZe@D{NjmmZL{r0Ku(108|4|r(`G5XuLYXiHRx8iot9fi@H zrt-XPrOZvG)7yU<=f93xJnBAW@Ez8gdKnfi{$5c2ZZ0!T%eHi?Uk|q_s?X`4(cTo@ zaf|u*N6n3b%myZmvog+_ucQ7mT!f#bz$LQ(=5ZV<3Y42adM8rO<%gGXlxYQjh6NsZ z(HXHC?4kL}INh?FTxZ5F!lts(MxT!Mk4yySOl^E#IoF`6_bGF6a~&@Ykn)f4i-U$0 z{YG-J>fS9Nv$9u@y==nCTh;jy+cfQ?Lo9nYMAAsR)qv{g$m41B?SQ$SrhFW)PtJew zI(v3}X_m-}3fQu{o@Lw`sLRUm*jzVB0#nCA65ZHwq?}vQHr>sE#Fjbi{i8HPbHCZn z)BP&!cCD@Fk8Kp|vck#XsLv(Oag^-CleCTE!x+hfq6d~IPm8N=&Y(a`+mq^Ks9K4W z^P^b7h}Q--jAKuK5g{IoyPEhY??lOuB!!`nji^E@QxEHUnL4Q)zXmSu**gEHGIflD z!|g1AR|sJzn|bocD`iuw_7o5~K37p>evs1BFyg7}E!`%rZGkMrP5ccF+(P)|fk<%f|v41L>TUUDL1A27tB zXLI_!qj= zaqV*ER-LKbC{Hx~8~&rZgdcXJsqbVW5~!0oj2-vt+l)P_+l%u!SQ@kb; zRA6z6klF);GZe5E?J4QAH+c26KB;>bpB%A^bt>pg7f2}xv_72d_M(hwK}s5kmcD`O z+$t9dU&sz5U&7I%7uPUV`ux2Jk=VZ357Eo`QxsR|qtj1SwfKf(J`8R4?@W?$mG*}k zzg9xUR@s9G24p}@SJ$|J@sCAVk~&)^Y^_JBAad&i}w=rjA%34 zNfPF$XQ}B3$FhfD#}Jo~k`;8HS@dNe7Vtm}D#z}KHl6>t9u*?5LiC*q$%X98@9-P< zChv6Fj0)Uv_?xE;B5kMailNfMIhz9tLdlyZcc)kOf~bMx$`r~2ci&3Z-|_W5GS(0@ zQuHMUXYR`ODGge(UVckU{pRvgaMuag2+o}j z*SS{^8)m(s_rfe$_Qmv`>{STEJ{6%r0xJZW=!*h88)phExIsXaXO# zb?Jd(o2U=-`%cc^Zb?ei@0$yTN@?LxER7`6g=C{WYwYiZ`szv9l2G~h6sqyj#t!iZ zGV{dM_Vd>%Cy_JTloP0>N`hDPMtA!7ir#d!X5_(D?k#%D6-AV$Djh_xsYLg?v{Yop zvBg39>@7F7s5tlP;2JRL?m;mPB}?AS3h-D}=^3#5$@#$!6(cWz{#pFG@fvQO;#1vi zb4)JGa55=vi}8mLbe3-E&FpTT@E($zAU>k-FxKP2Af4bZi;6uI9<}n<$SLcBm%-7x zBfJwV9I6cR2#0Rl$%@dLms4=L2d3|9<{~bgrT5f6W~;0*5EDuXe>M$*UtmV#(<+MO z)w<7l8P2=Y%!kxVq?{_KCi?5u1cvl;z;1U-itb3lQ|q5L#qE%>?j~yz82q&Z+E66^Pr(kB!UA z;H(sBL^|ofni!?-Tg^2;U)hT8wTu`)?nkEit?#8Cj>*WcyQ-sSrVmp=gePw4;m$|? z*9Hl7-b=W=$aD)Z?Gu)h{P|Mt95%UYVLn;0ocmyZ)Dn4~ruE%-q|2ZvTc@e;0$3~efnz2H#fsftJ}?Xgx)2z`trPD} z!`Y2Bb8;KQ!y?mnMw{HnDRX{J&*2aF+~OgL-EY;B#J-voCw=~u!qk@R_C!B@;@Edu zxv6yE%0)9x*2(g*P?#v@<3|x9vqST4LCZ1+CKv3@u@?9bMIVTeOD$Km593T?6FWSV3AYdTEY=8H+-1WF=Z(K`f>hSc-HW7NQ0`0%iSv6}+(C^Yc zU+}OVMLemLLh!Y+T;a|t15=x4wFW9ZpCq++j(uxk>jGI(h}OF!9tIq_mU6pEYUs|( z3Jxd7Pvlc!YzHom*0Ua8c7LF+mi2$MpiPrzUW5G|RY2p!F(noXg|43t`%%=dB#7&> zTaaXl*B?6&!@W49pe+1)D+E{FWaHqxb{R7f_r<3%x1$`5&0Gg#|F_nripuNA?G+8T z{zrwF5G?rwNbvm?A+52eo?d9@?WL625DeegafrTcV~1U&OTEfM z;&lvUOegkj*a|a{(D9&PyvTan_lhyP_UaeQwugk1+iU-bhC6k}iA{vkpYgmuddGE9 zlafOSW_KCv9NfL#&orx}N3`@uqpjueov541TlI)Zm#a;JJ}^czMmPAsKRhX^n!34w z{S+<#?kFL7^qWiZCH7@+qejiD5r=yjNLg z0|YBKXkXesux(4Xizy;M3J;}(;z;yvHTD;M>EtAI0S4ds*~eM=*{ve>Z4|!m!PT)@ zz#c5C8xmJS9yAQD!Y%#Li|sTl`RyvXt?sA2VD#~am3$kl!5@52RE&%^3$m$?f9&RX zZ{K9V-M5NM`i;0tm6MI@>dytDZDCP1*2l_@t;GwyJTr`7u;WxEr*UUq_Lx4>32)ua z&-!Seo9RW1BhoVHa?XONNfgrd0AyD*?&#NnxhOw3iQV{P(WuwN3dhJ|o4vnwYM7r! zevoz*gju?4rt67WZ3-72(kcC_COA{GQnexwyIt3Px4#`C#xT0sLa$L_Ouh54chA{+ zR;+!Ps=FG_l$X{5&T~ZU%E95)AHK7 z%EzgU_Epd2Lw@WP(`IQ7^YlwGGl9jSiVHjObZIfeXuy*q7nhQH`d_W8Z1RW~y-@^+IC zc9>OK3mD-Ug_X$Nw>HNga*-rq3f{hq4A?{l1|2l%t@Ec+h62XvrQzZ5+EYfg%8=gM zf2VzXGE-*ojU_r2Vg1b%HuXbyMa{2~G6malte=HY1Lu8lEbJM7-7Un&Pq44nJXFYD z4K}>6;dHsARZxdLNT@8~SAb7~Ki@03a23VQmboe=vN7eb~(YQMn{euxd5H{?XI z(J>YiwOgZp3WtN7If5&@XB_9_oJ-H!9KjOWBV7a21+UUF2HkIXbs!_4I0& zcle_}U>FJM(`g2AiAc5L}vop)U1giacLyiB8cjBM?G1af$rR?~#{{8aBSR9G59&^7hG`C<_FwY;ifT8cs zp#{b#uq4d5s}p77M29RMGBLeq~?`AwMOB_8{_i_q7mb-TeJVMqz z#uBmJ%>>*StB1Zdw0cDz=-p~P7PzmaG&Q;1ZtAXAYd(5b=rw=<4HL6IY9(K*$aD@Ewv~mB_E-z!CJCSag`q`t%oppaM zCA<}usl|&PTT41BSkZ}$x6_XbNo+n64~Uj2o~>{5{KYiFW=by<+0cj;gHo%mR~Jk+ z?g#e=WSg=eDdux5tl8p>i`EbT2jYsWDHF%&zU9G;MEbn90$ri%Y9tiLM$%yI(wK*< zzC1Z2JA3G?%Wevs$6Xhds2ofK`>FMfUEb}Xp<1IvPw#Nk`Jm@15 z5z#_)ZTmr|VmAg1v@AQpFYE20Tl^_Ejj*PiVWI0^Vr~|xH4!bD<%| zR3nF!ot+nkm*0^=T5X6n6`6n4Er{baiIBM+X*c?jwf4mcm0m=$%n|u=!wr$(CZQHhO+nG3- z*!Fj3?&n?Wx4u7!Cw7g5U%u}xeJaKpJYY<(^OWt9rlh8nfvihLvw$<{K^Gzkw0?W+k z?b6WTodAL>=s0NtDED@~6CaD^?6D0~+MnYXg|McB1Lj(f8?FPne9cTXwS2Bm)^6)m z4Z%I_Su$zz@x)^Usn^FsjMd?t&3BV!mm?frO(}vCUq^-n^_HW(7wtX z)XqFgue)P_sT`hlau8U_aBBGB?(zYxm2(E@Gm(A7!tyYWqHJI>@q5``8?-_PP>OoB z^}p38EUmg`m+#*HG;6Q-n_Frzv^Z7$s3sB&R!}HMfXW3YI4Mh6Yk%a|n7PZ?a5sZ0 zT2EIuu7nge=oMB;^|PYVZQN2%YeVdMJOf!eJJYDZtO;zoB~U)gHN!q;^L=!MX4(T< zuPgJpbW z_9eNmjIl-44trJ3HBKsLF}7mR0al33#wgR+7!qahLQ ziV8!2@A>k;@57gR7_d82(w21TNsL>%snCF1CGmia9;JumSE?_}Ti~cUxnOtYRxh~V z)66z2&O&9|Sp3q~jRxjsj-r`l%!gRy#o&5q;MP59)Eb3oq(Z*;JK9hWgG&|g8z@#2 z9Z(m+E&YEFkuO1%8mar4Dut%PrW;#S`)%=uV#$K)0c_

    )1=jYiQ|M+q;YI(ln}g z&3>X%<5Vfc5D;ez-Ek<`>^YPZbCu&4Y8N!Nf@FQKPg%D)mV4kQuEHdyOm|}Hii@Rm zKLrdWzWZ)wxxh{@&Yi*kIB#W+TwkV%b8_OBG|9YJ@|R12j6KR6jLhR81x>GdZ05-&l3!zV*HDvo9+fIP@EO ztOpGjbqxn4P0qF0F0!jCcl!hBliEuw%u5D4T}|}KKEvJVqWk=PMNaxmb{a$gmT4~h zIi3D2BBLcsjOml3nTu#sE$z%q@6UC%cDAlg(I6}& z)dF_5Dom+KLM@VzSB1;gfI@FCk}?9=J5Px$q85Dx1IRR`J5RwccGui+rhmJ1T`-uK zyfQNk!+{1}G1@J}xPoLCmxlC#$BrTkycHSZt$mYgq^`ik8HXIXZ>s~&`Bn8%L^p%o z@Q1H;YAZWC_a&Ck>+jm*=&<5dX)i*r&yQFe?oyx6`#iGfQen}?i<{35iwKHpAOf=y z+-BEDyMR)R?POb*%q%KopPg6gM_ba)Yd_3TLX-tx>ffR`_?AqLCJ89cgHfnLl+A({ zA{JMrOXgP>VRMY%%?5&T`c|w82@yHsYLVu1u@F_56WwjGFycHlh_E2^S;M~d2=G7+4(45F6R zT}9(gu+zYBQOau<>U-SSeZ{n1^Oux?aDZ-OPBrPl;a-ruRuXVBjbpd9e0;`sj$;;T zw`BIlWTvnlG+0&xSH7@cYmSoWKu}{mj&0j5kh`M)uGzr`v1qxkKp62s>(qGAZ}WHg z%bFl}YQz@$yC8Q~>}+QEy14%Pur1gXxob+sJ`dDZl_w40@c;iz4PO_DKN!8~HK09G zt|{#Yfxpk+Z=cW9-qf+Qup*XI3L+vN)yxZ?-j7ei$!faAJ;r^gh&kKXP%nC#XcT{4 zCciU|q)+|qxO6`e`znYCd(Z#Q5$mw(h>5wE___b1D$>e^#iKI&4Z`=AJZRkut(kkpV{osCgg zsjOEwYME&We1bP_vcFMPT|67mSz#`RX$x4jP;;J*0dC0A%GF^6cQr+}$*ZMeCB-$AkEqG!XMM7g zR_pEGncAMqN(Q5aN(a+t(so_lh>9nnv1& zk@S~XQLe3lbz=Npxhy0A0wu=N)d<55rU+&^+z&w(9ngsf$=7EZd9b^=m3UPp0pCOXDgd^a+Zp63y zX%TaJl59A7;V2;q&hf+5=2X~H7X+_ zELL{6WgecdEk>s4E~JyYjfNH1j0dZpoKufW-~G`NvdFt!3J@AV76H*YZ`L8@#?si7 zjH~V9cfZt10R=QW-AIB{_b$A+Q&@MP+bfFgx64Pu@3gTCU)XMD+aH(UKPe_oIETSG z_V#XzH<5A{v1oudpRtMNRCeyt33s_oGn{8pA%lmDG6DOqa`ew&2pO@%rRy@AUXJJ(avt zRxijXysDNzxT+u04ZU`NAZ;0n!t<2_CT=rfLb{>~8JzA4LwI)<12yif%#Rk(ns6&+ z8#^bDAE{R?1Z|Os27IAz9W?(tu+6$0k{>8cxC!ZqHrtKF_c;e7@KDyJP8xH?dq6`! z?b6UzYdH*|PTVz_c=mQwmKXLdoX)#W+V5T-{6!_)=ie#JWj9vA_n~z;{-sxZndzWESp1>9l;8{e(I${I_#&Y-!02x2bwh;ct563+g+&0AbVafWq#F)p>OYEmv_e4x z{e2xu1C2p%uYM>F5ORxLhADibg=Mtj9rf&pc|@J{Gey*NqaLRDcvGsSw-vN#o$Sbny}j36X; zKJfsgDw>OBn@M{w2gf@l7sc?#GH*s-B!*&0S>EUv())sqalhI|D6`CI`T<5!o1Q&YVHl&fr!mlAuBOd$=^rrMpeO<6*e>2psrgd@m>w=JvXP&eASrW&*JhhsWz)yV*kL=$3k79uDQx z_rtZn>{fPkj3q42Tgd!I_S?7mOu+*m1vuoeQIR`!I_Q3%<`-&Sz@cXOvJTlWH}}WJ z$%Bzd1^u7_6SRy53%G7BAGGc@={Q1@io)?izEk$X$c57v*^nKb5)jgU>Weweee4!(g-zKtahlxpxzdnq;bY_4Z z+d2d}LPsRO{{H*51@h!8SB+=Z0Z8koy6`$5r}3-KV<6M=mr{p=xCOicA{O(R@tqT+ z@EOy$G{BBqS`?#7LO403xW}aXQ-SY{eKy!lQb@mK7!OXD8bd9QWYJ!)6iMMyWA@LJ z!`_(~FGBkPIBEfbBUv^1GYA_q^Yi~)1yU0oXrIzKShonW#~8puPYw<(lmlTM!SSF| zVF5NTbPRngMU`g**x$nsW{ZrU)X>>!3;l>AX2mjA z?x2Izmdu>9E6N&_r59t45i zs`iB6`y0$koXy-pAQoTUp}wf7bO61n_%ye*A*8<+`3?{y5-lz|Qewn_n~%`QV% zz=sCdIn;kk&;pi_RmX=0EYbgeODHpd|Hp4sKrKh6NnP4h8BfmmAqg+K>*GaqpUeXd zH5eU}i{|YD1MMbzGwqe)4RKGaE8Lqje_{e+iWQQH!g@1F zWJz0a&BKt$zjbvz5oU#YRx4H88sHSIcwDPfOdo~NgpYXH96t5 zzK8H_01yPaP7S5Osc@7Ff(pe6ME)_acq#i*xVD;QhfeZg}zuhn887A3vB)}BH*|b;eo7vT_HJ0T`wqn@81Ve zSC^U>&a0S<&jb3XLbUMe3vPesB$W)f5j4P!T#~C0Txgg5dXWhgNsT)T^P_z&MyRBP z5rtnwDPh@LKmZh-nA&+QpVDHn0HOSl0i(bh8SW2Hv}2OTt1iV|mhGdbbyv;>=@tPa z2Rx-WwjBHSst=bc_|UQS2?m=&wByAbgn|Eukl3E@3lrIf!Jcao$nf*Oh+c|@5D2lE zMl5qUh2JUth?RLRd?ZI&8GPaw$%AF%VLg%O*%QqVWSxW$?Pjn&2`u?W%vfm~ioX#2 zZpEHF%l}z1?E?9hE$utJotx7G;Im5$<=8=)tf%2*L!oGk?qiO{*PwL|LkEonPu^;)_+5QtsuVYI`1(QgbANi?(xp-Hh z_pQO^BvhkpPxct{TPNe1*^8YzE$u8>HCAIOpQ@5~RZ+NBj~NfezgmALs{>ogxkqY} zrj$JuR5-u(hw~V5qb_)Q?e|U3y_68z9X?+Q?n!&Jve(F5xRlWjK>0&cJUr!~8jd2& zSLD0S`e)z{z3G#U{9j!9tI(+5$@pzJ{OlnscbzT!NaGYxWSD_1_4CgBfY-AIv9ang z`kzFoYyU6aQkL!x?il&tqe?J%s1%I_W_zCBG-!(8=m7{#3PgyIBgs ze_0OvdO(%~4=`@)EOPV_1|d!Fmg+z4R6XF2hy9U;WAd~&!cgRZw)MNpa`TYFrtA=J zk*vGaXSYEY&)@ia@>oRSN#;wDuFANR;8UP(umE^0rA;O5-rs_jj6$HrnBh&yFIj`Q z$DAm`%FPsQUpS)jNCvlGY59G( z|Mx^Cr9soQKNe=kbo&3EUWsHyQ1V|j|nbR5sC`0z1276cXLj%Cf zbT)o2wWa{b-bvd}gtlGB;2Qn~fH}_HXZkV4<4qT;3q@xq<6u$HMr{>l+c1EPzlNu8V`&jMb_Cb5l&^qSx~CJ(`sr1G- z0EE(<%z&@sUVuW6uA5Y80Iv!Xg`_sZ_%Hc})lqDNRb?<~UfVY`p&8cnJ0b;Ir^(e1 z@Elyz7;1%o4yN6U44BElLBP8;xz7EyB@~)}N}QY~*Ikf!CN{MZhmiCFAB;ln9wX>l zN&w>OQhZx}HSJNKRfNL8mTAg$8v>I8x12&@%+2riwg0;!6L9tMzgHjs@9O9-^GnN()yiytd8;LIlfTS5^7L}JuPU=kTtP8h zQ29fydPJFooFiD-3c7rX{@#P&qEfYjKQRNMhkxmuAq)nYf9b;j(m$F?QX%VBOBuKY z{LfYXXjFPbB(f!d!-vW^qN+pys~gsuyVf)e%GmW#Y-Ix=l?D}C>#W`1P&@pmRV$6= zhZ{hSUuh6teStxS|Jm0r-!^5es4Y7PL~arYYZq}|JNiHCno6r+nJ(i$=-P+&ca}dq zhiv#A%QdA8>^xdm=gVcG6NMK_cNtgFHCF9^_K$tl)QK%bQkh{0D?A21rY!*I@yg;1 zTG(8t?%LXG;;7^D3K9IL-=@I5M9O~M+o^cx#tb=Sr8msCOB35LD*7@2K_JYm!}iI5uJl;((3@gZhF-Ld|A|=b>F*nokF&POyloXmtOxjIsEec zUb@l#x?c5lgWDuRrK2G|?m1JVe)-WzG+VQhV{Qpt5ei0>JG%gy1>y-*`oJ#qS1yPW zd)38_QX8(3J2x3Onv%}~rID`2yZuNHrD~xEtmIH#3ig=s=I)-Wpf~{=n~?^@7;On; zK3Nqer#(vro4&)3pL;0KwFUp5fHKOm9tZmn;QYX_hsv2?XvkKFYmU# zd+G>iv`sc9@j9Tr0J2fVThTbmtPcQOcw7(k43#1_rr27Yg)HYRR18Ezzv81<0Re-k zOw>8vwzpJ!K;pr#&D~tHG(VE9KIZ=ti4XJ~l_EZ@RV~`{xUd5Ny4w@pGm8~%R@&~$yS_TeLnavR0fpAW{Hw0IWQ zKXlFU=Hnso9AaUY`_bfKjM>g5zD*{Z$#nRz0IZLpyBUVBNf| zY|yT)7AqnHW2pZ4%@DRMFvlcP5nRwX!QB~^ZPgV#DwV_+8oW!J#zFZ`4F^Csjh;T4 zcWHfq(i4kS_)q?I`v-kD7kY))nLjd@b!@sbwIj}GQUJ29p_1ljM`y=4B>LJcyX9!BM%Mw!b2Dw@Dael1q%Oz9`C8!%XWBg&P71v{$dt|i*080QZ)-~ zH|;3nPVh97y&p4l9quJiM&rF=Fa25j_$(xZ;0&5rgcU@yM2MS~5 z_l+D2flp@akW1N537KTv3lFjg&(tfaE8OQiPCT!!9XCpAb#Bp5t0%GEYd%Q$FT8Vr z>Q69dpp0hwWIOsQDL^IOj&7LTwh|Nu%^=CMTLG!`;4Xs=EL5X;YiSa6x^NBUAp@OS z59Ex9^>}=&^(=a`R-${gslAEkOX=<5OaKPM<9R45PZ%IlVfy($k;g18flPEd1?L$!5hL_e|gywx-kcI=(9DH5iP(dQXFLW(15h#4Lzb{P@ z{7LZGN#EpkckJZl@m{ro`CFp15pbm&CmaUslG&S!Lez;aS9XN%SCEAkXNUO5SCI;O3kT*b+?sPhKC3(#r-FxhJbi zs|OJ}Bg|sgs=Rs|9l#Xctb)7C!N&`PGWGsqo+&Q{**8p{^aPAS>en-<(;8I8uVJ`**$;HN2_+u`zKPuP7ttSSEEGZ?SXsJJBd0ll3w+oZoRcuM%GZ4t#gAyNN zXH=W-10Jkf!wzcGLoGdnpc>-l{x`$`>^Dpv?7|BAcz#pTc85b$&8sQcz*ADBFUhY?cBqHWU4Op=m!Wge=?a1%n@X=j z|Kfrh3boNE98^l89tzXEs2s6dHBoZYrax_*-C_Zi#|C@_ol$8*r@Frs#t(MOHZUJL z@;K}}%}DK#t^}Tl^DM!>R3}l6Z`E>tGc^t^rSwbyn={src=4$t$W!@q+eQbE)7O#g zF1iekos1odOFDZxFJFi)bDZMdY=gnnzhv#7OV)xYwz1OQ)TI|u zA%g5yCWVv|8;vc1Q)M?Wc{0x$wN8Wi0jG%ncM5Kw(>k@&SMEd6=0&3n`^6c}X2!yu zbBQov>z@sM6xR73YWWj(bzM1RqqDE#Hy)(oh%d_0lPKJgucId=o7q8(OKl!k?^Q1B ziAN)aP1qX4ly~)6B21puoDM#lCE*i}=|T>-`?r{V(n8uNDZWFS_f;RtB|PG-g8iqi zk)_HE!;DRL8T(S6aI@Eh&!*VZW!VLm?u+Qnn-B4X1J$8MW+fk_#fRaTTh2l(4wr?u zB-1t?TQW4_D6%$VTu5_|eTeJ*1ch+_IGY;&4MwA8jVkN2+r453H)6l}qszmwF{igb zGv?e&fL{iq6pu&t3PWAMT!6Lv>Ls7W@f^L7W`n3|LOMjr$N9x=j(BIqUwG}AI-WlK z=xt7}UP^9zs0WN<*>JDN37~Wtir3@BN;P>UoRcG{o8}k{190_dQ_Ey+l@uXPu*`? zPO+~u<_UBUQuv!189u4|r@Lb0oky+qMB&nDHG@DZI-grsHzzz}OmDKX7nnRe6);+x zdZOLm!(AK$@-`dc2&{>*^!j6pLZ->t!VpXLCj@xJBf zvTY6S2&#u#*KO!(Sbo|CuoyA+)riSeQAciBL=T; zF->Kmi|^tau>4dDW}=HsV21P|HH~GV3xxUYhpP5#J#^i3pfe2r90ubLZw*-C$vABU zLFFi|4G3{fh@NS7ij_;iuFF{RtKux9jXtde@*lY1M;DTC&2Hc~w5?d}HHhy$^lzPE zc^5DnM^d@RO!YCI;x0MTo#i~?YKH~dV4_nNrpT`FBAqopq*~h^b=^;prylzNJoajx zSbi1eb>%4H%zHQ+-vedV)&1hasVN5bU7k1pl3vN`%eDh?`{7_`_@*N4NTCRCa|H~h z_9ozK4!2~Fd|qhpm9bj{m0xTrk+b`(QKwpt*?Z^)JgWX>MWj=x!1De5CLwC?sYy7j zo7yz7g`?#9^IdrT;6j=V(;{Jtr}rA%>eiVgQEAPPHBY`E1zIWNKmK zx}1&~MKmR8wy-WREIo^Rk(WM1<>3Blw60P;Q>>zUC`(;t=~>P3{C5KG z{!!x=K#=#g^w7pooVjwOtRipWMjyQKPEppQdH}a~zjy!V{`maf2cYVvp(z}qe8Ai$ zrTMXEBX1phst{JbJ)(8lBdp!CaREM%{iVY91$k0ej3PYw?mRk^Vd5k3iBP_uWoc%v~s zNK(yke&l$Mv{BMl!FGQtMVGnJ$3h5xUL{(52H^tF{?X~3y+^q*V`h=;#dQs?w*uGC zQN#HcXtB^Hi%>+ zE2#o%5Y$NGH(R{Lp2t%+7Y5r0J;*n*0+Jw^4(Z{nY^y%=bhUX)-vy1If6IEDWzvGT zwQV<7Ml;7hBgssd^a><4U(bOZntPrKd0O{pC0J0>80j!cG^0xjIP8=Cj=3I!pUSP;y=75O@ zaOj$mw56UVLP>$I<_GFg>=`7*rEwB!Z)sPRxVIb_c<)!zJ(?DPgg!gyT6Y@LV}@~r z!$6?(e-%~^j*DlvLPCt6!`Mb5np5l}F6m)IhNLh%QP^wwSg~e{-l9*xMeXb)7!gSo=MKf-7RB0>*oao+W#yj~ z38&#oSYWcS=P=xXA2i2LejKB&sr_0Lg{7+#tXIqUw*6-#m3Vp;Cs;rTv#*I3xn*^hQ+Y;Yw z_n839F5X(g?$#&9F|s6ZN?4ZF2k^~^RXVblt55vIgaVGsmuT!!2q^)UZoOw3Mza!( z6An5AvAg53Kg}Mu4R{|h9`@ldAT>wp-&%3B)(8_=7dtF8uf`HkCH#*!~N|Oygv=-s8H-OJHqa zWD%HY3MLTC#)!hergIABYLqOIvv-;6<0DJZc#p50$VH7m@+Ny3!aN9P#pQ2J6}4AH zYfr^D|Do-IV&nL`6%K!;`^#{R=+rW4iio%9*6$Ma%4lGtIsWs0`GdTTJ}ys;b#jwH zjCvQ$FbRClbK=PV3(Q`Qe(Bx+kQ&*K1@G-f6onDbk|Aj{DghTgVHRiL*b{UwCGV6z z=I&3(zHg)*jzcKJLN8K@6KF6Q!YNYUm%HPm)^u@YB_CAl1{JlTIso>NvXGephIVh& z!{Ob0=8$}gbq z0n_cs6y~SrJ zPmGwt7QciL|4R8o6gK5)L$obDU9y~k`2M@Er&$N&286gcmP#6lCS@I!Wn1ip#zePjYoS|ewpYzx?86s<57dI?Uyv$G5 zBI#A@*S-KcWH;`g>N)kEpCM7@!manI^pO)l^LMy|nDkfk96OC{h31#3$H^ipSF;ff z#ae)i&EckxfsV%Igk(LAm93(PIBth%(%LQ_PyfI*Yr#jxd0}@RAokme)BN3z2&v%# z3aMXi`w+b&vBm+A^k+QQy(3lmE74M^r~MR6a!}p}Yv`GFhPK1TsrRi2K&cc4NK2vC z^8JDl26a*B@DnSHc$X(CMMb+Tv#jL7@~YO_)Xj34!QMzaB{hI2^FT5MDf13%5N-PH z#y@ogFIG-iUrPBGQsV0crqny%9*%EHcs1oqY2nQ)D&JX~sJ^h*60B*C#pfQz`Jz-q zif@7gaOi>l3&Neyhr67ErD@j7h_b|72b#0Nk+fk~N7Hc4IT+vDz3BJ51V5p#&O8FI z-tzT+bVoZ_!VQsd#Pawk+SU2u3P=^F+ml_Bmx)}e>Uq5wbao}05l4@f@%e!c#Jlh! zZbY+UmmVjP}@P#r($@GuJE_@!2&$bd9ghroSA)+GzW%BaSysW|rocOmk z);breqAFPd*ECNx=R`j`zcI>h+bmDf!pp>Co~jNn6dEy0jrW}#Nhd5rmW-`Vbpi@Q zx5h{;rUKK;a2d~xHxf9LswxWFK<&1;ZJcUkW@@I_HwoF=9cN;y6O$ke^-rv*qxeH3 z_XoorDbieBpIiTEb*6=g7bS4f6m1m+h(;_VIabtNP_HRXD-l*1%Q8F+7;m0SqK({9 z>6#EaHkZw_O!!8TtM(N+&XaYy~06o z_@E@g>>uh>vulkR!;{CbmXop_tge!}>8nRUhmxEG8wdOf7X`T`=dJ#$`~Vw8C7J^c z3<=v#8g1fu9M*aXoV{2RxKnLA!S@T`R1gaX)ScP^_K#f}W3vr%feZ(7Gx8Jxzvq=j zIls%dGAfgd*}OrTnC3yUCdy@1ED@Q#KNPg_9|f3!&4ZZ3f66qZpek|vx-kR#@X=V{ zBeYLM3qcp(B`OyiMhwx4io7#ZC{$!J2fo6aU-{e=KOKK#v+sK_+W7~cdK5!F3Ht?g zq%|dT?YadN-QpeHmi^%FNQAmT_%n^cV9>zoK##U|$}8RI8vV0nzjHzj$K_Ajqss=i zyzwLy$~4&yI({JfGdMu;%>uq1rDR}ZroD#y0LOcr0sYW%>Liyh4!q-K4Bbf>4e2TX z5D9ICnK9AhWfwwKHwKG?b^cA&kneQig~5_Qvw*mQu7(cI$rFZ*#9mrz`LbY|P5HH? zi4K>Mx>Yu!^k!H#efDxdC`(Q#>f(@rcbW`qf?ZQvpCBDX0`)_?1c>3**5FR*-vqGXaxRu?QQt#rY_b9p}s=CL$VodU8{W@k;!^|2P+3 z;NH>ZS+%-I_rKiuNz0N|a3XyW%T8dm4Bh*LWfIg6;8*jn!4NGB`8vgVzOm`*wh9=~ z;??Z5{!Jc$jR1@(43+ngPzTe4yDrs7MJ) zzXe08Ass)8Z)Ot8^20LbTRHCK>BdMfmswXz%?DpviUfCkSX-~K=7fMc%cnv)4;d-q z+KXisX!mI_N%Vx|^(Nc&4(UJFMYiBz}<| zj@6HTrOlb_k&)nh@tVT&!FmMkD-S{4n4E)g3s2l6^RS8g&9+rz@rzNa03VsV`MRqejo>4VxEIdI2N5U_rpZ84?8oN1 ztBb77s=CwA%jFHlual0rb^?7ik%1Xr-mo{TM_ja z;+FHb&%>S|Gkd7?cEMTJ5Usf5RT{(=mV3aj^F>1H?x7-Iw-KxWB z3Z^3_DAeDvT52{-E|#UBz4q1LI+yq!pb-Zqk+*UL=BHJYE@CoIG^qlQD2|5UpEVHFu|kcli^4_8lQbM^(%Q}Ia%`?m5f4*ofsQwWtYP+xgNe(9C3D$@?>#;o z-6iA!w16RR0x=WJ*QEVL=L#H&>(iD?ryVs%bip@OD`kVgKwv-3UB(EL-y(@8A3A5Q zy&cb4;%Lt04H?2@jw_$a^=fK2-i(7uF_X=lzTy0cT}Mb*Q|%Q1cK=pyX*s1P&6|iu z@MZq7jG`mW*gCV`)2kpV-|wuyUfa7e;q-JbkFr*N=~3n69F)uiT}>#U*RAYoOcPl@?ahhyXg> zh#6LM2@0b6RA~niV5hyvskp#4^K5(|tZ1ThKcQn){3!m_kJvT=c2^@?&wNZFnMQ&< zVr8rzkX`VllR(@{HMpp(B_b}$Wt~D3g!g@u17Rsi-A13P?kt-J8zD^rkIdo8H=01PC z8W59Qs4Xjvr12WD;=!0=y(C%JY+ll|tK0`^I!Aj9nDLMYOPzghkD|$ZHQ0D6HgM9x zycnJLGHI0G)tGPH%O!_)<+;B+*K==h4r$0Y$y<~rPbBZb29!!d6tF;w0zn2iM!wXauI;79%H#4E6{on7lWSczU$`be_2u7d}tN7 z@wh+pF3vw~s7x%aVxhaoU64gZd+_CT^p}~4-9AJKZft}jrbeZFXp`(r7j8>w#}~OD z*uV@wY#5+=F+;fkl*ze$kLdpxM=rRrg9?5NfUqIg8_?|KarnwN8_Y3!Pa^0o5By_w zbYCn*l=V1gmv5U5>a85gbN-oXx(Q*Yjw{8mHg&hk_r{ygZi(yUcO6q<%=}qE;8d3D zdpB?>UWD|Xv&qphUT3QR)PdO0SE_BZ{9qH!=;6D|r4PKwOT@)QKX}4RkmcMH#Ra4Ou!4r__!(vZR(Tp9&C+#{WiusnW@%@F&5;Rn3f9L{8Br{}g94AIrAo zguyDR4GqM*8knA1N-kBfY?==ocY}Q3Ms@W^uc4;eh zhW2xN+>zTsl)*RQ3?i-8Axxa6;R|pQ3o~O6$?G&|=-W%u?=rSkixSyE7&YjZK1+Q( zon|a67X#u6rqlMsHiO)r^bC_vBP_UC%>~D_fKcth^61aC@_5ygEouPHq>{}knmVGeuCqp9{kpe0QPqd$)UE9V=0^s{6Yg;1-Z%I1q}en zpauDILfy>D{-#SdFAMv9R%46>S_B&noQKc#XIuayK3=3=wAShgFU6E}qS;h@CV8E? z0W*=%AW!8iy_`9(3sDMT@EAk#5@YbD@O^F$h}~(flVQ;UUarFaT-nF{3r!NSP?~gk zNU5M$k`n?pLH-c4p%Sp}(MVu*_c}s}CmhTWf(W6BQl72L-o_&j(3<>jz@+wt3*6BtnV%mYC zkP9GT0(UF3RL45tdA!OuDx}gph`rf_Ll5>)o*E9ir)4wS75acJbeoeIn{UfV9O1%v zJinB2nodXTLGt#2=rn!IOyBPNC$s?9A#kzd1d`zaKacpu^3cMwOil87bk23{lF=4? zA@8TBvP2+82UO>7;*~=TjqZML59E9U&%7`g)ybPcQ*X;jTlLBjJOLNI#|3f>Q&{Vu zprE5@JSYT|u&+4^uuh)e`33ehB^=oGuEDmuGbX02o)2Ou0VFW%)$`qtk4O>Jp`LI`iPO@{4cn} z6u@@cMHqqw87Wbs4)`uFV)IOeV@;|QTnuv5AwbA{M#;^Z^t+Kv#De*hM($e2tF&WJT5JE?AItC%UL33@hF z&_v}yju%m3Tb=MhIdmN0-qZ)$>?X>joS|jM5Z3lPj`I;B339XI>zvJkgFtcQa3$UL z=ls$#%jR%%J)IY(YO59c^8EqIDEGBmnXxI4os_W5fuc`NpBEs4x1AL|_PyvNNhGiv z6KM?6bTJ*K>spjYLPitse;rP&e)7iKQE*50df)e)_g(XuTEn9UNcsZMTukI zn(I86I*HvNu^btS$v~ZG)6yHlicqZ)FzW0F7xn@hk~YMInZ}|GslFK04}ZzE?aJpC z`y?7vM$i$JlAy-<0+h<)G~y|6j4tB1zm=};M;Y^=Cdc>u>qq*(zS)^3(H|&vHfd@p z=-GG6ZrVP%&e+EE#DTIGjq*98!-F$MCwj5rcI~eFdJg)6EH|7jf|@04wRmus&mJJV z*(YYS)F6eFKhka_;f3~KyKmfYXN5-WBY3&sNr}V#66UwSipw9+qUMsOKB}_X0+Wh1 zY+GzzU-6c~G~MP(K_TbcnI8`_KyQ@e({o;{w%iBJ0v}CGs{7zzxnBxyErHct#d;_q z4Xtw4YPrhJhuB{8!+aOI0J#nh6SpbZL~RqyZxy)eJCO;I&T%2~ zD=;*V!CQ0AI+U3=_9N^{-VSU&%2L~yivu?+xPnCvl4RNg)Chy!qQa3MdFXa1swC=A z*2`69w>F`XO#C4@t2nrpQyeu=2GaFWF()eYLUh0MC~Fq}P`DTC*4`OQ`HsVxlOK*` zP!CG-jOV(*My-e21Bt6>=dQ3G5_g*Fl7k&rj*9f7mqU!1srHu=W=A0VmB`IV9i(`< zRmobx^S3ZAEcX~sZ{f00Ldz=*u)&w|+@s_;?=sR;osR;mO z)&P|+#&q;3f#DK_*$6B3=n=n(9)EWI+dS8wX{@q$V;Lzb4!fJuLJZ`G60t;41TguQ zK+L3?G$A}QibfHfv7fOo+d_6H9!BBS=Rq=8^o8<&ZlkD0|ftb6~sn-VQcnR!aT;D!EZ62|N>%I%4<{Uh?^a>RM6TkaWR(dG{CEJy1 zzx?)MP*L|>AgZ=08%9NwO-$-phg8Eg4f3c{Z#mq}KlX_|=S3c(H4aSXpyd=Z+x>^n zmCZyO*Sbqd6*OCwol!4umL_!i-j|1qt;<&4{`XHF*z_hJYq7I1gBP?ZRtMhR_A=Om&%0OTPCKpyXiTx69{hr`VC`R)j*WI5~W z2!G_U-M(YZwfBqB_4}zM2{fH9Aw5{*|8aIhT090 zkK9wBIhKbqKC@!4Hv?D7x56XD;e{~-^by#&W)%wA*0L;=wj{!#HBA>^K1n=7<;z@; zDTp!TTqaPHalSUiI(P)t>*}bOyCoIBmHI#<86QJVk{ZLi3cDXrX15R|6ypS%L+dTb zEEWo1nW&R&HYxj)+?`xOz=0npm#rnpTl4522XvWuG3`9gON#^89!n-eMPwq0#u3iP z8ibPP0*G^aYK4SB+viJ9P}U+F)(HZzGP;D4nd^j61~cx(V}HO7pO{BLcZ)O$B?IaX zHxOwVY!AZ=Bv3)obE;Nn7)lC{;p`sr;gN(lE-6H&k*wU4$~Oy zszLyeOVMJ?93&z5Xv4xT*VjafrM>2n=pM_Zcn|hwcUQgahji40F zBSAp8gxQ87LD~ja!bFtd2jU-Rk?`e~L1+ol984zNz%AqgC6bv8ksGF8>@DXPg$Fbl zAc=>~nIKXBBT1AQh8XnjX$djc6E>&@clk$_=-LxV-UhRcgOjuINB)Xs3QI|rJf4AC5k!6a^BC1ztObmN<1R*39u)Sc&BJGYI-k97C`pv zSG}>%JkocV7>qC&W$^s_1v72y5_j4qX^Vma+L+N+0oR&{SVau3Nq+Xok_a3|@O~j+ znQ^K_?<#(0IW_0_Z2D0Ej%yNw*>7rpxTk<)(C?1&n!R-v+?+%yognErIgyodI6$CC zy4gQ3+jNd7{jjf^Fm*Fu5dz5ZGt#ZbCYW)Z_-so_V_uVzKDLDKiG_6skm!BcPhg6bdmZtX6@F7>ebBT{C3W|(+{3nzDjPg5dCrLL zfqo$w-^Dgsb;mihE&otih<71-IKfo)*KGUWE5utwGzR9xnbhZ73=QELBRkIt^ya~Y ztiXErJ(c~j0M@6uE6s$`!djl+MDwG`;RXU3ChQ^pQCfT*`Se&mYRN2~7UcDOaAA=i zOm08>=s<`T(u+=k=js#Q18f5ZDjl^rq&rY}CcY~+?{J8Bizqo0SX$K)S zD40TZ4;M%L^6Mb(1l2OOknM7=as{t3k%#W?qLA>KSmizOtIYWi5iSp#Yy=Ktj*MTR z9)4n^u4GU)+dt9#g_HmZ=s}$EA@^BHr%`t_C#NQghp7!&!fd(&lNW#?0H=x{|+%m8i>%$(LuTxZ}TWmhwFdE;}+U^Li=t~!+ z8s9Caw<@s@~nEwBZNU(sdJ_DmKliVbq} ziyny>?ZMRdO;S*!0&ftp;e@4WMI*%QX(ggd>qXdJ58SV}@BqtI(XOb$gf!12{8 zw(YxzI^%H^f4v^kK27!0jzWXE$ho?iayJtQff-JpxID0`ySP*`#}zdhp%8{4U8EqP zcS-Ygqlz6tDg_=y1-^re?vRXSc+2Q4>@}MUb-aL zG)a01ts9lqmdl%~lE`Nqi^h;p;079^l&MVyx2N!0x(cGrunR0RmU{-`xwdlTA5oR> zvo2@6li)C#Gp*iNB{`eHmQXfTcEi}NSa{V5CT|^SEN^mR;7|>mhn=h@K&G3AK{xG0 zY{H+piEUy*2?=sjaPJQ`iuyhmNU(iQb<<3C*XHb}i{*R)BQC^@N{R!erQr&|Z`@mz zzn(x%r93+=lHB)V7+F@D5Ua1AAKdO13MpDtOG9c&} zSF|ofkv->Icfw#PJ{!-idsMI{X{3%RgfD+SH|{AD%&TJ0fsM|mtPADLl z=yK-jJpMUtxFCQy&S-6fZ#K{44~TFB%E>5udYmleOuOiSHa-|-T}n)8mKTsUs!ckDRycqksAl_^@4>gIFl;_GLu4QV7T zphSdMx~!V*&0e0X*=DNR6zkXRrvJ5%ERY8^cT(=(7VN{;PoXey}5M&IY zu})}6gF4x|NgGd%;W{FF&#{Pfabsszl!5ug(pJO)&ERfgF$s_F`Q0X8XJwwGW+nj$ zF~dIqV%B@cIB#Y4S4$KM6{M3n$fEduLQB1&xLs(~(W68tBcojeZgq2&zN4(`XW7y^ z@T}7C%5f>b0#|{dSSQbwI63|h4~~Y&_!6aKXngAjwSTk;TKe$-O!&4ZR^)nNFr{k} z7IEzHCirg%VKV5D%)JoZJ+DYH-D4blobe3o`fB z$2X`EN5yt91jU4W5lS(rZ=;x0r`q00GD$b7K@^{=5nN&OBC7Ou4sv7;dT=7B3z`Rf z0uC#k;1uE_c(p&J*z%yj0Oj##KfN$8{4H3w66_-^qzKAO0hU=G3W(HMLYlHB(BF@f zQflppCSHoT_4X3(#L_NFC|d30J%>NY(WIzX*+kA!8;pI~6}DKEHi7;hsldaj{#~B@ zGXKPW2GMq!&6HG-^onUTFWk2PS1QXFR>IhfUPY^LM{ z#Xkq6Z#6;5Ms6g*ByCNj*~9oQn?u_5G&;TkQNv7QK;Z3_mmb7BO2gl^pD31iBf!!d zLHoe46eH|e=69(0^ERuf?rK-5mD|t4^D( z)<>@8)?f9%I5i1Nz!rq@1s*CkZED${_R@lfx-lhd&HmPE=}uP9z&(r;E)4lA57>m? zDdXpn3l&)g3?Ud(FI6zy46FLsF=CE)TOKGvn+^tJ$*$HMkY0T?#I7?ia(5K(*I5so zNLf&|f=jsj$7MaT-#1Zp&Hp2Ty_AmiTBqS^)?Y)<*~Jv3CpIJ5Ia_t+jdYs6k%|DMQWGwsK+<-NO(AAFv?Ql_uY|Dw2Q>ad9M>&n4INNx!uhx5rl{H1 zxlD9631}~5u6GndeFaA`pNOt|hWfyxLw;>4Xpd`|{CdF#QKLKvN{E7KxP!%|O=0;v zR}>yV`&@{1W|oc?8N!sqx9c4n>`X=Okjw|lvn72Af%lyZVNcQP4-R{+6BQ6&+lmH6 z+I;wehRdcJ))sOS|3LU>=ZTb*c$|4|>#d}$$%EMLOYN#4(VtLET3$YSTcwifd0Irj zn03plxIaW3oX97-x^7ej#QitSXT`{i-dh=O!N}jLVi(#&&Q_DDSkrhTx*k{sD3Bjk zIBt2OD7F$!CiwI|z*!b-UJV(}`tcswlH5RWJ%hy|O@!vT40~qdaveR?kBu#f3O>j9 z;v#R&e;`%55Y?-9Ew6|{Ux0^?_}^coo(dy~L3g`>KVS2o8=lhNY5^W5t!b9-CfI4bem;XJ{{xHziNALp6?=pZOkb4# zGQ<`cT?U4Q3PnD+8NP2)jpo;8ai+5jTEAH_E|sh(ZTU^ggzNYSM6=EB>{z{t@b) z4nu^{O8}{8i1*LbbfFhv$*uX46~xEG@+T2=$M5>A1;HR3?56-|Vc1RH0iN3hkw zS&>h6oq44LureAe==bR*Bg}jFfCs1#09n$7y{wC5p)3{_0jJENLu`a7%~td>=%N~_ zfRfTt_M!kSM50qM*0Hj6q(mDs>J$_bsMLs)%F1?2!0Tsx{n}P>mv<=`4tUIunQs$Z z=@RER!BGoQ6}w8gCHpf3x1H$n1Ir9^JHE%#vp!U~nE-dMbg4HQLIDdd%_|>iea@kq zxbIm()EZUfZNX6iO7}IiI|YnN^EWGRcn`CG)He ziqlDXfOyMCLbWMt!HiNlimB9m@`EpT#ZwMo;P$L1B~YNo&i_6$xeZOAI!oe&10h=L1Y3b98|oFI7yv5^koG!VUNSF?bGXdB zJiw<9pC$R9pu4+^HBQJ3_T{*3G@&7<U`t$bkG~VK0x5oOjjD`boU3 zF-%p;)L|i4s1Y6-VeLBj^7J3z@YBlr;jQzsP|W%v+a6fTpN>b9YiEAQa|U!1rbsLa z%AZ0s-&p7)mfpS?=pB{fp8EbF@1gn z5zGzeGTaXYj!s@qqw&zM!6rys12;U@$hi)hZ-S1p8l*A_sl{L@_0+{#>YiekFf)-8b+Q-(s-gbDOSm&>j9raFsn$lhX+O z!x~GfweWpjKIi}J+d4l|f0S)wPiCBs?v(LcC1?@K>bfs6tiBa+-9aoWgfjL4)*h~u zk-!=S%8MQNSQbdZ181P9RI&@#FdJ_;&x>wAyk#`d|nA83hu#-8dH*s0 zDV$)2#Vtr17zBYw+xq<&`x43iXCd;GXA2i1cLf1$9bwOqhM%bn^pc9tJLNMaxIJ@o z;(@n6izA4B9_M;E(T6>ajRtoCIr31iKE`(Y3C4x|c0G7}*={-s?KWHZrebb6W1Q}x zYqI7;w?p+U-p9}Bx{k?EJ(sO6R;A*H%owlE@_|pKdzBi8lTaxxA7rG<53%=YL?=S zKR2EGsq4EK>eMIxwdyogap0#!e+daa#?z53;yqK_b~=1H*Fn|Vsrc6|`&UOxP+?Vq zFr&GWp@P>pGIojn%`I8B$sb+0uF;|mH(5XeO;mKb-~iTR^-TnZ>ZfTWO()e^wx?isNp*GEGlN7XHgS=cG!Z$F$6 zFaAthWn{mLb%{{rubyV+I8n$0HIcWg=9C++0JPKf&7pT0LyE&yf@!C#ZgSsl`(B6m zg7;*ZRVlLpnc)`r9gL%?!#Du3JD4`i37RuFKt7A?`Yba(??4W9QLlialtpu6oSa-> z%^A{{*UdwluU-wV2B{Y)hyBkrjQkpENJ-MY`_H$OHAXUVaZ5TuoScE)4)XF))|zfL zhdhC|p0nBT%dVX;$}3k%dOmqvJX|>BwRcL4mt$T)_=tIyUi}^ao047bB=nqQDv|ajcBPrDHcu!6E?U1atU^%v`K)H z)BzPf1i4@S^RU(a7j9T#sU+dYTo4AYgd|x|E2)-YAo_tPXuzZLopdHcawM5IUnf5w zduuI$YpUi(<6_`xsGh1LmDU+M;58LX-l1HCB0q6lOe2-ywKE5vSLIaSg)%;Oq7>@_ z1wq-@o%yHFTFdSysV$EryT)d%lA6#rt9=VC+vVn?E@N|lO8vO;l!bHP zuNvOt1NUA2s_WT_C7TF=O3R=ejrxqVb(?JZG)bk{szaCoED4iCf2hrwqlaOF7H6o(^Zt|6T z-;OR7q2II~XW>RAXqIKu7=z1g8A#5&10MRS0u~QE;{g@}@xa%Lkgu&KM1E`KSLXOO z`a^}M*+V|!l-iM)%sYA~#$)?)*4cyeo4FR|91dA*-AJey7qQgYYJlE?KlSpDS?0NH z#a9>A9)5=BnV+t)ZrUjSlQN0Fu`WoKellD`-Gj*9VJ;I+;*I_!nxgenvR%Mqu=CB(J<6C-p=NCdSx(*$i$NgP~D3zSjEVv zi)p*~DKUa$kKK>lsn9u%8bs@XD3YArn#Xl=YJH~qVW z)J%q(3#VT&0*q6?8D}C zWN~-ot>%#=d`Ev{j*mB;Hs4h5`LktSRZe!jyU@ghg;eDS6YTAm-u>xz1ngEIE_u&L50= z#1w$mKj5T6qS0FRU{5UFAxKEf+A30cLd}>f2bzm60jZrph1bhK7!FoE zge#SLg!N>;*dh-!e_;YGi6zjIym_+PmEYaPn%6Y$CHl6TuYkpoLC3Pn?H9h`2W}vC z+F?XSsY=vRDNYm2XcF&Agd=Uty8MhGfzd8UQRUPizqk5#Ud?rdpEl@@F^ujax|}i3Lu&Yd@1y=oY&Kos%UryW>4L(4qtaLTR(w}|3e2<&-}uXjcUM&)YbH~+?1FE5a|>40 zTE?);IK3*FC>??@9AZsE*J~uWwa;L$7d?OqTJsP|_TJE*IoUYp+2%Dg`Psq`EAqWU zueqQG+l?rcY@5EfrOU!gvq7W_vMSa?Sq6uEfy4*wwiYcF)iu_?`%~ic>kGAOoQgmD z(^rp%*_8v~LsYU*!Z`_-U-hkZwgkgrg<1%HdYX55_E#b|!4(X|oFQD=2V{S^Imu!g zLy=S2GX-3EnO--_KN1Xep^e5KYSX%uu^uA?%!TS=H@K=|x5`FzpjE_Cn5qaSjGW6}ygsk$3$7g?)bJa3S>+Ioj=Cb2^jTcvIPyY*C`9FBS+!6>*0s=nKRm-Xj)B zgQ!AARK)7vLnL_I2ee*Zoo*y@3XD8?j4(Y9+ceWbTX0|+kk+OTGah4E_1OAa2IS&s z^497*IeK~4qKQz?@abyUHTaBFM4|};%(hcKP<;bF~N^nbn-5Krt98{u7#}JIf(yJ)P^Qd4Z@S`}6a2hEmSd<4o z<6P}7If3QpE-$8wG0diH!L@A1m;BpiZQ=&$7mJ)&1N@m}T6E5TR6lkHs-?5xH?2Tk z-b1St0pJ0MpaOM$ zJjIUWpu%%@S?_3&^%_Pmz8#H)oI>y3p=uFT-7eEA744O_K7lZr0Bec%xmc z=Tn}h0Q%%8jzz zR*F!e^GY4dM0F-}9=^uJmpg7Q5S=(NviZk-U}VCvT!1+dV`QI(OjGw$)L`iaE;i>2 zvNT5&2M^m4AYr2Y>fYh?OQ!RLQMPXE&)AZiwKmXk|M7-;ao42JpT$)1yb9_2l<~G` z6_t9B(AtA*I4|3H9*U3GeZHKbONM1l1?V9D4I{Zqiwd$`7y)4lJf-$&X;_dA*7+-V zlDzl7e*uAOB-=NNji#93tlg5j@{Uu|xIOQNk5i4UcH}b4+taneSsycx-{lnI+P=37 zpfr)Y(@CZ*By3!+hV#IOK~Uh|EfE98-(S_f2h+tfg#`*{COG{tSubLZ44-H-6{JRQ z%I11u+sRZ?WX%CoLVoYQYnNQkYsOxGMBx8Uk}dF)7>C*VisKVzK>*gOBBI>$V1OUO zsEJTwT1uieu$Vx*0)5f@KE(~BI)?JF1SyOtQIB<8H^U*20*?JV*LK6)Zg7AEZOLMY zkL0m0^O*qi_W9dq1K$VgV|SDlR*FPSYY~kn#ezqJry0pW6oWJuPMQ%HQ5phEQe zR#O9Kf=*xFm%Y%B@YAc5(k}izKG`Wvx8(;H7B0NT`F*fh0Dj8&3foaYKW!=0shHlD zDkaPKXP_XfPfwE7txC62^SEmW28$$Bd8dU;x%2VhD zs1R-(|Cquro-)q`xh<(?f)TVBx8TD5lIC8E9HFK7Lj0KlQ$ASKY#e-nvyP2GPru|G z-Qvm5d-nRHVk?=y?DXaS4X>EzJDLRIW^mxUR(fsSp3!sxUA`iSf z?yEJiycnz%2UN;J6GS-oo9)If%4%x}4|lV4-uWtOn+hE5_lMbI3q%`2voB)XfBjEQ zs?=$jl}cqkq#5w^7i7JUksoYk4hwuKHFV|ZI?4>D7#)FIG zURfCiaPnWLYF4>~f(JZOV%u=dl=}>9D8n@EeiEy5>S-t4P91+eYrZ>#gu~AhcjF91CWCXdso5cT=p|IDnC#~x0sK#Gtc&X_^L0j zmfx#4)YG0%+OutNR~m`>c_k)YF_(k)=+b!ovcaaFEar+|8d@4W(*pqQKJjN;Z+c=n zrh;hBRw|1wPdCTrwEVT8!^8dJ>8cqgYU!kNxfsyjQ2_jsUegoe`c4?^42`?Bi)qjC zF9oyiUv2eg@2K6n0`6XTu4*5mjP>Ye?k5VJ$|iFg0xMqy6{LBa4=85y`Fwuv84yhx z@8Qpl;x^wbSFRqvGSXdoJ`ZhN95yeDT)f&4c?bY2!HwrwV|^8B9Y8E*wxLxWx2~=S zTX#`uG5HufO%>P7*2dZE_IphZ%y;Pgk~QeilMQinb~GqKMCI^QD9Pl{fm7vq7J8~} z*0VtUGXI5zEYOOO019RtM}|CoXv$hoxZriV7s%hq4tvjoNJ4{=7PG^LMy(ETDQ{pY z`9u3q<8HBx6yP&8Vd#J0YsGq;fSQ}FR|<9EsU?&$q!ZMDR6&ow%7Ha;B2CzUShZWM z^40Yi>c_N3Y&?=BnD(7vd)6xWsW-`>w(NHnmelewlPjdh{S%tL8|71#P*fqLL9p|V zw@b=8_>v1FYrRr$10P^@QvA%1rA9w6L`UlH?4oan7gcT3>w(hoY^DE(-3J&k?BL6w zLY9dNza^6VEA~06QL*>uSmxB=?BD%|uUzX?!aq(6wetJXb-X;0TR-vNb>}DS60U}j zCRLg8rl|}y5T*H$3ko0J4_<8Qb&q@!4*VvMZ+hjsH{T!E7sTMWE%zO}hq27o(nI%4 zM#p`k-J7xxu^2M1G+2eYmy2--EHk61K-8 zqEXFN5ar@|xQMp$bn=u+85T7!lKE3IMe^oGHBU6nRCn`eS?Jm~$f)}lM2S-Pof7dX z6no1XIJvd@E%+0Na9PC7dp=j4DbroX9C|xF(RF6A@-f}c^$=c{c%XY$axqi5qoXws zLN|wg8s0R89daGkaAKQT{** z)1t&uPzzy!_z8q|KU#8;1q~Wy}S9L49u~d7kvt%>RH{WCNhB&ogzLSAPsufdx?l9jc$bEcw z5sLCoWWM)yCRNcN!+5a#vyJlTk*iuHz|gSOGD=Ccrc(UWb&8`V%ZtQZYEs;`b6ED4MY!pD4k=>g)T5e0CtVMUi9seJGzD&^ zz%>F|mV|f`4qVqmOxd9H9r;aLs?6NU-Nn(h*w@SL#^&Q3v4Ipou;8%(Ab{sG0Xhyi zfAT27>+=rWuX)M4$89*b?&>=~W4SC!hpTv`KW>hkm+$>X!nf9IiEwV6;C$PVXQ4dq z>e@e>?#xSKXE+=hICWpj18xRz==*p&4Ovx+nn5#CHA_x!9=|N5eBb+DUjoy&WQ9t_ z7*05RX2ok!|TQ1W= z9Tox+IxEc+=)L<-(pgAMtRbnA*(7UTEVD_m34*d9WS3lToR^`A@mnS)Z4jHjrS1ht z9}EeR+W{WVO0{1_JhG6^hF>xt6+_QYwCU=d*4+x*r{G@U8x}dx`5$eaGKLS~)2}aZ zACxk%ttq(`FzOBq(lK+9i@t?YRyEc~jL-7JYEjuZ0`HtSeC_LeiY1662AWQ~Ke%5+ z9cVaGIq!#F>0^*Q{M_@ zZ!$cXz2|MkID#~?Kl-*A6k9OrBm9nk;%M``ol&y4SXZfk5_)<784=JHwe6({-suVT^mEv)Ichb}m$;49@UK!9l^_Wm7ezzPqENvtnoD0O|Lm{g zOL9Fb&v}lRD5c=he~0*MY1{B(x;Dk`$=1r|cA_}0&(|o)hU3iB1~@EBPf6<=@8Bp< z3Z0A&ya}=oq}MPaev^}9j++gjtd{%Z3g)(z0LzgE1EN6A0rwZ_xTiLy7~57Vf~D-H zEb?!{FSeBYl)YYW_!t_n^pGTzYu+M!py+KrrM`aDGmZ?&mH8xE*DY0KRJBe(Ce z2bOTnl)2ig=EwSUFPO4u5(I7$=Z?ZzI6HKexxW5{->!Ao+R$5`R%)Rn=Lo=!<>lBl znZypp4G+EG>$)p!)v7}U`Yg!@K%eDtVG{;gQsZ_J!vl591dO_6`{K_)H23lxjo_K=us#PpDuqkUx7n@_Uyl31x|95!&h!(! z3OL{!EV8|7+>dD->G$GWRog?U}xttt@&k zqD>KsFNr6wLMoXq`938!Uz_i0RaV?D{w^Wln=}{iE|rqWcY8jf3h8JB3+{}*?!Hd< zcQ>Pd#l#03o9%raJ`?Omd4RmJX6(}$^P3W^L3&@Z-5WgNVSXX!ZY*b~bougy)qc~i z2Jc4*&@rz;t>Sm}!Q2TQf6dl;iVfA9GKom;CEah~e>y)+d>Hw@JqcwC_*gV6wJqCF~G?N1Q{5fvbRUYWu z`I>A77F3h^w-Z%s1;UT-hW^^mxEUrEf?6F@#x!7cH?2 zX@Vl}pI`&Dta^OFRdpzJl_f$!hHrbJ)T(f+peM$8frXQ9S_WD>Oaok3y9+m2$v5Nc z?_c}(qSa&qLV5TMUj04n*k}6ACfO9H3W?6yG^YxINfKr7Y`*MR!;>wpLVv7 z6pZgrJe|Cr01{8n_nV`hPp|j>igWH&g2ao$`Vc6bdF}p|Txf{T!laJG2vNJm%QG@t zosnKLo=Evqv#*ZXVv7W7{#DK3Qm%`DLAuZwYp%BpiyK|elPdEJg8NDid8#mXt+}Q( z==(Z(&E|&lAu9$wSrN8JD~6L9;Vdkuq3e{qj>p?i-F*K=X?rIBH>oG-Ztxk>T7_it z;$YlZ&f-bQR2J}Z3bDA_>6s$>Rr(IZQS-YD1^0V$4H9`CJSc%~yr_2T_#f4x)m84g zn#%c0+1XZSy}@z0Ej=Z_aqBwr zDcV2;x%<}+XgS0@+{AiVpks9Ax7a7*pvuIv#7ZGWC%gcna~UsBDLca^q>B!4R6*iN zZ|K!NIe#s~jOK*J+XF8W{wq9FIHnJM0Z+c0K0kNv&X0xc^=y%5lkX`ygj5Jc0W2Nt zw+EwI$t3eujt+p+?D|ntFFBaejoevKO0T}9X8s9z@3U?1Tq}bd9rl7d?M8may2;RQ;ow%loo&M&-R^DKO&q%6EQm=UJle z5=(DU-Og99uxpceF?`+K7dyT^z2G1qQM%y}%3EU>a(|n2ET_4P38YZ*B6hFK6N@Kp zUqbd4f^Y9Mj)|f#*NneV%iI~hBdB5w{q8Mawy*< zN>TaE&@~^|%XvMIu?57zz?AeQ+&3?8q~IYdgIEXrFnS z{8nJcJG*7rIV?jl*s0@Ib%}JkaES`#tWh&1%Wg0Wx$vVUG z_SnyTNdGr#_Nu7AFq}L6KuNGRh4v90;(x!4wg2T}_?e3( zds19qOpn8NwC$xkjn%m?<-6!rJPn`5eXLv46xsIkRt>;uT}Q(L0A-U+X`$4kADkq% zfMU?zKl*6w)?z#@^7(*Wy>s}=n$4= zf-rweUlc!5?%%-I>@|=v5o*P>T@300F^s@Y8~&UemFNCB5eM{kp<`|)Q3Xrr z_DUPiI>Pl85c!_}YxZCNylnDvWgx1kz)P=ii68@L9b`;>5UX(}F_@v=j!L}7omo!_ z<2mL1SysT|H?|VuMboN43+x_KCOuq((4T+~^Z9Jw^pAzp$J$DIj@3^Cv*gi7BLiG* zV4!5L2(N8MP131&&3G?Krf;1~vPKzcMbsbYQ*Kt~AT~@AIM!Jz_dPnb2A3cdWEg5xS-C%Nc4l5iHtc&8&o} zrgGjA3DuJdO}swPQuS%%xTJ#0_2t%|boSV|-?$TZz%B-paJ z6^Z%r^hMD~bKn#h>45#eJjK3R@pBUR@5&%@T}ibBhM^dj5hkfL7RYi+u?73gs{dlB2@5QT8PW#HR|A(xMm2#;Hbq$b zpc0yk&^hfF-RQRo(1hln1(^WdE2}gFxE``WiZRi?#v876*KF?M=Vlk<&0B3h65mgN z4<`of^K|ZtyIyTI=g7i~`d5@_`pfrfz~I81WnVPhy)C(S09>%kgvyofOAp)w|JGyA z`#CNedAmFK)jnnLp?#c;V{!DE*G?cYh4eGr$vHdV>f#Hbu-x8zagiG@WT6-?;FC@ z38N6p$OPvMtJ!m04?%x@OM57~{k2SzEcI_KrfR}eJ?U%jRXwE-RaE}ZFpF=smq0|~ z#tNNUXw?acGeN6?ze*<;-7;sWdNR8e-3>VX#!-v2X4UMqlVLuSIRvd0qmBKiAKCgS zz=sV0#katx3;5%p9)T`wq3q$`D$qdUWU0fS8fE;#oZvd~V})_FGKa?O#kWT1(#PTd zkG?r;^i)wLLw6vS^WOq(znhx`knYH{ICTuzLBuUEu?JMP7~16FI;d}f>V(Pt8u_;% ztMHZ*w6UTU4SJqFFgBWmgscB)u}9Tq;9H{6QsNl6L8v;R=VS?=cL%8? zfu9;(EcgsRGjv#CO_!c$+QcPa5+MLdAZ5+OH(Rmd8|AU7S3!R&N|n;Gx->d)Nt_lY z&}hjc1X@H%R8SX==)&0(WoTiNvj5F_LK$l-lLl(}aB-3}Z$lC)WM@fz<^O)GKY@5L zMq7!hUYp0Z@QPDmtPKs0gk^C=GaZ#0J#wA8nl~s?`3RVR(rOLygp@?XW zO+uAalZ64QV~KVQvk9!K0u)_K(6=K28j2lPX_|Q8=2~BGQ;>uj+-M*RLqnmt3Y;EA zs$z&j&^_W}@dpnLY6@XDFr9eSg0wej8sKy%0jJv{;(rF_@#pfUlVH+YRkr6WPL&ks zvszdzi_=iR+H@wNs>)W?g#sgVMOhe0@BtCo@Y5R|ec8Nohz8PPah4~VBvij_R#7?` z7*GyEcNi3j|9m%a^bJl3=j(&z zlr8$rCH0ey&1=K%n3i#Df6i@3&vRc%)|4e%QItbTkXUbgw83D0UL3b-J`eItd`;h( zQr|2^cdUp8TZQ)`_CfB0yf7uIt!&w);ASQYcS8UiEyr{LxbqfH{d>REda%(lII95D zh1JpDssF^C`dfmE7A)|FspjC%>XEWuUId-EC|)9n(K3ocMt56Y1%Bqjty<=5R_g>6 zV6YIy`!5Y=I0Z{y$XEoKpkhIVX7Hbw6H80#(?BGsB!0)}*T_*Rbj58T#&Hz{HZLcs zf4Sn4;bAF>FqIAV|93oTD)Wl2#TA-~)0i}_l5$Sgz}%Pfsh$T8Uz`D}b}s@2^RbL7 z(9kBF0ySGeKoNe9(2%Lz;HfZ8;D5BHYf2~rhk-`rv}wzNC3|+SQpmdt$+X0`R+8pM zFK1-JT{^UuLbhYgMrxE#1c`NRnuL;(*;s1@snu=C`ZL-=mCz zG5T(GHT3uDR9+hTGF>@il^Gk}O)pDh&>T@owOn*epiuq!CsgwNObm>+fH0k_0k?UOB>^2OAzVSBQ0UNmVYNS;ZjdNSat7Aqy1IN6SFdv^O4 z!ZYKHbny1t$m-P*^VSk2Y5uYCqW;`4kF# zEsv@HfPq+Tsf++4)7C{-KgYhow2HpJmn|_|%N%Cvqf;e<7?F{!g=(|;I_nw{MHT2* zie@5Nx3=6beRSKB!812{^3@m%UcJe(Tr0`*GC)v}&|_#YYwmFDHP8fRRo zt^&ks&9uXS4A8Mxcz`=1Uk85}k#uzcJCP7DI*Kmv{gFdfvd4^F`EFmu|MhtPDw+Il zA|&hC>9`HpeCt%A{lHVa49xKq=8u*(B82(6xL@9G%C_-Wbk;wb-jaWSL%=hqC4OzL z6Jmk!kI~`c57P7sL|lk%z<(f{qL zh5Ik;Rr#9Hqbv8c2Pd%gmHrhGhnN`=iM!9M>_|lt#-7gS-fMCC4cvkIF1ws7(~gg5 zHKy>?NMAIW+^7o%}9&m}X{Qkb~p9rMjfR$QSOzQoK;c?`;>VNt}E>nUhL0 zkq09S^a;tW4)?3F6@@;Id-#lE?P=1B&VGFZLUEir;3fWTp+~F{PpcNS!yf=o2zZ8e7)1-{mpuceyNBF9(MS z@0+t9m6{onMQFlTH}Iwt4gF?Gi}ucPHPlkC%HxQ>6hpcecxgck7cG%r{mon!zVsft zRW-CeHVzlpflS*U{!h&t@9uvB67PdD>bg9(&8Ipuuq-O3n0>d6h`wy5bEhWXPrdWo zY$rp@ub@rt)NW8XPhl~wf84)CKbo=Kwsr1OaV)JU2I#B^Z5$tpKuhrb2;d%34PeQ0 zT*y~?(7^K&%7*V`PV*--_wso->KxT;qA|Rh)iXuK$>?2(GAFGrA!jJ()naw7j@v9z zU!3^OyCP-b?@n!T+sFKTuC{cL&iVFf(I>andG*jJ(`{Hup~^uN386^Hw#hCXy)|9(8jZi1ZAC8F{DvC*D$Nc`0=fzEFZ*s z{BtXeZhxsGI=+W9{86XVp9|{SMUG;IALtkY(T_^NZ-PI5oyL?HbDg`3`E#0qM`!SG zH^_DB{bGv)dOS-&k0-IMyG*eGTf&hQ^u~%%`7fnZS@}%q4jq;RTeQwk!z{_O>d}Ja zv%njnCnVjkxx|aXMWqF$g$%i;I7=7~u*=KcfOrpQzbuqhKR|<@=j;>o){ipEMqSzK z^4B@cL-_P~ip0OCHuk0y{<8uVN^JAGV%^;*08PkHze-NLu{@t3+>6`y*ZJ@T}XpajOZK##eN z=3_Vx^t*yD({;gwo+t}ZqG$3;tv|di2%`$bsU9=gZoPI*1>Bciks5uEz3=5>zq-6i zwAQxO9hwo>eUPXDCS~))7{mzjd&MfDRW63Ut*Mfm^*`w_H%znuqifqBx#0yL9}kb8 z#(1WS#N^=q^?hlr{W*7Ti+JZ6WcUMI>xtnbe_%g~)A2?9(HTVT)G*XaP)zNyn!7G9 zPP^X|kM4u~Io44y*>v=Wa&=0Ge(9>@#Xt5Muk$iAUBTqlf)>j9gSm#82u#4o9r~h|NWK^yI^|7cNC~#Pg~(ot;4T5gPg_`-oOHB&@u6<;Ct-bUG1fy<4C| z<6syU6~Cgu_i#Q%x1erWr-Wmrbs?D2$N$Y-NgB)R?!HOLUj>&nb3O&*+c@Z^=u43# z>c}@%9-AWqv4c5k3S4Ma80Gu@H=o;)TPGx)h?J4~=DU&4VofL+o$J!l6C=ue_bzX^ zaOlOU_iTxy+?c$AkG7`wc+2T+e!6%zx4}_B^Ks@s=& zp0nfFraiWYz84__Qm!Y?48y2dbGDp!@53rx#Dz)iBkXrs@zAgJnZmZs>7bO8-K9bK z8Lrc{z8M;_oamwYofoELTXC@YL&XRo$h2BcrEnL1d>6gQZ(c`C%Y`jKaDzDWcJb=O z%4T6`?Mk*ZHUwtFdwl2!>3g+h*TgV`@b5P&vN;m)%Ut>R`{B-bonOowC$I7~BD3L^ z(nYa{5i^m2!)S6L%ykT2SrT0&n?^+1xQ`@;5Vel^)lri7$Quu*CQC$a;#xV6+k<%> zeCYRFfUVQoukO zDX2eGTP^Ak@Zm)8GV#88=Kn35Vs}Q@ZSMJY9T@MgJL@}=T^3D;*FL%XK*S&59kz5Y z$pg>-ZpWwiH}@slGQS>l51yK~LO`N8R>$Q~vxFzm8qyKHm06Cv<>Y9>6toLpT~@{0 zaQKzAncm^(AahpJZ<2NOMwQMy>{*@zy!BHtSkEzCPik!11Rp|SQ z9M(qL{9uWeG3(TB{%;%kd!{4>v=0y8-+Q!>Qta)R|2_9yU`p4^Tv5$r_%Jqdb@Jf5 zu}itNMa-#92LJda-ORHXFIba{mUMYo>3esxniLbY(6DdwLS&xJJUnooMT|(^Z zRQ$MTVEyVhwiL!hA_jIM3dU~v$+6)L!wIb5Gu;1`q`HJ;85Vu>`aze~2TJq^hUs0T6p2gSZKrTc8nxec%t#{&%Kf-Gssct9#nLxD&fi`rbfcLe zkbK3jQo3&MxS?qBj>ZK4z(%>PfSBxbTMLvc_pRzU^~bkX_DFIH#EiB=!N@5LFMcqt zo%yFl?o`i{kyt^>a@>jDv1`SjA9m!Di|XN{G8H}ZmAD^^IaAQQ+{3CaE;0{W#?`0X zacke=a1~B_H-TC_uB7#2G5&t=KN?Dtq{V7X9}agb4eV|jZ56;9<1)XbIq{7AG0uvy zVD4Tgl>v&G`@zG~Rq`F(k&BftTgA6TaWbmyv%CZ4!FD$9 znT->%0`Y;CyrGPK`qvu)pg#`EUI$8fd1L67^Ss_Lm}Wp);WcCH;EuaAn;63H9O%_- zUg?orUIMSejjh?>vSnpH@C__2YP0sQ2CvOM7b+WT0iATN9c<3gi{PQ5(BjnC4XYgy z!JYQ}0~fC`HQq!uzM@`uu()2;g{15?m4pQIH>UhwA6)nm=>{o$I66)p=d=Cwz6v7edlE_4f87CHb8HMfkzXQ7J_ z|LqHX`lsau_bb+6IL`{fjuvYub$!nex-drx%Sy3uJ1+ z)li%Z??R7bf`83L%lUYw;RYx`4}61-6#M^0;^3a>oX;z-Z__~nLgD$s#4-P{Zc)F4 z>xgXMy@>1xys7Zv#t1ba!wNlQ-4ED z{(7h99^aRHTDJDV=t(-Zl-xvTNkd)DHh05ITNG)~7h;}hkW;3y0kFaAGdp7x5mfT7 zw|vArRqePl=bIXM$B$X1c_l2+@48lj?3dG$16o4*;MHEUb7=N5U#VXd_mZ z2Jv%FGwBOk&f>3Zi=;=bZHUmcv0z=qW%exrwBq3J3pB(>xjIKr4QyaOh&p|OuH^G; zbuTXT)Lq=h(fzE82c=_VAxmZdtbuaZ5!5*5oL3@`l;rr?~PEjhWpg)AGFM zS}%Gtn#`S)W_%HGYyJ=|^gx`$lZ^C10Lj*_Z-jb9P7w@C-x-$72!R&Wjpaxz;IJ%Q zLLN387=ENtAur)a)mkrdzD0)pLIP{Pc z^HN6MeSC8!9_WI3Q~>5^L8cp`zZz%I34kPqB1g~h<8EO?0tKI;&r3~BwV7xMYxFfZAb7T%mx?kLu{5aArk z@!}t8c6~}KCRnkiFl`R*uO@j#_?ElEn&hqbF=?!`;@NxW#)$>}z_{oGFF!EBEz{_? zbKyOwH|H^SH=3Z1RFt%3_z$tN8;eqSkyY>jaEZ67>44FGP-)&Uq6%)-&+Xp|# zM3+}Z8FjZJxfH8~X16`8+~S2{kqsjA*_XNv3gx;DlA>{wD_GyxKPboj0ea=X{u8Ko z!-uvYbShd2p@7EsBJP6bz zZg?8lKdD#VXRJ~;p`#qxKj>jC1dAn%An=-rYkWcxP7sNZ!fa@ zaCrLX?{FiROGKnx`avouCvlmo($3^6%fL_b`}03m>I079VPb5ET zNsg|%3uj^!Z6?j1d-&gE!2P=LO0nma22yqH`e_*za3rwx4!iy-NRI064MWl$5rSRY zihX&oKLv4b(I{YU7FV6EhfB1B%*eDlPE;W9s`NV6x5!}iaFU?4C6KQ@?NblNhg-6+ zw$OJ>uqAw4;%1ZBwM^>c;517{zDJY{0EyhPf#fw7HImZzLE?lsvI13DfYPevdUAB- zrElkrm_T2vZ|E)1l=MLkbU<#YQzrZ9zL#J{D3WbFH&xqyQEup_XTo9pV|Cgt^*~n2 zC*6xgd{C_Zb(aw{)w$u(Ub_7D!zUe?NqvdX`LrLd>9oJ?^wbQY9F(JoqL?C8yE)^H zw;KYr7w8j+U{8FDGLXS>5fQucZDGycWxS=9>n8%Jv54Vq?!gR#X!+mUrC&!36JMwj@lH#p-p)3xbgvhz`lAIg4080Q;$5y`YQ=GK~PWUL*p04GwBK)E8Q%rYo zdB|(WTXl5;=C$|b?TGk>nwXdOcW*wz&_zfGsS}sb#;G-zW@yL7qSiGt|d~da5$~6(GF+utk3<1lo5kDs>%bXm1 z#K+<(W5bpVF6vG5VcqUQ9-l@AgUx)r9LIIJG(WP=ZjL>Kh9TD0mjBVu)R!GWo}S*` z707A(%jiC#RA5y9nfH%AN4?0d4l$2Lwh4nl-QgY9(!@Ix9iFM}UAX30;VZr)06SFr z>@YI!kp&u=MyKBv_GH~^H=P(|o4hh4t=b;?z+Rs_hWYL>(qna3C{K!UJYUumar)cG zvi^@(MkxY6I`6nprL3lAj4FOR*QMY8#fGocsU~Cn>w`F=R>*5JcxgQyxX4{{+^^!S zM@VqI0Z;84Pc#RdnigrG!c~> z#w?)tA;VitaP|phl$3B>FaFloyh7i7$8SzktK-vpXo`LBSg0KlN0s4}w|n6u9kKeZ ze3wq>-fYJ8r{oT7(EZV2ePM7Cq-p0ex8q>~8V^OkG^8YS0Fdz(WPC4?F=_v?uOYYo z{Aa4GvA@c4uWN5wq4VEWh9gI3;;q;>_a7YNB*cH38>_U2@Hjq{usUENkEC1`*)Gpa zDbkN@^ZM?W*1G>X${Mnn5P_ulX7*IxDco`n?GAyuG3H)rQ-j?-vT)_E;(*%fd+EUx zx;CixV>ruo5Yn#GP-Jl|n1eQodv8AhqssC^vKVb-VPj8(QKHqu#&hR@lG0d_Kw)Q~ zw{1O7_6Dc4qvm1!C+2ucj(xQ)i;{Z&jB?_r%j;z>U7e5_23gI7DRSMZZ$CfipZ`5QjLcq@8(v0l zQS{?r2TWz{zh$`m(C@ zZ^03urs-SFR0aG)nqnEC+|hk!7U{_`0biGQ>>&Ic-d;(QOqw50k)_2D@a9otXUnDB zk%5^vD`sT;K5l7-S4JGaR{$!zUnd#RJ+J3&qP(C{g}~BwUs%pz_U5ys1+U@p^j5v2K+RcEZ?3_Hx{k>p7Ga$ysi~aFm6?JwVVzp}Ss$^e^mjk8UJ1P0M`tHHHNr~x_@OFx z;es!13A{=zBttuVs&D>vcYuz=>|4aw)`9$5xUK6V4@U>51Vr(3*%1=HPt$N9$z&Wk&n#&FkwdmqOX0_ZGdI=eQm_PHXi)zKS}JY!R0{?0PidgQq%eIh8} zKvZB!D3KPOyqeDnwFRYDt}LkcPS%s`USVoAQUG!5F1?v}F{yn~)2H47d^=$hm)7o} z#<2~On^{dydGJ0TAlm^g2@{0hcu*aH(%m1NZ$d@UJjowMWn+NPI1fO}z+EwCE=P*M zb6XQHuJmMm1P5+-uOx*GA6CY|9_@MU8Jl;l?N~mwK&&F3>`Xoxm8lVm-DSAE8|b6ks=Y+ct6{60B7pBuP& z(6L$-xOvd?F11q=xE^+_{sLSNd*0o)KV6SHRyzULqn>x#txwnEj@3cH^|NHwUkJoY>tEDT9uST%iQ@gO*4Uq(z%kZStYZ& z>UiU3d7Ua7zft}0X1Mq)Kb!ccRs|Xb@BfDJq)}S*~=hK z{xt&55CQmFlNw!52e?QFxG2;#BjOw3exi{|+sxTqEd^fQ;hBYjm&aK=>_@>9hdy!X zTorGe4{!-K8~r~7c-}wF!GE9D=AGhjtwl2eJiHMg&$COP@N|vL&egkK_L)RpcG?k6 zd3&@~O_|)r*itqZ;FUH%HVN9Q6Qmsg5{{-z*jD)lxIIniR@` z04o3ck=OtGn%fs5fI)G1BJuKtM3*Yy2LQ+4+IcoR`u;qT`Oh70=Py5K27XX)oa=T@ zzH@x{W389q2S5@q)e=u6>H;LDzFhbHcP&mXji{wG16*uSaR-Aqw9NE~>zjxfnpp*8Zznrs$J|dzQyL_tE-1&nzWtl^cIJ&70}WI@sH1(T$aWk~;&uLJVX0)?W2) zmtp`pTU=7>eu)o<=R8)ryII+|Kp&ARwAtg{Ldramtsq7H@e;f(+r00xA;|Sys4Xyt zoz;}&bGvTT?5#e~0>QybEpF4^^M=s06MR_zyGeE#drj?tMTX(Mani0=`VGO<{bJ9A z$Ikxded>@*d}w#!H~b7|y_oC|eVr2Jppvv4qu=B*z$O$9nSs7UW*BPmY?l!myLh&s zX0#kiGwF_)k8$#2jLnJI#PVetv{7osgXXa#=KqC1_74hIk>UIVr^;8ewn%a0u^syG zdl;MYJq;JltO|41WsYcFh8odTR+uijI>-s!Hh$PVOlpu=KiIi->Y*x`6EC=N)SDRO zvVk<8%>5tRqE_$b%&UMs80It-lfgrJlOblGR1~;!M@kL{t$p+|a2K(;th04%GH`zL z-_#zFx5|&z=HK35UtEmL)9!FyJgW8=G%m^Xf2=WtrO5i}e%Uv18)|W}Wpeg~>?B8h z#Iu3V+rbcfV)PT*T6x%O$u|H5LiY6PchZdUH%zLC?Vz+Ur@W)6tBsoFEC}#6dN|kh z_U69V)n;1l>%G4O3zZr}v)BO2h{71Y^dharV zPiC15q8n2KinVZnniHO>*bC1O8IguN``;yfvRAXN{3-G3Wo;7N&GPW2KX;8`e$`;X zufS&GZ){%1FP)Hdm0R_8o#hv3&2ucdefTrSAa@(w=p{=_Xmj(IJ_^`vF!^4N*tqRY z0Ywh}#ho?N5BWbmA0C5xgC5F@HnLCo@o?Ou=t58(S?O^m#6Ray6)!OJaMh%4>qhO9 zxsjljtmh8-Pe0}j9%jxSUilw+ZX4;8v`sk7^09tMAUjvqyU+i?ojolX#UQYx(#u?fW3 z!iY9`!HHE$>7wWY9d9n)TU#^2w^vL)?{B3!i6Qz(0WzLyn-s#XOhz4<2^jJs@Guog z`o}h;?)Y!G!8-x7wGgs&tWGKjA=8IP-L3@#U;sF&`86dK***janf+flq7; zkct-PqzunW&f1R^S4D3zn~xPQrFDH>X9j**HxJ+G+RuHuXw@9u5k8uMneRpus)-Q3*KLf z$w7g{Fp@e#WG;k~vO##un<`}WoBhjz|+Tc(qx9$z0u{c zYzeM|XJ&p`(j1B~t5?}K!e9X^WZ-(!gDa&KhNtu3)ov1iG8ZE| zV(xy+=_rA*T+ipjg!hYRNfGKRLc`j9KVJDhJZv3bq77?TTpyYH+XjBe>1PrQgCi6@aYds(vj`k2 z!T3cS^T6;tH80qQB8266XSP!PRKV6FoC%D_I4~ZZuXvzdG!gA^rTgy=tI#+jBd_S4s7z^M;NP*#>W_Ar&T z!VwZ(QXpl+e#QGoLAj<`6Ds11Mc2RU8%ogrq*=X&eNjP@tdv=lF%!rUq7V+L5K^v$ zP(UF@xQqMpBBLgL)Tmy3EhSmI{-?r$Z47=r0uAVH#rig2mv9!R(#`Kyd4<#S&b@<4 zdk%G(vE@5GWqR;N?lWpGIO{>QYdTa?WT;8+43}{64#aCDpX=0`P(Fr#QTwCi5M1M7 zySva)bWfC`82wfE3uJ2j@ulUikDbUn+Jn96g$ZY`rl;^6sR0sz_-Ug;((`ripwUmA zs?))}$X8c*EwwLqW9T6F0R8=jF+9z4V{BUm(iA*C*>lXjjEKjBtt?1`s8z%w zphCg)+gR(NwWt996%dXpKmQsk;H z<67xj>W^d6-?8B+8{u19Y1||`s9w*s(&&v;}OHq~R=|cg;_v!B*89!GclRO1Np7_cstN)~VP-)Cydvw{@vJH?LE- zF;715r-q+XIYmadcdlO6+Se&`sKtna6F-^k-&!pm&0XRtbWm(V(OUe)<8lmMTX!lG z;A~EQcLg+^2!7jG1W9cVtaTcDrySf^g*OA4wc6S_{Xw&&V%B=qCvuEp3^Xk%^zb?T z^k+`hzkM+q8;*dt%0z4L|21x|#cWjCG^YS634tWgP`h??vHd|!KkPDQ&81Q3(qFx8 zi{E=T_r~TcDZx~9^(3l{)2Kmx%O*kN~dDOe`A;v_#- z8Y%A9(g)L<|8qQ^w?jiV%P^jF`NmK>nsS&$X|{Nl$~m?#V(YsP!>U6R7l^_Lu<@Q+ zeC~=FJBeKE+#7+DWAqzf{j{0O6=I$n!Dbb6s|)<1UZ?s+p8~A+in%ZxZ?E30Z zHFDwa4o^s^aY{FfVFGDpfXdifL}ofRDJ-rXN=-#sqKUkX-2KH27U0*adA}e@7g1hj z(`0i1mkog6@yOS8t=~J|yIy+0ukV7WoX9E+hwfa+p(;sXBjS&PF!v#iAyO*8y5FWd zLA5%^f2dr8)n(}JZldXTc)Z*OgE#kk8+jT98gD=uzp?pNczH@guinXacmN>yMl1Pq zLmZ-_TTgw7sgyN-S3>`*r^L~vX^0Vkdmq4hynx?C_r^ykUN#&q+p*2OJZniSf0#44 zI=C{^qdSIOfFd%-ytZ+Z`mwe`#7judzbt~Krw2zp@VpWrtgEn>%hY9Pp;Ga**ASX8Qsd{B9lV01+ap2U#|F=+0J^;R(Sf>ZSY!$%vvIm zPwqcJ`lcAo`(66@aCdaN*Fr;9nr&lF#N>NVw%fsV5411HR0&DHunh~QwUylYH5rfz zbnP*}Z@xaRnn7^Bvg9;xoIy7MypGqv-cwyu?l67gCTEXwFAZz5mt1grD6*gqQF|lz z9+7U^s*dj5dbIPwtCGNe+L|Ee00Jr1EH`~mvNAq?!B)ixPaijDdqZ`Cy5%k!NsgV{ z@Y5Uyu-rypsmg0__w^T&btXzlH?i&RInX(N zvMrAEV|pAr^Tig;=9R4;b9JTIoKw|c4rwy)oIc+@hHqN|kdC$?x+A8PN)PtYXi;!L z+Ot1?r)|~cu6!zslOsQ8>2@6&>#nnP2;_6??6VB-O5lqqxbw%K?61wACLfP-jG&?7 zQ2p|i79St?2ioe|Lw^20PVOsKwRF~h^Q7(N0h_eo(KNryVoXwN>bf9;+nA1AE^58= zXDd!}Vnkmz|pjM~tKT)n?=AH(lxzF6G0V z8%LHis+wNvg6!>EExo~I1f(T2hY;T zIz^OeGp1iM((n^r{a!sqnn+x(j1lm0@cwkx_Dmlgp|_Ga3Xqta(F-%nM$a%Rph z-;;=o!M-HC2xrZOX2QeMCp_o}X|Fh5-0YIP>?a>0v-zAR{$O3Cb3e$P`^G|VPkvd= z1uv{w7;{aZk<50l04E>Gu7Cy4T-->7r7ONk@)RVuy~>;H12TSSO}x4C?&^AQ-`~;J zDzr0jE1rTyq>F){{Dr572fGThL?FSNP3uAleZPLbgS<1;D(I{NDg1kkQ3AwRrkYkB z9LpH-P=7nbyPzcgXx)7>fnK>yMmSr`htpes&Yv{q$6ZIIYtmZ&6;8M9htp$2BX>5W z{UyBHEPp2C=ZEE$+^4^L;}AE8S_4Pchxw}<7^n^$a31WETfAv+pkri=UYQg1kn#9+ zzyvyj3Om-eMn!)Lx>nEUV7sbZjfY((h&ba8oR1{Sc!lWQr4NjyCa3>oO)qoLaOe{) znf7?s*SotBbpNA#Kh1WLJ3OxlnJS5Ug$r&!_T(7<{!`i;_2kaE#)~P0!t<_Vw<3ed zOzA3p33&^(yuCCG}s2T;>+X#?<0!`SRAG3ia3?L%#dX`Cl0a!0JbNrhrEH8#nV-p|l^=ZHU=v!H8)*W`N zwFxB4G{`K(Ku4+?3H*paEibu~HG9_VwRON|3vPbUf8-;PbPy#@8c{92X* zj^{@p0WP7pbisT6=~PSdFV4~KqJk?Q@F)UClQ}`l5^rS?mExCkXu|>MAloKDWf4}O z38N586{b)v{-1@aA7$Rimo(+a?XPlJh0)I!4HX3k2W;!avDhjUOJ1~*TP1c4T~AxV z=Wa)z#=r_gL^CgwXy;5hzxSzo_$|p7)FVKQwJ4`ar;#j#jNkh?Rj9HN3n!xc=bRiN z=HhEiWOf>czxZLFI|vY_V@}{#!Vrx`ge!p|>3JEF&#*nuLqgPJytn`DVN5r#7-Df0 zVG%1Z6)`ze!vphHOM#B#X}Z4ChlGnOiF~I1IAFMn*RLe0$CG=lM*F&0d!`ffDs;6q zocXAaNx@-H+LM;|vpQavOyU&|zULx!#a#S#UBSESx}uk@5bv-3ZHBfwcp!#fds-w8 zAhhX*+vs-Gzs*rp$e?ID%(=!|BOC90(_KGo*?_ltG~H3p>u&?hYmisK3H|#fKP|oo zI(;>YYb?FswMAeb8lmoS>Dr>S6`79!=4xG{9i2gawv=#HvH@a4Eqr~MxR;2vRnCy% zBxa*5I!*;?{g4)7Z(|u2nMLYK;F`LN9$z>%f?;)~oA5@8$R>rARmecYTDp zdnmo8t@3(JTNN;`7C;i)6S8gV)ZhkU8{xQi$QS0i46e-zvh9WT<7FvdMku+=ASwh; z2Qe(sVvV(CZTRaWq~jpGx7e4caBU>5@a6;8)x{^U*MLl|r9R8l@!K`+LaWWOV5rqm zmfoOW^(6BjD`2i?Alg!1AsyF7Gek-$|59gFwODH|sl~W9U$a5=WQlz#RD=@G6qQ~kmQWPgqm=lZA;Flt73^IyI~d9FJl9FGA0(gf@^(sAiD z$7w$Q@rd1$rp-0=Z3vS?w+ZW~S8>|VTjrNk?`OrE_$XzwbnYu!*avlIw7%Q357vt} zreS?(ta5RAQW0(v)xwP)unf%@TYw;J{VNCx){T4`0>0e-_J=Ga!i~j>M-iDzNR#gi z#xS;ya^GW@d;|veo4o@<#JU3A;Bt9@{T1w%NO%bHEnN1J*9=NdLYSbf22v6tED##L zihCK`K`*%XiC3?l0IY`^;l^;Rzar)bQCi`bfzu0;iGAG((^v%u-2^(tb{07X#(7m! z)*gGjLlMBPlX%LvtD2PBFALcP`j;Xk)-pC-N`z@t;=30#P>~KcG+`*95if~MW13<4 z6`fXynBWzh%PCTo^fTF^NBJ6<2Dsy$y`L0U@bKwUx-?OyK2`1t6VkbpXgsM|V5md= zG0_WpHp)j_4A|ZvVF6L41{+X~B7sduqfryXcAAfh^~Jei5>CC=*d=&M+dbN=Y3O&d z{QFzH>-$n|d5+cu$wY}f$he}hT+BFgGF_rr`0VLjLIb?q6c^u8%EC|Et)JA}X7yzi zzEJHyub17$*VE7unMIS+vh2IcF7A(|ypKgjkt*}M-k0YZ*0&3w+nvmy0< z#n5ys)_7}%Ic*|kgpTnp^xG@bbwrH$rODwn@`V1jGEpOa5bTt{DoW?#cwj#g{Q+S6zcPT4p;%ijM9HdGa`} zFzOT4>NqYip?~)$r0=nR_}_IyO0iFc!@NQ!k=yDJff+9Rz~*}e`$}DLEjL=Yzzs99 zmgSFl=exA48{3sx>K#}yc+*c^T;_Z$?sloZdYOuLek(fT z+FP}r^O`h7zRtKmeDwhM$Njm7O*l;JON?cGPbgF#7pR1hcS;ftx2-bh<$IM&Uh?yo z3|WA}*?S`33p^!^hqah-t6U0F4Fe%$cIi$m98DoVY`E=$m?)d&Jo4e4(~lxUGlACW zDdX`euYk3c#o0i)+5ApPMx4Zz0B<-*=?#FGq%b|Lt=0aNS2f|5pK=xJAJEvdEFY+s z?_zzrYUVEtS2UvLuit=JAw9l|$G&wRfl;bMnYY1>aX6L^1FV?nq8&-4l~48 z?hvvoiZSzqx8bMZYtd-dukvTHze|1Bm}D9lp&YUg3Rg^~RU_U!ng99hLx_qixB{xg z5wNM9hm+#{MOjdc;V2>_*{%pk^6W4{kEWPM!0Uav#zjyu+fJIZPZ46*UFnc)W`)G zv>vM;CZ^ukPLH#73`7v>p6dV#yv?bian{-l=3OYZ>3+UElgguW*~Kt+j)67B{0s=I zl5#N(i+s@@>d&)Gjv9*9UGSMp)rInWwbUj^!Kv|}#>_)^WD=3CiyRHz@Tjk~D=~Yq!+5@@*E^Nnr^`{%EzDP#PTfg?y{Z_+@nqLK5LZ2^Eh6C9TxWeJs z9SeZPdJDU)@`v-+t$%It`{T)el4-t>V1q*y(TdB+-i1RL3$g+@E!P+gUe0Q!j}bi! z={y?EWE%L-%LvCJK=V}r1=)Cn8p6z1KtDaTvXa0qq1R{z^plCGhBgS<`1qWrB>X%D zF~`74ri7o^daKeoE>RbMZTh21ppEv~A&$}kG;gVk8>2<3(Ym{eR<*4ha+U4;R_o;R zqS36hC1jGp(wmmja6Kn0miua?;JQZ%f1HwXK?6ytYCJkD zVi%KY%+O-CIGSbzFsVS9)2@k@dl-v50d1tW>S!-hv0A{zKthn^NKd(&_ z{~%HVn_`mqo+U`~BU;XL8S9MyfI3iXOy;v-aN3|_(>v5zF@(eMDTU(O^5f7iOzzxn zz$B8RZ_Ng1R~zby?z*(Cw&&KeETAIU)gaB+<50J&J~DI+jM-aU2r#0CL53&7uY^z? zOc~L+*(>%PZ=OrUh>9}F>j|*sI9fQZkH4y^1 zMNcAYm}Bq=;KQc*&!S)Zqatd164~3+Ow9mSfmBoB){w;6hlIVuqW0CPvca_+jbY`D z4hlO>**Jb!=oOIH*5ZS5xh4wR7U}2#{ATRu&Pe{D8ITNcR?ynlbZI(%t8RBWgUcXX4)TOTw&*kn=P=A`N? zIP!HY85>-yA*u6DNKN%)V*-3_5R2NhR(t1Uj25;NO6@4bJSsOQPpjnxXwo5@H4#5l z{E&4=+$2SncyKg)lq2<KY)P8HMD>^Vpkg>WuoJR22762ij)nk4_?lksg$gs==86GBdf zt5~G>)~bM-<38>m=fpAq%|g!ILRGv72V~vyQHl}F!fRB>IbdiEo`(ji0@gqsh_b3l zeF?3=A0arRYm8|e*Js(UYgeME?-rh>KK$6CI%_IIzuj2!+}wM_OxXLLu3qwjVOMkxZ~TY zgV1hrp-QSDd&G{2lqm?_jz59rwGIjMPUQ6P0@yiz>@93~^8TemTl8n5=~zYkoes$J7pBL8>_>uXIA=WEl?cnSpnzxbQQuC{VNuS~0Lh zwP(*v2ouVL0~W;$z`6Fzq9}#ce&(Fn(n>Dsm8Gs!6CWOW-;BFNo`D76s6?^(mtM@n zCd@7Tt`8__WG{y6sI_d-dv;LFN`BR@P}?Auh4R4ZaoWDJQI}Q5;V~6*q{W`RF8=}Lg(d)T|s{dEf z|2ovs-%bz41d;>5whlkH1lwDZphW{eNP0f0hI9u=(QS=}`zEv{Z+hE*RK9h9CnTWq zUlANYZ;SXX0xVj;Om01_^$Uv)rJQLj5S1_yrp>80266%WLajRviL`^5^Wn*@=%>Al*5Kr3CUU5gCi7bVur)WnQ@1i|A(4SgD4M}}|M8%~ z;XtlwI7ViVwYbt>K;5VMC&9yK52Hkq?G` z2h0NE%lXHF9(MRJbg1T^@Olo4o=>bMO~M}q+i;>v8=k(|KjB68CaRV(V#0)Y=SWNe z-J7}f90-qBWo|tM!W@AK&8;^~p$Q(w!Zvx5*iCefZne+&41U%SnCq=}QwgYhZt4rb z$d~!WmS-D0r7`iP6?!&?0hpgAg8P2)A6$f2R?8BJigwgG#_X;Qe3QXa`Z^g{=;;x% z6DD#8)rHlc2^=EWHih>5pB=9*FfzW`m-0R7T2@~?ieb@(6svh+8v0e4ye2X7{TY`H z+`Tl^R%q>$v4cfg?b4>z-qMZ9rU(|>nhx{H_}dVe+zwq&@j|$*nHNR~eIg*pa}H*5 zsP<;_7yseg&WzuPzR^*!&vx%zf&*X&^RUQ=$}5$hh$lh*)+9$reb^jlB~4W^gCub@ zN#yg}2FHC8ZsextnveTN^AfQb zbe~`X;|9moR{?=CZzN6ggs|y!p=DC1<_4xncn(cqM#*lSUVnh9fW4bQ& z)67^)J3P;2KXZ>zc{P@5VWy0bEG(-bR{;4qZBCz*h=$3Bq~t zmEIUCEIj#23&Jp@y+C(GoM&As5*CE>tV^jsmt zh3CyQsZ`9woT{NUOmYKw9IU^=ZeTfBdsP z#Z;Ravp`mRG8HKJCBqrfS;?Vk(VqaQBE~qXiqe`rs>)L0*$NV=(B_n^!kc}M1FRtR zlNF3mdzj3i0>m+&H%id`Y^BwKuhGHUKf35+&G6}0qpyMoiy=d7jd6m27idt0E39f@ zzt6#K`wx#K7)eh&);{xS@PBwr`d=O?LAgx0bW8w`h_Mc@qDVi{eOxJr1_qAuWd^%8 zUl1lC+cK0SWLQc-ER)in(YudWNjlGBX~1$AKhn9WSM!5YIR{yx3^I=0<#ndzGn>9u z;->7rReu%#!)9iQ{-!A+z$T(XgsS&kR)5O-zMp|{UGsb~I>v*F@cO9n7qUHHKIkCD zYlgp7m=F6IqQGq}GAd)7`|QieiX;HOj561=FQfUdFC&uhKfX-N)_oiubQvrV+!=98 zz~IvL#%u-f7~Kfh}bY`!ZqS40Ors;2r^#rO%-syLcje}7tOY4Biw&50`CZ; zmRhOJpsPo{&9K6Cv} z%P1HTyhtu39%UHGvxBz8C=IM5H+LwR`G^B6J{vfJ*ZSLcqN>^L85vY4HK_6S%BBco z*vG+1Pxjyhj3sz z=(a-&OM;35w2CnJL6ImR*}(Smb7s)U#^hV+N>v@6`d$`=@U6-61KYjX&fFKv+sM|B z?W@HCb@LPxtWN^+Eb}bS_yf5>5(7XQm$e$sX|#czxno}&90hr*)^XD^Am2UZlNlm= z11cN^5mZV3vwg?7+Z!jO z#2bH@+6p(@uT=^(KxTTM0+7C}0)7kO7P zl`uYhq~9^ZzUBD}d@+macJk zcMAk}cMTF8g1fuBLxA9x;4VQD+}(q_1$Pea?)-;v-@E_IM-@e#Q}mwQ(>>j*SI?fk z2$-nInP6s?(!ac=6~>D4h5FRmw_}Zex`og+AZa$3)c%y00|FaSHjsOjwq;pi{ttQq z<^np+Rqtx!31BYx&_^S9n7u>8q`BB0nJ8_*2E?CqNv(+Ev4DOy#6-12`_aen^rPXo z64@VuE@@~HfB=?wbj~U1`!7kRK6+)c;vxC=xE4mT8EoP*1|4__q~;u7#V}>Esy;X8 zB`!_xXMihV#S&JSP0E#o_N@M>tUf*oi@I6$d+n}qDuc0=eA`Jnz!#%V^vREd?5ccWkww|tGJzA zLC#EfVlnQu_``n8XYSCbDN1<}0&2Fy9WD(#$9%@2uA ztnh(7>QzfWL=$;M{z2aZEXj}o|A_&lL%m)GYyEqSiW41Cc%)XLdS%}%CKb2Vw2P{! z@xA45#&5*|sV2m4h%9>{+mt`~P{B#DCwtqu$gV$NbdSB*PmODw+i4&SOoyr10L2mb z%!g%tg7Pk8$8JkEadz345E zhow5nGNng;7-@DW=imAkz;5M4vE1NEDJ)6WuX`c=Pb-03CGUnIgK z5NN5?25X`1a zjI=7Q5`=lP;YJnx79hL{%;d}p;H5>(8_M8!*k8-@_DJdY$^p>a0FW&N00kCem)-ngChgDY(rv1t7 z@}Dx2t3mm34wq>K=(4CGWrIQ4D;a7h|*JN}wMHM5Yo< z{u7NfgBXC($OK6w>8Oe;)bHPDr1Mual1jQkYl@u1GB>!`WyzA&oB$AD8js@uo6QH~ z0H2(px3a?7Ba0pQ;(&LtAz#mg0otE?l z`| z2?pLDsypk|zYdt={RXWFOuM~PcKPFA=x zm$*4QB{5kwO+AKK152)+5==mJ!b^aF^>Ln$Ng-HpC~VYSf#j9<2nrH>O*U9vSx4u5 zFrojN*Y7X$4rC!KJtMpp$=|ldxUrc|BLQRO2d6u;U0HAG^^WxoeRWcE>N8+G11)>& z^omy*9yM;AD1eyD^wz1Kli2jmiBWSbje0Uzc-CnA;X|@^urRCTNRT3qvn*6;j6qRn zwh86spJFk4fyo@WhH;z~DGbIddy#o(G(>mRkP;qdIQ6m!?KbyvwGNOQlY zRME6TSQ^J&W5;;#Ebcer?Q6%bqenBjsD6!37qkWQr+>PI$N>|LZNt3CuP;hKVT=O1 zpfk8Uzz_$=c`d5jk-&}%)1UKz zv2o~`n*MZzBcrXZOLhqfvs(Z8%L9_bPqahpMG>x#P=Fq>FZ2CG-ZBoFi2h4=m;7p0y8#_t(t8NxnjSh%-`t&m6hhx z0#2Gv1sYd5hc(;Q)nVq-_B72m5v*Bn1ar|K|9_A+<}1=JaY~Rv)Bv8&XF!3_s7*xv zxr4x<-<6s$sO4XGCjDP`b~5hgEe#@l_ZgUHxxQ#q%xZPUUL3}N>eGq39xxfJ;rvsb zh}LO|d_{!`#|O@YC~zhaxc~H?zR)2wzRm>Gzm0`Z(wjj0ArI7(Rb{E7k1iH?VVp6X z-J%e%oPj}E098Y#6@O-x!61)6u+uvML~pa>dRv}j*LQ8^V|vaY-~(0Yk)6QMNA zQx1Z=9v4zD6%}7O1-qy!tlcrF{%JXaAjl^I(5ML53sdYxQo~@ZcIYo0luO@I1SLPBkg3?lTtjj7Fc%FZAlq< zjNQ(>6N>^-=?IZyQl%DaNFE)jYYZSBlv_vJJI5&nhaZw#Pw4&h0~fBcsWt@GeEEXMecw;z&Qyx#5N3H-4K9eIrzWz)hX9s$b-+e@D%5*%8mh|D$zD|_oW}; zF}z?gZ)OXo1^fALq&7IxScA`f)Lw!o< zlaR;HenZP0uV@*Ujcm68*O`ttTn$e--;nCpAROUAeYHmJX0F`lXrlyTR{;l1*ODW> z_nrBN$w0vPd1%GUOvv6ib-RQ18rjVELp1q6#kNpa0MM!|K&v8ICnX9i{A*RNzpaY2 zB*o2?tpMZ^1_DwnY}lb!esl-81%bb@2u}LVp5#OUc5jtq2QVXp|H;T*0m0y}s1XB6 z`Xr0b60NP>gR?@H)bnIEu@J|k+w++G?65o6^9WBswxjpxUmWeeDMMmZh;wJBq zDWWYZ>-E2VqJG~hRNw^beq%81l7`VEjVUps1jYRdgk>FOO z6qvviU+JFDPEusumFgHRTF{UuaByz`QM@zzD<}{kLa@UDArvGKLSei?C^#&PR|uu7 zVBfe3JZ9RtF$rI|(-S_EAMOu&%3c#!sIVr`wU9|@%0;22#aN=&U!I|ADEgMYwkyGL z&a{yXVRezzXiE(XWSi0WCU+2C+2*l#K(@IL^}r|s$TpKin~8B-xoiBvO6z3S4ZvvQ z4vaS4u0QaC>i>;4i2oaHs*SswsqxEVS@>Nz(xs(vD|)KdTY0SA<>#2*ND%xLqY>bH z5dVN)M4(0-ZyMoaas1I}?q7`zx;?uy`0@W}RIx5TS7D9*UyV3gl-F8{=j|2yD%Ruu zZ2LWa?Ww#%+!!vW5g^26E;dNEdxf~xT(1yUzxzkv7S;NHsB_>Le3GaB++AOel-ObH z{>_m1e`m-qH%c6D8Pd3$yP(gXJ`wR`)}Z^L>&x3Jnm-k=f_mNd!SxGrIJoNzaQ_zm zpM&Xx5#jO6$fF*qts9o?fP0ObmWHA#3|ei*G7w!Gpw?eo77>xKI)(Uksa6+5P8%H_c-IHQz#vu{e8-=sXlT)evH#G}j;tI_Gg^ zM{&2`nv9HHfxuXy1dJ6#)=8Pd`v1lX_y0duyu4hO)pFYyFZu$HC*|GgPWjvi9qQ&+ z`tF3P$kCoyI=iaKb)NR`t>Wd2p$m5qdqlJf&A7{n2s9Y!W+_w4vEMI+2TX)_2ZwgM zwx0ItS1qZLSFoUk$fJv#m^yInp@(-r#~coDcPrX(aY>703K9w8epU+Yt|pg6R-#N~ zOow;bxE;SWMl$FoQ)bo zC$u^L=(pb+yxZ%lc=jLtCZkp<*w#jx94009dcEwS&SpDVtdm||JPFS-nhyml?k~{~ zqKWQ~LTbVoY2S;Pdc=BYv&dnlNW~zAS7H>fQukgP8}bF^n44Qohm{zn+ajA2!}QVg znnECbY#I-!69>)NMkP{Zj-F=8;M)Qz5f-Xp2iunT6e<7Fss~2~$U-L-;YcJ1h#Zq) z8d1g=9;)}?cp9hY+^92iq=^8HIO+>(l%o;})UfAG!=5>sHw_K{)eys|v1&q_`HzM) zy}?wyuKEAfP$_bia(Z^tQtaVEH;YZ@VFIs5^pq= zLlE(cWV|aP-ss&s_#BEj$3sOT?(6=+$~S!+>2M$efR5N11%m@$N&sKpJy@wYmJ7c; zSg9I4VjOjD0hqgN$x$~yxTMqK#(IwgDXLXi=z;H8qGR67oJ?0E7?2Q0K#L5?6mRrR zAcx@KrQeNr@`n1r+DDk9|J$U|U4k^b+Q(AE3F~mzA)6U_i(acI*X6QUyD-e=Iv?(mA8S)LW8v?H5dp+`>n;;4^*N zGv*??N_s2@1b!!KpB-hKwxdIuA2>Ux_ay0B(}t)_F57;R{K1EMPLQWH|AWiU0y$^{ z1&O!6C%;r!lEGS#@Luz&FF;OP+`vz9>^O~!1D@BVo!PK0wX=K^bSVw zHI54M+iaj<+4N8lnIvlI%kL#jW92d@Y$y@V`y)k&0GqL+F+-%ajW#2so!*dm^SnsZ zKS_pAP$=UZ5tu0BM(vU~Yhz00P0VH%B;;NQ&VI74YD_g zVe}83WagvoW}3s)I-}`?)5KUBaxjfX+F0D0t`X z<62l>#5Q5Zz=Mr`6NNj z(>f{Np6}c0wNKhhmI7n6kLro15Hr3b=WVqWm*8oRZ7jww(ry@HoaOX<$ynO$#CcS% z_SxrsZl2Z@RoJ{Im*_`FH_^1bZ10aEJUOUo#~$^L{d6p6SDwutPQQ!QnpIYwboczW zKR(T$sVc9w<&7vRcqo-SW{*13hnbLcPZZ89C4fL|b|jM6=b~_NlY$g(1*9KyLyRJk znxAXYA%dNm3BZgOrwhy7;C!C2-yPwXn_FToekrV;BI>*-zkxY3lj8!h0l)JRw?E8v zGxv;3P0eCrw!;iP;bfkQ=kgmITbjx4BfSDX+meJz*~sr(|L)8Cdw69gyz{2GGPo)$ zm|h0Y9{w>X^m%<>4kfWkvX0v=*{?zn#M|JV_R0%HpGjCMeNY|&4Z`d8?<&lkUl6zM=QWnCPWcq0t;k4rP-fjNXU;vdgmMux+5L)3dniV}y|G+Wjw{kp z;U&(8n54a8;B{MKzm{SkP@F_z@(Rs!*QLyCuIMp8w>WHl=E*?Ty=WWYP4=$Zyna|Q zT=t>efE3LFoFhLS=)YT^L&rDokvo~N|J8i(HSD^JlCBEkme^74-kL3}Xih%(w!ne@ zA^(vRI~{N|*wXAjwaQSQnLqKQu(owV`^gj@G;BZP!-hdKfxRcU&Zr1N`Zc2A!|kPn zxA%Rg;=W?rA#Puw_Ay*PzwS2mPdzo+qUU5+}piJT(YiGNi5gv_gO@ zD6tD+{|LjHv{-IVNw_z1(kbE>it2Z1+2Ay%(-hv8)H>d%dQUB%Rx3goxj4x$Xaokn zPT#j)&UkrMy2{TCd0r9W>66#lj-8#V{Y!_pJmXwHPZl9}Fm8$s#>_BVCycofiSI-0)Wcd6U&1#hr-x7M-svNG z(IdA+u#Zn^Dij3!lfSQfB(ZsDk!6inIIv(sY&+ZYoIXLk&&!+}YLsJn5zGE{OLxna zTC^kT5cy2#^5V8z!VL(KGGe-~L9O88!u02e)JO*(B$}VqKh z^l3nBS_nK7eQ0~dJqxZ$ai>_%MC$Lbb()UYq-nG880A>VRifsS!9O>sF5=II4jRmTkcggCl4|-M1W?-qla-DxNxp~TA;r_H;pAX ze|-<1(zi*`jIs9-d)lC#lvjFpl;`uYTuhorB&h zeqN4_&RvMk&{AmU;9^St`eJZ}er$vOiH!lc~>dPCKQgHwajd)&1@ERqk-5RSjN!oBaOjpjV=#t zIMiT>?mR6y2@(&&`sDc3tHU_V3(9NEW5geqSv1wRh(W6d>YH1o+qkvK6fBO_J=)^= zjx2#hrVc3!;`*WYsYbvWuo?f9nIB{GZ4WgQ+K3uN&XY&(0h!sBOlj@gvI$OPQrL*u z(qiYn*5l3+gE+Qx}?QlT47)VgOma6dI8W~>1M)gB+yZVaxwW&C}q@#I<2 z&b1$2h=?))eSwI)T4o121>6b+!6wRa6>)G?FQ~VV?5aY!-0>)~;xo%q!}~ljq&`d% z`p=Qv&S=@(Hi(}=qwIz&JU>RF9SVvHpp1R#LF^I28_+ZsmEv!R!->94R-rMEWoEd{ z8$`81Mzi8jp7QumIsO|axDHRChGq6kyvsfOV6lNm60Ir1QU&YyZxXDgBUuYXs|Pj3 zS_8wrDfv7Bo#m?AuL(LZAj^Uah}B)LG$hg_g{JNSb;5Mci!cGB&JB+=s)@sZfMiS!KgH>ucwO( z0EupV^u(WKVrTUIR@wTm`|qh4J<>I*%a3 zqAn5RRm{bv?eajt{P}?hN|6r}!`;mn%j*duK>PKY-20U|M%S|%PnHZpN4}3D6;5hH zdwImXSpT|NKot0Xi&bi zbJ*dl@i7|D*n;rAn@?ScL46Ayu!uyE0olP&0;t%vhX0Sl6B8w_}h zsB?PC#W_BDCBi%J8koXM&XX+`s!NyWORM_Zb;5bgwSJ~gd>_{4_CFTT0fXgQ!$-e- z7jMxizhA{EQ`dAqjuyy%KvnfE4D1t)Z_e)%@id9y^xJTjv(|S(zvdb^;@1ozDAO1C zutLHTY3uB`qLzMB15KsT2s_&kUIBuFYD=6@-(r7PvQfq!$H<5 zO0^RC^O|vNUcbi@eYV;vZHpB{Cwn?rib~^rx|#?S8@O3S?x}GyJsPT^W<`xxVVu8C1!2IxFSs zls$~bdTHZ--t|LGKf>~kB_{G&*m)Q0#|KBG;$MCiltq});v}%lmUO-`a{n~tV==6c|T$8=i!^Lxmv3kp*?fYxZLTTkSpg}9{Rwt2bO!i zJi_5JS>MUw=S1VrO52N{9zLCxGeZkUCbf(4C8B4Du8Tj_nxn2P=x1jRn)rJ2ug#8> z9{7BJO1IA2PB+Yq%wXQA`w@{fYqdYgr{vz|DFBN4r=$uF>x?9=t>Hn#kyUp^1LJAPyIwQ?mld@V}0mD+9%5c zW}{udzNJqX*D1w#$M1II*}e!1q!hj`&9|jv|};k zE{dx&?uS)HOVw*vU+P;qK@m$Du546c;5*OHp-Djs?+6es;!&6l# zyJyxKl3<2pSX&1%sOH-ed1d+Ufa(#3dD`YLjKF7%Sw_!`5Hja?;swcpvmt+O2m*h^ z{ImyVAJ>qekFA{ZzM*>F{nuH_eIMx1*tcJsxic+_V_zY>P}#)l$gp#Up~{5RV{y+Q zUv}eO5MIP~*hGr@JIvGTzfSNqY_3~z*Z!s0|hoD16=6+6>`yLWvE~K3)3E@v-q;#zV1s|!vRu1+iiud-}Y|cCG6NsK)Oz?tCa+ zlH0j{NawNmt`<$WQCas~yVeReS4o*^%E(2Mw_bE2mnc(%ojFWjx$PI!^G%Fx^s`Gt zS+21f(g5k=jBExMqkupuK|+8<$;`LB!86{G%k8?wrlYFf+VsbqpKenP9B5bHTTP~b z5vj_8Se*=P3w6aTjef0;0Jx_bFs?Y(Wz{mHyqRN=ZH=NUf5 z%nxOP>7_y`&(3+KuQ1SdV+-&a^3gI@D#(!>9o+cNya3)5`>ArhzNo}Au>~Ir4*#Sn z%wSuzKrS`XB9U-wHxDN>m1Ye2A=Xf?-+2mu?A*MU35`&a=+JRc5&3SvF~O3P(Ybg* zV^e%7KeO zvW|;-tAobVH_J`|w!T`6JvUE7qagB~!)gleyczkHgdd_b($ZWRoYejQ&4cp!Q4bgM63Xhyw6<{$GyRn+mib;`u z`yD-XZ&$5#RSu4al11hbaFWzI8ggOVJlnACd!N;)^g^UfIhb#-zi1jsskYD9%D9sJ zquKwiOOUd*KRqINYNcrs?oSy?CnnlKGw$m4n{oR zPSC~)nt@I;4#?z+zsStE(KgA+0_joT!x-|v5wD4D* zT&=l=W1_2j1qHZumBzzlojbvwlNc9;rfm4N+1UdSobD4fv$plW2d6 zJ&G_%XU$2A8n2N9)pCu4>&P2nlT?#S5ymdOUm{w0``4@bY>A%BWa9_FE;4|}jjxvH zMZd%%hvv8aO8NYlbO9ZcfHdvV0?$o*`K4Ok){gD)D(S*uk1;c$J*xvkX`GoC^sfK3 zw#4V170)Ua5EIkqZ0b9w7v|>0VfduNgyIq03*&E#jr6B-Kvj;*z6(!O+>dr*4g2a{ zG-t4k?`UKzvpFg=MCO~ABphQlG-UY7%8o7b9aQ{^Y(m;H4bvb)YfXH_PPrQ1))2^w zmp4aNs1aq%hl)e5fD)egUDVcN{;up%0TyJR0*23Rs?i;^dD`&vtoQ@kFnWH{EsSz$ z?Jp`(s3?M=zJ#iIR(`XwNd`(&-#u%N490mw9*mQQwaw=oKHq!ImIaY#is(!%(;30k zbeA&=+uiFxwa*Xu4$F`dv2J-}%y)S!+$<8o%KGDeLSGW*Ot-*Fge8Hkj}N-8Y*Rce zoalnHB7|D-@$hE_sHA3S$EewD(Y;2EbQ~a&U7n)&T42rANUn`a9BJh-H^_&MC3-2j zgg0Z5ZkF$~x)z!H(&Sy%zTo&5j;3=ug8n8UU*JKs+X-{;dvaROSm;kYWk}i7`RT6) zPIfwtVf8k)3*JgT({ zHmJSt7B3sM=;6-i7eWKXT5f@s2#eLQe|!k$Jlj5RwY->jUT;@5VRmhI*R16g&p=|! zX_84qN?P#mXdi!m-@yogcq!fc&B)z`=K*4cf@ zRH}!$*$p$WG!DE13UuN(%*_eU@9=0>UkWJg&12V34#UT?J?d8fG>!&&<`;={es~F5 zlu#@%9okg{ckyb&v~#Dq3}Qmtlld3m*hCQk0a$3AFWw`!xK?gdVOM+YnQE6_`_EK( z>d;6D$J#DJb@A;; z9GvwTJWOU#Cp4ymA=NQ13b~UR#Yp{$=d+#L+u^0)6EzLIq*I~ka-p$jX#uQncjRw=Qk!jlk3Bd|`9?z;Ek{R7s?gNyZ`B1+bY4m%~iFsc+UA5r0rSUJ3GYVpr zQxpogb?lg&-l1MKE=|lGR#pF;Gs{r7FD0~&^Qd&$HNw^e(hkkzn&3&HU>--?_UO(1 zsjrI|TjP~?Sec@~E3}h8v4BQFa~1+*G*M(N#E$u`%Q#>)kgobUDQ!R93gbWW*3#+` zLi*nTis{b`rdF-Ye4X_Ka1MmP8|Px;z-@s0$yGTkA;@n4W?Wa)S1?5ZZtasuesC{K z{Iw`XQ7sBamapV_#DB8!bKY_HqudBmW=q%NzIjbXd-3!5(LcKc@?KZB5{H~uH1ZXd3 zePep!3|0fm;tfYzN#NWMkyy{2e$dv=yM#pM<^B$RMjSc<{ZL@*h7`J(on2Y_Wq3__ z(s)Q3Zu{`q&?T4hN8dGz+2!QsHZ3bL#%zDd_a{Z{g7xGOmnd-jLW@VWlYCegB3<`| zCgb|iCn@_2IpvO#>yOe* zq)&7*1#g$}ENqqh5I;X7`*dA3VK8&RQ|wcutH;Su3*D+VqbjXgXUm=W z*dEQsccNR_dlF^kvfvi=g6R}hhSr>g)E4GP><$on))k2M^SXLbkOqgq009Ak0m(0t zRVAkA6M;Yk0YM4_0YLzMYwyIVXJKpM%;0QfeU$NFx7d%`=NJ7F{=pDKDq<;aI`Gp1 zZ%4r|(edw6n_HSBOb{P(2}!HAzB&@YJhr>JU3XG6R%^eP+qh12>sQ)u?}_k59)R3dl&7wlP!my$%II^McxwgQ|N3<5C( z)=hWmXTyG%I7|YNNeD~=TYtRH~4c+F_%AhYv+Nff-4oq>o@@kkhz7Wr_)pW8` z)ai0lB!uD5>=2+>vc)O^y-F8WeF1nG*2c6cu#+W~_Y3Nqdy+!$3o1iZk~z8LvHQ4S zS>mBN&AlN4f*Wk;#4~$E%{AT2h*N2A4dNrC6*Kq7vTHk#L#o%QQpgM>Jqog>I{FmR z2n(xGd%HKV&6K}XYvplCZkUJP6Td$ODJi5G2B$-y)(dXjXWXB}0pQ;U-$85|&`sYN z*z*ZpAtXP?hX1$>T6YhZsfwR{Z<}>+3Q-PE0)U!PwlIXPWQgoKE7;>Z_8b0+vNJ%4X zonju}?vGo2KG?}koU50(g|MK6mmhY_&&k{wW47AzgYt^H^va5ug1g&k=h=GRpr<8X zXScIS!bxXos+&3yoatHnxMARo)olE}B`pPdo0Vs@-_Sb<4=mebk-4LL%wP_r zk#$QLkNKunL+oOb%+c14Fuf?o2?WFn(mji3{Pix zOz4{F-mfMkoo)7ad#{8fJpuYJo?v;atjXoUTiW&gCiDCZ{J`L7d@;o59y|7ZueU)Yn?H(cvF|xsoA!8S}O0vT}GdaKVhvD5!*4+>7iJCMgHbYP=JFxq!u;y zJ}k;k){gLX=8~Sxv{>d>%p>d6=-lkN_*^FMiZ&+9_CCk#8RqOsk&*it#1KIK>MiF& zJbMnGQ7+|)>Cq~IO6Y~=(7m6EQ$u#u@d)&#T~%(^X29dymv7YOx`2ABd!8g>{NbL* zhhy!O>D8sC*~@9@Nw##Ao6OnVr6eekIEU24-1wA3r$ zExR^p+8n-_&Pu+@)GcCCHYlzuQE)WExijPB zN0#8|VJA@Jdb*q_sp*{ms*wLm-fKVWdMYdQ$_HeII9)Keu>SyW(CGnBP`|~U&q%WA zd*-&*6WI?aVsA=vLz>uJ*zgdiY3~=y)Up@ z$c2p`;RKYcoTEtt6Niq7xy=(dr}YL#L{uL}cMsRRg*wjQkuCN*r)R+;%}g$g8^W#% z16d-?>^f$6tTpmP#eYYfJ+l?H?(~s+es-aJPY;mRLuqc;s|SV4(TSyX*nD+XOM7zx zu=T1FXpd85pJ*+EBseFb4NYZqg*?Hz^5p;Uygj(`#Ta-XjzWH39$QA#uj6c3S%U0r z*gb~Q1V(Wz;c+79!u#_N&9b5zYH2rsh)4TV?nEfE)H4p?x4vAr1k#8oBYI5297EW4 z#-`_hh>pDL7ZO0kmAa)b{XGq|MIx2n^q>*W;Se@^=H3q5sT?2z%&cDg5~}a~LuotI z7dD|&m1Nq?rs-HHn6{j(MTsGoHoZH;UDYxV+9B)@?r{8pY_nf8LZQI04=dR9o zt~k$It3BZ*6A)d=hj{vY4v5|!UW#3NU1sOEj(rTTYv_cyVM&ouPpr<4YSp0K(;KXT z(XGV&&GQ-E4%fW)ZvfG*D@nYrr~FqBjuOp2ddG7>_X6GnFVLrb8jYY=YguAZ}-vIyD_gyZ|db}kkHQX)6=e_gciQ9WTTNeD#Ve4{ZF78 zi)`@$wH|uM{m9T+MiwNwxORDrZd)ONW0lh&6OWMS#??z_;->HQj$!yLUyzlK)noFv zXLHLPV@>ZICG?KfcYGRw0wrgLnoab8=r#i83hM$N?p&^(-aJMLghPN|8$o5D-NV%2 zgQFPl$q*`V?j#P^{+T1`KXY^g2xVKdHR0Zn?Y-l#@T9Zs zvw*0iXXh>8bz9rLxyeq8eDtE{I@7N5F2WckAc(YxeYg#=?S99czYfN^UwNwzVgTQ?@^|TT#VTxCIL#Q@3w{?I} zlQzn+DZdeUB0-OIfrq}wn|XKzr=-DFtCqo!lzTJd-U&}cQl9J^YB8DZsb-9(FXTaW zTJE7l7`gClNgti_A;mNqKY zt=M@kiaXaUCIi3B6_p$2?z`~id!83}jo7h}uF0%^(q>m5xZRNY16jGAjxny6Ax3hA zuWjPu^3?mq9pL4#W&@-zkJxBRikOW8#bt^;IS9R}jv@@@*A$Hpjy`cGW!GCD+SJ=d z)CA)ShmXdQ&EWU_F*U}0)8zDq<>ZLYwqpw=DE<6?L8^|BZpp?muKXCAwRe>@`uV%t zdo6;&lzzr5S?@a{-`LH?(M(TTOY+I+_K^ILtnR4AR`??Fd{j%Pvju+|Hg~I6+g#Z; zz*q5b$7`WzW3gvowV!mi0t)Wn+X)I4BK^`qs&ck>Ooc9r)9|B@Zv4S=BHV8sy|Q^o zF@lUmeVvb=>qLIo>Xva128~liKHt-ZeYNVuzI*;T=V&(I_55?Mcw~Eq4h9eV&`HuvM6}id@^~!fQziK4gkXS9DSwNjN3BnlHgrr zI&DQ?WjY-J_3qgjo@ zxaBq@8m_ODFM(c=xi_x^$L$O+p}$Hda3M=qtM@y8UkktN66w*qmSO&}t32DVq%k#s zlVUa!`fTs`^Yy3EYRsmJxQnX?Z(1IsRtoHzi@|i))t_7FR(-#(s~c1rUVwXrO+Nmn z(6APu6G(v2?BxWkkD<HBN@mV$Qc~-Z6lr-qjPdUUHkMa`M0cLn0e!p_Ha3LKxfRt$LM1~{yOilD=h@l zPvQe+gr*nx|E-qb!e)9nz(7E#AwWQ&fz^_`lL3Rfjdk$1McWM~lrJY9a6_|NFa}yp zp$ZOE^k^8r_Bb3fNUvxrTcf8$vV8lbU}`ii7|k9Zvg}L`pSzi5`+1XPsBp(!r}7}k z)#73ugxnVQM)-Yj*zT?J>E@HFARkH*EG;rnsw9^tg#%-s(ff0LvwA3O1?QuTx4N6f z{RDts@vqw5$4Bmf9xb^nwjWPe(<;rWC+_<*#FHz#Qyd|kE%Kk#?YO|M?2W4`0+08| zO^Vc>$de4>Q({pX7OSSpuA%YFp>=3IX-G~M>Wvz&^QWPfLO?^PMu{_Xe$x2m}Fhb#Giyu*khqBZ06#=d@Z)^LzO~!(h1B#rXZ1nmk z0>(}VBs%#+mU^E0#c#d7D*_^1mL}HB#_3&D*ivGyxW>gUHlE@=!kR7L5rgKX7C1kC zNf+JVQ8pzfXDzJ!iba0j0+*%%j_|NpEheTH&HPOiYdrLTSgosc5*`x(8{a)DmlDkO z$b`_$0Z1jt)f$`;7)&6gU{$ZTgm9^j?}^RmCPV#Jb+j{Jx&7rESH$2=n(>+6z+=`| z--9Omc9k{NPKXuAb|w{vnIYjmgnC`i)ja0je3I-e%DY0ht!4SK8&AG4KTqA0-g2)G z#g!~(c>s5!GU6=Lp`?oIO;}{aU$^0>fkha^AZyB%4S~ETsjYPGrY~KKZW+3BI-gSH z-7Y-1QfE!{nWsYYBUZDsCmO3aU?Fs7LG4;qLxWn9qZXQl-U= zzQCMyk~b%nAfv}w5!nv)POuv8Er+N;)$H5rI6^D zo4jzK#N@hJt4d!G_Bh8s+Sodyv{cc$j}wjg1Hvom zyMr1rf}S&nr|zF&D+IR)A=5V96;2B_Sy{DiMFG~1g*#@HzAhz=l&J<~q~EacV2Lgr z&}w*vm*jHGrKS;Oun6rwOl4A?=uYqTF7LLW*9mBr3Mxp0f?$fR}Rea56SA zeT~I`%atVc)V|LF0pVPM`b*A1>$*G($^ z>1hoNBn^`m1jrx$f8)|c{wvF1?)-mE@;B%BD*JZJpKM_MJM1e1`S&FKoqzw8{Ok$y zpKScM(BF~uU!i61H=)-!s~`;toQYQw6age37>9fPU_cl^KCnqxi*Y$R%9}_?iK;n^ jvonioaD9+b + + +Table of Contents +================= + + I. Adding the meta-user layer to your build + II. Misc + + +I. Adding the meta-user layer to your build +================================================= + +--- replace with specific instructions for the meta-user layer --- + +In order to use this layer, you need to make the build system aware of +it. + +Assuming the meta-user layer exists at the top-level of your +yocto build tree, you can add it to the build system by adding the +location of the meta-user layer to bblayers.conf, along with any +other layers needed. e.g.: + + BBLAYERS ?= " \ + /path/to/yocto/meta \ + /path/to/yocto/meta-poky \ + /path/to/yocto/meta-yocto-bsp \ + /path/to/yocto/meta-meta-user \ + " + + +II. Misc +======== + +--- replace with specific information about the meta-user layer --- diff --git a/project-spec/meta-user/conf/layer.conf b/project-spec/meta-user/conf/layer.conf new file mode 100644 index 0000000..bb9aff6 --- /dev/null +++ b/project-spec/meta-user/conf/layer.conf @@ -0,0 +1,16 @@ +# We have a conf and classes directory, add to BBPATH +BBPATH .= ":${LAYERDIR}" + +# We have recipes-* directories, add to BBFILES +BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \ + ${LAYERDIR}/recipes-*/*/*.bbappend" + +# Define dynamic layers +BBFILES_DYNAMIC += " \ +xilinx-tools:${LAYERDIR}/meta-xilinx-tools/recipes-*/*/*.bbappend \ +" + +BBFILE_COLLECTIONS += "meta-user" +BBFILE_PATTERN_meta-user = "^${LAYERDIR}/" +BBFILE_PRIORITY_meta-user = "7" +LAYERSERIES_COMPAT_meta-user = "honister" diff --git a/project-spec/meta-user/conf/petalinuxbsp.conf b/project-spec/meta-user/conf/petalinuxbsp.conf new file mode 100644 index 0000000..828a0af --- /dev/null +++ b/project-spec/meta-user/conf/petalinuxbsp.conf @@ -0,0 +1,4 @@ +#User Configuration + +#OE_TERMINAL = "tmux" + diff --git a/project-spec/meta-user/conf/user-rootfsconfig b/project-spec/meta-user/conf/user-rootfsconfig new file mode 100644 index 0000000..77d124e --- /dev/null +++ b/project-spec/meta-user/conf/user-rootfsconfig @@ -0,0 +1,5 @@ +#Note: Mention Each package in individual line +#These packages will get added into rootfs menu entry + +CONFIG_gpio-demo +CONFIG_peekpoke diff --git a/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/files/system-user.dtsi b/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/files/system-user.dtsi new file mode 100644 index 0000000..f3270db --- /dev/null +++ b/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/files/system-user.dtsi @@ -0,0 +1,3 @@ +/include/ "system-conf.dtsi" +/ { +}; diff --git a/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend b/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend new file mode 100644 index 0000000..d7d03f8 --- /dev/null +++ b/project-spec/meta-user/meta-xilinx-tools/recipes-bsp/uboot-device-tree/uboot-device-tree.bbappend @@ -0,0 +1,16 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" + +SRC_URI:append = " file://config file://system-user.dtsi" + +python () { + if d.getVar("CONFIG_DISABLE"): + d.setVarFlag("do_configure", "noexec", "1") +} +export PETALINUX +do_configure:append () { + script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" + data=${PETALINUX}/etc/hsm/data/ + eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ + -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ + -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" +} diff --git a/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend b/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend new file mode 100644 index 0000000..b4a4917 --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend @@ -0,0 +1,28 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:${SYSCONFIG_PATH}:" + +SRC_URI:append = " file://config file://system-user.dtsi" +DEPENDS:append = "${@' lopper-native' if d.getVar('SYSTEM_DTFILE') != '' else ''}" + +# We need the deployed output +PROC_TUNE:versal = "${@'cortexa72' if d.getVar('SYSTEM_DTFILE') != '' else ''}" +PROC_TUNE:zynqmp = "${@'cortexa53' if d.getVar('SYSTEM_DTFILE') != '' else ''}" + +python () { + if d.getVar("CONFIG_DISABLE"): + d.setVarFlag("do_configure", "noexec", "1") +} + +export PETALINUX +do_configure:append () { + if [ ! -z "${SYSTEM_DTFILE}" ]; then + user_dtsi="${TOPDIR}/../project-spec/decoupling-dtsi/system-user.dtsi" + apu_dts="${TOPDIR}/../project-spec/decoupling-dtsi/${PROC_TUNE}-${SOC_FAMILY}-linux.dts" + lopper -f -v --enhanced --permissive -i ${user_dtsi} ${apu_dts} system-default.dtb + else + script="${PETALINUX}/etc/hsm/scripts/petalinux_hsm_bridge.tcl" + data=${PETALINUX}/etc/hsm/data/ + eval xsct -sdx -nodisp ${script} -c ${WORKDIR}/config \ + -hdf ${DT_FILES_PATH}/hardware_description.${HDF_EXT} -repo ${S} \ + -data ${data} -sw ${DT_FILES_PATH} -o ${DT_FILES_PATH} -a "soc_mapping" + fi +} diff --git a/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi b/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi new file mode 100644 index 0000000..7e7cb18 --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/device-tree/files/pl-custom.dtsi @@ -0,0 +1,4 @@ +/*Add pl custom nodes for pl.dtsi which is generated from base xsa file. +Changes in this file reflects only when enabled the FPGA manager/Device tree overlay.*/ +/ { +}; diff --git a/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi new file mode 100644 index 0000000..db54a2d --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -0,0 +1,93 @@ +/include/ "system-conf.dtsi" +#include + +/ { + leds { + compatible = "gpio-leds"; + gpio-led1 { + label = "led1"; + gpios = <&gpio0 54 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + gpio-led2 { + label = "pl_led0"; + gpios = <&gpio0 55 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + gpio-led3 { + label = "pl_led1"; + gpios = <&gpio0 56 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + gpio-led4 { + label = "ps_led0"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + gpio-led5 { + label = "ps_led1"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + gpio-led6 { + label = "led2"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + gpio-key1 { + label = "pl_key1"; + gpios = <&gpio0 57 GPIO_ACTIVE_LOW>; + linux,code = <105>; // Right + debounce-interval = <20>; // 20ms + }; + gpio-key2 { + label = "pl_key2"; + gpios = <&gpio0 58 GPIO_ACTIVE_LOW>; + linux,code = <106>; // Left + debounce-interval = <20>; + }; + gpio-key3 { + label = "ps_key1"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + linux,code = <103>; // Up + debounce-interval = <20>; + }; + gpio-key4 { + label = "ps_key2"; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + linux,code = <108>; // Down + debounce-interval = <20>; + }; + touch-key { + label = "touch_key"; + gpios = <&gpio0 59 GPIO_ACTIVE_HIGH>; + linux,code = <28>; // ENTER + gpio-key,wakeup; + debounce-interval = <20>; + }; + }; + + beeper { + compatible = "gpio-beeper"; + gpios = <&gpio0 60 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + eeprom@50 { + compatible = "24c64"; + reg = <0x50>; + pagesize = <32>; + }; + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + diff --git a/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg b/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg new file mode 100644 index 0000000..c2895e0 --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/u-boot/files/bsp.cfg @@ -0,0 +1,2 @@ +CONFIG_SYS_CONFIG_NAME="platform-top" +CONFIG_BOOT_SCRIPT_OFFSET=0x9C0000 diff --git a/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 0000000..0aa486a --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1 @@ +#include diff --git a/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend b/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend new file mode 100644 index 0000000..c23e081 --- /dev/null +++ b/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend @@ -0,0 +1,15 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files:" + +SRC_URI:append = " file://platform-top.h file://bsp.cfg" + +do_configure:append () { + install ${WORKDIR}/platform-top.h ${S}/include/configs/ +} + +do_configure:append:microblaze () { + if [ "${U_BOOT_AUTO_CONFIG}" = "1" ]; then + install ${WORKDIR}/platform-auto.h ${S}/include/configs/ + install -d ${B}/source/board/xilinx/microblaze-generic/ + install ${WORKDIR}/config.mk ${B}/source/board/xilinx/microblaze-generic/ + fi +} diff --git a/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg b/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/bsp.cfg new file mode 100644 index 0000000..e69de29 diff --git a/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2023-02-14-13-57-00.cfg b/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2023-02-14-13-57-00.cfg new file mode 100644 index 0000000..f2e4518 --- /dev/null +++ b/project-spec/meta-user/recipes-kernel/linux/linux-xlnx/user_2023-02-14-13-57-00.cfg @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="-phosphor-7020" +CONFIG_DEFAULT_HOSTNAME="zynq" +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_COMMON_CLK_PWM is not set +CONFIG_COMMON_CLK_XLNX_CLKWZRD=y +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_CADENCE is not set +CONFIG_PWM_XILINX=y diff --git a/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend b/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend new file mode 100644 index 0000000..3e3d049 --- /dev/null +++ b/project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend @@ -0,0 +1,6 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" + +SRC_URI:append = " file://bsp.cfg" +KERNEL_FEATURES:append = " bsp.cfg" +SRC_URI += "file://user_2023-02-14-13-57-00.cfg" +