Paul Pan 17f64e1f2f 1. add cache (D-Cache Address) inst ... 2. fix bug in ALR 3. fix bug in MMU and DCache 4. Register File rst		2021-09-02 19:20:19 +08:00
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ctrl_maker.py	add control signals	2021-09-02 19:05:23 +08:00
decoder.py	1. add cache (D-Cache Address) inst	2021-09-02 19:20:19 +08:00
ectrl.txt	add control signals	2021-09-02 19:05:23 +08:00
exc.txt	handle CpU exception	2021-08-25 20:59:32 +08:00
global.txt	add control signals	2021-09-02 19:05:23 +08:00
mctrl0.txt	add control signals	2021-09-02 19:05:23 +08:00
mctrl1.txt	1. add cache (D-Cache Address) inst	2021-09-02 19:20:19 +08:00
pcs.txt	add control signals	2021-09-02 19:05:23 +08:00
privilege.txt	add control signals	2021-09-02 19:05:23 +08:00
wctrl.txt	add control signals	2021-09-02 19:05:23 +08:00