816 lines
16 KiB
Verilog
816 lines
16 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module TFIFO (
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clk,
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rst,
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ramwe,
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ramaddr,
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ramdata,
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fifowe,
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fifoeof,
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fifobe,
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fifodata,
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fifonf,
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fifocnf,
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fifoval,
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flev,
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ici,
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dpdi,
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aci,
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statadi,
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cachere,
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deo,
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lco,
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loo,
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nco,
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eco,
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csne,
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ico,
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uro,
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cco,
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statado,
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sofreq,
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eofreq,
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dpdo,
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aco,
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beo,
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eofad,
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wadg,
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tireq,
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winp,
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dei,
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lci,
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loi,
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nci,
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eci,
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uri,
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cci,
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radg,
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tiack,
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sf,
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fdp,
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tm,
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pbl,
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etiack,
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etireq,
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stopi,
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stopo
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);
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parameter DATAWIDTH = 32;
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parameter DATADEPTH = 32;
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parameter FIFODEPTH = 9;
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parameter CACHEDEPTH = 1;
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`include "utility.v"
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input clk;
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input rst;
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output ramwe;
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wire ramwe;
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output [FIFODEPTH - 1:0] ramaddr;
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wire [FIFODEPTH - 1:0] ramaddr;
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output [DATAWIDTH - 1:0] ramdata;
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wire [DATAWIDTH - 1:0] ramdata;
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input fifowe;
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input fifoeof;
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input [DATAWIDTH / 8 - 1:0] fifobe;
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input [DATAWIDTH - 1:0] fifodata;
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output fifonf;
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reg fifonf;
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output fifocnf;
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wire fifocnf;
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output fifoval;
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reg fifoval;
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output [FIFODEPTH - 1:0] flev;
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wire [FIFODEPTH - 1:0] flev;
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input ici;
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input dpdi;
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input aci;
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input [DATADEPTH - 1:0] statadi;
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input cachere;
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output deo;
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wire deo;
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output lco;
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wire lco;
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output loo;
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wire loo;
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output nco;
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wire nco;
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output eco;
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wire eco;
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output csne;
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wire csne;
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output ico;
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wire ico;
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output uro;
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wire uro;
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output [3:0] cco;
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wire [3:0] cco;
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output [DATADEPTH - 1:0] statado;
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wire [DATADEPTH - 1:0] statado;
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output sofreq;
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wire sofreq;
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output eofreq;
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reg eofreq;
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output dpdo;
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wire dpdo;
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output aco;
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wire aco;
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output [DATAWIDTH / 8 - 1:0] beo;
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wire [DATAWIDTH / 8 - 1:0] beo;
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output [FIFODEPTH - 1:0] eofad;
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reg [FIFODEPTH - 1:0] eofad;
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output [FIFODEPTH - 1:0] wadg;
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reg [FIFODEPTH - 1:0] wadg;
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input tireq;
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input winp;
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input dei;
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input lci;
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input loi;
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input nci;
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input eci;
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input uri;
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input [3:0] cci;
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input [FIFODEPTH - 1:0] radg;
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output tiack;
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wire tiack;
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input sf;
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input fdp;
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input [2:0] tm;
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input [5:0] pbl;
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input etiack;
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output etireq;
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reg etireq;
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input stopi;
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output stopo;
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reg stopo;
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parameter CCWIDTH = (3 + DATADEPTH + DATAWIDTH / 8 + FIFODEPTH);
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reg [CCWIDTH - 1:0] ccmem[(1'b1 << CACHEDEPTH) - 1:0];
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wire ccwe;
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wire ccre;
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reg ccne;
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reg iccnf;
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wire [CACHEDEPTH - 1:0] ccwad_c;
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reg [CACHEDEPTH - 1:0] ccwad;
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reg [CACHEDEPTH - 1:0] ccrad;
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reg [CACHEDEPTH - 1:0] ccrad_r;
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wire [CCWIDTH - 1:0] ccdi;
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wire [CCWIDTH - 1:0] ccdo;
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parameter CSWIDTH = (DATADEPTH + 11);
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reg [CSWIDTH - 1:0] csmem[(1'b1 << CACHEDEPTH) - 1:0];
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wire cswe;
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reg csre;
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reg [CACHEDEPTH - 1:0] cswad;
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wire [CACHEDEPTH - 1:0] csrad_c;
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reg [CACHEDEPTH - 1:0] csrad;
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reg [CACHEDEPTH - 1:0] csrad_r;
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wire [CSWIDTH - 1:0] csdi;
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wire [CSWIDTH - 1:0] csdo;
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wire [DATADEPTH - 1:0] statad;
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wire ic;
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reg icsne;
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reg tprog;
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reg tprog_r;
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reg winp_r;
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reg [FIFODEPTH_MAX - 1:0] tlev_c;
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reg tresh;
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reg [FIFODEPTH - 1:0] stat;
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reg [FIFODEPTH - 1:0] wad;
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reg [FIFODEPTH - 1:0] rad_c;
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reg [FIFODEPTH - 1:0] rad;
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reg [FIFODEPTH - 1:0] radg_0_r;
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reg [FIFODEPTH - 1:0] radg_r;
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reg [FIFODEPTH - 1:0] sad;
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wire [FIFODEPTH - 1:0] eofad_bin;
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reg pblz;
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reg [FIFODEPTH_MAX - 1:0] sflev_c;
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reg tireq_r;
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reg tireq_r2;
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reg stop_r;
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wire [FIFODEPTH - 1:0] fone;
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wire [FIFODEPTH - 1:0] fzero;
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always @(posedge clk)
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begin : ccmem_reg_proc
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if (rst)
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begin : ccmem_reset
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integer i;
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for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1)
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begin
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ccmem[i] <= {CCWIDTH{1'b0}};
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end
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ccrad_r <= {CACHEDEPTH{1'b0}} ;
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end
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else
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begin
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if (fifowe | fifoeof)
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begin
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ccmem[ccwad] <= ccdi ;
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end
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ccrad_r <= ccrad ;
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end
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end
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assign ccwad_c = (fifoeof) ? ccwad + 1 : ccwad ;
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always @(posedge clk)
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begin : ccaddr_reg_proc
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if (rst)
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begin
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ccwad <= {CACHEDEPTH{1'b0}} ;
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ccrad <= {CACHEDEPTH{1'b0}} ;
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end
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else
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begin
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ccwad <= ccwad_c ;
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if (ccre)
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begin
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ccrad <= ccrad + 1 ;
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end
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end
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end
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always @(posedge clk)
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begin : ccfe_reg_proc
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if (rst)
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begin
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iccnf <= 1'b1 ;
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ccne <= 1'b0 ;
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end
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else
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begin
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if ((ccwad_c == ccrad) & ccwe)
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begin
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iccnf <= 1'b0 ;
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end
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else if (ccre)
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begin
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iccnf <= 1'b1 ;
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end
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if (ccwad == ccrad & iccnf)
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begin
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ccne <= 1'b0 ;
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end
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else
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begin
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ccne <= 1'b1 ;
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end
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end
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end
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assign fifocnf = iccnf ;
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assign ccdo = ccmem[ccrad_r] ;
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assign ccdi = {ici, aci, dpdi, wad, fifobe, statadi} ;
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assign ccwe = fifoeof ;
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assign ccre = tireq_r & ~tireq_r2 ;
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assign ic = ccdo[CCWIDTH - 1] ;
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assign aco = ccdo[CCWIDTH - 2] ;
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assign dpdo = ccdo[CCWIDTH - 3] ;
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assign eofad_bin = ccdo[CCWIDTH - 4:CCWIDTH - 3 - FIFODEPTH] ;
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always @(posedge clk)
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begin : eofad_reg_proc
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if (rst)
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begin
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eofad <= {FIFODEPTH{1'b0}} ;
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end
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else
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begin
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eofad[FIFODEPTH - 1] <= eofad_bin[FIFODEPTH - 1] ;
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begin : eofad_loop
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integer i;
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for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
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begin
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eofad[i] <= eofad_bin[i] ^ eofad_bin[i + 1] ;
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end
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end
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end
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end
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assign beo = ccdo[DATADEPTH + DATAWIDTH / 8 - 1:DATADEPTH] ;
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assign statad = ccdo[DATADEPTH - 1:0] ;
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always @(posedge clk)
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begin : csmem_reg_proc
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if (rst)
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begin : csmem_reset
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integer i;
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for(i = ((1'b1 << CACHEDEPTH) - 1); i >= 0; i = i - 1)
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begin
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csmem[i] <= {CSWIDTH{1'b0}};
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end
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csrad_r <= {CACHEDEPTH{1'b0}};
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end
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else
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begin
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csmem[cswad] <= csdi ;
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csrad_r <= csrad ;
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end
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end
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always @(posedge clk)
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begin : csaddr_reg_proc
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if (rst)
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begin
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cswad <= {CACHEDEPTH{1'b0}} ;
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csrad <= {CACHEDEPTH{1'b0}} ;
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end
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else
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begin
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if (cswe)
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begin
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cswad <= cswad + 1 ;
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end
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csrad <= csrad_c ;
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end
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end
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assign csrad_c = (csre) ? csrad + 1 : csrad ;
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always @(posedge clk)
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begin : icsne_reg_proc
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if (rst)
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begin
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icsne <= 1'b0 ;
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end
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else
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begin
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if (cswad == csrad | (csre & cswad == csrad_c))
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begin
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icsne <= 1'b0 ;
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end
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else
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begin
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icsne <= 1'b1 ;
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end
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end
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end
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assign csne = icsne;
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assign csdo = csmem[csrad_r] ;
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assign csdi = {dei, lci, loi, nci, eci, ic, cci, uri, statad} ;
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assign deo = csdo[CSWIDTH - 1] ;
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assign lco = csdo[CSWIDTH - 2] ;
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assign loo = csdo[CSWIDTH - 3] ;
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assign nco = csdo[CSWIDTH - 4] ;
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assign eco = csdo[CSWIDTH - 5] ;
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assign ico = csdo[CSWIDTH - 6] ;
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assign cco = csdo[CSWIDTH - 7:CSWIDTH - 10] ;
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assign uro = csdo[CSWIDTH - 11] ;
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assign statado = csdo[DATADEPTH - 1:0] ;
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assign cswe = tireq_r & tprog ;
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always @(posedge clk)
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begin : csre_reg_proc
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if (rst)
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begin
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csre <= 1'b0 ;
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end
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else
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begin
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csre <= cachere ;
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end
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end
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always @(posedge clk)
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begin : tprog_reg_proc
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if (rst)
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begin
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tprog <= 1'b0 ;
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tprog_r <= 1'b0 ;
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end
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else
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begin
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tprog_r <= tprog ;
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if (tireq_r)
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begin
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tprog <= 1'b0 ;
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end
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else if ((!sf & !tprog & !tireq_r & tresh) | ccne)
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begin
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tprog <= 1'b1 ;
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end
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end
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end
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always @(posedge clk)
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begin : eofreq_reg_proc
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if (rst)
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begin
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eofreq <= 1'b0 ;
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end
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else
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begin
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if (tprog & ccne)
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begin
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eofreq <= 1'b1 ;
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end
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else if (tireq_r)
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begin
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eofreq <= 1'b0 ;
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end
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end
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end
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always @(posedge clk)
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begin : tireq_reg_proc
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if (rst)
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begin
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tireq_r <= 1'b0 ;
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tireq_r2 <= 1'b0 ;
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end
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else
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begin
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tireq_r <= tireq ;
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tireq_r2 <= tireq_r ;
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end
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end
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always @(posedge clk)
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begin : etireq_reg_proc
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if (rst)
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begin
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etireq <= 1'b0 ;
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end
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else
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begin
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if (fifoeof)
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begin
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etireq <= 1'b1 ;
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end
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else if (etiack)
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begin
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etireq <= 1'b0 ;
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end
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end
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end
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assign tiack = tireq_r2 ;
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assign sofreq = tprog ;
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always @(posedge clk)
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begin : addr_reg_proc
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if (rst)
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begin
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wad <= {FIFODEPTH{1'b0}} ;
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wadg <= {FIFODEPTH{1'b0}} ;
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radg_0_r <= {FIFODEPTH{1'b0}} ;
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radg_r <= {FIFODEPTH{1'b0}} ;
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rad <= {FIFODEPTH{1'b0}} ;
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sad <= {FIFODEPTH{1'b0}} ;
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end
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else
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begin
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if (fifowe)
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begin
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wad <= wad + 1 ;
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end
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wadg[FIFODEPTH - 1] <= wad[FIFODEPTH - 1] ;
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begin : wadg_loop
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integer i;
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for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
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begin
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wadg[i] <= wad[i] ^ wad[i + 1] ;
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end
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end
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radg_0_r <= radg ;
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radg_r <= radg_0_r ;
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rad <= rad_c ;
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if (!tprog & tprog_r)
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begin
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sad <= eofad_bin ;
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end
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end
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end
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always @(radg_r)
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begin : rad_proc
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reg[FIFODEPTH - 1:0] rad_v;
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rad_v[FIFODEPTH - 1] = radg_r[FIFODEPTH - 1];
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begin : rad_loop
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integer i;
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for(i = FIFODEPTH - 2; i >= 0; i = i - 1)
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begin
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rad_v[i] = rad_v[i + 1] ^ radg_r[i];
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end
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end
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rad_c = rad_v ;
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end
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always @(posedge clk)
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begin : stat_reg_proc
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if (rst)
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begin
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stat <= {FIFODEPTH{1'b0}} ;
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end
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else
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begin
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if ((!winp_r & !fdp & tprog & !tireq_r) | !tprog_r)
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begin
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stat <= wad - sad ;
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end
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else
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begin
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stat <= wad - rad ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : winp_reg_proc
|
|
if (rst)
|
|
begin
|
|
winp_r <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
winp_r <= winp ;
|
|
end
|
|
end
|
|
|
|
always @(tm)
|
|
begin : tresh_proc
|
|
tlev_c <= {FIFODEPTH_MAX{1'b0}} ;
|
|
case (DATAWIDTH)
|
|
8 :
|
|
begin
|
|
case (tm)
|
|
3'b000, 3'b101, 3'b110 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00010000000 ;
|
|
end
|
|
3'b001, 3'b111 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00100000000 ;
|
|
end
|
|
3'b010 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b01000000000 ;
|
|
end
|
|
3'b011 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b10000000000 ;
|
|
end
|
|
default :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00001000000 ;
|
|
end
|
|
endcase
|
|
end
|
|
16 :
|
|
begin
|
|
case (tm)
|
|
3'b000, 3'b101, 3'b110 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00001000000 ;
|
|
end
|
|
3'b001, 3'b111 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00010000000 ;
|
|
end
|
|
3'b010 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00100000000 ;
|
|
end
|
|
3'b011 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b01000000000 ;
|
|
end
|
|
default :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00000100000 ;
|
|
end
|
|
endcase
|
|
end
|
|
default :
|
|
begin
|
|
case (tm)
|
|
3'b000, 3'b101, 3'b110 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00000100000 ;
|
|
end
|
|
3'b001, 3'b111 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00001000000 ;
|
|
end
|
|
3'b010 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00010000000 ;
|
|
end
|
|
3'b011 :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00100000000 ;
|
|
end
|
|
default :
|
|
begin
|
|
tlev_c[10:0] <= 11'b00000010000 ;
|
|
end
|
|
endcase
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : tresh_reg_proc
|
|
if (rst)
|
|
begin
|
|
tresh <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (stat >= tlev_c[FIFODEPTH - 1:0])
|
|
begin
|
|
tresh <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
tresh <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(pbl or pblz)
|
|
begin : sflev_proc
|
|
sflev_c[FIFODEPTH_MAX - 1:6] <= {(FIFODEPTH_MAX-6){1'b1}} ;
|
|
if (pblz)
|
|
begin
|
|
sflev_c[5:0] <= 6'b000000 ;
|
|
end
|
|
else
|
|
begin
|
|
sflev_c[5:0] <= ~pbl ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : fifoval_reg_proc
|
|
if (rst)
|
|
begin
|
|
fifoval <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (stat <= sflev_c[FIFODEPTH - 1:0])
|
|
begin
|
|
fifoval <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
fifoval <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : pblz_reg_proc
|
|
if (rst)
|
|
begin
|
|
pblz <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (pbl == 6'b000000)
|
|
begin
|
|
pblz <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
pblz <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : fifonf_reg_proc
|
|
if (rst)
|
|
begin
|
|
fifonf <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
if ((stat == {fone[FIFODEPTH - 1:1], 1'b0} & fifowe) |
|
|
(stat == fone))
|
|
begin
|
|
fifonf <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
fifonf <= 1'b1 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign flev = stat ;
|
|
|
|
assign ramaddr = wad ;
|
|
|
|
assign ramdata = fifodata ;
|
|
|
|
assign ramwe = fifowe ;
|
|
|
|
always @(posedge clk)
|
|
begin : tstop_reg_proc
|
|
if (rst)
|
|
begin
|
|
stop_r <= 1'b1 ;
|
|
stopo <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
stop_r <= stopi ;
|
|
|
|
if (stop_r & !ccne & !icsne & stat == fzero & !tprog)
|
|
begin
|
|
stopo <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
stopo <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign fone = {FIFODEPTH{1'b1}} ;
|
|
|
|
assign fzero = {FIFODEPTH{1'b0}} ;
|
|
|
|
endmodule
|