523 lines
14 KiB
Verilog
523 lines
14 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module MAC_AXI (
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clkt,
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clkr,
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rsttco,
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rstrco,
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interrupt,
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tps,
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rps,
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mhclk,
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mhresetn,
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mawid_o ,
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mawaddr_o ,
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mawlen_o ,
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mawsize_o ,
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mawburst_o ,
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mawlock_o ,
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mawcache_o ,
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mawprot_o ,
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mawvalid_o ,
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mawready_i ,
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mwid_o ,
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mwdata_o ,
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mwstrb_o ,
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mwlast_o ,
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mwvalid_o ,
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mwready_i ,
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mbid_i ,
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mbresp_i ,
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mbvalid_i ,
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mbready_o ,
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marid_o ,
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maraddr_o ,
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marlen_o ,
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marsize_o ,
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marburst_o ,
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marlock_o ,
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marcache_o ,
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marprot_o ,
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marvalid_o ,
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marready_i ,
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mrid_i ,
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mrdata_i ,
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mrresp_i ,
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mrlast_i ,
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mrvalid_i ,
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mrready_o ,
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shclk,
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shresetn,
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sawid_i ,
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sawaddr_i ,
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sawlen_i ,
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sawsize_i ,
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sawburst_i ,
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sawlock_i ,
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sawcache_i ,
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sawprot_i ,
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sawvalid_i ,
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sawready_o ,
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swid_i ,
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swdata_i ,
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swstrb_i ,
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swlast_i ,
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swvalid_i ,
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swready_o ,
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sbid_o ,
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sbresp_o ,
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sbvalid_o ,
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sbready_i ,
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sarid_i ,
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saraddr_i ,
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sarlen_i ,
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sarsize_i ,
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sarburst_i ,
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sarlock_i ,
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sarcache_i ,
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sarprot_i ,
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sarvalid_i ,
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sarready_o ,
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srid_o ,
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srdata_o ,
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srresp_o ,
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srlast_o ,
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srvalid_o ,
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srready_i ,
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trdata,
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twe,
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twaddr,
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traddr,
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twdata,
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rrdata,
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rwe,
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rwaddr,
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rraddr,
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rwdata,
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frdata,
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fwe,
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fwaddr,
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fraddr,
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fwdata,
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match,
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matchval,
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matchen,
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matchdata,
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sdi,
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sclk,
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scs,
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sdo,
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rxer,
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rxdv,
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col,
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crs,
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rxd,
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txen,
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txer,
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txd,
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mdc,
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mdi,
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mdo,
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mden
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);
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parameter MAXIADDRESSWIDTH = 32;
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parameter SAXIADDRESSWIDTH = 32;
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parameter TFIFODEPTH = 9;
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parameter RFIFODEPTH = 9;
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parameter TCDEPTH = 1;
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parameter RCDEPTH = 2;
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parameter MAXIDATAWIDTH = 32;
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parameter SAXIDATAWIDTH = 32;
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`include "utility.v"
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input clkt;
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input clkr;
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output rsttco;
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wire rsttco;
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output rstrco;
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wire rstrco;
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output interrupt;
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wire interrupt;
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output tps;
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wire tps;
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output rps;
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wire rps;
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input mhclk;
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input mhresetn;
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output [ 3:0] mawid_o ;
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output [ 31:0] mawaddr_o ;
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output [ 3:0] mawlen_o ;
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output [ 2:0] mawsize_o ;
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output [ 1:0] mawburst_o ;
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output [ 1:0] mawlock_o ;
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output [ 3:0] mawcache_o ;
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output [ 2:0] mawprot_o ;
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output mawvalid_o ;
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input mawready_i ;
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output [ 3:0] mwid_o ;
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output [ 31:0] mwdata_o ;
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output [ 3:0] mwstrb_o ;
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output mwlast_o ;
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output mwvalid_o ;
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input mwready_i ;
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input [ 3:0] mbid_i ;
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input [ 1:0] mbresp_i ;
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input mbvalid_i ;
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output mbready_o ;
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output [ 3:0] marid_o ;
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output [ 31:0] maraddr_o ;
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output [ 3:0] marlen_o ;
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output [ 2:0] marsize_o ;
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output [ 1:0] marburst_o ;
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output [ 1:0] marlock_o ;
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output [ 3:0] marcache_o ;
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output [ 2:0] marprot_o ;
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output marvalid_o ;
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input marready_i ;
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input [ 3:0] mrid_i ;
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input [ 31:0] mrdata_i ;
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input [ 1:0] mrresp_i ;
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input mrlast_i ;
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input mrvalid_i ;
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output mrready_o ;
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input shclk;
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input shresetn;
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input [ 3:0] sawid_i ;
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input [ 31:0] sawaddr_i ;
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input [ 3:0] sawlen_i ;
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input [ 2:0] sawsize_i ;
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input [ 1:0] sawburst_i ;
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input [ 1:0] sawlock_i ;
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input [ 3:0] sawcache_i ;
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input [ 2:0] sawprot_i ;
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input sawvalid_i ;
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output sawready_o ;
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input [ 3:0] swid_i ;
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input [ 31:0] swdata_i ;
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input [ 3:0] swstrb_i ;
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input swlast_i ;
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input swvalid_i ;
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output swready_o ;
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output [ 3:0] sbid_o ;
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output [ 1:0] sbresp_o ;
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output sbvalid_o ;
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input sbready_i ;
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input [ 3:0] sarid_i ;
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input [ 31:0] saraddr_i ;
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input [ 3:0] sarlen_i ;
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input [ 2:0] sarsize_i ;
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input [ 1:0] sarburst_i ;
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input [ 1:0] sarlock_i ;
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input [ 3:0] sarcache_i ;
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input [ 2:0] sarprot_i ;
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input sarvalid_i ;
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output sarready_o ;
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output [ 3:0] srid_o ;
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output [ 31:0] srdata_o ;
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output [ 1:0] srresp_o ;
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output srlast_o ;
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output srvalid_o ;
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input srready_i ;
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input [MAXIDATAWIDTH - 1:0] trdata;
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output twe;
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wire twe;
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output [TFIFODEPTH - 1:0] twaddr;
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wire [TFIFODEPTH - 1:0] twaddr;
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output [TFIFODEPTH - 1:0] traddr;
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wire [TFIFODEPTH - 1:0] traddr;
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output [MAXIDATAWIDTH - 1:0] twdata;
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wire [MAXIDATAWIDTH - 1:0] twdata;
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input [MAXIDATAWIDTH - 1:0] rrdata;
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output rwe;
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wire rwe;
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output [RFIFODEPTH - 1:0] rwaddr;
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wire [RFIFODEPTH - 1:0] rwaddr;
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output [RFIFODEPTH - 1:0] rraddr;
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wire [RFIFODEPTH - 1:0] rraddr;
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output [MAXIDATAWIDTH - 1:0] rwdata;
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wire [MAXIDATAWIDTH - 1:0] rwdata;
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input [15:0] frdata;
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output fwe;
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wire fwe;
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output [ADDRDEPTH - 1:0] fwaddr;
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wire [ADDRDEPTH - 1:0] fwaddr;
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output [ADDRDEPTH - 1:0] fraddr;
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wire [ADDRDEPTH - 1:0] fraddr;
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output [15:0] fwdata;
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wire [15:0] fwdata;
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input match;
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input matchval;
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output matchen;
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wire matchen;
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output [47:0] matchdata;
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wire [47:0] matchdata;
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input sdi;
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output sclk;
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wire sclk;
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output scs;
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wire scs;
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output sdo;
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wire sdo;
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input rxer;
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input rxdv;
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input col;
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input crs;
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input [MIIWIDTH - 1:0] rxd;
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output txen;
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wire txen;
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output txer;
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wire txer;
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output [MIIWIDTH - 1:0] txd;
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wire [MIIWIDTH - 1:0] txd;
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output mdc;
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wire mdc;
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input mdi;
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output mdo;
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wire mdo;
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output mden;
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wire mden;
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wire datareq;
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wire datareqc;
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wire datarw;
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wire dataeob;
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wire dataeobc;
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wire [(MAXIADDRESSWIDTH - 1):0] dataaddr;
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wire [(MAXIDATAWIDTH - 1):0] datao;
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wire dataack;
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wire [(MAXIDATAWIDTH - 1):0] datai;
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wire rstcsr;
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wire csrack;
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wire [SAXIDATAWIDTH - 1:0] csrdatao;
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wire csrreq;
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wire csrrw;
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wire [SAXIDATAWIDTH / 8 - 1:0] csrbe;
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wire [SAXIDATAWIDTH - 1:0] csrdatai;
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wire [7:0] csraddr;
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MAC
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#(SAXIDATAWIDTH,
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MAXIDATAWIDTH,
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MAXIADDRESSWIDTH,
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TFIFODEPTH,
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RFIFODEPTH,
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TCDEPTH,
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RCDEPTH)
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U_MAC (
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.clkdma (mhclk),
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.clkcsr (shclk),
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.clkt (clkt),
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.clkr (clkr),
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.rstcsr (rstcsr),
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.rsttco (rsttco),
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.rstrco (rstrco),
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.interrupt (interrupt),
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.rps (rps),
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.tps (tps),
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.csrreq (csrreq),
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.csrrw (csrrw),
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.csrbe (csrbe),
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.csrdatai (csrdatai),
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.csrack (csrack),
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.csraddr (csraddr),
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.csrdatao (csrdatao),
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.dataack (dataack),
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.datareq (datareq),
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.datareqc (datareqc),
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.datarw (datarw),
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.dataeob (dataeob),
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.dataeobc (dataeobc),
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.datai (datai),
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.dataaddr (dataaddr),
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.datao (datao),
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.trdata (trdata),
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.twe (twe),
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.twaddr (twaddr),
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.traddr (traddr),
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.twdata (twdata),
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.rrdata (rrdata),
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.rwe (rwe),
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.rwaddr (rwaddr),
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.rraddr (rraddr),
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.rwdata (rwdata),
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.frdata (frdata),
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.fwe (fwe),
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.fraddr (fraddr),
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.fwaddr (fwaddr),
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.fwdata (fwdata),
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.match (match),
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.matchval (matchval),
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.matchen (matchen),
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.matchdata (matchdata),
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.sdi (sdi),
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.sclk (sclk),
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.scs (scs),
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.sdo (sdo),
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.rxer (rxer),
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.rxdv (rxdv),
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.col (col),
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.crs (crs),
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.rxd (rxd),
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.txen (txen),
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.txer (txer),
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.txd (txd),
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.mdi (mdi),
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.mdo (mdo),
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.mden (mden),
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.mdc (mdc)
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);
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MAC2AXI
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#(MAXIDATAWIDTH,
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MAXIADDRESSWIDTH,
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SAXIDATAWIDTH,
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SAXIADDRESSWIDTH,
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MAXIDATAWIDTH,
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MAXIADDRESSWIDTH,
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SAXIDATAWIDTH,
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8)
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U_MAC2AXI (
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.mhclk (mhclk ),
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.mhresetn (mhresetn ),
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.shclk (shclk ),
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.shresetn (shresetn ),
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.mawid_o (mawid_o ),
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.mawaddr_o (mawaddr_o ),
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.mawlen_o (mawlen_o ),
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.mawsize_o (mawsize_o ),
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.mawburst_o (mawburst_o ),
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.mawlock_o (mawlock_o ),
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.mawcache_o (mawcache_o ),
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.mawprot_o (mawprot_o ),
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.mawvalid_o (mawvalid_o ),
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.mawready_i (mawready_i ),
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.mwid_o (mwid_o ),
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.mwdata_o (mwdata_o ),
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.mwstrb_o (mwstrb_o ),
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.mwlast_o (mwlast_o ),
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.mwvalid_o (mwvalid_o ),
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.mwready_i (mwready_i ),
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.mbid_i (mbid_i ),
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.mbresp_i (mbresp_i ),
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.mbvalid_i (mbvalid_i ),
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.mbready_o (mbready_o ),
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.marid_o (marid_o ),
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.maraddr_o (maraddr_o ),
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.marlen_o (marlen_o ),
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.marsize_o (marsize_o ),
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.marburst_o (marburst_o ),
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.marlock_o (marlock_o ),
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.marcache_o (marcache_o ),
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.marprot_o (marprot_o ),
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.marvalid_o (marvalid_o ),
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.marready_i (marready_i ),
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.mrid_i (mrid_i ),
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.mrdata_i (mrdata_i ),
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.mrresp_i (mrresp_i ),
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.mrlast_i (mrlast_i ),
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.mrvalid_i (mrvalid_i ),
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.mrready_o (mrready_o ),
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.sawid_i (sawid_i ),
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.sawaddr_i (sawaddr_i ),
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.sawlen_i (sawlen_i ),
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.sawsize_i (sawsize_i ),
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.sawburst_i (sawburst_i ),
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.sawlock_i (sawlock_i ),
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.sawcache_i (sawcache_i ),
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.sawprot_i (sawprot_i ),
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.sawvalid_i (sawvalid_i ),
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.sawready_o (sawready_o ),
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.swid_i (swid_i ),
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.swdata_i (swdata_i ),
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.swstrb_i (swstrb_i ),
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.swlast_i (swlast_i ),
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.swvalid_i (swvalid_i ),
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.swready_o (swready_o ),
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.sbid_o (sbid_o ),
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.sbresp_o (sbresp_o ),
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.sbvalid_o (sbvalid_o ),
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.sbready_i (sbready_i ),
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.sarid_i (sarid_i ),
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.saraddr_i (saraddr_i ),
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.sarlen_i (sarlen_i ),
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.sarsize_i (sarsize_i ),
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.sarburst_i (sarburst_i ),
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.sarlock_i (sarlock_i ),
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.sarcache_i (sarcache_i ),
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.sarprot_i (sarprot_i ),
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.sarvalid_i (sarvalid_i ),
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.sarready_o (sarready_o ),
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.srid_o (srid_o ),
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.srdata_o (srdata_o ),
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.srresp_o (srresp_o ),
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.srlast_o (srlast_o ),
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.srvalid_o (srvalid_o ),
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.srready_i (srready_i ),
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.datareq (datareq ),
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.datareqc (datareqc ),
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.datarw (datarw ),
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.dataeob (dataeob ),
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.dataeobc (dataeobc ),
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.dataaddr (dataaddr ),
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.datao (datao ),
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.dataack (dataack ),
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.datai (datai ),
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.rstcsr (rstcsr ),
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.csrack (csrack ),
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.csrdatao (csrdatao ),
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.csrreq (csrreq ),
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.csrrw (csrrw ),
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.csrbe (csrbe ),
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.csrdatai (csrdatai ),
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.csraddr (csraddr )
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);
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endmodule
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