369 lines
11 KiB
Verilog
369 lines
11 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module ethernet_top
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(
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hclk,
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hrst_,
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mawid_o ,
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mawaddr_o ,
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mawlen_o ,
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mawsize_o ,
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mawburst_o ,
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mawlock_o ,
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mawcache_o ,
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mawprot_o ,
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mawvalid_o ,
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mawready_i ,
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mwid_o ,
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mwdata_o ,
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mwstrb_o ,
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mwlast_o ,
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mwvalid_o ,
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mwready_i ,
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mbid_i ,
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mbresp_i ,
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mbvalid_i ,
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mbready_o ,
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marid_o ,
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maraddr_o ,
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marlen_o ,
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marsize_o ,
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marburst_o ,
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marlock_o ,
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marcache_o ,
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marprot_o ,
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marvalid_o ,
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marready_i ,
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mrid_i ,
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mrdata_i ,
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mrresp_i ,
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mrlast_i ,
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mrvalid_i ,
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mrready_o ,
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sawid_i ,
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sawaddr_i ,
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sawlen_i ,
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sawsize_i ,
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sawburst_i ,
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sawlock_i ,
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sawcache_i ,
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sawprot_i ,
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sawvalid_i ,
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sawready_o ,
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swid_i ,
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swdata_i ,
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swstrb_i ,
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swlast_i ,
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swvalid_i ,
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swready_o ,
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sbid_o ,
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sbresp_o ,
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sbvalid_o ,
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sbready_i ,
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sarid_i ,
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saraddr_i ,
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sarlen_i ,
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sarsize_i ,
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sarburst_i ,
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sarlock_i ,
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sarcache_i ,
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sarprot_i ,
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sarvalid_i ,
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sarready_o ,
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srid_o ,
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srdata_o ,
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srresp_o ,
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srlast_o ,
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srvalid_o ,
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srready_i ,
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interrupt_0,
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mtxclk_0,
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mtxen_0,
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mtxd_0,
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mtxerr_0,
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mrxclk_0,
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mrxdv_0,
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mrxd_0,
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mrxerr_0,
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mcoll_0,
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mcrs_0,
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mdc_0,
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md_i_0,
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md_o_0,
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md_oe_0
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);
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input hclk;
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input hrst_;
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output [ 3:0] mawid_o ;
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output [ 31:0] mawaddr_o ;
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output [ 3:0] mawlen_o ;
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output [ 2:0] mawsize_o ;
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output [ 1:0] mawburst_o ;
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output [ 1:0] mawlock_o ;
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output [ 3:0] mawcache_o ;
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output [ 2:0] mawprot_o ;
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output mawvalid_o ;
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input mawready_i ;
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output [ 3:0] mwid_o ;
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output [ 31:0] mwdata_o ;
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output [ 3:0] mwstrb_o ;
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output mwlast_o ;
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output mwvalid_o ;
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input mwready_i ;
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input [ 3:0] mbid_i ;
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input [ 1:0] mbresp_i ;
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input mbvalid_i ;
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output mbready_o ;
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output [ 3:0] marid_o ;
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output [ 31:0] maraddr_o ;
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output [ 3:0] marlen_o ;
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output [ 2:0] marsize_o ;
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output [ 1:0] marburst_o ;
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output [ 1:0] marlock_o ;
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output [ 3:0] marcache_o ;
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output [ 2:0] marprot_o ;
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output marvalid_o ;
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input marready_i ;
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input [ 3:0] mrid_i ;
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input [ 31:0] mrdata_i ;
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input [ 1:0] mrresp_i ;
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input mrlast_i ;
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input mrvalid_i ;
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output mrready_o ;
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input [ 3:0] sawid_i ;
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input [ 31:0] sawaddr_i ;
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input [ 3:0] sawlen_i ;
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input [ 2:0] sawsize_i ;
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input [ 1:0] sawburst_i ;
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input [ 1:0] sawlock_i ;
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input [ 3:0] sawcache_i ;
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input [ 2:0] sawprot_i ;
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input sawvalid_i ;
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output sawready_o ;
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input [ 3:0] swid_i ;
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input [ 31:0] swdata_i ;
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input [ 3:0] swstrb_i ;
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input swlast_i ;
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input swvalid_i ;
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output swready_o ;
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output [ 3:0] sbid_o ;
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output [ 1:0] sbresp_o ;
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output sbvalid_o ;
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input sbready_i ;
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input [ 3:0] sarid_i ;
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input [ 31:0] saraddr_i ;
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input [ 3:0] sarlen_i ;
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input [ 2:0] sarsize_i ;
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input [ 1:0] sarburst_i ;
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input [ 1:0] sarlock_i ;
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input [ 3:0] sarcache_i ;
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input [ 2:0] sarprot_i ;
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input sarvalid_i ;
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output sarready_o ;
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output [ 3:0] srid_o ;
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output [ 31:0] srdata_o ;
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output [ 1:0] srresp_o ;
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output srlast_o ;
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output srvalid_o ;
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input srready_i ;
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input mtxclk_0;
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output [3:0] mtxd_0;
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output mtxen_0;
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output mtxerr_0;
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input mrxclk_0;
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input [3:0] mrxd_0;
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input mrxdv_0;
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input mrxerr_0;
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input mcoll_0;
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input mcrs_0;
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input md_i_0;
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output mdc_0;
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output md_o_0;
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output md_oe_0;
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output interrupt_0;
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`define MAHBDATAWIDTH 32
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`define TFIFODEPTH 9
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`define RFIFODEPTH 9
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`define ADDRDEPTH 6
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wire [`MAHBDATAWIDTH - 1:0] trdata_0;
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wire twe_0;
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wire [`TFIFODEPTH - 1:0] twaddr_0;
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wire [`TFIFODEPTH - 1:0] traddr_0;
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wire [`MAHBDATAWIDTH - 1:0] twdata_0;
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wire [`MAHBDATAWIDTH - 1:0] rrdata_0;
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wire rwe_0;
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wire [`RFIFODEPTH - 1:0] rwaddr_0;
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wire [`RFIFODEPTH - 1:0] rraddr_0;
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wire [`MAHBDATAWIDTH - 1:0] rwdata_0;
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mac_top u_mac_top_0
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(
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.hclk(hclk),
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.hrst_(hrst_),
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.mawid_o (mawid_o ),
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.mawaddr_o (mawaddr_o ),
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.mawlen_o (mawlen_o ),
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.mawsize_o (mawsize_o ),
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.mawburst_o (mawburst_o ),
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.mawlock_o (mawlock_o ),
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.mawcache_o (mawcache_o ),
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.mawprot_o (mawprot_o ),
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.mawvalid_o (mawvalid_o ),
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.mawready_i (mawready_i ),
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.mwid_o (mwid_o ),
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.mwdata_o (mwdata_o ),
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.mwstrb_o (mwstrb_o ),
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.mwlast_o (mwlast_o ),
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.mwvalid_o (mwvalid_o ),
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.mwready_i (mwready_i ),
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.mbid_i (mbid_i ),
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.mbresp_i (mbresp_i ),
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.mbvalid_i (mbvalid_i ),
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.mbready_o (mbready_o ),
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.marid_o (marid_o ),
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.maraddr_o (maraddr_o ),
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.marlen_o (marlen_o ),
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.marsize_o (marsize_o ),
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.marburst_o (marburst_o ),
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.marlock_o (marlock_o ),
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.marcache_o (marcache_o ),
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.marprot_o (marprot_o ),
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.marvalid_o (marvalid_o ),
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.marready_i (marready_i ),
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.mrid_i (mrid_i ),
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.mrdata_i (mrdata_i ),
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.mrresp_i (mrresp_i ),
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.mrlast_i (mrlast_i ),
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.mrvalid_i (mrvalid_i ),
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.mrready_o (mrready_o ),
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.sawid_i (sawid_i ),
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.sawaddr_i (sawaddr_i ),
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.sawlen_i (sawlen_i ),
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.sawsize_i (sawsize_i ),
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.sawburst_i (sawburst_i ),
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.sawlock_i (sawlock_i ),
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.sawcache_i (sawcache_i ),
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.sawprot_i (sawprot_i ),
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.sawvalid_i (sawvalid_i ),
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.sawready_o (sawready_o ),
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.swid_i (swid_i ),
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.swdata_i (swdata_i ),
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.swstrb_i (swstrb_i ),
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.swlast_i (swlast_i ),
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.swvalid_i (swvalid_i ),
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.swready_o (swready_o ),
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.sbid_o (sbid_o ),
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.sbresp_o (sbresp_o ),
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.sbvalid_o (sbvalid_o ),
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.sbready_i (sbready_i ),
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.sarid_i (sarid_i ),
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.saraddr_i (saraddr_i ),
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.sarlen_i (sarlen_i ),
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.sarsize_i (sarsize_i ),
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.sarburst_i (sarburst_i ),
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.sarlock_i (sarlock_i ),
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.sarcache_i (sarcache_i ),
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.sarprot_i (sarprot_i ),
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.sarvalid_i (sarvalid_i ),
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.sarready_o (sarready_o ),
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.srid_o (srid_o ),
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.srdata_o (srdata_o ),
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.srresp_o (srresp_o ),
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.srlast_o (srlast_o ),
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.srvalid_o (srvalid_o ),
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.srready_i (srready_i ),
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.interrupt(interrupt_0),
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.mtxclk(mtxclk_0), .mtxen(mtxen_0), .mtxd(mtxd_0), .mtxerr(mtxerr_0),
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.mrxclk(mrxclk_0), .mrxdv(mrxdv_0), .mrxd(mrxd_0), .mrxerr(mrxerr_0),
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.mcoll(mcoll_0), .mcrs(mcrs_0),
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.mdc(mdc_0), .md_i(md_i_0), .md_o(md_o_0), .md_oe(md_oe_0),
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.trdata(trdata_0),
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.twe(twe_0),
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.twaddr(twaddr_0),
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.traddr(traddr_0),
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.twdata(twdata_0),
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.rrdata(rrdata_0),
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.rwe(rwe_0),
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.rwaddr(rwaddr_0),
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.rraddr(rraddr_0),
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.rwdata(rwdata_0)
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);
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wire [31:0] douta_nc;
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dpram_512x32 dpram_512x32_tx(
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.clka (hclk ),
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.ena (twe_0 ),
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.wea (twe_0 ),
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.addra (twaddr_0),
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.dina (twdata_0),
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.clkb (mtxclk_0),
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.addrb (traddr_0),
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.doutb (trdata_0)
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);
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wire [31:0] doutb_nc;
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dpram_512x32 dpram_512x32_rx(
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.clka (mrxclk_0),
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.ena (rwe_0 ),
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.wea (rwe_0 ),
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.addra (rwaddr_0),
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.dina (rwdata_0),
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.clkb (hclk ),
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.addrb (rraddr_0),
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.doutb (rrdata_0)
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);
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endmodule
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