417 lines
13 KiB
Verilog
417 lines
13 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`include "config.h"
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module axi2apb_misc
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(
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clk,
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rst_n,
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axi_s_awid,
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axi_s_awaddr,
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axi_s_awlen,
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axi_s_awsize,
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axi_s_awburst,
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axi_s_awlock,
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axi_s_awcache,
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axi_s_awprot,
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axi_s_awvalid,
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axi_s_awready,
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axi_s_wid,
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axi_s_wdata,
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axi_s_wstrb,
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axi_s_wlast,
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axi_s_wvalid,
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axi_s_wready,
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axi_s_bid,
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axi_s_bresp,
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axi_s_bvalid,
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axi_s_bready,
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axi_s_arid,
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axi_s_araddr,
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axi_s_arlen,
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axi_s_arsize,
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axi_s_arburst,
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axi_s_arlock,
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axi_s_arcache,
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axi_s_arprot,
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axi_s_arvalid,
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axi_s_arready,
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axi_s_rid,
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axi_s_rdata,
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axi_s_rresp,
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axi_s_rlast,
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axi_s_rvalid,
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axi_s_rready,
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apb_rw_dma,
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apb_psel_dma,
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apb_enab_dma,
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apb_addr_dma,
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apb_valid_dma,
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apb_wdata_dma,
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apb_rdata_dma,
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apb_ready_dma,
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dma_grant,
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dma_req_o,
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dma_ack_i,
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uart0_txd_i,
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uart0_txd_o,
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uart0_txd_oe,
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uart0_rxd_i,
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uart0_rxd_o,
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uart0_rxd_oe,
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uart0_rts_o,
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uart0_dtr_o,
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uart0_cts_i,
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uart0_dsr_i,
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uart0_dcd_i,
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uart0_ri_i,
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uart0_int,
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nand_int,
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nand_type,
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nand_cle ,
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nand_ale ,
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nand_rdy ,
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nand_rd ,
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nand_ce,
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nand_wr ,
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nand_dat_i ,
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nand_dat_o ,
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nand_dat_oe
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);
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parameter ADDR_APB = 20,
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DATA_APB = 8,
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L_ADDR = 64,
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L_ID = 8,
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L_DATA = 128,
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L_MASK = 16;
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input clk;
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input rst_n;
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input [`LID -1 :0] axi_s_awid;
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input [`Lawaddr -1 :0] axi_s_awaddr;
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input [`Lawlen -1 :0] axi_s_awlen;
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input [`Lawsize -1 :0] axi_s_awsize;
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input [`Lawburst -1 :0] axi_s_awburst;
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input [`Lawlock -1 :0] axi_s_awlock;
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input [`Lawcache -1 :0] axi_s_awcache;
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input [`Lawprot -1 :0] axi_s_awprot;
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input axi_s_awvalid;
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output axi_s_awready;
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input [`LID -1 :0] axi_s_wid;
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input [`Lwdata -1 :0] axi_s_wdata;
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input [`Lwstrb -1 :0] axi_s_wstrb;
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input axi_s_wlast;
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input axi_s_wvalid;
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output axi_s_wready;
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output [`LID -1 :0] axi_s_bid;
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output [`Lbresp -1 :0] axi_s_bresp;
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output axi_s_bvalid;
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input axi_s_bready;
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input [`LID -1 :0] axi_s_arid;
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input [`Laraddr -1 :0] axi_s_araddr;
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input [`Larlen -1 :0] axi_s_arlen;
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input [`Larsize -1 :0] axi_s_arsize;
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input [`Larburst -1 :0] axi_s_arburst;
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input [`Larlock -1 :0] axi_s_arlock;
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input [`Larcache -1 :0] axi_s_arcache;
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input [`Larprot -1 :0] axi_s_arprot;
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input axi_s_arvalid;
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output axi_s_arready;
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output [`LID -1 :0] axi_s_rid;
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output [`Lrdata -1 :0] axi_s_rdata;
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output [`Lrresp -1 :0] axi_s_rresp;
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output axi_s_rlast;
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output axi_s_rvalid;
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input axi_s_rready;
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output apb_ready_dma;
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input apb_rw_dma;
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input apb_psel_dma;
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input apb_enab_dma;
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input [ADDR_APB-1:0] apb_addr_dma;
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input [31:0] apb_wdata_dma;
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output[31:0] apb_rdata_dma;
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input apb_valid_dma;
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output dma_grant;
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output dma_req_o;
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input dma_ack_i;
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input uart0_txd_i;
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output uart0_txd_o;
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output uart0_txd_oe;
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input uart0_rxd_i;
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output uart0_rxd_o;
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output uart0_rxd_oe;
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output uart0_rts_o;
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output uart0_dtr_o;
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input uart0_cts_i;
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input uart0_dsr_i;
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input uart0_dcd_i;
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input uart0_ri_i;
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input [3:0]nand_rdy;
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output [3:0]nand_ce;
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output nand_cle;
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output nand_ale;
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output nand_rd;
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output nand_wr;
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output nand_dat_oe;
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input [7:0]nand_dat_i ;
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output [7:0]nand_dat_o ;
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output uart0_int;
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output nand_int;
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input [1:0]nand_type;
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wire nand_dma_req_o;
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assign dma_req_o = nand_dma_req_o;
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assign nand_dma_ack_i = dma_ack_i;
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wire apb_ready_cpu;
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wire apb_rw_cpu;
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wire apb_psel_cpu;
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wire apb_enab_cpu;
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wire [ADDR_APB-1 :0] apb_addr_cpu;
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wire [DATA_APB-1:0] apb_datai_cpu;
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wire [DATA_APB-1:0] apb_datao_cpu;
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wire apb_clk_cpu;
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wire apb_reset_n_cpu;
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wire apb_word_trans_cpu;
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wire apb_valid_cpu;
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wire dma_grant;
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wire [23:0] apb_high_24b_rd;
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wire [23:0] apb_high_24b_wr;
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wire apb_rw_dma;
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wire apb_psel_dma;
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wire apb_enab_dma;
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wire [31:0] apb_wdata_dma;
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wire [31:0] apb_rdata_dma;
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wire apb_clk_dma;
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wire apb_reset_n_dma;
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wire apb_uart0_req;
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wire apb_uart0_ack;
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wire apb_uart0_rw;
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wire apb_uart0_enab;
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wire apb_uart0_psel;
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wire [ADDR_APB -1:0] apb_uart0_addr;
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wire [DATA_APB -1:0] apb_uart0_datai;
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wire [DATA_APB -1:0] apb_uart0_datao;
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wire apb_nand_req;
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wire apb_nand_ack;
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wire apb_nand_rw;
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wire apb_nand_enab;
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wire apb_nand_psel;
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wire [ADDR_APB -1:0] apb_nand_addr;
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wire [31:0] apb_nand_datai;
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wire [31:0] apb_nand_datao;
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axi2apb_bridge AA_axi2apb_bridge_cpu
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(
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.clk (clk ),
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.rst_n (rst_n ),
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.axi_s_awid (axi_s_awid ),
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.axi_s_awaddr (axi_s_awaddr ),
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.axi_s_awlen (axi_s_awlen ),
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.axi_s_awsize (axi_s_awsize ),
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.axi_s_awburst (axi_s_awburst ),
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.axi_s_awlock (axi_s_awlock ),
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.axi_s_awcache (axi_s_awcache ),
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.axi_s_awprot (axi_s_awprot ),
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.axi_s_awvalid (axi_s_awvalid ),
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.axi_s_awready (axi_s_awready ),
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.axi_s_wid (axi_s_wid ),
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.axi_s_wdata (axi_s_wdata ),
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.axi_s_wstrb (axi_s_wstrb ),
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.axi_s_wlast (axi_s_wlast ),
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.axi_s_wvalid (axi_s_wvalid ),
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.axi_s_wready (axi_s_wready ),
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.axi_s_bid (axi_s_bid ),
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.axi_s_bresp (axi_s_bresp ),
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.axi_s_bvalid (axi_s_bvalid ),
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.axi_s_bready (axi_s_bready ),
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.axi_s_arid (axi_s_arid ),
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.axi_s_araddr (axi_s_araddr ),
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.axi_s_arlen (axi_s_arlen ),
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.axi_s_arsize (axi_s_arsize ),
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.axi_s_arburst (axi_s_arburst ),
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.axi_s_arlock (axi_s_arlock ),
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.axi_s_arcache (axi_s_arcache ),
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.axi_s_arprot (axi_s_arprot ),
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.axi_s_arvalid (axi_s_arvalid ),
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.axi_s_arready (axi_s_arready ),
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.axi_s_rid (axi_s_rid ),
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.axi_s_rdata (axi_s_rdata ),
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.axi_s_rresp (axi_s_rresp ),
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.axi_s_rlast (axi_s_rlast ),
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.axi_s_rvalid (axi_s_rvalid ),
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.axi_s_rready (axi_s_rready ),
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.apb_word_trans (apb_word_trans_cpu ),
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.apb_high_24b_rd (apb_high_24b_rd ),
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.apb_high_24b_wr (apb_high_24b_wr ),
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.apb_valid_cpu (apb_valid_cpu ),
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.cpu_grant (~dma_grant ),
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.apb_clk (apb_clk_cpu ),
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.apb_reset_n (apb_reset_n_cpu ),
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.reg_psel (apb_psel_cpu ),
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.reg_enable (apb_enab_cpu ),
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.reg_rw (apb_rw_cpu ),
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.reg_addr (apb_addr_cpu ),
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.reg_datai (apb_datai_cpu ),
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.reg_datao (apb_datao_cpu ),
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.reg_ready_1 (apb_ready_cpu )
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);
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apb_mux2 AA_apb_mux16
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(
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.clk (clk ),
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.rst_n (rst_n ),
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.apb_ready_dma (apb_ready_dma ),
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.apb_rw_dma (apb_rw_dma ),
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.apb_addr_dma (apb_addr_dma ),
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.apb_psel_dma (apb_psel_dma ),
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.apb_enab_dma (apb_enab_dma ),
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.apb_wdata_dma (apb_wdata_dma ),
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.apb_rdata_dma (apb_rdata_dma ),
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.apb_valid_dma (apb_valid_dma ),
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.apb_valid_cpu (apb_valid_cpu ),
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.dma_grant (dma_grant ),
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.apb_ack_cpu (apb_ready_cpu ),
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.apb_rw_cpu (apb_rw_cpu ),
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.apb_addr_cpu (apb_addr_cpu ),
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.apb_psel_cpu (apb_psel_cpu ),
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.apb_enab_cpu (apb_enab_cpu ),
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.apb_datai_cpu (apb_datai_cpu ),
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.apb_datao_cpu (apb_datao_cpu ),
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.apb_high_24b_rd (apb_high_24b_rd),
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.apb_high_24b_wr (apb_high_24b_wr),
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.apb_word_trans_cpu (apb_word_trans_cpu ),
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.apb0_req (apb_uart0_req ),
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.apb0_ack (apb_uart0_ack ),
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.apb0_rw (apb_uart0_rw ),
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.apb0_psel (apb_uart0_psel ),
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.apb0_enab (apb_uart0_enab ),
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.apb0_addr (apb_uart0_addr ),
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.apb0_datai (apb_uart0_datai ),
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.apb0_datao (apb_uart0_datao ),
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.apb1_req (apb_nand_req ),
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.apb1_ack (apb_nand_ack ),
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.apb1_rw (apb_nand_rw ),
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.apb1_enab (apb_nand_enab ),
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.apb1_psel (apb_nand_psel ),
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.apb1_addr (apb_nand_addr ),
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.apb1_datai (apb_nand_datai ),
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.apb1_datao (apb_nand_datao )
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);
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//uart0
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assign apb_uart0_ack = apb_uart0_enab;
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UART_TOP uart0
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(
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.PCLK (clk ),
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.clk_carrier (1'b0 ),
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.PRST_ (rst_n ),
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.PSEL (apb_uart0_psel ),
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.PENABLE (apb_uart0_enab ),
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.PADDR (apb_uart0_addr[7:0] ),
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.PWRITE (apb_uart0_rw ),
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.PWDATA (apb_uart0_datai ),
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.URT_PRDATA (apb_uart0_datao ),
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.INT (uart0_int ),
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.TXD_o (uart0_txd_o ),
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.TXD_i (uart0_txd_i ),
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.TXD_oe (uart0_txd_oe ),
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.RXD_o (uart0_rxd_o ),
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.RXD_i (uart0_rxd_i ),
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.RXD_oe (uart0_rxd_oe ),
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.RTS (uart0_rts_o ),
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.CTS (uart0_cts_i ),
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.DSR (uart0_dsr_i ),
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.DCD (uart0_dcd_i ),
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.DTR (uart0_dtr_o ),
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.RI (uart0_ri_i )
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);
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//NAND
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nand_module nand_module
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(
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.nand_type (nand_type ),
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.clk (clk ),
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.rst_n (rst_n ),
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.apb_psel (apb_nand_psel ),
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.apb_enab (apb_nand_enab ),
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.apb_rw (apb_nand_rw ),
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.apb_addr (apb_nand_addr ),
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.apb_datai (apb_nand_datai ),
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.apb_datao (apb_nand_datao ),
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.apb_ack (apb_nand_ack ),
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.nand_dma_req_o (nand_dma_req_o ),
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.nand_dma_ack_i (nand_dma_ack_i ),
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.nand_ce (nand_ce ),
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.nand_dat_i (nand_dat_i ),
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.nand_dat_o (nand_dat_o ),
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.nand_dat_oe (nand_dat_oe ),
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.nand_ale (nand_ale ),
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.nand_cle (nand_cle ),
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.nand_wr (nand_wr ),
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.nand_rd (nand_rd ),
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.nand_rdy (nand_rdy ),
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.nand_int (nand_int )
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);
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endmodule
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