MIPS/sim/config.vlt
Paul Pan 7b33e4213a a big update
1. add test soft
2. modify verilator (TODO: crossbar need to replace)
3. fix CP0: now CU0 is always 1
4. Controller: cacheop
5. Controller: fix TEN
6. mycpu_top fix CP0_i
7. fix AXI.sv
8. fix AXIReader.sv
9. fix AXIWriter.sv: getting the correct data and length
10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
2022-07-29 18:25:58 +08:00

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`verilator_config
lint_off -rule TIMESCALEMOD
lint_off -rule DECLFILENAME
lint_off -rule INITIALDLY
lint_off -file "model/*.v"
lint_off -file "../resources/func_test/*.v"
lint_off -rule UNOPTFLAT -file "model/axi_crossbar_addr.v"
lint_off -rule UNOPTFLAT -file "model/priority_encoder.v"
lint_off -rule BLKSEQ -file "../src/CP0/CP0.sv"
lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv"
lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv"