17 lines
330 B
Verilog
17 lines
330 B
Verilog
module ICData_bram (
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input [ 5:0] addra,
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input clka,
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input [255:0] dina,
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output reg [255:0] douta,
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input wea
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);
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reg [255:0] ram [0:63];
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always @(posedge clka) begin
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if(wea) begin
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ram[addra] <= dina;
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end
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douta <= ~wea ? ram[addra] : {8{$random}};
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end
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endmodule
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