18 lines
304 B
Verilog
18 lines
304 B
Verilog
module ICTag_bram (
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input [ 5:0] addra,
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input clka,
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input [21:0] dina,
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output [21:0] douta,
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input wea
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);
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reg [21:0] ram [0:63];
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always @(posedge CLK) begin
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if(wea) begin
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ram[addra] <= dina;
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end
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douta <= ~wea ? ram[addra] : {21{$random}};
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end
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endmodule
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