15 lines
221 B
Systemverilog
15 lines
221 B
Systemverilog
`include "defines.svh"
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module mul_signed(
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input logic CLK,
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input logic [31:0] A,
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input logic [31:0] B,
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output logic [63:0] P
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);
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always_ff @(posedge CLK)
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P <= $signed(A) * $signed(B);
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endmodule
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