309 lines
10 KiB
Systemverilog
309 lines
10 KiB
Systemverilog
`timescale 1ns / 1ps
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`define SIMULATION_PC
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`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
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`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
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//`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
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`define CONFREG_OPEN_TRACE 1'b0
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`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
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`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
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`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
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`define END_PC 32'hbfc00100
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module tb2_top ();
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logic resetn;
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logic clk;
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//goio
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logic [15:0] led;
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logic [1:0] led_rg0;
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logic [1:0] led_rg1;
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logic [7:0] num_csn;
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logic [6:0] num_a_g;
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logic [7:0] switch;
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logic [3:0] btn_key_col;
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logic [3:0] btn_key_row;
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logic [1:0] btn_step;
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assign switch = 8'hff;
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assign btn_key_row = 4'd0;
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assign btn_step = 2'd3;
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initial begin
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// $dumpfile("dump.vcd");
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// $dumpvars();
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resetn = 1'b0;
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#2000;
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resetn = 1'b1;
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end
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initial begin
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clk = 1'b0;
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forever begin
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#5 clk = ~clk;
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end
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end
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soc_axi_lite_top #(
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.SIMULATION(1'b1)
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) soc_lite (
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.resetn(resetn),
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.clk (clk),
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//------gpio-------
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.num_csn (num_csn),
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.num_a_g (num_a_g),
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.led (led),
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.led_rg0 (led_rg0),
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.led_rg1 (led_rg1),
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.switch (switch),
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.btn_key_col(btn_key_col),
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.btn_key_row(btn_key_row),
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.btn_step (btn_step)
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);
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//"cpu_clk" means cpu core clk
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//"sys_clk" means system clk
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//"wb" means write-back stage in pipeline
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//"rf" means regfiles in cpu
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//"w" in "wen/wnum/wdata" means writing
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logic cpu_clk;
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logic sys_clk;
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logic [31:0] debug_wb_pc;
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logic [3:0] debug_wb_rf_wen;
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logic [4:0] debug_wb_rf_wnum;
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logic [31:0] debug_wb_rf_wdata;
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logic [31:0] debug_wb1_pc;
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logic [3:0] debug_wb1_rf_wen;
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logic [4:0] debug_wb1_rf_wnum;
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logic [31:0] debug_wb1_rf_wdata;
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logic debug_wb_pc_A;
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assign cpu_clk = soc_lite.cpu_clk;
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assign sys_clk = soc_lite.sys_clk;
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assign debug_wb_pc = soc_lite.debug_wb_pc;
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assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
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assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
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assign debug_wb_rf_wdata = soc_lite.debug_wb_rf_wdata;
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assign debug_wb1_pc = soc_lite.u_cpu.debug_wb1_pc;
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assign debug_wb1_rf_wen = soc_lite.u_cpu.debug_wb1_rf_wen;
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assign debug_wb1_rf_wnum = soc_lite.u_cpu.debug_wb1_rf_wnum;
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assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
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assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A;
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// open the trace file;
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integer trace_ref;
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initial begin
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trace_ref = $fopen(`TRACE_REF_FILE, "r");
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end
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//get reference result in falling edge
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logic debug_end;
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logic trace_cmp_flag;
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logic [31:0] ref_wb_pc;
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logic [4:0] ref_wb_rf_wnum;
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logic [31:0] ref_wb_rf_wdata;
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typedef struct packed {
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logic trace_cmp_flag;
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logic [31:0] ref_wb_pc;
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logic [4:0] ref_wb_rf_wnum;
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logic [31:0] ref_wb_rf_wdata;
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logic [31:0] lineno;
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} TRACE_INFO;
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TRACE_INFO ref_trace[$];
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logic [31:0] lineno;
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initial begin
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lineno = 0;
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while (!$feof(
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trace_ref
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)) begin
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lineno = lineno + 1;
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$fscanf(trace_ref, "%h %h %h %h", trace_cmp_flag, ref_wb_pc, ref_wb_rf_wnum, ref_wb_rf_wdata);
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if (trace_cmp_flag == 1) begin
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ref_trace.push_back({trace_cmp_flag, ref_wb_pc, ref_wb_rf_wnum, ref_wb_rf_wdata, lineno});
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end
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end
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end
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//compare result in rsing edge
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logic debug_wb_err;
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logic dbg_0_rf_wen;
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logic [31:0] dbg_0_pc;
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logic [ 4:0] dbg_0_rf_wnum;
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logic [31:0] dbg_0_rf_wdata;
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logic dbg_1_rf_wen;
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logic [31:0] dbg_1_pc;
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logic [ 4:0] dbg_1_rf_wnum;
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logic [31:0] dbg_1_rf_wdata;
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always @(posedge cpu_clk) begin
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#2;
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if (!resetn) begin
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debug_wb_err <= 1'b0;
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end else if (!debug_end) begin
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if (debug_wb_pc_A) begin
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dbg_0_rf_wen <= debug_wb1_rf_wen;
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dbg_0_pc <= debug_wb1_pc;
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dbg_0_rf_wnum <= debug_wb1_rf_wnum;
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dbg_0_rf_wdata <= debug_wb1_rf_wdata;
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dbg_1_rf_wen <= debug_wb_rf_wen;
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dbg_1_pc <= debug_wb_pc;
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dbg_1_rf_wnum <= debug_wb_rf_wnum;
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dbg_1_rf_wdata <= debug_wb_rf_wdata;
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end else begin
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dbg_1_rf_wen <= debug_wb1_rf_wen;
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dbg_1_pc <= debug_wb1_pc;
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dbg_1_rf_wnum <= debug_wb1_rf_wnum;
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dbg_1_rf_wdata <= debug_wb1_rf_wdata;
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dbg_0_rf_wen <= debug_wb_rf_wen;
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dbg_0_pc <= debug_wb_pc;
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dbg_0_rf_wnum <= debug_wb_rf_wnum;
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dbg_0_rf_wdata <= debug_wb_rf_wdata;
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end
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if (|dbg_0_rf_wen && `CONFREG_OPEN_TRACE) begin
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$display("mycpu0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
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dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
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end
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if (|dbg_1_rf_wen && `CONFREG_OPEN_TRACE) begin
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$display("mycpu1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
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dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
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end
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if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
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if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
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|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
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|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
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)
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begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error!!!", $time);
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$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, lineno = %d",
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ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
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ref_trace[0].ref_wb_rf_wdata, ref_trace[0].lineno);
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$display(" mycpu0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_0_pc,
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dbg_0_rf_wnum, dbg_0_rf_wdata);
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$display(" mycpu1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_1_pc,
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dbg_1_rf_wnum, dbg_1_rf_wdata);
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$display("--------------------------------------------------------------");
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debug_wb_err <= 1'b1;
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#40;
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$finish;
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end else ref_trace.pop_front();
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end
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if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
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if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
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|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
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|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
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)
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begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error!!!", $time);
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$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, lineno = %d",
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ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
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ref_trace[0].ref_wb_rf_wdata, ref_trace[0].lineno);
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$display(" mycpu0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_0_pc,
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dbg_0_rf_wnum, dbg_0_rf_wdata);
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$display(" mycpu1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_1_pc,
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dbg_1_rf_wnum, dbg_1_rf_wdata);
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$display("--------------------------------------------------------------");
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debug_wb_err <= 1'b1;
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#40;
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$finish;
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end else ref_trace.pop_front();
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end
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end
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end
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//monitor numeric display
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logic [ 7:0] err_count;
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wire [31:0] confreg_num_reg = `CONFREG_NUM_REG;
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logic [31:0] confreg_num_reg_r;
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always_ff @(posedge sys_clk) begin
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confreg_num_reg_r <= confreg_num_reg;
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if (!resetn) begin
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err_count <= 8'd0;
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end else if (confreg_num_reg_r != confreg_num_reg && `CONFREG_NUM_MONITOR) begin
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if (confreg_num_reg[7:0] != confreg_num_reg_r[7:0] + 1'b1) begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error(%d)!!! Occurred in number 8'd%02d Functional Test Point!", $time,
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err_count, confreg_num_reg[31:24]);
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$display("--------------------------------------------------------------");
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err_count <= err_count + 1'b1;
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$finish;
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end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error(%d)!!! Unknown, Functional Test Point numbers are unequal!", $time,
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err_count);
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$display("--------------------------------------------------------------");
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$display("==============================================================");
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err_count <= err_count + 1'b1;
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$finish;
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end else begin
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$display("----[%t] Number 8'd%02d Functional Test Point PASS!!!", $time,
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confreg_num_reg[31:24]);
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end
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end
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end
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//monitor test
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initial begin
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$timeformat(-9, 0, " ns", 10);
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while (!resetn) #5;
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$display("==============================================================");
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$display("Test begin!");
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#10000;
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while (`CONFREG_NUM_MONITOR) begin
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#10000;
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$display(" [%t] Test is running, dbg_0_pc = 0x%8h, dbg_1_pc = 0x%8h", $time, dbg_0_pc,
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dbg_1_pc);
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end
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end
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// Uart Display
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logic uart_display;
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logic [7:0] uart_data;
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assign uart_display = `CONFREG_UART_DISPLAY;
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assign uart_data = `CONFREG_UART_DATA;
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always_ff @(posedge sys_clk) begin
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if (uart_display) begin
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if (uart_data == 8'hff) begin
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; //$finish;
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end else begin
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$write("%c", uart_data);
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end
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end
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end
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//test end
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wire global_err = debug_wb_err || (err_count != 8'd0);
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wire test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff);
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always @(posedge cpu_clk) begin
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if (!resetn) begin
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debug_end <= 1'b0;
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end else if (test_end && !debug_end) begin
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debug_end <= 1'b1;
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$display("==============================================================");
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$display("Test end!");
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#40;
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$fclose(trace_ref);
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if (global_err) begin
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$display("Fail!!!Total %d errors!", err_count);
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end else begin
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$display("----PASS!!!");
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end
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$finish;
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end
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end
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endmodule
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