30 lines
863 B
Verilog
30 lines
863 B
Verilog
module div_signed(
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input clk,
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input s_axis_dividend_tvalid,
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input [31:0] s_axis_dividend_tdata,
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input s_axis_divisor_tvalid,
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input [31:0] s_axis_divisor_tdata,
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output m_axis_dout_tvalid,
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output [63:0] m_axis_dout_tdata
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);
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reg valid, nxtValid;
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reg [63:0] data, nxtData;
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assign m_axis_dout_tvalid = nxtValid;
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assign m_axis_dout_tdata = nxtData;
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always @(posedge clk) begin
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nxtValid <= valid;
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nxtData <= data;
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if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin
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valid <= 1'b1;
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data <= {
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$signed(s_axis_divisor_tdata) % $signed(s_axis_dividend_tdata),
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$signed(s_axis_divisor_tdata) / $signed(s_axis_dividend_tdata)
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};
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end
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end
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endmodule |