25 lines
652 B
Tcl
25 lines
652 B
Tcl
# TODO: test whether it works
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set outputDir ./vivado
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# Add Source
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read_verilog -sv [ glob ./src/**/*.sv ]
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read_verilog -sv [ glob ../src/**/*.sv ]
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read_checkpoint ./src/lcd_module.dcp
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read_ip [ glob ./ip/*.xci ]
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read_xdc ./constraints.xdc
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# Run
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synth_design -top [lindex [find_top] 0] -part xc7a200tfbg676-2
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opt_design
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place_design
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phys_opt_design
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route_design
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# Report
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report_timing_summary -file $outputDir/post_route_timing_summary.rpt
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report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
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report_utilization -file $outputDir/post_route_util.rpt
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# Bitstream
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write_bitstream $outputDir/awesome.bit
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