23 lines
599 B
Systemverilog
23 lines
599 B
Systemverilog
`include "defines.svh"
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module mul_signed(
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input logic CLK,
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input word_t A,
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input word_t B,
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output logic [63:0] P
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);
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word_t A1, A2, A3, A4, A5, A6;
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word_t B1, B2, B3, B4, B5, B6;
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ffen #(64) ff_1 (CLK, { A, B}, 1'b1, {A1, B1});
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ffen #(64) ff_2 (CLK, {A1, B1}, 1'b1, {A2, B2});
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ffen #(64) ff_3 (CLK, {A2, B2}, 1'b1, {A3, B3});
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ffen #(64) ff_4 (CLK, {A3, B3}, 1'b1, {A4, B4});
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ffen #(64) ff_5 (CLK, {A4, B4}, 1'b1, {A5, B5});
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ffen #(64) ff_6 (CLK, {A5, B5}, 1'b1, {A6, B6});
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assign P = $signed(A) * $signed(B);
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endmodule
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