MIPS/model/div_unsigned.v
2021-09-24 16:37:47 +08:00

31 lines
876 B
Verilog

module div_unsigned(
input aclk,
input s_axis_dividend_tvalid,
input [31:0] s_axis_dividend_tdata,
input s_axis_divisor_tvalid,
input [31:0] s_axis_divisor_tdata,
output m_axis_dout_tvalid,
output [63:0] m_axis_dout_tdata
);
reg valid, nxtValid;
reg [63:0] data, nxtData;
assign m_axis_dout_tvalid = nxtValid;
assign m_axis_dout_tdata = nxtData;
always @(posedge aclk) begin
nxtValid <= valid;
nxtData <= data;
if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin
valid <= 1'b1;
data <= {
$unsigned(s_axis_divisor_tdata) % $unsigned(s_axis_dividend_tdata),
$unsigned(s_axis_divisor_tdata) / $unsigned(s_axis_dividend_tdata)
};
end
end
endmodule