231 lines
7.9 KiB
Verilog
231 lines
7.9 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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//*************************************************************************
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// > File Name : soc_top.v
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// > Description : SoC, included cpu, 2 x 3 bridge,
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// inst ram, confreg, data ram
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//
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// -------------------------
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// | cpu |
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// -------------------------
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// inst| | data
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// | |
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// | ---------------------
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// | | 1 x 2 bridge |
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// | ---------------------
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// | | |
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// | | |
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// ------------- ----------- -----------
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// | inst ram | | data ram| | confreg |
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// ------------- ----------- -----------
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//
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// > Author : LOONGSON
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// > Date : 2017-08-04
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//*************************************************************************
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//for simulation:
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//1. if define SIMU_USE_PLL = 1, will use clk_pll to generate cpu_clk/timer_clk,
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// and simulation will be very slow.
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//2. usually, please define SIMU_USE_PLL=0 to speed up simulation by assign
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// cpu_clk/timer_clk = clk.
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// at this time, cpu_clk/timer_clk frequency are both 100MHz, same as clk.
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`define SIMU_USE_PLL 0 //set 0 to speed up simulation
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module soc_lite_top #(parameter SIMULATION=1'b0)
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(
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input resetn,
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input clk,
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//------gpio-------
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output [15:0] led,
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output [1 :0] led_rg0,
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output [1 :0] led_rg1,
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output [7 :0] num_csn,
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output [6 :0] num_a_g,
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input [7 :0] switch,
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output [3 :0] btn_key_col,
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input [3 :0] btn_key_row,
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input [1 :0] btn_step
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);
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//debug signals
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wire [31:0] debug_wb_pc;
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wire [3 :0] debug_wb_rf_wen;
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wire [4 :0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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//clk and resetn
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wire cpu_clk;
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wire timer_clk;
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reg cpu_resetn;
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always @(posedge cpu_clk)
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begin
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cpu_resetn <= resetn;
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end
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generate if(SIMULATION && `SIMU_USE_PLL==0)
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begin: speedup_simulation
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assign cpu_clk = clk;
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assign timer_clk = clk;
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end
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else
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begin: pll
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clk_pll clk_pll
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(
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.clk_in1 (clk),
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.cpu_clk (cpu_clk),
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.timer_clk (timer_clk)
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);
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end
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endgenerate
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//cpu inst sram
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wire cpu_inst_en;
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wire [3 :0] cpu_inst_wen;
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wire [31:0] cpu_inst_addr;
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wire [31:0] cpu_inst_wdata;
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wire [31:0] cpu_inst_rdata;
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//cpu data sram
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wire cpu_data_en;
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wire [3 :0] cpu_data_wen;
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wire [31:0] cpu_data_addr;
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wire [31:0] cpu_data_wdata;
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wire [31:0] cpu_data_rdata;
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//data sram
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wire data_sram_en;
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wire [3 :0] data_sram_wen;
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wire [31:0] data_sram_addr;
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wire [31:0] data_sram_wdata;
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wire [31:0] data_sram_rdata;
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//conf
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wire conf_en;
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wire [3 :0] conf_wen;
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wire [31:0] conf_addr;
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wire [31:0] conf_wdata;
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wire [31:0] conf_rdata;
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//cpu
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ls132r_top cpu(
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.clk (cpu_clk ),
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.resetn (cpu_resetn),
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.int_n_i (6'b1111_11),//low active
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.inst_sram_en (cpu_inst_en ),
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.inst_sram_wen (cpu_inst_wen ),
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.inst_sram_addr (cpu_inst_addr ),
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.inst_sram_wdata (cpu_inst_wdata),
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.inst_sram_rdata (cpu_inst_rdata),
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.data_sram_en (cpu_data_en ),
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.data_sram_wen (cpu_data_wen ),
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.data_sram_addr (cpu_data_addr ),
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.data_sram_wdata (cpu_data_wdata),
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.data_sram_rdata (cpu_data_rdata),
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//debug
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_wen ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata(debug_wb_rf_wdata)
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);
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//inst ram
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inst_ram inst_ram
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(
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.clka (cpu_clk ),
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.ena (cpu_inst_en ),
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.wea (cpu_inst_wen ), //3:0
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.addra (cpu_inst_addr[19:2]), //17:0
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.dina (cpu_inst_wdata ), //31:0
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.douta (cpu_inst_rdata ) //31:0
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);
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bridge_1x2 bridge_1x2(
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.clk ( cpu_clk ), // i, 1
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.resetn ( cpu_resetn ), // i, 1
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.cpu_data_en ( cpu_data_en ), // i, 4
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.cpu_data_wen ( cpu_data_wen ), // i, 4
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.cpu_data_addr ( cpu_data_addr ), // i, 32
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.cpu_data_wdata ( cpu_data_wdata ), // i, 32
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.cpu_data_rdata ( cpu_data_rdata ), // o, 32
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.data_sram_en ( data_sram_en ), // o, 4
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.data_sram_wen ( data_sram_wen ), // o, 4
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.data_sram_addr ( data_sram_addr ), // o, `DATA_RAM_ADDR_LEN
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.data_sram_wdata ( data_sram_wdata ), // o, 32
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.data_sram_rdata ( data_sram_rdata ), // i, 32
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.conf_en ( conf_en ), // o, 1
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.conf_wen ( conf_wen ), // o, 4
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.conf_addr ( conf_addr ), // o, 32
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.conf_wdata ( conf_wdata ), // o, 32
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.conf_rdata ( conf_rdata ) // i, 32
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);
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//data ram
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data_ram data_ram
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(
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.clka (cpu_clk ),
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.ena (data_sram_en ),
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.wea (data_sram_wen ), //3:0
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.addra (data_sram_addr[17:2]), //15:0
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.dina (data_sram_wdata ), //31:0
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.douta (data_sram_rdata ) //31:0
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);
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//confreg
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confreg #(.SIMULATION(SIMULATION)) confreg
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(
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.clk ( cpu_clk ), // i, 1
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.timer_clk ( timer_clk ), // i, 1
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.resetn ( cpu_resetn ), // i, 1
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.conf_en ( conf_en ), // i, 1
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.conf_wen ( conf_wen ), // i, 4
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.conf_addr ( conf_addr ), // i, 32
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.conf_wdata ( conf_wdata ), // i, 32
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.conf_rdata ( conf_rdata ), // o, 32
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.led ( led ), // o, 16
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.led_rg0 ( led_rg0 ), // o, 2
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.led_rg1 ( led_rg1 ), // o, 2
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.num_csn ( num_csn ), // o, 8
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.num_a_g ( num_a_g ), // o, 7
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.switch ( switch ), // i, 8
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.btn_key_col ( btn_key_col), // o, 4
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.btn_key_row ( btn_key_row), // i, 4
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.btn_step ( btn_step ) // i, 2
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);
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endmodule
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