112 lines
4.8 KiB
Verilog
112 lines
4.8 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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//*************************************************************************
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// > File Name : bridge_1x2.v
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// > Description : bridge between cpu_data and data ram, confreg
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//
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// master: cpu_data
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// | \
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// 1 x 2 | \
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// bridge: | \
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// | \
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// slave: data_ram confreg
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//
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// > Author : LOONGSON
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// > Date : 2017-08-04
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//*************************************************************************
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`define CONF_ADDR_BASE 32'h1faf_0000
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`define CONF_ADDR_MASK 32'hffff_0000
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module bridge_1x2(
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input clk, // clock
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input resetn, // reset, active low
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// master : cpu data
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input cpu_data_en, // cpu data access enable
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input [3 :0] cpu_data_wen, // cpu data write byte enable
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input [31 :0] cpu_data_addr, // cpu data address
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input [31 :0] cpu_data_wdata, // cpu data write data
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output [31 :0] cpu_data_rdata, // cpu data read data
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// slave : data ram
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output data_sram_en, // access data_sram enable
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output [3 :0] data_sram_wen, // write enable
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output [31 :0] data_sram_addr, // address
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output [31 :0] data_sram_wdata, // data in
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input [31 :0] data_sram_rdata, // data out
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// slave : confreg
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output conf_en, // access confreg enable
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output [3 :0] conf_wen, // access confreg enable
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output [31 :0] conf_addr, // address
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output [31 :0] conf_wdata, // write data
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input [31 :0] conf_rdata // read data
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);
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wire sel_sram; // cpu data is from data ram
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wire sel_conf; // cpu data is from confreg
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reg sel_sram_r; // reg of sel_dram
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reg sel_conf_r; // reg of sel_conf
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assign sel_conf = (cpu_data_addr & `CONF_ADDR_MASK) == `CONF_ADDR_BASE;
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assign sel_sram = !sel_conf;
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// data sram
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assign data_sram_en = cpu_data_en & sel_sram;
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assign data_sram_wen = cpu_data_wen;
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assign data_sram_addr = cpu_data_addr;
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assign data_sram_wdata = cpu_data_wdata;
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// confreg
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assign conf_en = cpu_data_en & sel_conf;
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assign conf_wen = cpu_data_wen;
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assign conf_addr = cpu_data_addr;
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assign conf_wdata = cpu_data_wdata;
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always @ (posedge clk)
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begin
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if (!resetn)
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begin
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sel_sram_r <= 1'b0;
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sel_conf_r <= 1'b0;
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end
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else
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begin
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sel_sram_r <= sel_sram;
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sel_conf_r <= sel_conf;
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end
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end
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assign cpu_data_rdata = {32{sel_sram_r}} & data_sram_rdata
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| {32{sel_conf_r}} & conf_rdata;
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endmodule
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