25 lines
760 B
Systemverilog
25 lines
760 B
Systemverilog
`include "defines.svh"
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module div_signed(
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input logic aclk,
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input logic s_axis_dividend_tvalid,
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input logic [31:0] s_axis_dividend_tdata,
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input logic s_axis_divisor_tvalid,
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input logic [31:0] s_axis_divisor_tdata,
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output logic m_axis_dout_tvalid,
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output logic [63:0] m_axis_dout_tdata
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);
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always_ff @(posedge aclk)
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if (s_axis_dividend_tvalid & s_axis_divisor_tvalid) begin
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m_axis_dout_tvalid <= 1'b1;
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m_axis_dout_tdata[63:32] <= $signed(s_axis_dividend_tdata) / $signed(s_axis_divisor_tdata);
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m_axis_dout_tdata[31: 0] <= $signed(s_axis_dividend_tdata) % $signed(s_axis_divisor_tdata);
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end else begin
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m_axis_dout_tvalid <= 0;
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m_axis_dout_tdata <= 0;
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end
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endmodule
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