25 lines
470 B
Systemverilog
25 lines
470 B
Systemverilog
`include "defines.svh"
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module mul_unsigned(
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input logic CLK,
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input logic [31:0] A,
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input logic [31:0] B,
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output logic [63:0] P
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);
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logic [31:0] rA;
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logic [31:0] rB;
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logic [63:0] M[`MUL_PIPE_STAGES-2:0];
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always_ff @(posedge CLK) begin
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rA <= A;
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rB <= B;
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M[0] <= $unsigned(rA) * $unsigned(rB);
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for (integer i = 0; i < `MUL_PIPE_STAGES-2; i = i + 1)
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M[i+1] <= M[i];
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end
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assign P = M[`MUL_PIPE_STAGES-2];
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endmodule
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