692 lines
24 KiB
Verilog
692 lines
24 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 register (write)
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*/
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module axi_register_wr #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Width of ID signal
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parameter ID_WIDTH = 8,
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// Propagate awuser signal
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parameter AWUSER_ENABLE = 0,
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// Width of awuser signal
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parameter AWUSER_WIDTH = 1,
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// Propagate wuser signal
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parameter WUSER_ENABLE = 0,
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// Width of wuser signal
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parameter WUSER_WIDTH = 1,
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// Propagate buser signal
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parameter BUSER_ENABLE = 0,
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// Width of buser signal
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parameter BUSER_WIDTH = 1,
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// AW channel register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter AW_REG_TYPE = 1,
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// W channel register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter W_REG_TYPE = 2,
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// B channel register type
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter B_REG_TYPE = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [ID_WIDTH-1:0] s_axi_awid,
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input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire [3:0] s_axi_awqos,
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input wire [3:0] s_axi_awregion,
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input wire [AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [DATA_WIDTH-1:0] s_axi_wdata,
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input wire [STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s_axi_wuser,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s_axi_buser,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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/*
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* AXI master interface
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*/
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output wire [ID_WIDTH-1:0] m_axi_awid,
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output wire [ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire [3:0] m_axi_awqos,
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output wire [3:0] m_axi_awregion,
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output wire [AWUSER_WIDTH-1:0] m_axi_awuser,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [DATA_WIDTH-1:0] m_axi_wdata,
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output wire [STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire [WUSER_WIDTH-1:0] m_axi_wuser,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire [BUSER_WIDTH-1:0] m_axi_buser,
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input wire m_axi_bvalid,
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output wire m_axi_bready
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);
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generate
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// AW channel
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if (AW_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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reg s_axi_awready_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};
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reg [7:0] m_axi_awlen_reg = 8'd0;
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reg [2:0] m_axi_awsize_reg = 3'd0;
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reg [1:0] m_axi_awburst_reg = 2'd0;
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reg m_axi_awlock_reg = 1'b0;
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reg [3:0] m_axi_awcache_reg = 4'd0;
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reg [2:0] m_axi_awprot_reg = 3'd0;
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reg [3:0] m_axi_awqos_reg = 4'd0;
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reg [3:0] m_axi_awregion_reg = 4'd0;
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reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};
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reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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reg [ID_WIDTH-1:0] temp_m_axi_awid_reg = {ID_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] temp_m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};
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reg [7:0] temp_m_axi_awlen_reg = 8'd0;
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reg [2:0] temp_m_axi_awsize_reg = 3'd0;
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reg [1:0] temp_m_axi_awburst_reg = 2'd0;
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reg temp_m_axi_awlock_reg = 1'b0;
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reg [3:0] temp_m_axi_awcache_reg = 4'd0;
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reg [2:0] temp_m_axi_awprot_reg = 3'd0;
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reg [3:0] temp_m_axi_awqos_reg = 4'd0;
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reg [3:0] temp_m_axi_awregion_reg = 4'd0;
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reg [AWUSER_WIDTH-1:0] temp_m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};
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reg temp_m_axi_awvalid_reg = 1'b0, temp_m_axi_awvalid_next;
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// datapath control
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reg store_axi_aw_input_to_output;
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reg store_axi_aw_input_to_temp;
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reg store_axi_aw_temp_to_output;
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assign s_axi_awready = s_axi_awready_reg;
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assign m_axi_awid = m_axi_awid_reg;
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assign m_axi_awaddr = m_axi_awaddr_reg;
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assign m_axi_awlen = m_axi_awlen_reg;
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assign m_axi_awsize = m_axi_awsize_reg;
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assign m_axi_awburst = m_axi_awburst_reg;
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assign m_axi_awlock = m_axi_awlock_reg;
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assign m_axi_awcache = m_axi_awcache_reg;
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assign m_axi_awprot = m_axi_awprot_reg;
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assign m_axi_awqos = m_axi_awqos_reg;
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assign m_axi_awregion = m_axi_awregion_reg;
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assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
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assign m_axi_awvalid = m_axi_awvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axi_awready_early = m_axi_awready | (~temp_m_axi_awvalid_reg & (~m_axi_awvalid_reg | ~s_axi_awvalid));
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always @* begin
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// transfer sink ready state to source
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m_axi_awvalid_next = m_axi_awvalid_reg;
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temp_m_axi_awvalid_next = temp_m_axi_awvalid_reg;
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store_axi_aw_input_to_output = 1'b0;
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store_axi_aw_input_to_temp = 1'b0;
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store_axi_aw_temp_to_output = 1'b0;
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if (s_axi_awready_reg) begin
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// input is ready
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if (m_axi_awready | ~m_axi_awvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axi_awvalid_next = s_axi_awvalid;
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store_axi_aw_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axi_awvalid_next = s_axi_awvalid;
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store_axi_aw_input_to_temp = 1'b1;
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end
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end else if (m_axi_awready) begin
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// input is not ready, but output is ready
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m_axi_awvalid_next = temp_m_axi_awvalid_reg;
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temp_m_axi_awvalid_next = 1'b0;
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store_axi_aw_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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s_axi_awready_reg <= 1'b0;
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m_axi_awvalid_reg <= 1'b0;
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temp_m_axi_awvalid_reg <= 1'b0;
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end else begin
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s_axi_awready_reg <= s_axi_awready_early;
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m_axi_awvalid_reg <= m_axi_awvalid_next;
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temp_m_axi_awvalid_reg <= temp_m_axi_awvalid_next;
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end
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// datapath
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if (store_axi_aw_input_to_output) begin
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m_axi_awid_reg <= s_axi_awid;
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m_axi_awaddr_reg <= s_axi_awaddr;
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m_axi_awlen_reg <= s_axi_awlen;
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m_axi_awsize_reg <= s_axi_awsize;
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m_axi_awburst_reg <= s_axi_awburst;
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m_axi_awlock_reg <= s_axi_awlock;
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m_axi_awcache_reg <= s_axi_awcache;
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m_axi_awprot_reg <= s_axi_awprot;
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m_axi_awqos_reg <= s_axi_awqos;
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m_axi_awregion_reg <= s_axi_awregion;
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m_axi_awuser_reg <= s_axi_awuser;
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end else if (store_axi_aw_temp_to_output) begin
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m_axi_awid_reg <= temp_m_axi_awid_reg;
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m_axi_awaddr_reg <= temp_m_axi_awaddr_reg;
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m_axi_awlen_reg <= temp_m_axi_awlen_reg;
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m_axi_awsize_reg <= temp_m_axi_awsize_reg;
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m_axi_awburst_reg <= temp_m_axi_awburst_reg;
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m_axi_awlock_reg <= temp_m_axi_awlock_reg;
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m_axi_awcache_reg <= temp_m_axi_awcache_reg;
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m_axi_awprot_reg <= temp_m_axi_awprot_reg;
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m_axi_awqos_reg <= temp_m_axi_awqos_reg;
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m_axi_awregion_reg <= temp_m_axi_awregion_reg;
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m_axi_awuser_reg <= temp_m_axi_awuser_reg;
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end
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if (store_axi_aw_input_to_temp) begin
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temp_m_axi_awid_reg <= s_axi_awid;
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temp_m_axi_awaddr_reg <= s_axi_awaddr;
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temp_m_axi_awlen_reg <= s_axi_awlen;
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temp_m_axi_awsize_reg <= s_axi_awsize;
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temp_m_axi_awburst_reg <= s_axi_awburst;
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temp_m_axi_awlock_reg <= s_axi_awlock;
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temp_m_axi_awcache_reg <= s_axi_awcache;
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temp_m_axi_awprot_reg <= s_axi_awprot;
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temp_m_axi_awqos_reg <= s_axi_awqos;
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temp_m_axi_awregion_reg <= s_axi_awregion;
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temp_m_axi_awuser_reg <= s_axi_awuser;
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end
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end
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end else if (AW_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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reg s_axi_awready_reg = 1'b0;
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reg [ID_WIDTH-1:0] m_axi_awid_reg = {ID_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] m_axi_awaddr_reg = {ADDR_WIDTH{1'b0}};
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reg [7:0] m_axi_awlen_reg = 8'd0;
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reg [2:0] m_axi_awsize_reg = 3'd0;
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reg [1:0] m_axi_awburst_reg = 2'd0;
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reg m_axi_awlock_reg = 1'b0;
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reg [3:0] m_axi_awcache_reg = 4'd0;
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reg [2:0] m_axi_awprot_reg = 3'd0;
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reg [3:0] m_axi_awqos_reg = 4'd0;
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reg [3:0] m_axi_awregion_reg = 4'd0;
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reg [AWUSER_WIDTH-1:0] m_axi_awuser_reg = {AWUSER_WIDTH{1'b0}};
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reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next;
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// datapath control
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reg store_axi_aw_input_to_output;
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assign s_axi_awready = s_axi_awready_reg;
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assign m_axi_awid = m_axi_awid_reg;
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assign m_axi_awaddr = m_axi_awaddr_reg;
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assign m_axi_awlen = m_axi_awlen_reg;
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assign m_axi_awsize = m_axi_awsize_reg;
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assign m_axi_awburst = m_axi_awburst_reg;
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assign m_axi_awlock = m_axi_awlock_reg;
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assign m_axi_awcache = m_axi_awcache_reg;
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assign m_axi_awprot = m_axi_awprot_reg;
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assign m_axi_awqos = m_axi_awqos_reg;
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assign m_axi_awregion = m_axi_awregion_reg;
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assign m_axi_awuser = AWUSER_ENABLE ? m_axi_awuser_reg : {AWUSER_WIDTH{1'b0}};
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assign m_axi_awvalid = m_axi_awvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire s_axi_awready_eawly = !m_axi_awvalid_next;
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always @* begin
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// transfer sink ready state to source
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m_axi_awvalid_next = m_axi_awvalid_reg;
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store_axi_aw_input_to_output = 1'b0;
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if (s_axi_awready_reg) begin
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m_axi_awvalid_next = s_axi_awvalid;
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store_axi_aw_input_to_output = 1'b1;
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end else if (m_axi_awready) begin
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m_axi_awvalid_next = 1'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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s_axi_awready_reg <= 1'b0;
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m_axi_awvalid_reg <= 1'b0;
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end else begin
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s_axi_awready_reg <= s_axi_awready_eawly;
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m_axi_awvalid_reg <= m_axi_awvalid_next;
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end
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// datapath
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if (store_axi_aw_input_to_output) begin
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m_axi_awid_reg <= s_axi_awid;
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m_axi_awaddr_reg <= s_axi_awaddr;
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m_axi_awlen_reg <= s_axi_awlen;
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m_axi_awsize_reg <= s_axi_awsize;
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m_axi_awburst_reg <= s_axi_awburst;
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m_axi_awlock_reg <= s_axi_awlock;
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m_axi_awcache_reg <= s_axi_awcache;
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m_axi_awprot_reg <= s_axi_awprot;
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m_axi_awqos_reg <= s_axi_awqos;
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m_axi_awregion_reg <= s_axi_awregion;
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m_axi_awuser_reg <= s_axi_awuser;
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end
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end
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end else begin
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// bypass AW channel
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assign m_axi_awid = s_axi_awid;
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assign m_axi_awaddr = s_axi_awaddr;
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assign m_axi_awlen = s_axi_awlen;
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assign m_axi_awsize = s_axi_awsize;
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assign m_axi_awburst = s_axi_awburst;
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assign m_axi_awlock = s_axi_awlock;
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assign m_axi_awcache = s_axi_awcache;
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assign m_axi_awprot = s_axi_awprot;
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assign m_axi_awqos = s_axi_awqos;
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assign m_axi_awregion = s_axi_awregion;
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assign m_axi_awuser = AWUSER_ENABLE ? s_axi_awuser : {AWUSER_WIDTH{1'b0}};
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assign m_axi_awvalid = s_axi_awvalid;
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assign s_axi_awready = m_axi_awready;
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end
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// W channel
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if (W_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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reg s_axi_wready_reg = 1'b0;
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reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
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reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
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reg m_axi_wlast_reg = 1'b0;
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reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};
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reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
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reg [DATA_WIDTH-1:0] temp_m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
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reg [STRB_WIDTH-1:0] temp_m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
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reg temp_m_axi_wlast_reg = 1'b0;
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reg [WUSER_WIDTH-1:0] temp_m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};
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reg temp_m_axi_wvalid_reg = 1'b0, temp_m_axi_wvalid_next;
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// datapath control
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reg store_axi_w_input_to_output;
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reg store_axi_w_input_to_temp;
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reg store_axi_w_temp_to_output;
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assign s_axi_wready = s_axi_wready_reg;
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assign m_axi_wdata = m_axi_wdata_reg;
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assign m_axi_wstrb = m_axi_wstrb_reg;
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assign m_axi_wlast = m_axi_wlast_reg;
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assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
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assign m_axi_wvalid = m_axi_wvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axi_wready_early = m_axi_wready | (~temp_m_axi_wvalid_reg & (~m_axi_wvalid_reg | ~s_axi_wvalid));
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always @* begin
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// transfer sink ready state to source
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m_axi_wvalid_next = m_axi_wvalid_reg;
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temp_m_axi_wvalid_next = temp_m_axi_wvalid_reg;
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store_axi_w_input_to_output = 1'b0;
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store_axi_w_input_to_temp = 1'b0;
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store_axi_w_temp_to_output = 1'b0;
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if (s_axi_wready_reg) begin
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// input is ready
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if (m_axi_wready | ~m_axi_wvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axi_wvalid_next = s_axi_wvalid;
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store_axi_w_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axi_wvalid_next = s_axi_wvalid;
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store_axi_w_input_to_temp = 1'b1;
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end
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end else if (m_axi_wready) begin
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// input is not ready, but output is ready
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m_axi_wvalid_next = temp_m_axi_wvalid_reg;
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temp_m_axi_wvalid_next = 1'b0;
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store_axi_w_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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s_axi_wready_reg <= 1'b0;
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m_axi_wvalid_reg <= 1'b0;
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temp_m_axi_wvalid_reg <= 1'b0;
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end else begin
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s_axi_wready_reg <= s_axi_wready_early;
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m_axi_wvalid_reg <= m_axi_wvalid_next;
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temp_m_axi_wvalid_reg <= temp_m_axi_wvalid_next;
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end
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// datapath
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if (store_axi_w_input_to_output) begin
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m_axi_wdata_reg <= s_axi_wdata;
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m_axi_wstrb_reg <= s_axi_wstrb;
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m_axi_wlast_reg <= s_axi_wlast;
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m_axi_wuser_reg <= s_axi_wuser;
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end else if (store_axi_w_temp_to_output) begin
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m_axi_wdata_reg <= temp_m_axi_wdata_reg;
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m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
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m_axi_wlast_reg <= temp_m_axi_wlast_reg;
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m_axi_wuser_reg <= temp_m_axi_wuser_reg;
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end
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if (store_axi_w_input_to_temp) begin
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temp_m_axi_wdata_reg <= s_axi_wdata;
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temp_m_axi_wstrb_reg <= s_axi_wstrb;
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temp_m_axi_wlast_reg <= s_axi_wlast;
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temp_m_axi_wuser_reg <= s_axi_wuser;
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end
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end
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end else if (W_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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reg s_axi_wready_reg = 1'b0;
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reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};
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reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};
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reg m_axi_wlast_reg = 1'b0;
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reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};
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reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;
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// datapath control
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reg store_axi_w_input_to_output;
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assign s_axi_wready = s_axi_wready_reg;
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assign m_axi_wdata = m_axi_wdata_reg;
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assign m_axi_wstrb = m_axi_wstrb_reg;
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assign m_axi_wlast = m_axi_wlast_reg;
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assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
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assign m_axi_wvalid = m_axi_wvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire s_axi_wready_ewly = !m_axi_wvalid_next;
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always @* begin
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// transfer sink ready state to source
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m_axi_wvalid_next = m_axi_wvalid_reg;
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store_axi_w_input_to_output = 1'b0;
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if (s_axi_wready_reg) begin
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m_axi_wvalid_next = s_axi_wvalid;
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store_axi_w_input_to_output = 1'b1;
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end else if (m_axi_wready) begin
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m_axi_wvalid_next = 1'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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s_axi_wready_reg <= 1'b0;
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m_axi_wvalid_reg <= 1'b0;
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end else begin
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s_axi_wready_reg <= s_axi_wready_ewly;
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m_axi_wvalid_reg <= m_axi_wvalid_next;
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end
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// datapath
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if (store_axi_w_input_to_output) begin
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m_axi_wdata_reg <= s_axi_wdata;
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m_axi_wstrb_reg <= s_axi_wstrb;
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m_axi_wlast_reg <= s_axi_wlast;
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m_axi_wuser_reg <= s_axi_wuser;
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end
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end
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end else begin
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// bypass W channel
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assign m_axi_wdata = s_axi_wdata;
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assign m_axi_wstrb = s_axi_wstrb;
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assign m_axi_wlast = s_axi_wlast;
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assign m_axi_wuser = WUSER_ENABLE ? s_axi_wuser : {WUSER_WIDTH{1'b0}};
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assign m_axi_wvalid = s_axi_wvalid;
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assign s_axi_wready = m_axi_wready;
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end
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// B channel
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if (B_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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reg m_axi_bready_reg = 1'b0;
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reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};
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reg [1:0] s_axi_bresp_reg = 2'b0;
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reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};
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reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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reg [ID_WIDTH-1:0] temp_s_axi_bid_reg = {ID_WIDTH{1'b0}};
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reg [1:0] temp_s_axi_bresp_reg = 2'b0;
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reg [BUSER_WIDTH-1:0] temp_s_axi_buser_reg = {BUSER_WIDTH{1'b0}};
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reg temp_s_axi_bvalid_reg = 1'b0, temp_s_axi_bvalid_next;
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// datapath control
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reg store_axi_b_input_to_output;
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reg store_axi_b_input_to_temp;
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reg store_axi_b_temp_to_output;
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assign m_axi_bready = m_axi_bready_reg;
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assign s_axi_bid = s_axi_bid_reg;
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assign s_axi_bresp = s_axi_bresp_reg;
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assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
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assign s_axi_bvalid = s_axi_bvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire m_axi_bready_early = s_axi_bready | (~temp_s_axi_bvalid_reg & (~s_axi_bvalid_reg | ~m_axi_bvalid));
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always @* begin
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// transfer sink ready state to source
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s_axi_bvalid_next = s_axi_bvalid_reg;
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temp_s_axi_bvalid_next = temp_s_axi_bvalid_reg;
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store_axi_b_input_to_output = 1'b0;
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store_axi_b_input_to_temp = 1'b0;
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store_axi_b_temp_to_output = 1'b0;
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if (m_axi_bready_reg) begin
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// input is ready
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if (s_axi_bready | ~s_axi_bvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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s_axi_bvalid_next = m_axi_bvalid;
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store_axi_b_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_s_axi_bvalid_next = m_axi_bvalid;
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store_axi_b_input_to_temp = 1'b1;
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end
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end else if (s_axi_bready) begin
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// input is not ready, but output is ready
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s_axi_bvalid_next = temp_s_axi_bvalid_reg;
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temp_s_axi_bvalid_next = 1'b0;
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store_axi_b_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axi_bready_reg <= 1'b0;
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s_axi_bvalid_reg <= 1'b0;
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temp_s_axi_bvalid_reg <= 1'b0;
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end else begin
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m_axi_bready_reg <= m_axi_bready_early;
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s_axi_bvalid_reg <= s_axi_bvalid_next;
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temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
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end
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// datapath
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if (store_axi_b_input_to_output) begin
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s_axi_bid_reg <= m_axi_bid;
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s_axi_bresp_reg <= m_axi_bresp;
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s_axi_buser_reg <= m_axi_buser;
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end else if (store_axi_b_temp_to_output) begin
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s_axi_bid_reg <= temp_s_axi_bid_reg;
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s_axi_bresp_reg <= temp_s_axi_bresp_reg;
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s_axi_buser_reg <= temp_s_axi_buser_reg;
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end
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if (store_axi_b_input_to_temp) begin
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temp_s_axi_bid_reg <= m_axi_bid;
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temp_s_axi_bresp_reg <= m_axi_bresp;
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temp_s_axi_buser_reg <= m_axi_buser;
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end
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end
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end else if (B_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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reg m_axi_bready_reg = 1'b0;
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reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};
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reg [1:0] s_axi_bresp_reg = 2'b0;
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reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};
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reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
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// datapath control
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reg store_axi_b_input_to_output;
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assign m_axi_bready = m_axi_bready_reg;
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assign s_axi_bid = s_axi_bid_reg;
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assign s_axi_bresp = s_axi_bresp_reg;
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assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
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assign s_axi_bvalid = s_axi_bvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire m_axi_bready_early = !s_axi_bvalid_next;
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always @* begin
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// transfer sink ready state to source
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s_axi_bvalid_next = s_axi_bvalid_reg;
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store_axi_b_input_to_output = 1'b0;
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if (m_axi_bready_reg) begin
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s_axi_bvalid_next = m_axi_bvalid;
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store_axi_b_input_to_output = 1'b1;
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end else if (s_axi_bready) begin
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s_axi_bvalid_next = 1'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axi_bready_reg <= 1'b0;
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s_axi_bvalid_reg <= 1'b0;
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end else begin
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m_axi_bready_reg <= m_axi_bready_early;
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s_axi_bvalid_reg <= s_axi_bvalid_next;
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end
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// datapath
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if (store_axi_b_input_to_output) begin
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s_axi_bid_reg <= m_axi_bid;
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s_axi_bresp_reg <= m_axi_bresp;
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s_axi_buser_reg <= m_axi_buser;
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end
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end
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end else begin
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// bypass B channel
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assign s_axi_bid = m_axi_bid;
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assign s_axi_bresp = m_axi_bresp;
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assign s_axi_buser = BUSER_ENABLE ? m_axi_buser : {BUSER_WIDTH{1'b0}};
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assign s_axi_bvalid = m_axi_bvalid;
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assign m_axi_bready = s_axi_bready;
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end
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endgenerate
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endmodule
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`resetall
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