Paul Pan
7b33e4213a
1. add test soft 2. modify verilator (TODO: crossbar need to replace) 3. fix CP0: now CU0 is always 1 4. Controller: cacheop 5. Controller: fix TEN 6. mycpu_top fix CP0_i 7. fix AXI.sv 8. fix AXIReader.sv 9. fix AXIWriter.sv: getting the correct data and length 10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
#include <asm/r4kcache.h>
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int dcache_size = 0x4000;
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int icache_size = 0x4000;
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#define cpu_dcache_line_size() 32
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void dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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/*
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* Either no secondary cache or the available caches don't have the
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* subset property so we have to flush the primary caches
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* explicitly
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*/
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if (size >= dcache_size) {
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blast_dcache32();
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} else {
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blast_dcache_range(addr, addr + size);
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}
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}
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void dma_cache_inv(unsigned long addr, unsigned long size)
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{
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if (size >= dcache_size) {
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blast_dcache32();
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} else {
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unsigned long lsize = cpu_dcache_line_size();
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unsigned long almask = ~(lsize - 1);
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cache_op(Hit_Writeback_Inv_D, addr & almask);
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cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask);
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blast_inv_dcache_range(addr, addr + size);
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}
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}
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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if (end - start >= dcache_size) {
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blast_dcache32();
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} else {
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protected_blast_dcache_range(start, end);
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}
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if (end - start > icache_size)
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blast_icache32();
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else
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protected_blast_icache_range(start, end);
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}
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