141 lines
4.0 KiB
Verilog
141 lines
4.0 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module nand_module
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(
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nand_type ,
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clk,
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rst_n,
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apb_psel,
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apb_enab,
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apb_rw,
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apb_addr,
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apb_datai,
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apb_datao,
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apb_ack,
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nand_dma_req_o,
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nand_dma_ack_i,
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nand_ce ,
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nand_dat_i ,
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nand_dat_o ,
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nand_dat_oe,
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nand_ale ,
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nand_cle ,
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nand_wr ,
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nand_rd ,
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nand_rdy ,
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nand_int
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);
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input [1:0]nand_type;
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input clk;
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input rst_n;
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input apb_psel;
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input apb_enab;
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input apb_rw;
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input [19:0] apb_addr;
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input [31:0] apb_datai;
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output[31:0] apb_datao;
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output apb_ack;
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output nand_dma_req_o;
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input nand_dma_ack_i;
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output [3:0] nand_ce;
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input [7:0] nand_dat_i ;
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output [7:0] nand_dat_o ;
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output nand_dat_oe;
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output nand_ale;
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output nand_cle;
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output nand_wr;
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output nand_rd;
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input [3:0] nand_rdy;
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output nand_int;
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wire psel;
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wire penable;
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wire [10:0] paddr;
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wire pwr;
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assign apb_ack = apb_enab;
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assign psel = apb_psel;
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assign penable = apb_enab;
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assign paddr = apb_addr[10:0];
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assign pwr = apb_rw;
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reg [3:0] nand_iordy_r0;
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reg [3:0] nand_iordy_r1;
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always @(posedge clk) begin
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nand_iordy_r0 <= nand_rdy;
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nand_iordy_r1 <= nand_iordy_r0;
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end
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reg [1:0] nand_type_r1;
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reg [1:0] nand_type_r2;
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always @(posedge clk)
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if(~rst_n)begin
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nand_type_r1 <= nand_type;
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nand_type_r2 <= nand_type_r1;
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end
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NAND_top NAND
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(
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.nand_type (nand_type_r2 ),
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.pclk (clk ),
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.prst_ (rst_n ),
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.psel (psel ),
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.penable (penable ),
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.pwrite (pwr ),
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.ADDR (paddr ),
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.DAT_I (apb_datai ),
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.DAT_O (apb_datao ),
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.NAND_CE_o (nand_ce ),
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.NAND_REQ (nand_dma_req_o ),
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.NAND_I (nand_dat_i ),
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.NAND_O (nand_dat_o ),
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.NAND_EN_ (nand_dat_oe ),
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.NAND_ALE (nand_ale ),
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.NAND_CLE (nand_cle ),
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.NAND_RD_ (nand_rd ),
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.NAND_WR_ (nand_wr ),
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.NAND_IORDY_i (nand_iordy_r1 ),
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.nand_int (nand_int )
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);
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endmodule
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