1329 lines
28 KiB
Verilog
1329 lines
28 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module RLSM (
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clk,
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rst,
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fifodata,
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fifore,
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cachere,
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dmaack,
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dmaeob,
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dmadatai,
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dmaaddr,
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dmareq,
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dmawr,
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dmacnt,
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dmaaddro,
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dmadatao,
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rprog,
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rcpoll,
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fifocne,
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ff,
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rf,
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mf,
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db,
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re,
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ce,
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tl,
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ftp,
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ov,
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cs,
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length,
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pbl,
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dsl,
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rpoll,
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rdbadc,
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rdbad,
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rpollack,
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rcompack,
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bufack,
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des,
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fbuf,
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stat,
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ru,
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rcomp,
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bufcomp,
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stopi,
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stopo,
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insert_en_i
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);
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parameter DATAWIDTH = 32;
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parameter DATADEPTH = 32;
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parameter FIFODEPTH = 9;
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`include "utility.v"
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input clk;
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input rst;
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input [DATAWIDTH - 1:0] fifodata;
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output fifore;
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wire fifore;
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output cachere;
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wire cachere;
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input dmaack;
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input dmaeob;
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input [DATAWIDTH - 1:0] dmadatai;
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input [DATADEPTH - 1:0] dmaaddr;
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output dmareq;
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wire dmareq;
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output dmawr;
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wire dmawr;
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output [FIFODEPTH_MAX - 1:0] dmacnt;
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reg [FIFODEPTH_MAX - 1:0] dmacnt;
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output [DATADEPTH - 1:0] dmaaddro;
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reg [DATADEPTH - 1:0] dmaaddro;
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output [DATAWIDTH - 1:0] dmadatao;
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reg [DATAWIDTH - 1:0] dmadatao;
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input rprog;
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input rcpoll;
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input fifocne;
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input ff;
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input rf;
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input mf;
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input db;
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input re;
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input ce;
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input tl;
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input ftp;
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input ov;
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input cs;
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input [13:0] length;
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input [5:0] pbl;
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input [4:0] dsl;
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input rpoll;
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input rdbadc;
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input [DATADEPTH - 1:0] rdbad;
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output rpollack;
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reg rpollack;
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input rcompack;
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input bufack;
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output des;
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reg des;
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output fbuf;
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reg fbuf;
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output stat;
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reg stat;
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output ru;
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reg ru;
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output rcomp;
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reg rcomp;
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output bufcomp;
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reg bufcomp;
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input stopi;
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output stopo;
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reg stopo;
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input insert_en_i;
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reg [3:0] lsm_c;
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reg [3:0] lsm;
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reg [3:0] lsm_r;
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reg own_c;
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reg own;
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reg rch;
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reg rer;
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reg rls;
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reg rfs;
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reg rde;
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wire res_c;
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reg [10:0] bs1;
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reg [10:0] bs2;
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reg adwrite;
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reg [DATADEPTH - 1:0] bad;
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reg [DATADEPTH - 1:0] dad;
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reg [10:0] bcnt;
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reg [DATADEPTH - 1:0] statad;
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reg [DATADEPTH - 1:0] tstatad;
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reg dbadc_r;
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reg req_c;
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reg req;
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wire [2:0] dmaaddr20;
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wire [1:0] addr10;
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reg [DATADEPTH_MAX - 1:0] dataimax_r;
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wire [31:0] fstat;
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reg rprog_r;
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reg rcpoll_r;
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reg rcpoll_r2;
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reg whole;
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reg [13:0] fifolev_r;
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reg [13:0] fbcnt;
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reg [13:0] fbcnt_c;
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reg [13:0] length_r;
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wire ififore;
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reg ififore_r;
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reg icachere;
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wire [FIFODEPTH_MAX - 1:0] bsmax;
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wire [FIFODEPTH_MAX - 1:0] flmax;
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wire [FIFODEPTH_MAX - 1:0] blmax;
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reg fl_g_16;
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reg fl_g_bs;
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reg fl_g_bl;
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reg bl_g_bs;
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reg pblz;
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reg stop_r;
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wire [FIFODEPTH_MAX - 1:0] fzero_max;
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wire [DATAWIDTH_MAX + 1:0] dmadatai_max;
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wire [DATAWIDTH_MAX + 1:0] dzero_max;
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always @(posedge clk)
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begin : dataimax_reg_proc
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if (rst)
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begin
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dataimax_r <= {DATADEPTH_MAX{1'b1}} ;
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end
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else
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begin
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case (DATAWIDTH)
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8 :
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begin
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case (dmaaddr20)
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3'b000, 3'b100 :
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begin
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dataimax_r[7:0] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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3'b001, 3'b101 :
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begin
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dataimax_r[15:8] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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3'b010, 3'b110 :
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begin
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dataimax_r[23:16] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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default :
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begin
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dataimax_r[31:24] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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endcase
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end
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16 :
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begin
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if (!(dmaaddr[1]))
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begin
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dataimax_r[15:0] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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else
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begin
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dataimax_r[31:16] <= dmadatai_max[DATAWIDTH-1:0] ;
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end
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end
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default :
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begin
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dataimax_r <= dmadatai_max[31:0] ;
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end
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endcase
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end
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end
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always @(posedge clk)
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begin : fifolev_reg_proc
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if (rst)
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begin
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length_r <= {14{1'b0}} ;
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fifolev_r <= {14{1'b0}} ;
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fl_g_bs <= 1'b0 ;
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fl_g_16 <= 1'b0 ;
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fl_g_bl <= 1'b0 ;
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bl_g_bs <= 1'b0 ;
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pblz <= 1'b0 ;
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end
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else
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begin
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length_r <= length;
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fifolev_r <= length_r - fbcnt_c ;
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if (flmax >= bsmax)
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begin
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fl_g_bs <= 1'b1 ;
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end
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else
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begin
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fl_g_bs <= 1'b0 ;
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end
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case (DATAWIDTH)
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8 :
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begin
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if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:6],
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6'b111111}))
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begin
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fl_g_16 <= 1'b1 ;
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end
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else
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begin
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fl_g_16 <= 1'b0 ;
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end
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end
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16 :
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begin
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if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:5],
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5'b11111}))
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begin
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fl_g_16 <= 1'b1 ;
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end
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else
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begin
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fl_g_16 <= 1'b0 ;
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end
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end
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default :
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begin
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if (flmax > ({fzero_max[FIFODEPTH_MAX - 1:4],
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4'b1111}))
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begin
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fl_g_16 <= 1'b1 ;
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end
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else
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begin
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fl_g_16 <= 1'b0 ;
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end
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end
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endcase
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if (flmax >= (blmax + 1'b1))
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begin
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fl_g_bl <= 1'b1 ;
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end
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else
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begin
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fl_g_bl <= 1'b0 ;
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end
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if (blmax >= bsmax)
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begin
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bl_g_bs <= 1'b1 ;
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end
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else
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begin
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bl_g_bs <= 1'b0 ;
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end
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if (pbl == 6'b000000)
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begin
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pblz <= 1'b1 ;
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end
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else
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begin
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pblz <= 1'b0 ;
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end
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end
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end
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assign flmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:14],
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fifolev_r} :
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(DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:13],
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fifolev_r[13:1]} :
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{fzero_max[FIFODEPTH_MAX - 1:12],
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fifolev_r[13:2]} ;
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assign blmax = {fzero_max[FIFODEPTH_MAX - 1:6], pbl} ;
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assign bsmax = (DATAWIDTH == 8) ? {fzero_max[FIFODEPTH_MAX - 1:11],
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bcnt} :
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(DATAWIDTH == 16) ? {fzero_max[FIFODEPTH_MAX - 1:10],
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bcnt[10:1]} :
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{fzero_max[FIFODEPTH_MAX - 1:9],
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bcnt[10:2]} ;
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always @(lsm or
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fl_g_bs or
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fl_g_bl or
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bl_g_bs or
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pblz or
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blmax or
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bsmax or
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flmax or
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fzero_max)
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begin : dmacnt_proc
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if (lsm == LSM_DES0 |
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lsm == LSM_DES1 |
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lsm == LSM_DES2 |
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lsm == LSM_DES3 |
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lsm == LSM_STAT |
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lsm == LSM_FSTAT |
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lsm == LSM_DES0P)
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begin
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case (DATAWIDTH)
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8 :
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begin
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dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b100} ;
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end
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16 :
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begin
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dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b010} ;
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end
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default :
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begin
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dmacnt <= {fzero_max[FIFODEPTH_MAX - 1:3], 3'b001} ;
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end
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endcase
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end
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else
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begin
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if (pblz)
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begin
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if (fl_g_bs)
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begin
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dmacnt <= bsmax ;
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end
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else
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begin
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dmacnt <= flmax ;
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end
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end
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else
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begin
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if (fl_g_bl)
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begin
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if (bl_g_bs)
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begin
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dmacnt <= bsmax ;
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end
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else
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begin
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dmacnt <= blmax ;
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end
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end
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else
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begin
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if (fl_g_bs)
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begin
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dmacnt <= bsmax ;
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end
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else
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begin
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dmacnt <= flmax ;
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end
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end
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end
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end
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end
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always @(req or
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lsm or
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lsm_c or
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fifocne or
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fl_g_bl or
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fl_g_16 or
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pblz or
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whole or
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rprog_r or
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dmaack or
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dmaeob or
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flmax or
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fzero_max)
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begin : req_proc
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case (lsm)
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LSM_BUF1, LSM_BUF2 :
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begin
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if ((dmaack & dmaeob) | lsm_c==LSM_NXT)
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begin
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req_c <= 1'b0 ;
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end
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else if (fifocne | (rprog_r & ((fl_g_bl & !pblz) |
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(fl_g_16 & pblz))))
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begin
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req_c <= 1'b1 ;
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end
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else
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begin
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req_c <= req ;
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end
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end
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LSM_DES0, LSM_DES1, LSM_DES2,
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LSM_DES3, LSM_STAT, LSM_DES0P :
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begin
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if (dmaack)
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begin
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req_c <= 1'b0 ;
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end
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else
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begin
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req_c <= 1'b1 ;
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end
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end
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LSM_FSTAT :
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begin
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if (dmaack | !whole |
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(DATAWIDTH == 8 & flmax[1:0] != fzero_max[1:0])
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|
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(DATAWIDTH == 16 & flmax[ 1] != fzero_max[1]))
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begin
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req_c <= 1'b0 ;
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end
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else
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begin
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req_c <= 1'b1 ;
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end
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end
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default :
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begin
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req_c <= 1'b0 ;
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end
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endcase
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end
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always @(posedge clk)
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begin : req_reg_proc
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if (rst)
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begin
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req <= 1'b0 ;
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end
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else
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begin
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req <= req_c ;
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end
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end
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always @(lsm or bad or dad or statad)
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begin : dmaaddro_proc
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case (lsm)
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LSM_BUF1, LSM_BUF2 :
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begin
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dmaaddro <= bad ;
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end
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LSM_STAT, LSM_FSTAT :
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begin
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dmaaddro <= statad ;
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end
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default :
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begin
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dmaaddro <= dad ;
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end
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endcase
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end
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wire [13:0] real_length;
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assign real_length = (insert_en_i) ? (length - 2'b10) : length;
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assign fstat = {1'b0, ff, real_length, res_c, rde,
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RDES0_RV[13:12], rf, mf, rfs, rls, tl,
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cs, ftp, RDES0_RV[4], re, db, ce, ov} ;
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assign dmawr = (lsm == LSM_STAT |
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lsm == LSM_FSTAT |
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lsm == LSM_BUF1 |
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lsm == LSM_BUF2) ? 1'b1 : 1'b0 ;
|
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|
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always @(fifodata or lsm or addr10 or fstat)
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begin : dmadatao_proc
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if (lsm == LSM_BUF1 | lsm == LSM_BUF2)
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begin
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dmadatao <= fifodata ;
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end
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else
|
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begin
|
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case (DATAWIDTH)
|
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8 :
|
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begin
|
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case (addr10)
|
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2'b00 :
|
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begin
|
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dmadatao <= fstat[7:0] ;
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end
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2'b01 :
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begin
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dmadatao <= fstat[15:8] ;
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end
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2'b10 :
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begin
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dmadatao <= fstat[23:16] ;
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end
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default :
|
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begin
|
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dmadatao <= fstat[31:24] ;
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end
|
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endcase
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end
|
|
16 :
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begin
|
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if (addr10 == 2'b00)
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begin
|
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dmadatao <= fstat[15:0] ;
|
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end
|
|
else
|
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begin
|
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dmadatao <= fstat[31:16] ;
|
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end
|
|
end
|
|
default :
|
|
begin
|
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dmadatao <= fstat ;
|
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end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign dmareq = req ;
|
|
|
|
always @(lsm or
|
|
rcpoll_r or
|
|
rcpoll_r2 or
|
|
rpoll or
|
|
dmaack or
|
|
dmaeob or
|
|
own_c or
|
|
bs1 or
|
|
bs2 or
|
|
whole or
|
|
rch or
|
|
stop_r or
|
|
own or
|
|
bcnt or
|
|
dbadc_r)
|
|
begin : lsm_proc
|
|
case (lsm)
|
|
LSM_IDLE :
|
|
begin
|
|
if (!dbadc_r & !stop_r & ((rcpoll_r & !rcpoll_r2) | rpoll))
|
|
begin
|
|
lsm_c <= LSM_DES0 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_IDLE ;
|
|
end
|
|
end
|
|
LSM_DES0 :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
if (own_c)
|
|
begin
|
|
lsm_c <= LSM_DES1 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_IDLE ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES0 ;
|
|
end
|
|
end
|
|
LSM_DES0P :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
if (!own_c | whole)
|
|
begin
|
|
lsm_c <= LSM_FSTAT ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_STAT ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES0P ;
|
|
end
|
|
end
|
|
LSM_DES1 :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
lsm_c <= LSM_DES2 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES1 ;
|
|
end
|
|
end
|
|
LSM_DES2 :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
if (bs1 == 11'b00000000000)
|
|
begin
|
|
lsm_c <= LSM_DES3 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_BUF1 ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES2 ;
|
|
end
|
|
end
|
|
LSM_DES3 :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
if (bs2 != 11'b00000000000 & !rch)
|
|
begin
|
|
lsm_c <= LSM_BUF2 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_NXT ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES3 ;
|
|
end
|
|
end
|
|
LSM_BUF1 :
|
|
begin
|
|
if (whole | bcnt == 11'b00000000000)
|
|
begin
|
|
lsm_c <= LSM_DES3 ;
|
|
end
|
|
else if(dbadc_r)
|
|
begin
|
|
lsm_c <= LSM_IDLE ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_BUF1 ;
|
|
end
|
|
end
|
|
LSM_BUF2 :
|
|
begin
|
|
if (whole | bcnt == 11'b00000000000)
|
|
begin
|
|
lsm_c <= LSM_NXT ;
|
|
end
|
|
else if(dbadc_r)
|
|
begin
|
|
lsm_c <= LSM_IDLE ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_BUF2 ;
|
|
end
|
|
end
|
|
LSM_NXT :
|
|
begin
|
|
if (whole)
|
|
begin
|
|
if (stop_r)
|
|
begin
|
|
lsm_c <= LSM_FSTAT ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES0P ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_DES0P ;
|
|
end
|
|
end
|
|
LSM_STAT :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
lsm_c <= LSM_DES1 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_STAT ;
|
|
end
|
|
end
|
|
default :
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
if (own & !stop_r)
|
|
begin
|
|
lsm_c <= LSM_DES1 ;
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_IDLE ;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
lsm_c <= LSM_FSTAT ;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : rlsm_reg_proc
|
|
if (rst)
|
|
begin
|
|
lsm <= LSM_IDLE ;
|
|
lsm_r <= LSM_IDLE ;
|
|
end
|
|
else
|
|
begin
|
|
lsm <= lsm_c ;
|
|
lsm_r <= lsm ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : rpollack_reg_proc
|
|
if (rst)
|
|
begin
|
|
rpollack <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (rpoll & !dbadc_r)
|
|
begin
|
|
rpollack <= 1'b1 ;
|
|
end
|
|
else if (!rpoll)
|
|
begin
|
|
rpollack <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : bcnt_reg_proc
|
|
if (rst)
|
|
begin
|
|
bcnt <= {11{1'b1}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (lsm == LSM_DES2)
|
|
begin
|
|
bcnt <= bs1 ;
|
|
end
|
|
else if (lsm == LSM_DES3)
|
|
begin
|
|
bcnt <= bs2 ;
|
|
end
|
|
else
|
|
begin
|
|
if (dmaack)
|
|
begin
|
|
case (DATAWIDTH)
|
|
8 :
|
|
begin
|
|
bcnt <= bcnt - 1 ;
|
|
end
|
|
16 :
|
|
begin
|
|
bcnt <= {(bcnt[10:1] - 1), 1'b0} ;
|
|
end
|
|
default :
|
|
begin
|
|
bcnt <= {(bcnt[10:2] - 1), 2'b00} ;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(own or
|
|
dmaack or
|
|
dmaeob or
|
|
lsm or
|
|
dmadatai_max)
|
|
begin : own_proc
|
|
if (dmaack & dmaeob & (lsm == LSM_DES0 | lsm == LSM_DES0P))
|
|
begin
|
|
own_c <= dmadatai_max[DATAWIDTH - 1] ;
|
|
end
|
|
else
|
|
begin
|
|
own_c <= own ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : des1_reg_proc
|
|
reg ft22;
|
|
if (rst)
|
|
begin
|
|
rer <= 1'b0 ;
|
|
rch <= 1'b0 ;
|
|
bs2 <= {11{1'b0}} ;
|
|
bs1 <= {11{1'b0}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (lsm == LSM_DES1 & dmaack)
|
|
begin
|
|
case (DATAWIDTH)
|
|
8 :
|
|
begin
|
|
case (dmaaddr20)
|
|
3'b000, 3'b100 :
|
|
begin
|
|
bs1[7:0] <= dmadatai_max[7:0] ;
|
|
end
|
|
3'b001, 3'b101 :
|
|
begin
|
|
bs1[10:8] <= dmadatai_max[2:0] ;
|
|
bs2[4:0] <= dmadatai_max[7:3] ;
|
|
end
|
|
3'b010, 3'b110 :
|
|
begin
|
|
bs2[10:5] <= dmadatai_max[5:0] ;
|
|
end
|
|
default :
|
|
begin
|
|
rer <= dmadatai_max[1] ;
|
|
rch <= dmadatai_max[0] ;
|
|
end
|
|
endcase
|
|
end
|
|
16 :
|
|
begin
|
|
case (dmaaddr20)
|
|
3'b000, 3'b100 :
|
|
begin
|
|
bs1[10:0] <= dmadatai_max[10:0] ;
|
|
bs2[4:0] <= dmadatai_max[15:11] ;
|
|
end
|
|
default :
|
|
begin
|
|
bs2[10:5] <= dmadatai_max[5:0] ;
|
|
rer <= dmadatai_max[9] ;
|
|
rch <= dmadatai_max[8] ;
|
|
end
|
|
endcase
|
|
end
|
|
default :
|
|
begin
|
|
rer <= dmadatai_max[25] ;
|
|
rch <= dmadatai_max[24] ;
|
|
bs2 <= dmadatai_max[21:11] ;
|
|
bs1 <= dmadatai_max[10:0] ;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : rdes_reg_proc
|
|
if (rst)
|
|
begin
|
|
own <= 1'b0 ;
|
|
rfs <= 1'b1 ;
|
|
rls <= 1'b0 ;
|
|
rde <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (lsm == LSM_FSTAT & dmaack & dmaeob)
|
|
begin
|
|
rfs <= 1'b1 ;
|
|
end
|
|
else if (lsm == LSM_STAT & dmaack & dmaeob)
|
|
begin
|
|
rfs <= 1'b0 ;
|
|
end
|
|
|
|
if (lsm == LSM_FSTAT)
|
|
begin
|
|
rls <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
rls <= 1'b0 ;
|
|
end
|
|
|
|
if (lsm == LSM_FSTAT & !whole)
|
|
begin
|
|
rde <= 1'b1 ;
|
|
end
|
|
else if (lsm == LSM_IDLE)
|
|
begin
|
|
rde <= 1'b0 ;
|
|
end
|
|
|
|
own <= own_c ;
|
|
end
|
|
end
|
|
|
|
assign res_c = rf | ce | rde | cs | tl ;
|
|
|
|
always @(posedge clk)
|
|
begin : adwrite_reg_proc
|
|
if (rst)
|
|
begin
|
|
adwrite <= 1'b0 ;
|
|
dbadc_r <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (dmaack & dmaeob)
|
|
begin
|
|
adwrite <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
adwrite <= 1'b0 ;
|
|
end
|
|
|
|
dbadc_r <= rdbadc ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : dad_reg_proc
|
|
if (rst)
|
|
begin
|
|
dad <= {DATADEPTH{1'b1}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (dbadc_r)
|
|
begin
|
|
dad <= rdbad ;
|
|
end
|
|
else if (adwrite & lsm == LSM_NXT & rch)
|
|
begin
|
|
dad <= dataimax_r[DATADEPTH - 1:0] ;
|
|
end
|
|
else if (adwrite)
|
|
begin
|
|
case (lsm_r)
|
|
LSM_DES3 :
|
|
begin
|
|
if (rer)
|
|
begin
|
|
dad <= rdbad ;
|
|
end
|
|
else
|
|
begin
|
|
dad <= dmaaddr + ({dsl, 2'b00}) ;
|
|
end
|
|
end
|
|
LSM_DES0, LSM_DES0P :
|
|
begin
|
|
if (own)
|
|
begin
|
|
dad <= dmaaddr ;
|
|
end
|
|
end
|
|
LSM_DES2 :
|
|
begin
|
|
dad <= dmaaddr ;
|
|
end
|
|
LSM_DES1 :
|
|
begin
|
|
dad <= dmaaddr ;
|
|
end
|
|
default :
|
|
begin
|
|
dad <= dad ;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : bad_reg_proc
|
|
if (rst)
|
|
begin
|
|
bad <= {DATADEPTH{1'b1}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (adwrite)
|
|
begin
|
|
if (lsm_r == LSM_BUF1 | lsm_r == LSM_BUF2)
|
|
begin
|
|
bad <= dmaaddr ;
|
|
end
|
|
else
|
|
begin
|
|
bad <= dataimax_r[DATADEPTH - 1:0] ;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : stataddr_reg_proc
|
|
if (rst)
|
|
begin
|
|
tstatad <= {DATADEPTH{1'b1}} ;
|
|
statad <= {DATADEPTH{1'b1}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (lsm == LSM_DES1 & adwrite)
|
|
begin
|
|
statad <= tstatad ;
|
|
end
|
|
|
|
if ((lsm == LSM_DES0 | lsm == LSM_DES0P) & dmaack & dmaeob)
|
|
begin
|
|
tstatad <= dad ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(fbcnt or icachere or ififore)
|
|
begin : fbcnt_proc
|
|
if (icachere)
|
|
begin
|
|
fbcnt_c <= {14{1'b0}} ;
|
|
end
|
|
else
|
|
begin
|
|
if (ififore)
|
|
begin
|
|
case (DATAWIDTH)
|
|
8 :
|
|
begin
|
|
fbcnt_c <= fbcnt + 1 ;
|
|
end
|
|
16 :
|
|
begin
|
|
fbcnt_c <= fbcnt + 2'b10 ;
|
|
end
|
|
default :
|
|
begin
|
|
fbcnt_c <= fbcnt + 3'b100 ;
|
|
end
|
|
endcase
|
|
end
|
|
else
|
|
begin
|
|
fbcnt_c <= fbcnt;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : fbcnt_reg_proc
|
|
if(rst)
|
|
begin
|
|
fbcnt <= {14{1'b0}};
|
|
end
|
|
else
|
|
begin
|
|
fbcnt <= fbcnt_c;
|
|
end
|
|
end
|
|
|
|
always @(fbcnt or length or fifocne)
|
|
begin : whole_proc
|
|
if (fbcnt >= length & fifocne)
|
|
begin
|
|
whole <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
whole <= 1'b0 ;
|
|
end
|
|
end
|
|
|
|
assign ififore = (((lsm == LSM_BUF1 | lsm == LSM_BUF2) & dmaack) |
|
|
(lsm == LSM_FSTAT & !whole &
|
|
flmax != fzero_max[14:0] & !ififore_r) |
|
|
(lsm == LSM_FSTAT & !whole &
|
|
fifocne & !ififore_r)) ? 1'b1 : 1'b0 ;
|
|
|
|
always @(posedge clk)
|
|
begin : ififore_reg_proc
|
|
if (rst)
|
|
begin
|
|
ififore_r <= 1'b0 ;
|
|
icachere <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
ififore_r <= ififore ;
|
|
|
|
if (lsm == LSM_FSTAT & dmaack & dmaeob)
|
|
begin
|
|
icachere <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
icachere <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign fifore = ififore ;
|
|
|
|
assign cachere = icachere ;
|
|
|
|
always @(posedge clk)
|
|
begin : rprog_reg_proc
|
|
if (rst)
|
|
begin
|
|
rprog_r <= 1'b0 ;
|
|
rcpoll_r <= 1'b0 ;
|
|
rcpoll_r2 <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
rprog_r <= rprog ;
|
|
rcpoll_r <= rcpoll ;
|
|
if (lsm == LSM_IDLE)
|
|
begin
|
|
rcpoll_r2 <= rcpoll_r ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : stat_reg_drv
|
|
if (rst)
|
|
begin
|
|
des <= 1'b0 ;
|
|
fbuf <= 1'b0 ;
|
|
stat <= 1'b0 ;
|
|
rcomp <= 1'b0 ;
|
|
bufcomp <= 1'b0 ;
|
|
ru <= 1'b0 ;
|
|
end
|
|
else
|
|
begin
|
|
if (lsm == LSM_DES0 |
|
|
lsm == LSM_DES1 |
|
|
lsm == LSM_DES2 |
|
|
lsm == LSM_DES3 |
|
|
lsm == LSM_DES0P)
|
|
begin
|
|
des <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
des <= 1'b0 ;
|
|
end
|
|
|
|
if ((lsm == LSM_BUF1 | lsm == LSM_BUF2) & req)
|
|
begin
|
|
fbuf <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
fbuf <= 1'b0 ;
|
|
end
|
|
|
|
if (lsm == LSM_STAT | lsm == LSM_FSTAT)
|
|
begin
|
|
stat <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
stat <= 1'b0 ;
|
|
end
|
|
|
|
if (lsm == LSM_FSTAT & dmaack & dmaeob)
|
|
begin
|
|
rcomp <= 1'b1 ;
|
|
end
|
|
else if (rcompack)
|
|
begin
|
|
rcomp <= 1'b0 ;
|
|
end
|
|
|
|
if (lsm == LSM_STAT & dmaack & dmaeob)
|
|
begin
|
|
bufcomp <= 1'b1 ;
|
|
end
|
|
else if (bufack)
|
|
begin
|
|
bufcomp <= 1'b0 ;
|
|
end
|
|
|
|
if (own & !own_c)
|
|
begin
|
|
ru <= 1'b1 ;
|
|
end
|
|
else if (own)
|
|
begin
|
|
ru <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin : stop_reg_proc
|
|
if (rst)
|
|
begin
|
|
stop_r <= 1'b1 ;
|
|
stopo <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
stop_r <= stopi ;
|
|
|
|
if (stop_r & (lsm == LSM_IDLE |
|
|
((lsm == LSM_BUF1 | lsm == LSM_BUF2) &
|
|
!fifocne & !rprog_r)))
|
|
begin
|
|
stopo <= 1'b1 ;
|
|
end
|
|
else
|
|
begin
|
|
stopo <= 1'b0 ;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign dzero_max = {DATAWIDTH_MAX{1'b0}} ;
|
|
|
|
assign fzero_max = {FIFODEPTH_MAX{1'b0}} ;
|
|
|
|
assign dmadatai_max = {dzero_max[DATAWIDTH_MAX+1:DATAWIDTH],
|
|
dmadatai};
|
|
|
|
assign dmaaddr20 = dmaaddr[2:0] ;
|
|
|
|
assign addr10 = dmaaddr[1:0] ;
|
|
|
|
endmodule
|