373 lines
7.3 KiB
Verilog
373 lines
7.3 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module BD (
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clk,
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rst,
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col,
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crs,
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fdp,
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tprog,
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preamble,
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tpend,
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winp,
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tiack,
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coll,
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carrier,
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bkoff,
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lc,
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lo,
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nc,
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ec,
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cc
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);
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`include "utility.v"
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input clk;
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input rst;
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input col;
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input crs;
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input fdp;
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input tprog;
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input preamble;
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input tpend;
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output winp;
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wire winp;
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input tiack;
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output coll;
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wire coll;
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output carrier;
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wire carrier;
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output bkoff;
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wire bkoff;
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output lc;
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wire lc;
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output lo;
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reg lo;
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output nc;
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wire nc;
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output ec;
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reg ec;
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output [3:0] cc;
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wire [3:0] cc;
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reg crs_r;
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reg inc;
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reg ibkoff;
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reg ibkoff_r;
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reg icoll;
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reg ilc;
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reg [3:0] ccnt;
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reg [9:0] bkcnt;
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reg [8:0] slcnt;
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reg [9:0] bkrel_c;
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wire [9:0] p_rand;
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reg [31:0] lfsr;
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reg [31:0] lfsr_c;
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reg iwinp;
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always @(posedge clk)
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begin : crs_reg_proc
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if (rst)
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begin
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crs_r <= 1'b0 ;
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lo <= 1'b0 ;
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inc <= 1'b0 ;
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end
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else
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begin
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if (fdp)
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begin
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crs_r <= 1'b0 ;
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end
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else
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begin
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crs_r <= crs ;
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end
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if (tprog & !inc & !crs_r)
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begin
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lo <= 1'b1 ;
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end
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else if(!tpend & !tprog)
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begin
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lo <= 1'b0 ;
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end
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if (tprog & crs_r)
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begin
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inc <= 1'b0 ;
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end
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else if (!tpend & !tprog)
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begin
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inc <= 1'b1 ;
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end
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end
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end
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assign nc = inc ;
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always @(ccnt or p_rand)
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begin : bkrel_proc
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case (ccnt)
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4'b0000 :
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begin
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bkrel_c <= {9'b000000000, p_rand[0]} ;
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end
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4'b0001 :
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begin
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bkrel_c <= {8'b00000000, p_rand[1:0]} ;
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end
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4'b0010 :
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begin
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bkrel_c <= {7'b0000000, p_rand[2:0]} ;
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end
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4'b0011 :
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begin
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bkrel_c <= {6'b000000, p_rand[3:0]} ;
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end
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4'b0100 :
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begin
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bkrel_c <= {5'b00000, p_rand[4:0]} ;
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end
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4'b0101 :
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begin
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bkrel_c <= {4'b0000, p_rand[5:0]} ;
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end
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4'b0110 :
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begin
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bkrel_c <= {3'b000, p_rand[6:0]} ;
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end
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4'b0111 :
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begin
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bkrel_c <= {2'b00, p_rand[7:0]} ;
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end
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4'b1000 :
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begin
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bkrel_c <= {1'b0, p_rand[8:0]} ;
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end
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default :
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begin
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bkrel_c <= p_rand[9:0] ;
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end
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endcase
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end
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always @(posedge clk)
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begin : slcnt_reg_proc
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if (rst)
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begin
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slcnt <= {9{1'b1}} ;
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end
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else
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begin
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if (tprog & !preamble & !icoll)
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begin
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if (slcnt != 9'b000000000)
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begin
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slcnt <= slcnt - 1 ;
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end
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end
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else if (ibkoff)
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begin
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if (slcnt == 9'b000000000 | icoll)
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begin
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slcnt <= SLOT_TIME ;
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end
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else
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begin
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slcnt <= slcnt - 1 ;
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end
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end
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else
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begin
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slcnt <= SLOT_TIME ;
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end
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end
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end
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always @(posedge clk)
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begin : bkcnt_reg_proc
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if (rst)
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begin
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bkcnt <= {10{1'b1}} ;
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end
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else
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begin
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if (icoll & !ibkoff)
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begin
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bkcnt <= bkrel_c ;
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end
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else if (slcnt == 9'b000000000)
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begin
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bkcnt <= bkcnt - 1 ;
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end
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end
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end
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always @(posedge clk)
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begin : rand_reg_proc
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if (rst)
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begin
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lfsr <= {31{1'b1}};
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end
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else
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begin
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lfsr <= lfsr_c;
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end
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end
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always @(lfsr)
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begin : lfsr_drv
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reg [31:0] lfsr_n;
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integer i;
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for(i=0; i<=30; i=i+1)
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begin
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lfsr_n[i] = lfsr[i+1];
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end
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lfsr_n[31] = 1'b0;
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if(lfsr[0]==1'b1)
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begin
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lfsr_n = lfsr_n ^ 32'b10000000000000000000111010100110;
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end
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lfsr_c <= lfsr_n;
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end
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assign p_rand = lfsr[9:0] ;
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always @(posedge clk)
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begin : ibkoff_reg_proc
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if (rst)
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begin
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ibkoff <= 1'b0 ;
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ibkoff_r <= 1'b0 ;
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end
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else
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begin
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ibkoff_r <= ibkoff ;
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if(icoll & ccnt!=4'b1111 & !iwinp & !ilc)
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begin
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ibkoff <= 1'b1 ;
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end
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else if (bkcnt == 10'b0000000000)
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begin
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ibkoff <= 1'b0 ;
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end
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end
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end
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always @(posedge clk)
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begin : coll_reg_proc
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if (rst)
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begin
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icoll <= 1'b0 ;
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ilc <= 1'b0 ;
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ec <= 1'b0 ;
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iwinp <= 1'b1 ;
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ccnt <= 4'b0000 ;
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end
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else
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begin
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if ((preamble | tprog) & col & !fdp)
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begin
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icoll <= 1'b1 ;
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end
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else if (!tprog & !preamble)
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begin
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icoll <= 1'b0 ;
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end
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if (tiack)
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begin
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ilc <= 1'b0 ;
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end
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else if (tprog & icoll & iwinp)
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begin
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ilc <= 1'b1 ;
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end
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if (tiack)
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begin
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ec <= 1'b0 ;
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end
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else if (icoll & ccnt == 4'b1111 & tprog)
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begin
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ec <= 1'b1 ;
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end
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if (slcnt == 9'b000000000 | !tprog)
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begin
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iwinp <= 1'b1 ;
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end
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else
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begin
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iwinp <= 1'b0 ;
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end
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if (!tpend & !tprog)
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begin
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ccnt <= 4'b0000 ;
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end
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else if (ibkoff & !ibkoff_r)
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begin
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ccnt <= ccnt + 4'b0001 ;
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end
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end
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end
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assign winp = iwinp ;
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assign lc = ilc;
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assign carrier = crs_r ;
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assign coll = icoll ;
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assign bkoff = ibkoff ;
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assign cc = ccnt ;
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endmodule
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