18 lines
327 B
Verilog
18 lines
327 B
Verilog
module ICTag_bram (
|
|
input [ 5:0] addra,
|
|
input clka,
|
|
input [21:0] dina,
|
|
output reg [21:0] douta,
|
|
input wea
|
|
);
|
|
|
|
reg [21:0] ram [0:63];
|
|
always @(posedge clka) begin
|
|
if(wea) begin
|
|
ram[addra] <= dina;
|
|
end
|
|
douta <= ~wea ? ram[addra] : {$random}[21:0];
|
|
end
|
|
|
|
endmodule
|