387 lines
15 KiB
Verilog
387 lines
15 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 crossbar
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*/
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module axi_crossbar #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 1,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 2,
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Input ID field width (from AXI masters)
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parameter S_ID_WIDTH = 4,
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// Output ID field width (towards AXI slaves)
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// Additional bits required for response routing
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parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
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// Propagate awuser signal
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parameter AWUSER_ENABLE = 0,
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// Width of awuser signal
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parameter AWUSER_WIDTH = 1,
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// Propagate wuser signal
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parameter WUSER_ENABLE = 0,
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// Width of wuser signal
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parameter WUSER_WIDTH = 1,
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// Propagate buser signal
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parameter BUSER_ENABLE = 0,
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// Width of buser signal
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parameter BUSER_WIDTH = 1,
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// Propagate aruser signal
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parameter ARUSER_ENABLE = 0,
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// Width of aruser signal
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parameter ARUSER_WIDTH = 1,
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// Propagate ruser signal
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parameter RUSER_ENABLE = 0,
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// Width of ruser signal
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parameter RUSER_WIDTH = 1,
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// Number of concurrent unique IDs for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_THREADS = {S_COUNT{32'd2}},
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// Number of concurrent operations for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_ACCEPT = {S_COUNT{32'd16}},
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// Number of regions per master interface
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parameter M_REGIONS = 5,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
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// set to zero for default addressing based on M_ADDR_WIDTH
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parameter M_BASE_ADDR = {{32'h1fc00000, 32'h20000000, 32'h40000000, 32'h80000000, 32'h0}, {32'h1faf0000, 32'hffffffff, 32'hffffffff, 32'hffffffff, 32'hffffffff}},
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_WIDTH = {{32'd22, 32'd29, 32'd30, 32'd28, 32'd28}, {32'd16, 32'd0, 32'd0, 32'd0, 32'd0}}, //{M_COUNT{{M_REGIONS{32'd24}}}},
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// Read connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
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// Write connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd4}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AW_REG_TYPE = {S_COUNT{2'd1}},
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_W_REG_TYPE = {S_COUNT{2'd1}},
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_B_REG_TYPE = {S_COUNT{2'd1}},
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AR_REG_TYPE = {S_COUNT{2'd1}},
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_R_REG_TYPE = {S_COUNT{2'd1}},
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AW_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_W_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_B_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_R_REG_TYPE = {M_COUNT{2'd1}}
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interfaces
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*/
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input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid,
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [S_COUNT*8-1:0] s_axi_awlen,
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input wire [S_COUNT*3-1:0] s_axi_awsize,
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input wire [S_COUNT*2-1:0] s_axi_awburst,
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input wire [S_COUNT-1:0] s_axi_awlock,
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input wire [S_COUNT*4-1:0] s_axi_awcache,
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input wire [S_COUNT*3-1:0] s_axi_awprot,
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input wire [S_COUNT*4-1:0] s_axi_awqos,
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input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire [S_COUNT-1:0] s_axi_awvalid,
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output wire [S_COUNT-1:0] s_axi_awready,
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input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,
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input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,
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input wire [S_COUNT-1:0] s_axi_wlast,
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input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,
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input wire [S_COUNT-1:0] s_axi_wvalid,
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output wire [S_COUNT-1:0] s_axi_wready,
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output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid,
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output wire [S_COUNT*2-1:0] s_axi_bresp,
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output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,
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output wire [S_COUNT-1:0] s_axi_bvalid,
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input wire [S_COUNT-1:0] s_axi_bready,
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input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [S_COUNT*8-1:0] s_axi_arlen,
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input wire [S_COUNT*3-1:0] s_axi_arsize,
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input wire [S_COUNT*2-1:0] s_axi_arburst,
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input wire [S_COUNT-1:0] s_axi_arlock,
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input wire [S_COUNT*4-1:0] s_axi_arcache,
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input wire [S_COUNT*3-1:0] s_axi_arprot,
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input wire [S_COUNT*4-1:0] s_axi_arqos,
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input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,
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input wire [S_COUNT-1:0] s_axi_arvalid,
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output wire [S_COUNT-1:0] s_axi_arready,
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output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,
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output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,
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output wire [S_COUNT*2-1:0] s_axi_rresp,
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output wire [S_COUNT-1:0] s_axi_rlast,
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output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,
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output wire [S_COUNT-1:0] s_axi_rvalid,
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input wire [S_COUNT-1:0] s_axi_rready,
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/*
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* AXI master interfaces
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*/
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output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid,
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [M_COUNT*8-1:0] m_axi_awlen,
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output wire [M_COUNT*3-1:0] m_axi_awsize,
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output wire [M_COUNT*2-1:0] m_axi_awburst,
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output wire [M_COUNT-1:0] m_axi_awlock,
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output wire [M_COUNT*4-1:0] m_axi_awcache,
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output wire [M_COUNT*3-1:0] m_axi_awprot,
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output wire [M_COUNT*4-1:0] m_axi_awqos,
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output wire [M_COUNT*4-1:0] m_axi_awregion,
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output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,
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output wire [M_COUNT-1:0] m_axi_awvalid,
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input wire [M_COUNT-1:0] m_axi_awready,
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output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,
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output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,
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output wire [M_COUNT-1:0] m_axi_wlast,
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output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,
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output wire [M_COUNT-1:0] m_axi_wvalid,
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input wire [M_COUNT-1:0] m_axi_wready,
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input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid,
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input wire [M_COUNT*2-1:0] m_axi_bresp,
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input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,
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input wire [M_COUNT-1:0] m_axi_bvalid,
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output wire [M_COUNT-1:0] m_axi_bready,
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output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid,
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [M_COUNT*8-1:0] m_axi_arlen,
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output wire [M_COUNT*3-1:0] m_axi_arsize,
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output wire [M_COUNT*2-1:0] m_axi_arburst,
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output wire [M_COUNT-1:0] m_axi_arlock,
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output wire [M_COUNT*4-1:0] m_axi_arcache,
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output wire [M_COUNT*3-1:0] m_axi_arprot,
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output wire [M_COUNT*4-1:0] m_axi_arqos,
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output wire [M_COUNT*4-1:0] m_axi_arregion,
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output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser,
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output wire [M_COUNT-1:0] m_axi_arvalid,
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input wire [M_COUNT-1:0] m_axi_arready,
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input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid,
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input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata,
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input wire [M_COUNT*2-1:0] m_axi_rresp,
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input wire [M_COUNT-1:0] m_axi_rlast,
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input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser,
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input wire [M_COUNT-1:0] m_axi_rvalid,
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output wire [M_COUNT-1:0] m_axi_rready
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);
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axi_crossbar_wr #(
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.S_ID_WIDTH(S_ID_WIDTH),
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.M_ID_WIDTH(M_ID_WIDTH),
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.AWUSER_ENABLE(AWUSER_ENABLE),
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.AWUSER_WIDTH(AWUSER_WIDTH),
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.WUSER_ENABLE(WUSER_ENABLE),
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.WUSER_WIDTH(WUSER_WIDTH),
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.BUSER_ENABLE(BUSER_ENABLE),
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.BUSER_WIDTH(BUSER_WIDTH),
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.S_THREADS(S_THREADS),
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.S_ACCEPT(S_ACCEPT),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_WIDTH(M_ADDR_WIDTH),
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.M_CONNECT(M_CONNECT_WRITE),
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.M_ISSUE(M_ISSUE),
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.M_SECURE(M_SECURE),
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.S_AW_REG_TYPE(S_AW_REG_TYPE),
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.S_W_REG_TYPE (S_W_REG_TYPE),
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.S_B_REG_TYPE (S_B_REG_TYPE)
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)
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axi_crossbar_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interfaces
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*/
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.s_axi_awid(s_axi_awid),
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.s_axi_awaddr(s_axi_awaddr),
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.s_axi_awlen(s_axi_awlen),
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.s_axi_awsize(s_axi_awsize),
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.s_axi_awburst(s_axi_awburst),
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.s_axi_awlock(s_axi_awlock),
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.s_axi_awcache(s_axi_awcache),
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.s_axi_awprot(s_axi_awprot),
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.s_axi_awqos(s_axi_awqos),
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.s_axi_awuser(s_axi_awuser),
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.s_axi_awvalid(s_axi_awvalid),
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.s_axi_awready(s_axi_awready),
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.s_axi_wdata(s_axi_wdata),
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.s_axi_wstrb(s_axi_wstrb),
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.s_axi_wlast(s_axi_wlast),
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.s_axi_wuser(s_axi_wuser),
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.s_axi_wvalid(s_axi_wvalid),
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.s_axi_wready(s_axi_wready),
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.s_axi_bid(s_axi_bid),
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.s_axi_bresp(s_axi_bresp),
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.s_axi_buser(s_axi_buser),
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.s_axi_bvalid(s_axi_bvalid),
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.s_axi_bready(s_axi_bready),
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/*
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* AXI master interfaces
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*/
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awqos(m_axi_awqos),
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.m_axi_awregion(m_axi_awregion),
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.m_axi_awuser(m_axi_awuser),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wuser(m_axi_wuser),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_buser(m_axi_buser),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready)
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);
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axi_crossbar_rd #(
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.S_ID_WIDTH(S_ID_WIDTH),
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.M_ID_WIDTH(M_ID_WIDTH),
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.ARUSER_ENABLE(ARUSER_ENABLE),
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.ARUSER_WIDTH(ARUSER_WIDTH),
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.RUSER_ENABLE(RUSER_ENABLE),
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.RUSER_WIDTH(RUSER_WIDTH),
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.S_THREADS(S_THREADS),
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.S_ACCEPT(S_ACCEPT),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_WIDTH(M_ADDR_WIDTH),
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.M_CONNECT(M_CONNECT_READ),
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.M_ISSUE(M_ISSUE),
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.M_SECURE(M_SECURE),
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.S_AR_REG_TYPE(S_AR_REG_TYPE),
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.S_R_REG_TYPE (S_R_REG_TYPE)
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)
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axi_crossbar_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interfaces
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*/
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.s_axi_arid(s_axi_arid),
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.s_axi_araddr(s_axi_araddr),
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.s_axi_arlen(s_axi_arlen),
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.s_axi_arsize(s_axi_arsize),
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.s_axi_arburst(s_axi_arburst),
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.s_axi_arlock(s_axi_arlock),
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.s_axi_arcache(s_axi_arcache),
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.s_axi_arprot(s_axi_arprot),
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.s_axi_arqos(s_axi_arqos),
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.s_axi_aruser(s_axi_aruser),
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.s_axi_arvalid(s_axi_arvalid),
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.s_axi_arready(s_axi_arready),
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.s_axi_rid(s_axi_rid),
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.s_axi_rdata(s_axi_rdata),
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.s_axi_rresp(s_axi_rresp),
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.s_axi_rlast(s_axi_rlast),
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.s_axi_ruser(s_axi_ruser),
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.s_axi_rvalid(s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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/*
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* AXI master interfaces
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*/
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.m_axi_arid(m_axi_arid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlen(m_axi_arlen),
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.m_axi_arsize(m_axi_arsize),
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.m_axi_arburst(m_axi_arburst),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arprot(m_axi_arprot),
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.m_axi_arqos(m_axi_arqos),
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.m_axi_arregion(m_axi_arregion),
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.m_axi_aruser(m_axi_aruser),
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|
.m_axi_arvalid(m_axi_arvalid),
|
|
.m_axi_arready(m_axi_arready),
|
|
.m_axi_rid(m_axi_rid),
|
|
.m_axi_rdata(m_axi_rdata),
|
|
.m_axi_rresp(m_axi_rresp),
|
|
.m_axi_rlast(m_axi_rlast),
|
|
.m_axi_ruser(m_axi_ruser),
|
|
.m_axi_rvalid(m_axi_rvalid),
|
|
.m_axi_rready(m_axi_rready)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|