73 lines
2.3 KiB
Makefile
73 lines
2.3 KiB
Makefile
####################
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# Program #
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####################
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VERILATOR = verilator
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VERILATOR_COVERAGE = verilator_coverage
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####################
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# Flags #
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####################
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VERILATOR_BUILD_FLAGS += -cc --exe --timing
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VERILATOR_BUILD_FLAGS += -MMD
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VERILATOR_BUILD_FLAGS += -O3 --x-assign unique --x-initial unique
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VERILATOR_BUILD_FLAGS += -Wall -Wpedantic
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VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
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VERILATOR_BUILD_FLAGS += --assert
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VERILATOR_BUILD_FLAGS += --coverage
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#VERILATOR_BUILD_FLAGS += --report-unoptflat
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VERILATOR_COV_FLAGS += --annotate logs/annotated
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VERILATOR_COV_FLAGS += --annotate-min 1
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VERILATOR_COV_FLAGS += --write-info logs/coverage.info
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VERILATOR_COV_FLAGS += logs/coverage.dat
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VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
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####################
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# Sources #
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####################
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SOURCE = ./config.vlt $(wildcard ./model/*.v ./model/*.sv ../src/*.v ../src/*.sv ../src/**/*.v ../src/**/*.sv)
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INCLUDE = $(addprefix -I, $(dir $(wildcard ../src/*/. ../src/**/*/.)))
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VERILATOR_INPUT = -top testbench_top sim_main.cpp
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TB_FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resources/func_test/**/*.v)
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####################
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# Targets #
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####################
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.phony: lint verilate func_soft tlb_soft build coverage run clean
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default: build
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lint:
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$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top
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verilate:
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$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(TB_FUNC_SOURCE) $(VERILATOR_INPUT)
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func_soft:
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cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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perf_soft:
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cd ../resources/soft/perf_func && make clean && make && cp obj/allbench/axi_ram.mif ../../../sim && cd ../../../sim && mv axi_ram.mif inst_ram.mif
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tlb_soft:
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cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
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build: verilate
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make -C obj_dir -f Vtestbench_top.mk -j `nproc`
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coverage:
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@rm -rf logs/annotated
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$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)
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run: build
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@rm -rf logs
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obj_dir/Vtestbench_top
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# gtkwave logs/trace.fst
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clean:
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-rm -rf obj_dir logs
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