MIPS/src/Gadgets.sv

module ffen #(
    parameter WIDTH = 8
) (
    input  logic             clk,
    input  logic [WIDTH-1:0] d,
    input  logic             en,
    output logic [WIDTH-1:0] q
);

  always_ff @(posedge clk) if (en) q <= d;
endmodule

module ffenr #(
    parameter WIDTH = 8
) (
    input  logic             clk,
    input  logic             rst,
    input  logic [WIDTH-1:0] d,
    input  logic             en,
    output logic [WIDTH-1:0] q
);

  always_ff @(posedge clk)
    if (rst) q <= {WIDTH{1'b0}};
    else if (en) q <= d;
endmodule

module ffenrc #(
    parameter WIDTH = 8
) (
    input  logic             clk,
    input  logic             rst,
    input  logic [WIDTH-1:0] d,
    input  logic             en,
    input  logic             c,
    output logic [WIDTH-1:0] q
);

  always_ff @(posedge clk)
    if (rst) q <= {WIDTH{1'b0}};
    else if (en) q <= c ? {WIDTH{1'b0}} : d;
endmodule

module mux2 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic             s,
    output logic [WIDTH-1:0] q
);

  assign q = s ? d1 : d0;

endmodule

module mux3 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic [WIDTH-1:0] d2,
    input  logic [      1:0] s,
    output logic [WIDTH-1:0] q
);

  assign q = s[1] ? d2 : s[0] ? d1 : d0;

endmodule

module mux4 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic [WIDTH-1:0] d2,
    input  logic [WIDTH-1:0] d3,
    input  logic [      1:0] s,
    output logic [WIDTH-1:0] q
);

  assign q = s[1] ? s[0] ? d3 : d2 : s[0] ? d1 : d0;

endmodule

module mux5 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic [WIDTH-1:0] d2,
    input  logic [WIDTH-1:0] d3,
    input  logic [WIDTH-1:0] d4,
    input  logic [      2:0] s,
    output logic [WIDTH-1:0] q
);

  assign q = s[2] ? d4 : s[1] ? s[0] ? d3 : d2 : s[0] ? d1 : d0;

endmodule

module mux6 #(
    parameter WIDTH = 8
) (
    input logic [WIDTH-1:0] d0,
    input logic [WIDTH-1:0] d1,
    input logic [WIDTH-1:0] d2,
    input logic [WIDTH-1:0] d3,
    input logic [WIDTH-1:0] d4,
    input logic [WIDTH-1:0] d5,

    input  logic [      2:0] s,
    output logic [WIDTH-1:0] q
);

  always_comb begin
    case (s)
      3'b000:  q = d0;
      3'b001:  q = d1;
      3'b010:  q = d2;
      3'b011:  q = d3;
      3'b100:  q = d4;
      default: q = d5;
    endcase
  end
endmodule

module prio_mux4 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic [WIDTH-1:0] d2,
    input  logic [WIDTH-1:0] d3,
    input  logic [      2:0] s,
    output logic [WIDTH-1:0] q
);

  assign q = s[2] ? d3 : s[1] ? d2 : s[0] ? d1 : d0;

endmodule

module prio_mux5 #(
    parameter WIDTH = 8
) (
    input  logic [WIDTH-1:0] d0,
    input  logic [WIDTH-1:0] d1,
    input  logic [WIDTH-1:0] d2,
    input  logic [WIDTH-1:0] d3,
    input  logic [WIDTH-1:0] d4,
    input  logic [      3:0] s,
    output logic [WIDTH-1:0] q
);

  assign q = s[3] ? d4 : s[2] ? d3 : s[1] ? d2 : s[0] ? d1 : d0;

endmodule

module onehot_bin4 (
    input  logic [3:0] onehot,
    output logic [1:0] bin
);
  assign bin = {onehot[3] | onehot[2], onehot[3] | onehot[1]};
endmodule

module onehot_bin8 (
    input  logic [7:0] onehot,
    output logic [2:0] bin
);
  logic [1:0] bin1, bin0;
  onehot_bin4 onehot_bin4_1(onehot[7:4], bin1);
  onehot_bin4 onehot_bin4_0(onehot[3:0], bin0);
  assign bin = {|{onehot[7:4]}, bin1 | bin0};
endmodule

module onehot_bin16 (
    input  logic [15:0] onehot,
    output logic [ 3:0] bin
);
  logic [2:0] bin1, bin0;
  onehot_bin8 onehot_bin8_1(onehot[15:8], bin1);
  onehot_bin8 onehot_bin8_0(onehot[ 7:0], bin0);
  assign bin = {|{onehot[15:8]}, bin1 | bin0};
endmodule

module onehot_bin32 (
    input  logic [31:0] onehot,
    output logic [ 4:0] bin
);
  logic [3:0] bin1, bin0;
  onehot_bin16 onehot_bin16_1(onehot[31:16], bin1);
  onehot_bin16 onehot_bin16_0(onehot[15: 0], bin0);
  assign bin = {|{onehot[31:16]}, bin1 | bin0};
endmodule

module extender #(
    parameter OWIDTH = 8,
    parameter IWIDTH = 8
) (
    input  logic [IWIDTH-1:0] d,
    input  logic              s,
    output logic [OWIDTH-1:0] q
);

  assign q = {{(OWIDTH - IWIDTH) {s & d[IWIDTH-1]}}, d};

endmodule

module buffer0 #(
    parameter WIDTH = 8
) (
    input                    clk,
    input                    rst,
    input  logic [WIDTH-1:0] data,
    input  logic             en,
    output logic [WIDTH-1:0] bdata
);

  logic [WIDTH-1:0] data1;

  ffenr #(WIDTH) data_ff (
      clk,
      rst,
      data,
      en,
      data1
  );

  assign bdata = en ? data : data1;
endmodule

module buffer #(
    parameter WIDTH = 8
) (
    input                    clk,
    input                    rst,
    input  logic             prev_valid,
    input  logic [WIDTH-1:0] prev_data,
    input  logic             next_en,
    output logic             next_valid,
    output logic [WIDTH-1:0] next_data
);

  logic             valid;
  logic [WIDTH-1:0] data;

  ffenr #(1) valid_ff (
      clk,
      rst,
      prev_valid,
      prev_valid ^ next_en,
      valid
  );
  ffen #(WIDTH) data_ff (
      clk,
      prev_data,
      prev_valid,
      data
  );

  assign next_valid = valid | prev_valid;
  assign next_data  = valid ? data : prev_data;
endmodule