226 lines
6.1 KiB
Verilog
226 lines
6.1 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`timescale 1ns/1ps
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`define APP_FLASH "../../../../../../simu/soft/func/flash.vlog"
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`define UART_CLK soc_up_top.APB_DEV.uart0.regs.enable
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module godson_system;
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// ========================================================================== //
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// Signal Declarations //
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// ========================================================================== //
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// Clocks
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reg clk,resetn;
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reg mac_clk;
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initial begin
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clk = 1'b0;
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mac_clk = 1'b0;
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resetn = 1'b0;
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#2000;
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resetn = 1'b1;
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end
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always #15.15 clk = ~clk;
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always #20 mac_clk = ~mac_clk;
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//------DDR3 interface------
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wire [15:0] ddr3_dq;
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wire [12:0] ddr3_addr;
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wire [2 :0] ddr3_ba;
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wire ddr3_ras_n;
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wire ddr3_cas_n;
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wire ddr3_we_n;
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wire ddr3_odt;
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wire ddr3_reset_n;
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wire ddr3_cke;
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wire [1:0] ddr3_dm;
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wire [1:0] ddr3_dqs_p;
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wire [1:0] ddr3_dqs_n;
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wire ddr3_ck_p;
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wire ddr3_ck_n;
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//----mac controller------
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//I/O pad interface signals
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// Tx
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wire mtxclk_0; // Transmit clock (from PHY)
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wire [3:0] mtxd_0; // Transmit nibble (to PHY)
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wire mtxen_0; // Transmit enable (to PHY)
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wire mtxerr_0; // Transmit error (to PHY)
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assign mtxclk_0 = mac_clk;
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// Rx
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wire mrxclk_0; // Receive clock (from PHY)
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wire [3:0] mrxd_0; // Receive nibble (from PHY)
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wire mrxdv_0; // Receive data valid (from PHY)
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wire mrxerr_0; // Receive data error (from PHY)
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assign mrxclk_0 = mac_clk;
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// MII Management interface
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wire mdc_0; // MII Management data clock (to PHY)
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wire mdio_0; // MII data inout
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wire phy_rstn;
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wire [7:0] LED;
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wire UART_RX, UART_TX;
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wire UART_CTS, UART_RTS;
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wire UART_DTR, UART_DSR;
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wire UART_RI, UART_DCD;
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//nand
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wire NAND_CLE ;
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wire NAND_ALE ;
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wire NAND_RDY ;
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wire [7:0] NAND_DATA;
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wire NAND_RD ;
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wire NAND_CE ; //low active
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wire NAND_WR ;
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wire SPI_CLK, SPI_CS, SPI_MISO, SPI_MOSI;
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wire TDI = 1'b0;
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wire TDO;
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wire TCK = 1'b0;
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wire TRST = 1'b0;
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wire TMS = 1'b0;
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soc_up_top soc_up_top (
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.clk (clk ),
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.resetn (resetn ),
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.ddr3_dq (ddr3_dq ),
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.ddr3_addr (ddr3_addr ),
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.ddr3_ba (ddr3_ba ),
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.ddr3_ras_n (ddr3_ras_n ),
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.ddr3_cas_n (ddr3_cas_n ),
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.ddr3_we_n (ddr3_we_n ),
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.ddr3_odt (ddr3_odt ),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_cke (ddr3_cke ),
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.ddr3_dm (ddr3_dm ),
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.ddr3_dqs_p (ddr3_dqs_p ),
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.ddr3_dqs_n (ddr3_dqs_n ),
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.ddr3_ck_p (ddr3_ck_p ),
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.ddr3_ck_n (ddr3_ck_n ),
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//------gpio----------------
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.led (),
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.led_rg0 (),
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.led_rg1 (),
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.num_csn (),
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.num_a_g (),
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.switch (8'd0),
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.btn_key_col (),
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.btn_key_row (4'd0),
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.btn_step (2'd0),
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.UART_RX(UART_RX),
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.UART_TX(UART_TX),
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.SPI_CLK(SPI_CLK),
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.SPI_CS(SPI_CS),
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.SPI_MISO(SPI_MISO),
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.SPI_MOSI(SPI_MOSI)
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);
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MX25L6405D #
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(
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.Init_File(`APP_FLASH)
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)
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spi_flash
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(
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.SCLK (SPI_CLK ),
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.CS (SPI_CS ),
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.SI (SPI_MOSI),
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.SO (SPI_MISO),
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.WP (1'b1 ),
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.HOLD (1'b1 )
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);
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uart_dev #
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(
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.uart_number (0),
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.STRLEN (80)
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)
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uart_dev0
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(
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.clk (`UART_CLK),
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.rst_n (resetn),
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.rx (UART_TX),
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.tx (UART_RX)
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);
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ddr3_model u_comp_ddr3
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(
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.rst_n (ddr3_reset_n),
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.ck (ddr3_ck_p),
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.ck_n (ddr3_ck_n),
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.cke (ddr3_cke ),
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.cs_n (1'b0 ),
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.ras_n (ddr3_ras_n),
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.cas_n (ddr3_cas_n),
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.we_n (ddr3_we_n),
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.dm_tdqs (ddr3_dm),
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.ba (ddr3_ba),
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.addr (ddr3_addr),
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.dq (ddr3_dq),
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.dqs (ddr3_dqs_p),
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.dqs_n (ddr3_dqs_n),
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.tdqs_n (),
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.odt (ddr3_odt)
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);
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`ifdef DUMPDUMP
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initial
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begin
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$fsdbDumpfile("wave.fsdb");
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$fsdbDumpvars(0, godson_system);
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#57888881
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$fsdbDumpon;
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#100000000
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$fsdbDumpoff;
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end
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`endif
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initial begin
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forever begin
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#500000;
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$display("\t\t@%0t: CPU commit PC is %x", $time, godson_system.soc_up_top.u_cpu.debug_wb_pc);
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end
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end
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endmodule
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