module DCTag_bram (
    input      [ 6:0] addra,
    input             clka,
    input      [22:0] dina,
    output reg [22:0] douta,
    input             wea
);

	reg [22:0] ram [0:127];
	always @(posedge clka) begin
		if(wea) begin
			ram[addra] <= dina;
		end
		douta <= ~wea ? ram[addra] : {$random}[22:0];
	end

endmodule