# TODO: test whether it works
set outputDir ./vivado

# Add Source
read_verilog -sv [ glob ./src/**/*.sv ]
read_verilog -sv [ glob ../src/**/*.sv ]
read_checkpoint ./src/lcd_module.dcp
read_ip [ glob ./ip/*.xci ]
read_xdc ./constraints.xdc

# Run
synth_design -top [lindex [find_top] 0] -part xc7a200tfbg676-2
opt_design
place_design
phys_opt_design
route_design

# Report
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_utilization -file $outputDir/post_route_util.rpt

# Bitstream
write_bitstream $outputDir/awesome.bit