`include "defines.svh"

module mul_signed(
  input  logic        CLK,
  input  logic [31:0] A,
  input  logic [31:0] B,
  output logic [63:0] P
);

  logic [31:0] rA;
  logic [31:0] rB;
  logic [63:0] M[`MUL_PIPE_STAGES-2:0];

  always_ff @(posedge CLK) begin
    rA   <= A;
    rB   <= B;
    M[0] <= $signed(rA) * $signed(rB);
    for (integer i = 0; i < `MUL_PIPE_STAGES-2; i = i + 1)
      M[i+1] <= M[i];
  end

  assign P = M[`MUL_PIPE_STAGES-2];

endmodule