`include "defines.svh"

module mul_unsigned(
    input  logic        CLK,
    input  word_t       A,
    input  word_t       B,
    output logic [63:0] P  
);

    word_t A1, A2, A3, A4, A5, A6;
    word_t B1, B2, B3, B4, B5, B6;

    ffen #(64) ff_1 (CLK, { A,  B}, 1'b1, {A1, B1});
    ffen #(64) ff_2 (CLK, {A1, B1}, 1'b1, {A2, B2});
    ffen #(64) ff_3 (CLK, {A2, B2}, 1'b1, {A3, B3});
    ffen #(64) ff_4 (CLK, {A3, B3}, 1'b1, {A4, B4});
    ffen #(64) ff_5 (CLK, {A4, B4}, 1'b1, {A5, B5});
    ffen #(64) ff_6 (CLK, {A5, B5}, 1'b1, {A6, B6});

    assign P = $unsigned(A) * $unsigned(B);

endmodule