module DCData_bram (
    input      [  6:0] addra,
    input              clka,
    input      [127:0] dina,
    output reg [127:0] douta,
    input              wea
);

	reg [127:0] ram [0:127];
	always @(posedge clka) begin
		if(wea) begin
			ram[addra] <= dina;
		end
		douta <= ~wea ? ram[addra] : {4{$random}};
	end

endmodule